correlated double sampler (CDS) Fixed gain noise optical black clamp c
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Correlated Double Sampler (CDS) AD9823
correlated double sampler (CDS) Fixed gain noise optical black clamp circuit single-supply operation 14-lead TSSOP package
AD9823
3.5dB FIXED GAIN OUTPUT BUFFER
CCDIN
OUTPUT
APPLICATIONS
Digital still cameras Digital video camcorders CCTV cameras cameras Portable imaging devices
BYP2
OUTPUT BUFFER REFOUT
INTERNAL TIMING
INTERNAL REFERENCE
04538-0-001
BYP1
BYP3
Figure Functional Block Diagram
PRODUCT DESCRIPTION
AD9823 correlated double sampler digital camera applications. features amplifier with fixed gain, internal voltage reference supply, timing control sampling clocks. Output buffers also included, providing drive strength traces direct connection image signal processor such AD9821. AD9823 ideal applications that need place VGA/ADC circuits separate boards. "pseudo differential" outputs AD9823 provide good signal integrity when interfaced with differential input AD9821. AD9823 operates from single power supply, typically dissipates packaged 14-lead TSSOP package.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2003 Analog Devices, Inc. rights reserved.
AD9823 TABLE CONTENTS
Specifications. General Specifications Analog Specifications. Digital Specifications Timing Specifications Absolute Maximum Ratings. Thermal Characteristics Caution.5 Configuration Function Descriptions.6 Timing Outline Dimensions Ordering Guide
REVISION HISTORY
Revision Initial Version
Rev. Page
AD9823 SPECIFICATIONS
GENERAL SPECIFICATIONS
Table
Parameter Temperature Range Operating Storage Power Supply Voltage Power Consumption: fSAMP MHz, Maximum Clock Rate Minimum Clock Rate +150 Unit
ANALOG SPECIFICATIONS
Table TMIN TMAX, fSAMP MHz, unless otherwise noted.
Parameter Analog Input (CCDIN) Input Range Before Saturation1 Allowable Reset Transient1 Black Pixel Amplitude1 Gain Nonlinearity, Input Input Referred Noise Clamp Time Constant Analog Outputs Typical Data Signal Range REFOUT Voltage Level Unit µsec Notes
deviation from ideal straight line Output noise divided gain BYP2 capacitor (proportional capacitor value) corresponds black level Fixed reference signal output
Input signal characteristics defined follows:
specifications subject change without notice.
DIGITAL SPECIFICATIONS
Table
Parameter Logic Inputs (SHP, SHD, CLP) High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance Symbol Unit
04538-0-002
500mV RESET TRANSIENT 100mV OPTICAL BLACK PIXEL 850mV INPUT SIGNAL RANGE
Rev. Page
AD9823
TIMING SPECIFICATIONS
Table TMIN TMAX, fSAMP MHz, unless otherwise noted.
Parameter (See Figure Sample Clocks SHP, Clock Period Pulse Width Pulse Width Pulse Width1 Rising Edge Rising Edge Rising Edge Rising Edge Internal Clock Delay Recommended Data Timing (for AD9821) Symbol tSHP tSHD tCOB tREC 12.0 12.0 Unit pixels
6.25 6.25 12.5 12.5
Minimum pulse width functional operation only. Wider typical pulses recommended achieve noise clamp performance. Specifications subject change without notice.
Rev. Page
AD9823 ABSOLUTE MAXIMUM RATINGS
Table
Parameter SHP, BYP1, BYP2, BYP3 CCDIN DATAOUT, REFOUT Junction Temperature Lead Temperature sec) With Respect -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Unit
THERMAL CHARACTERISTICS
Thermal Resistance 14-Pin, TSSOP Package 89.2°C/W
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD9823 CONFIGURATION FUNCTION DESCRIPTIONS
VIEW CCDIN (Not Scale) DATAOUT
AD9823
REFOUT
BYP1
BYP3 BYP2
CONNECT
Figure Configurations
Table Function Descriptions
Number Name REFOUT DATAOUT BYP1 BYP2 BYP3 CCDIN Type1 Description Input Clamp Clock Input (active low, latched internally). connection should connected VDD. Analog Supply. Output Reference Level. Output Data Signal. Analog Ground. Internal Bias Level Decoupling. Internal Bias Level Decoupling. Internal Bias Level Decoupling. connection should connected VDD. Input. Analog Ground. Sampling Clock Input (For Data Level). Sampling Clock Input (For Level).
Analog Input, Analog Output, Digital Input, Digital Output, Power, Connect.
TIMING
SIGNAL
04538-0-003
N+10
tSHD
tSHP
DATAOUT
tREC
Figure Timing
Rev. Page
04538-0-004
DATACLK (FOR AD9821)
AD9823
EFFECTIVE PIXELS OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS
SIGNAL
Figure Timing
ANALOG SUPPLY
4.7µF
0.1µF
0.1µF
REFOUT
(CONNECT VIN- AD9821)
REFOUT DATAOUT BYP1 0.1µF
AD9823
DATAOUT
(CONNECT VIN+ AD9821)
VIEW CCDIN (Not Scale)
CCDIN
BYP3 BYP2
04538-0-005
CONNECT
0.1µF
0.1µF
Figure AD9823 Circuit Configuration
ANALOG SUPPLY 0.1µF 1.0µF SERIAL INTERFACE 1.0µF
SDATA STBY DVSS DVDD2
ANALOG SUPPLY ANALOG SUPPLY
(MSB) DATA OUTPUTS
IDENTIFIER
AD9821
VIEW (Not Scale
TEST AVSS TEST AVDD2 BYP1 VIN- VIN+ TEST TEST AVDD1 AVSS AVSS
0.1µF 4.7µF 0.1µF IMAGER INPUT, NEGATIVE IMAGER INPUT, POSITIVE 0.1µF
REFOUT DATAOUT BYP1 0.1µF
AD9823
VIEW (Not Scale)
CCDIN BYP3 BYP2 0.1µF
0.1µF
OUTPUT FROM
0.1µF
ANALOG SUPPLY 0.1µF 4.7µF
DRIVER SUPPLY
DRVDD DRVSS DVSS DATACLK DVDD1 PBLK CLPOB TEST TEST TEST
INTERNALLY CONNECTED
0.1µF CLOCK INPUTS
04538-0-006
0.1µF ANALOG SUPPLY
Figure Circuit Configuration with AD9821 12-Bit Image Signal Processor
Rev. Page
04538-0-007
AD9823 OUTLINE DIMENSIONS
5.10 5.00 4.90
4.50 4.40 4.30
6.40
1.05 1.00 0.80 0.65 1.20 0.15 0.05 0.30 0.19 0.20 0.09 0.75 0.60 0.45
SEATING COPLANARITY PLANE 0.10
COMPLIANT JEDEC STANDARDS MO-153AB-1
Figure 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown millimeters
ORDERING GUIDE
Model AD9823BRUZ1 Temperature Range -25°C +85°C Package Description TSSOP Package Option RU-14
Pb-free part.
2003 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. C04538-0-11/03(0)
Rev. Page
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