High accuracy, high resolution voltage outputs 12-bit input resolution

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High accuracy, high resolution voltage outputs 12-bit input resolution

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High Performance 12-Bit, 6-Channel Output, Decimating DecDriver® AD8382
High accuracy, high resolution voltage outputs 12-bit input resolution Laser trimmed outputs Fast settling, high voltage drive settling time 0.25% into load Slew rate V/µs Outputs within supply High update rates Fast, Ms/s data update rate Voltage controlled video reference (brightness) full-scale (contrast) output levels Flexible logic STSQ/XFR allow parallel AD8382 operation reverses polarity video signal Output overload protection static power dissipation: Includes STBY function logic, analog supplies Available 48-lead LFCSP
DB(0:11)
2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH
VID0
AD8382
VID1
STBY
VID2
BIAS
VID3
STSQ SEQUENCE CONTROL
VID4
VID5
SCALING CONTROL VREFHI VREFLO
APPLICATIONS
analog column driver
Figure Functional Block Diagram
PRODUCT DESCRIPTION
AD8382 DecDriver provides fast, 12-bit latched decimating digital input that drives high voltage outputs.12-bit input words sequentially loaded into separate, high speed, bipolar DACs. flexible digital input format allows several AD8382s used parallel higher resolution displays. STSQ synchronizes sequential input loading, controls synchronous output updating, controls direction loading either left-to-right right-to-left. channels high voltage output drivers drive within rail. output signal adjusted reference, signal inversion, contrast maximum flexibility. AD8382 fabricated Analog Devices' XFHV, fast bipolar process, providing fast input logic bipolar DACs with trimmed accuracy fast settling, high voltage, precision drive amplifiers same chip. AD8382 dissipates nominal static power. STBY reduces power minimum, with fast recovery.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2003 Analog Devices, Inc. rights reserved.
AD8382
TABLE CONTENTS
Specifications. Absolute Maximum Ratings. Timing Characteristics. Configuration Functional Descriptions. Typical Performance Characteristics Functional Description Transfer Function Accuracy Applications. VBIAS Generation-V1, Input Functionality Power Supply Sequencing Design Optimized Thermal Performance Layout Considerations. Outline Dimensions Ordering Guide
REVISION HISTORY
Revision Initial Version
Rev. Page
AD8382
SPECIFICATIONS
Table 25°C, AVCC 15.5 DVCC TMIN 0°C, TMAX 85°C, VREFHI VREFLO unless otherwise noted.
Parameter VIDEO PERFORMANCE VCME
Conditions TMIN TMAX Code 1500 3200 Code 1500 3200 Code 2048 Code 4095 MAX, Step,
-3.5
+3.5
Unit
VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling Time Data Switching Settling Time 0.25% Invert Switching Settling Time Invert Switching Settling Time 0.25% Invert Switch Overshoot Data Feedthrough2 All-Hostile Crosstalk3 Amplitude Duration Transition Glitch Energy VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing Delay: Delay: Output Current Output Resistance RESOLUTION Coding DIGITAL INPUT CHARACTERISTICS Max. Input Data Update Rate Data Setup Time: STSQ Setup Time: Setup Time: Data Hold Time: STSQ Hold Time: Hold Time: High Time: Time: IIL-All Inputs except IIL-CLK
+0.5
12.4
V/µs V/µs nV-s
Code 2047 Code 2048 AVCC VOH, VOL- AGND VIDx VIDx
10.4
14.4
Bits Ms/s
Binary Input (10% 90%)
0.05
Rev. Page
AD8382
Parameter REFERENCE INPUTS1 Range Range Input Current Input Current VREFLO Range VREFHI Range (VREFHI VREFLO) Range VREFHI Input Resistance VREFLO Bias Current VREFHI Input Current Range POWER SUPPLY DVCC, Operating Range DVCC, Quiescent Current AVCC, Operating Range Total AVCC Quiescent Current STBY AVCC Current STBY DVCC Current OPERATING TEMPERATURE RANGE Ambient Temperature Range, Ambient Temperature Range, Junction Temperature Range, Conditions 0.25 0.25 -7.5 VREFHI (VREFLO 2.75 VREFHI (VREFLO 2.75 VREFLO -0.2 (VREFHI VREFLO) STBY HIGH STBY HIGH Still 100% Tested 0.15 0.45 AVCC AVCC 2.75 AVCC AVCC Unit
differential error voltage. VCME common-mode error voltage. maximum deviation between outputs. Full-scale output voltage (VREFHI VREFLO). Accuracy section page Measured outputs differentially DB(0:11) driven STSQ held LOW. Measured outputs differentially other four transitioning Measured both states INV. Measured from falling edge output change. Measurement made both states INV. Operation 85°C ambient temperature requires thermally optimized layout (see Applications section), minimum airflow lfm, input clock rate exceeding MHz, black-to-white transition
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AD8382
ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings1
Parameter Supply Voltages AVCCx AGNDx DVCC DGND Input Voltages Maximum Digital Input Voltage Minimum Digital Input Voltage Maximum Analog Input Voltage Minimum Analog Input Voltage Internal Power Dissipation2 LFCSP Package 25°C Ambient Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering sec)
Rating DVCC DGND AVCC AGND 3.84 85°C -65°C +125°C 300°C
MAXIMUM POWER DISSIPATION
maximum power that AD8382 safely dissipate limited junction temperature. maximum safe junction temperature plastic encapsulated devices, determined plastic's glass transition temperature, approximately 150°C. Temporarily exceeding this limit cause shift parametric performance change stresses exerted package. Exceeding junction temperature 175°C extended periods result device failure.
OPERATING TEMPERATURE RANGE
Although maximum safe operating junction temperature higher, AD8382 100% tested junction temperature 125°C. Consequently, maximum guaranteed operating junction temperature 125°C. ensure operation within specified operating temperature range, necessary limit maximum power dissipation
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum ratings extended periods reduce device reliability. 48-lead LFCSP Package: 26°C/W (JEDEC STD, 4-layer still air) 20°C/W. 11°C/W Still
PDMAX where TJMAX 125°C
(TJMAX-TA -0.9 Airflow lfm)
OVERLOAD PROTECTION
AD8382 employs two-stage overload protection circuit that consists output current limiter thermal shutdown. maximum current output AD8382 internally limited average. event momentary short circuit between video output power supply rail (VCC AGND), output current limit sufficiently provide temporary protection. thermal shutdown "debiases" output amplifier when junction temperature reaches internally trip point. event extended short circuit between video output power supply rail, output amplifier current continues switch between typ. with period thermal time constant hysteresis thermal trip point. thermal shutdown provides long-term protection limiting average junction temperature safe level.
AD8382 4-LAYER JEDEC WITH THERMALLY OPTIMIZED LANDING PATTERN DESCRIBED APPLICATION NOTES 2.00 1.75 120MHz 1.50 STILL 1.25 60Hz
POWER DISSIPATION
1.00 Quiescent
0.75
0.50
MAXIMUM AMBIENT TEMPERATURE (°C)
Figure Maximum Power Dissipation Temperature.
Note: Quiescent power dissipation 0.74 when operating under conditions specified this data sheet.
EXPOSED PADDLE
ensure high degree reliability, exposed paddle must electrically connected AVCC. ensure optimized thermal performance, exposed paddle must thermally connected AVCC plane described Applications section.
When driving 6-channel panel with input capacitance AD8382 dissipates total 1.14 when displaying pixel wide alternating white black vertical lines generated standard input video. total power dissipation AD8382 1.67 when operating maximum specified frequency MHz, under conditions specified this data sheet (Figure
Rev. Page
AD8382
TIMING CHARACTERISTICS
Table Timing Parameters Conditions
Parameter Data Setup Time Data Hold Time STSQ Setup Time STSQ Hold Time Setup Time Hold Time High Time Time VIDx Delay t10, VIDx Delay VIDx VIDx Conditions (10% 90%) 10.4 12.4 14.4 Unit
DB(0:11)
STSQ
VID(0:5)
Figure Timing Requirement HIGH
Figure Output Timing
DB(0:11)
STSQ
Figure Timing Requirement
Rev. Page
AD8382
CONFIGURATION FUNCTIONAL DESCRIPTIONS
AGNDDAC AVCCDAC VREFLO VREFHI AGND0 STSQ
DB10 DB11
INDICATOR
VID0 AVCC0,1 VID1 AGND1,2 VID2 AVCC2,3 VID3 AGND3,4 VID4 AVCC4,5 VID5 AGND5
AD8382
VIEW (Not Scale)
DGND
DVCC
AVCCBIAS
STBY
AGNDBIAS
CONNECT
Figure 48-Lead LFCSP, Package
Table Function Descriptions
Mnemonic DB(0:11) STSQ Function Data Input Clock Start Sequence Description 12-Bit Data Input. DB(11). Clock Input. data loading sequence begins rising edge when this input HIGH preceding rising edge input held HIGH. data loading sequence begins falling edge when this input HIGH preceding falling edge input held LOW. data loading sequence begins left, with Channel when this input LOW, right, with Channel when this input HIGH. active edge rising edge when this input held HIGH falling edge when this input held LOW. Data loaded sequentially rising edges when this input HIGH falling edges when this input LOW. Data transferred outputs immediately following falling edge when this input HIGH rising edge CLK. These pins directly connected analog inputs panel. voltages applied between these pins AGND reference levels analog outputs. voltage applied between these pins sets full-scale output voltage. When this HIGH, analog output voltages above When this LOW, analog output voltages below Digital Power Supply. This normally connected analog ground plane. Analog Power Supplies. Analog Supply Returns. capacitor connected between this AGND ensures optimum settling time. When HIGH, internal circuits debiased power dissipation drops minimum.
Right/Left Select Even/Odd Select
VID0-VID5 V1,V2 VREFHI, VREFLO DVCC DGND AVCCx AGNDx STBY
Data Transfer Analog Outputs Reference Voltages Full-Scale References Invert Digital Power Supply Digital Supply Return Analog Power Supplies Analog Supply Returns Bypass Standby
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AD8382
TYPICAL PERFORMANCE CHARACTERISTICS
1.00 0.75 0.50 0.25 OUTPUT OUTPUT 0.00 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50
1.50 1.25 1.00 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00
TIME (ns)
TIME (ns)
Figure Output Settling Time (Rising Edge), Step,
1.00 0.75 0.50 0.25 OUTPUT OUTPUT 0.00 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50
Figure Output Settling Time (Falling Edge), Step,
1.50 1.25 1.00 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00
TIME (ns)
TIME (ns)
Figure Output Settling Time (Rising Edge), Step, HIGH
Figure Output Settling Time (Falling Edge), Step, HIGH
0pF, 47pF, 100pF,
OUTPUT OUTPUT
0pF, 47pF,
0.25%/DIV
150pF,
0.25%/DIV
200pF, 250pF, 300pF,
100pF, 150pF, 200pF, 250pF, 300pF,
TIME (ns)
TIME (ns)
Figure Output Settling Time (Rising Edge) Step, HIGH
Figure Output Settling Time (Falling Edge) Step, HIGH
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AD8382
SWITCHING STEP RESPONSE SWITCHING STEP RESPONSE 20ns/DIV 20ns/DIV TIME (ns)
TIME (ns)
Figure Invert Switching Step Response (Rising Edge), Step,
Figure Invert Switching Step Response (Falling Edge), Step,
SWITCHING STEP RESPONSE
SWITCHING STEP RESPONSE 20ns/DIV
20ns/DIV
TIME (ns)
TIME (ns)
Figure Data Switching Step Response (Rising Edge), Step, CL=200
Figure Data Switching Step Response (Falling Edge), Step,
SWITCHING STEP RESPONSE
SWITCHING STEP RESPONSE 20ns/DIV
20ns/DIV
TIME (ns)
TIME (ns)
Figure Data Switching Step Response (Rising Edge), Step, HIGH
Figure Data Switching Step Response (Falling Edge), Step, HIGH
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AD8382
-0.5 -1.0 -1.5 -2.0 -0.5 -1.0 -1.5 -2.0
(LSB)
1024
1536
2048
2564
3072
3584
4096
(LSB)
1024
1536
2048
2564
3072
3584
4096
INPUT CODE
INPUT CODE
Figure Differential Nonlinearity (DNL) Code,
Figure Differential Nonlinearity (DNL) Code, HIGH
(LSB) -0.5 -1.0 -1.5 -2.0 (LSB) 1024 1536 2048 2564 3072 3584 4096
-0.5 -1.0 -1.5 -2.0
1024
1536
2048
2564
3072
3584
4096
INPUT CODE
INPUT CODE
Figure Integral Nonlinearity (INL) Code,
Figure Integral Nonlinearity (INL) Code, HIGH
3.500 2.625 1.750
VCME (mV)
5.00 3.75 2.50 1.25 (mV) 1024 1536 2048 2564 3072 3584 4096
0.875
-0.875 -1.750 -2.625 -3.500
-1.25 -2.50 -3.75 -5.00
1024
1536
2048
2564
3072
3584
4096
INPUT CODE
INPUT CODE
Figure Common-Mode Error Voltage (VCME) Code
Figure Differential Error Voltage (VDE) Code
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AD8382
NORMALIZED VDE, VCME (mV)
NORMALIZED VDE, VCME (mV)
VCME
VCME
10.0
11.0
Figure Normalized VDE, VCME Code 2048
Figure Normalized VDE, VCME Code 2048
NORMALIZED VDE, VCME (mV)
VCME
NORMALIZED (mV)
VREFLO
Figure Normalized Code 2048
Figure Normalized VDE, VCME VREFLO Code 2048
3.500 2.625 1.750
5.00 3.75 2.50 1.25
VCME (mV)
0.875
(mV)
CODE 2048
CODE 2048
-0.875 -1.750 -2.625 -3.500
-1.25 -2.50 -3.75 -5.00
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure Common-Mode Error Voltage (VCME) Temperature
Figure Differential Error Voltage (VDE) Temperature
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AD8382
7.05 7.04 7.03 7.02 7.01 20ns/DIV 7.05 7.04 7.03 7.02 7.01
7.00 6.09 VID0, 6.08 6.07 6.06 6.05 TIME (ns)
(VID4 VID5)
(VID4 VID5) 7.00 6.09 6.08 6.07 6.06 6.05 TIME (ns) 20ns/DIV 3.3V (0:11)
Figure All-Hostile Crosstalk
Figure Data Switching Transient (Feedthrough)
SLEW RATE (V/µs)
SLEW RATE (V/µs)
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure Slew Rate (Falling Edge)
Figure Slew Rate (Rising Edge)
(dB)
HIGH
100k
FREQUENCY (Hz)
Figure AVCC Power Supply Rejection Frequency
Rev. Page
AD8382
FUNCTIONAL DESCRIPTION
AD8382 system building block designed directly drive columns microdisplays type popularized projection systems. comprises channels precision, 12-bit digital-to-analog converters loaded from single, high speed, 12-bit wide input. Precision current feedback amplifiers, providing well-damped pulse response fast voltage settling into large capacitive loads, buffer outputs. Laser trimming wafer level ensures absolute output errors tight channel-to-channel matching. Tight part-to-part matching high resolution systems guaranteed external voltage references.
INPUTS-VOLTAGE REFERENCE INPUTS
external analog voltage references levels outputs. sets output voltage Code 4095 while input LOW, sets output voltage Code 4095 while input held HIGH.
VREFHI, VREFLO INPUTS-FULL-SCALE REFERENCE INPUTS
Twice difference between these analog input voltages sets full-scale output voltage VFS.
(VREFHI VREFLO)
START SEQUENCE CONTROL-INPUT DATA LOADING
valid STSQ control input initiates 6-clock loading cycle, during which input data-words loaded sequentially into internal channels. loading sequence begins current active edge only when STSQ held HIGH preceding active edge. Active edge defined Control.
CONTROL-ANALOG OUTPUT INVERSION
analog voltage equivalent input code subtracted from VFS) while held HIGH added VFS) while held LOW.
Transfer Function
AD8382 regions operation, where video output voltages either above reference voltage below reference voltage transfer function defines video output voltage function digital input code follows:
VIDx(n) n/4095), HIGH VIDx(n) n/4095),
EVEN/ODD CONTROL-INPUT DATA LOADING
facilitate 12-channel, single data systems, active edge, which input data loaded, selected with control input. Input data loaded rising edges while input held HIGH; input data loaded falling edges while input held LOW.
RIGHT/LEFT CONTROL-INPUT DATA LOADING
facilitate image mirroring, direction loading sequence control. loading sequence begins channel proceeds Channel when control held LOW. begins Channel proceeds channel when control held HIGH.
where input code
(VREFHI VREFLO)
number internal limits define usable range video output voltages, VIDx, shown Figure
AVCC 1.3V
CONTROL-DATA TRANSFER OUTPUTS
Data transfer outputs initiated control. While held HIGH during rising edge, data simultaneously transferred outputs immediately following falling edge.
HIGH
INTERNAL LIMITS USABLE VOLTAGE RANGES
5.5V
VIDx
AVCC
(AVCC 5.5V (AVCC 1.3V
STBY CONTROL-STANDBY MODE
HIGH applied STBY input debiases internal circuitry, dropping quiescent power dissipation milliwatts. Upon returning STBY LOW, normal operation restored. Since both analog digital circuitry debiased, stored data will lost standby mode.
AGND INPUT CODE
4095
Figure Transfer Function Usable Voltage Ranges
Rev. Page
AD8382
Accuracy
best correlate transfer function errors image artifacts, overall accuracy AD8382 defined three parameters: VDE, VCME,
VDE, differential error voltage, measures difference between value output value ideal. defining expression
AVCC
VFS)
VIDx
VOUTN(n)
VDE(n)
[VOUTN [VOUTP(n) 4095
VFS)
VOUTP(n)
VCME, common-mode error voltage, measures one-half bias output. defining expression VCME(n) VOUTN +VOUTP(n)
AGND
INPUT CODE
4095
Figure AD8382 Transfer Function
measures maximum deviation between output voltages. defining expression max{VN(n), VP(n)} where VN(n) max{VOUTN(n)(0-5)} min{VOUTN(n)(0-5)} VP(n) max{VOUTP(n)(0-5) min{VOUTP(n)(0-5)}
Rev. Page
AD8382
APPLICATIONS
OPERATING MODES-6-CHANNEL SYSTEMS
Depending speed microdisplay, 6-channel systems compatible with resolutions require AD8382 color. input/output timing diagram AD8382 such systems shown Figure
DB(0:11) STSQ XFRF
PIXEL DB(0:11) STSQ STSQ
INPUTS
INPUTS
EVEN
INTERNAL LATCHES
VID0 VID1
AD8382 EVEN INTERNAL LATCHES
VID0 VID1 VID2 VID3 VID4 VID5
OUTPUTS
VID2 VID3 VID4 VID5
Figure Timing Diagram Typical 6-Channel System, E/O=HIGH, R/L=LOW
AD8382 INTERNAL LATCHES
OPERATING MODES-12-CHANNEL SYSTEMS
12-channel systems usually those requiring video line doubling compatibility with SXGA higher resolutions. Depending input data rates, types 12-channel systems common use.
OUTPUTS
VID0 VID1 VID2 VID3 VID4 VID5
12-Channel, Even/Odd Systems
Single data systems characterized image processor with single data output. They require AD8382s color. AD8382 operate EVEN mode, while other operate mode. Both AD8382s share same data CLK. timing diagram such system shown Figure
OUTPUTS
Figure 12-Channel Even/Odd System Timing Diagram
OPERATING MODES-BEYOND CHANNELS
12-Channel Parallel Systems
Dual data systems characterized image processor with data outputs. They require AD8382s color. Both AD8382s dual data systems independently. timing diagram each AD8382 such systems identical that 6-channel system. number AD8382s cascaded even/odd pairs parallel facilitate very high resolution systems.
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AD8382
IMAGE PROCESSOR STSQ2 STSQ1 Pixel DB1(0:11) STSQ1 INV1 E/O1 STSQ2 INV2 E/O2 DB(0:11) STSQ VREFHI VREFLO VID0 VID1 VID2 VID3 VID4 VID5
AD8382
REVERSE
COUNTER
COUNTER HSTART
CHANNEL
AD8382
DB(0:11) VID0 HSYNC VSYNC INV1 INV2 STSQ VREFHI VREFLO VID1 VID2 VID3 VID4 VID5
REFERENCES VREFHI VREFLO
Figure Single Data 12-Channel Even/Odd System Block Diagram
IMAGE PROCESSOR D(0:9) D(0:9) Even Pixel REVERSE COUNTER HSTART DB1(0:11) STSQ INV1 INV2 DB(0:11) STSQ VREFHI VREFLO
AD8382
VID0 VID1 VID2 VID3 VID4 VID5
CHANNEL
AD8382
D(0:9) Even D(0:9) HSYNC VSYNC INV1 INV2 DB2(0:11) DB(0:11) VID0 STSQ VREFHI VREFLO VID1 VID2 VID3 VID4 VID5
REFERENCES VREFHI VREFLO
Figure Dual Data 12-Channel Even/Odd System Block Diagram
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AD8382
VBIAS Generation-V1, Input Functionality
order avoid image flicker, symmetrical voltage required bias voltage approximately minimum must maintained across pixels HTPS LCDs. AD8382 provides methods maintaining this bias voltage.
APPLICATIONS CIRCUIT
circuit Figure ensures VBIAS symmetry within with minimum component count. Bypass capacitors omitted clarity.
AVCC 15.5V
5.1V
INTERNAL BIAS VOLTAGE GENERATION
Standard systems that internally generate bias voltage reserve uppermost code range bias voltage remaining code range encode video gamma correction. high degree symmetry guaranteed AD8382 these systems. inputs these systems tied together normally connected VCOM, shown Figure
VCOM
AD8382
VCOM AD8132
DVCC 3.3V
Figure External VBIAS Generator with AD8132
AD8382
VCOM VCOM VBIAS VBIAS 3280 4095
RESERVED CODE RANGE
VCOM
VBIAS VBIAS 4095
Figure Connection Transfer Function Typical Standard System
EXTERNAL BIAS VOLTAGE GENERATION
systems that require improved brightness resolution higher accuracy, inputs, connected external voltage references, provide necessary bias voltage, VBIAS, while allowing full code range used gamma correction.
Figure AD8382 Transfer Function Typical High Accuracy System
8.75 7.50 6.25 5.00
V1)/2 VCOM (mV)
3.75 2.50 1.25 0.00 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 -8.75
ensure symmetrical voltage AD8382's outputs, VBIAS must remain constant both states INV. Thus, defined VCOM VBIAS VCOM VBIAS
85°C
25°C
10.2
10.7
Figure Typical Asymmetry Outputs AD8132 Power Supply Application Circuit
AD8132 typically produces symmetrical output 85°C when supply, (V+) (V-), (Figure 45).
Rev. Page
AD8382
Power Supply Sequencing
indicated Absolute Maximum Ratings, voltage input cannot exceed supply voltage more than ensure compliance with these ratings, following powerup power-down sequencing recommended. During power-up, initial application nonzero voltages input must delayed until supply voltage ramps least highest maximum operational input voltage. During power-down, voltage input must reach zero during period exceeding power supply's hold-up time. Failure comply with Absolute Maximum Ratings result functional failure damage internal diodes. Damaged diodes cause temporary parametric failures, which result image artifacts. Damaged diodes cannot provide full protection, reducing reliability.
Power Power
AD8382 package designed provide superior thermal characteristics, partly through exposed paddle bottom surface package. order take full advantage this feature, exposed paddle must direct thermal contact with PCB, which then serves heat sink.
Table AD8382 Power Dissipation
CLOAD (pF) PQUIESCENT 0.74 0.74 0.74 VSWING PDYNAMIC PTOTAL 0.93 1.67 1.16 1.90 1.39 2.13 VSWING PDYNAMIC PTOTAL 0.74 1.48 0.93 1.67 1.11 1.85
thermally effective must incorporate thermal thermal structure. thermal provides solderable contact surface surface PCB. thermal structure provides thermal path inner bottom layers remove heat.
Apply power supplies. Apply power other I/Os.
Remove power from I/Os. Remove power from supplies.
THERMAL DESIGN
Thermal performance AD8382 varies logarithmically with contact area between exposed thermal paddle thermal layer PCB. order minimize thermal performance degradation production PCBs, contact area between thermal should maximized. Therefore, size thermal should match exposed paddle size 5.25 5.25 addition, second thermal same size should placed bottom side PCB. least thermal should direct thermal (and electrical) contact with AVCC plane.
Design Optimized Thermal Performance
total maximum power dissipation AD8382 partly load dependent. 6-channel, MHz, system, total maximum power dissipation 1.14 input capacitance clock rate Ms/s, total maximum power dissipation exceed shown below black-to-white video output voltage swing Although maximum safe operating junction temperature higher, AD8382 100% tested junction temperature 125°C. Consequently, maximum guaranteed operating junction temperature 125°C. limit maximum junction temperature below guaranteed maximum, package, conjunction with PCB, must effectively conduct heat away from junction.
THERMAL STRUCTURE DESIGN
Effective heat transfer from inner bottom layers requires thermal vias incorporated into thermal design. Thermal performance increases logarithmically with number vias. reaches specified value approximately vias, provided AD8382 standard JEDEC PCB. approaches optimum value slope such curve approaches zero, above vias. Near optimum thermal performance production PCBs attained when number thermal vias least
Rev. Page
AD8382
AD8382 DESIGN RECOMMENDATIONS
SOLDER MASKING
minimize formation solder voids solder flowing into holes (solder wicking), diameter should small. Solder masking holes layer plugs holes, inhibiting solder flow into holes. optimize thermal coverage, solder mask diameter should more than larger than diameter.
Land pattern Dimensions Size: 0.25
Pitch: Thermal Size: 5.25 5.25 Thermal structure: 0.25 diameter. Vias 0.5mm grid.
Solder Mask-Top Layer
Pads: customer's Design Rules
LAND PATTERN LAYER
Figure Land Pattern-Top Layer
Thermal Vias: 0.25 dia. circular mask, centered vias.
THERMAL CONNECTIONS
Thermal Pads connected AVCC. PCBs with AVCC plane located outer layers, direct connection least thermal AVCC plane recommended. PCBs with AVCC plane located internal layers, direct connection thermal vias AVCC plane recommended.
Solder Mask-Bottom Layer
customer's Design Rules.
SOLDER MASK LAYER
Figure Solder Mask-Top Layer
LAND PATTERN BOTTOM LAYER
Figure Land Pattern-Bottom Layer
thermal spokes recommended when connecting thermal pads structure AVCC plane.
Rev. Page
AD8382
Layout Considerations
AD8382 mixed-signal, high speed, high accuracy device. order fully realize specifications, essential properly designed printed circuit board.
POWER SUPPLY BYPASSING
power supply reference pins AD8382 must properly bypassed analog ground plane optimum performance. analog supply pins connected directly analog supply plane located close part possible. chip capacitor should placed close each analog supply possible connected directly between each analog supply analog ground plane. minimum tantalum capacitor should placed near analog supply plane connected directly between supply analog ground planes. minimum tantalum capacitor should placed near digital supply connected directly analog ground plane. chip capacitor should connected between digital supply analog ground.
LAYOUT GROUNDING
analog outputs digital inputs AD8382 opposite sides package. Keep these sections separated minimize crosstalk coupling digital inputs into analog outputs. signal trace lengths should made short direct possible prevent signal degradation parasitic effects. Note that digital signals should cross should routed near analog signals. imperative provide solid analog ground plane under around AD8382. ground pins part should connected directly this ground plane with extra signal path length. This includes DGND, AGNDBIAS, AGND5, AGND3,4, AGND1,2, AGND0, AGNDDAC. return traces signals should routed close ground that section prevent stray signals from coupling into other ground pins.
VREFHI, VREFLO, REFERENCE DISTRIBUTION
ensure well-matched video outputs, AD8382s must operate from equal reference voltages. Each reference voltage should distributed each AD8382 directly from source reference voltage with approximately equal trace lengths. chip capacitor should placed close each reference input possible directly connected between reference input analog ground plane.
Rev. Page
AD8382
OUTLINE DIMENSIONS
7.00 0.60 0.60
0.30 0.23 0.18
INDICATOR
INDICATOR
VIEW
6.75
BOTTO VIEW
5.25 5.10 4.95
0.50 0.40 0.30 0.80 0.65 0.05 0.02 0.50 SEATING PLANE COPLANARITY 0.08
1.00 0.90 0.80 0.20
5.50
COMPLIANT JEDEC STANDARDS MO-220-VKKD-2
Figure 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)-Dimensions shown millimeters
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD8382 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Ordering Guide
Table
Model AD8382ACP Temperature Range 85°C Package Description 48-Lead LFCSP Package Option CP-48
Rev. Page
AD8382
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AD8382
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AD8382
2003 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective companies. Printed U.S.A. C03371-0-2/03(0)
Rev. Page

High accuracy, high resolution voltage outputs 12-bit input resolution

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