AMD64 Architecture Programmer's Manual Volume 64-Bit Media FloatingPoi
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AMD64 Architecture Programmer's Manual Volume 64-Bit Media FloatingPoint Instructions
Publication 26569 Revision 3.04 Date September 2003
2002, 2003 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, arrow logo, combinations thereof, 3DNow! trademarks, AMD-K6 registered trademark Advanced Micro Devices, Inc. trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
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Contents
Figures Tables Revision History .xiii Preface About This Book Audience Contact Information. Organization Definitions. Related Documents xxvii 64-Bit Media Instruction Reference.
CVTPD2PI CVTPI2PD CVTPI2PS. CVTPS2PI. CVTTPD2PI CVTTPS2PI EMMS FEMMS. FNSAVE (FSAVE) FRSTOR FXRSTOR. FXSAVE MASKMOVQ MOVD MOVDQ2Q MOVNTQ MOVQ MOVQ2DQ PACKSSDW PACKSSWB PACKUSWB PADDB PADDD PADDQ PADDSB PADDSW. PADDUSB. PADDUSW
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PADDW PAND PANDN PAVGB. PAVGUSB PAVGW PCMPEQB PCMPEQD PCMPEQW PCMPGTB PCMPGTD PCMPGTW PEXTRW. PF2ID PF2IW PFACC. PFADD PFCMPEQ PFCMPGE PFCMPGT PFMAX PFMIN PFMUL PFNACC PFPNACC PFRCP PFRCPIT1 PFRCPIT2 PFRSQIT1 PFRSQRT PFSUB PFSUBR PI2FD PI2FW PINSRW PMADDWD PMAXSW PMAXUB PMINSW PMINUB PMOVMSKB PMULHRW. PMULHUW PMULHW PMULLW PMULUDQ POR.
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PSADBW. PSHUFW PSLLD. PSLLQ. PSLLW PSRAD PSRAW PSRLD PSRLQ PSRLW PSUBB PSUBD PSUBQ PSUBSB PSUBSW PSUBUSB PSUBUSW PSUBW PSWAPD PUNPCKHBW PUNPCKHDQ PUNPCKHWD PUNPCKLBW PUNPCKLDQ PUNPCKLWD PXOR
Floating-Point Instruction Reference
F2XM1 FABS FADDx FBLD. FBSTP FCHS. FCLEX (FNCLEX) FCMOVcc FCOMx FCOMIx FCOS. FDECSTP FDIVx FDIVRx. FFREE FICOMx FILD FINCSTP. FINIT
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(FNINIT). FISTx FLD1 FLDCW FLDENV FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ. FMULx FNOP FPATAN FPREM FPREM1 FPTAN FRNDINT FRSTOR FSAVE (FNSAVE) FSCALE FSIN FSINCOS FSQRT FSTP FSTCW (FNSTCW) FSTENV (FNSTENV) FSTSW (FNSTSW) FSUBx. FSUBRx FTST FUCOMx. FUCOMIx FWAIT (WAIT) FXAM FXCH FXRSTOR. FXSAVE FXTRACT FYL2X
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FYL2XP1
Index.
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Figures
Figure 1-1. Diagram Conventions 64-Bit Media Instructions
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Tables
Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 1-7. Table 1-8. Table 1-9. Immediate-Byte Operand Encoding 64-Bit PEXTRW. Numeric Range PF2ID Results Numeric Range PF2IW Results Numeric Range PFACC Results Numeric Range PFADD Results Numeric Range PFCMPEQ Instruction. Numeric Range PFCMPGE Instruction. Numeric Range PFCMPGT Instruction Numeric Range PFMAX Instruction
Table 1-10. Numeric Range PFMIN Instruction Table 1-11. Numeric Range PFMUL Instruction Table 1-12. Numeric Range PFNACC Results Table 1-13. Numeric Range PFPNACC Result (Low Result) Table 1-14. Numeric Range PFPNACC Result (High Result) Table 1-15. Numeric Range PFRCP Result. Table 1-16. Numeric Range PFRCP Result. Table 1-17. Numeric Range PFSUB Results Table 1-18. Numeric Range PFSUBR Results Table 1-19. Immediate-Byte Operand Encoding 64-Bit PINSRW Table 1-20. Immediate-Byte Operand Encoding PSHUFW Table 2-1. Table 2-2. Storing Numbers Integers. Computing Arctangent Numbers
Tables
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Tables
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Revision History
Date September 2003 April 2003 Revision 3.04 Description Clarified condition codes FPREM FPREM1 instructions. Corrected tables numeric ranges results PF2ID PF2IW instructions. Corrected numerous typos stylistic errors. Corrected description FYL2XP1 instruction. Clarified description FXRSTOR instruction.
Chapter
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Preface
About This Book
This book part multivolume work entitled AMD64 Architecture Programmer's Manual. This table lists each volume order number.
Title Volume Application Programming Volume System Programming Volume General-Purpose System Instructions Volume 128-Bit Media Instructions Volume 64-Bit Media Floating-Point Instructions Order 24592 24593 24594 26568 26569
Audience
This volume (Volume intended programmers writing application system software processor that implements x86-64 architecture.
Contact Information
submit questions comments concerning this document, AMD64.Feedback@amd.com.
Organization
Volumes describe AMD64 architecture's instruction detail. Together, they cover each instruction's mnemonic syntax, opcodes, functions, affected flags, possible exceptions. AMD64 instruction divided into five subsets: General-purpose instructions System instructions 128-bit media instructions
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64-bit media instructions floating-point instructions Several instructions belong to-and described identically in-multiple instruction subsets. This volume describes 64-bit media floating-point instructions. index cross-references topics within architecture, information instructions other subsets, tables contents indexes other volumes.
Definitions
Many following definitions assume in-depth knowledge legacy architecture. "Related Documents" page xxvii descriptions legacy architecture. Terms Notation addition notation described below, "Opcode-Syntax Notation" volume describes notation relating specifically opcodes. 1011b binary value-in this example, 4-bit value. F0EAh hexadecimal value-in this example 2-byte value. [1,2) range that includes left-most value this case, excludes right-most value this case, range, from inclusive. high-order shown first. 128-bit media instructions Instructions that 128-bit registers. These combination SSE2 instruction sets. 64-bit media instructions Instructions that 64-bit registers. These Preface
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instruction sets, with some additional instructions from SSE2 instruction sets. 16-bit mode Legacy mode compatibility mode which 16-bit address size active. legacy mode compatibility mode. 32-bit mode Legacy mode compatibility mode which 32-bit address size active. legacy mode compatibility mode. 64-bit mode submode long mode. 64-bit mode, default address size bits features, such register extensions, supported system application software. #GP(0) Notation indicating general-protection exception (#GP) with error code absolute Said displacement that references base code segment rather than instruction pointer. Contrast with relative. biased exponent floating-point value's exponent constant bias particular floating-point data type. bias makes range biased exponent always positive, which allows reciprocation without overflow. byte Eight bits. clear write value Compare set. compatibility mode submode long mode. compatibility mode, default address bits, legacy 16-bit 32-bit applications without modification.
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commit irreversibly write, program order, instruction's result software-visible storage, such register (including flags), data cache, internal write buffer, memory. Current privilege level. CR0-CR4 register range, from register through CR4, inclusive, with low-order register first. CR0.PE Notation indicating that register value direct Referencing memory location whose address included instruction's syntax immediate operand. address absolute relative address. Compare indirect. dirty data Data held processor's caches internal buffers that more recent than copy held main memory. displacement signed value that added base segment (absolute addressing) instruction pointer (relative addressing). Same offset. doubleword words, four bytes, bits. double quadword Eight words, bytes, bits. Also called octword. DS:rSI contents memory location whose segment address register whose offset relative that segment register.
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EFER.LME Notation indicating that EFER register value effective address size address size current instruction after accounting default address size address-size override prefix. effective operand size accounting default operand size operandsize override prefix. element vector. exception abnormal condition that occurs result executing instruction. processor's response exception depends type exception. exceptions except 128-bit media SIMD floating-point exceptions floating-point exceptions, control transferred handler service routine) that exception, defined exception's vector. floating-point exceptions defined IEEE standard, there both masked unmasked responses. When unmasked, exception handler called, when masked, default response provided instead calling handler. Notation indicating that first byte opcode, subfield second byte value flush often ambiguous term meaning writeback, modified, invalidate, "flush cache line," invalidate, "flush pipeline," change value, "flush zero." Global descriptor table. Interrupt descriptor table. Preface
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Ignore. Field ignored. indirect Referencing memory location whose address register other memory location. address absolute relative address. Compare direct. virtual-8086 mode interrupt-redirection bitmap. long-mode interrupt-stack table. real-address mode interrupt-vector table. Local descriptor table. legacy legacy architecture. "Related Documents" page xxvii descriptions legacy architecture. legacy mode operating mode AMD64 architecture which existing 16-bit 32-bit applications operating systems without modification. processor implementation AMD64 architecture either long mode legacy mode. Legacy mode three submodes, real mode, protected mode, virtual-8086 mode. long mode operating mode unique AMD64 architecture. processor implementation AMD64 architecture either long mode legacy mode. Long mode submodes, 64-bit mode compatibility mode. Least-significant bit. Least-significant byte.
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main memory Physical memory, such (but cache memory) that installed particular computer system. mask control that prevents occurrence floatingpoint exception from invoking exception-handling routine. field bits used control purpose. Must zero. software attempts general-protection exception (#GP) occurs. memory Unless otherwise specified, main memory. ModRM byte following instruction opcode that specifies address calculation based mode (Mod), register (R), memory variables. moffset 64-bit offset that specifies memory operand directly, without using ModRM byte. Most-significant bit. Most-significant byte. multimedia instructions combination 128-bit media instructions 64-bit media instructions. octword Same double quadword. offset Same displacement. overflow condition which floating-point number larger magnitude than largest, finite, positive negative
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number that represented data-type format being used. packed vector. Physical-address extensions. physical memory Actual memory, consisting main memory cache. probe check address processor's caches internal buffers. External probes originate outside processor, internal probes originate within processor. protected mode submode legacy mode. quadword Four words, eight bytes, bits. Read zero (0), regardless what written. real-address mode real mode. real mode short name real-address mode, submode legacy mode. relative Referencing with displacement (also called offset) from instruction pointer rather than base code segment. Contrast with absolute. instruction prefix that specifies 64-bit operand size provides access additional registers. RIP-relative addressing Addressing relative 64-bit instruction pointer.
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write value Compare clear. byte following instruction opcode that specifies address calculation based scale (S), index (I), base (B). SIMD Single instruction, multiple data. vector. Streaming SIMD extensions instruction set. 128-bit media instructions 64-bit media instructions. SSE2 Extensions instruction set. 128-bit media instructions 64-bit media instructions. sticky that cleared hardware that remains that state until explicitly changed software. top-of-stack pointer. Task-priority register (CR8). Task-state segment. underflow condition which floating-point number smaller magnitude than smallest nonzero, positive negative number that represented data-type format being used. vector integer floating-point values, called elements, that packed into single operand. Most 128-bit 64-bit media instructions vectors operands. Vectors also called packed SIMD (single-instruction multiple-data) operands.
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index into interrupt descriptor table (IDT), used access exception handlers. Compare exception. virtual-8086 mode submode legacy mode. word bytes, bits. legacy x86. Registers following list registers, names used refer either given register contents that register: AH-DH high 8-bit registers. Compare AL-DL. AL-DL 8-bit registers. Compare AH-DH. AL-r15B 8-bit SIL, DIL, BPL, SPL, R8B-R15B registers, available 64-bit mode. Base pointer register. Control register number Code segment register. eAX-eSP 16-bit registers 32-bit EAX, EBX, ECX, EDX, EDI, ESI, EBP, registers. Compare rAX-rSP. Extended base pointer register. EFER Extended features enable register.
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eFLAGS 16-bit 32-bit flags register. Compare rFLAGS. EFLAGS 32-bit (extended) flags register. 16-bit 32-bit instruction-pointer register. Compare rIP. 32-bit (extended) instruction-pointer register. FLAGS 16-bit flags register. GDTR Global descriptor table register. GPRs General-purpose registers. 16-bit data size, these 32-bit data size, these EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP. 64-bit data size, these include RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8-R15. IDTR Interrupt descriptor table register. 16-bit instruction-pointer register. LDTR Local descriptor table register. Model-specific register. r8-r15 8-bit R8B-R15B registers, 16-bit R8W-R15W registers, 32-bit R8D-R15D registers, 64-bit R8-R15 registers. rAX-rSP 16-bit registers, 32-bit EAX, EBX, ECX, EDX, EDI, ESI, EBP, registers, 64-bit RAX, RBX, RCX, RDX, RDI, RSI, Preface
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RBP, registers. Replace placeholder with nothing 16-bit size, 32-bit size, 64-bit size. 64-bit version register. 64-bit version register. 64-bit version register. 64-bit version register. 64-bit version register. 64-bit version register. rFLAGS 16-bit, 32-bit, 64-bit flags register. Compare RFLAGS. RFLAGS 64-bit flags register. Compare rFLAGS. 16-bit, 32-bit, 64-bit instruction-pointer register. Compare RIP. 64-bit instruction-pointer register. 64-bit version register. 64-bit version register. Stack pointer register. Stack segment register. xxvi Preface
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Task priority register, register introduced AMD64 architecture speed interrupt management. Task register. Endian Order AMD64 architectures address memory using littleendian byte-ordering. Multibyte values stored with their least-significant byte lowest byte address, they illustrated with their least significant byte right side. Strings illustrated reverse order, because addresses their bytes increase from right left.
Related Documents
Peter Abel, Assembly Language Programming, Prentice-Hall, Englewood Cliffs, 1995. Rakesh Agarwal, 80x86 Architecture Programming: Volume Prentice-Hall, Englewood Cliffs, 1991. AMD, AMD-K6MMXEnhanced Processor Multimedia Technology, Sunnyvale, 2000. AMD, 3DNow!Technology Manual, Sunnyvale, 2000. AMD, Extensions 3DNow!and MMXInstruction Sets, Sunnyvale, 2000. Anderson Shanley, Pentium Processor System Architecture, Addison-Wesley, York, 1995. Nabajyoti Barkakati Randall Hyde, Microsoft Macro Assembler Bible, Sams, Carmel, Indiana, 1992. Barry Brey, 8086/8088, 80286, 80386, 80486 Assembly Language Programming, Macmillan Publishing Co., York, 1994. Barry Brey, Programming 80286, 80386, 80486, Pentium Based Personal Computer, Prentice-Hall, Englewood Cliffs, 1995. Ralf Brown Kyle, Interrupts, Addison-Wesley, York, 1994. Penn Brumm Brumm, 80386/80486 Assembly Language Programming, Windcrest McGraw-Hill, 1993. Geoff Chappell, Internals, Addison-Wesley, York, 1994. Preface xxvii
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Chips Technologies, Inc. Super386 Programmer's Reference Manual, Chips Technologies, Inc., Jose, 1992. John Crawford Patrick Gelsinger, Programming 80386, Sybex, Francisco, 1987. Cyrix Corporation, 5x86 Processor BIOS Writer's Guide, Cyrix Corporation, Richardson, 1995. Cyrix Corporation, Processor Data Book, Cyrix Corporation, Richardson, 1996. Cyrix Corporation, Processor Extension Opcode Table, Cyrix Corporation, Richardson, 1996. Cyrix Corporation, Processor Data Book, Cyrix Corporation, Richardson, 1997. Duncan, Extending DOS: Programmer's Guide Protected-Mode DOS, Addison Wesley, 1991. William Giles, Assembly Language Programming Intel 80xxx Family, Macmillan, York, 1991. Frank Gilluwe, Undocumented Addison-Wesley, York, 1994. John Hennessy David Patterson, Computer Architecture, Morgan Kaufmann Publishers, Mateo, 1996. Thom Hogan, Programmer's Sourcebook, Microsoft Press, Redmond, 1991. Katircioglu, Inside 486, Pentium, Pentium Pro, Peer-to-Peer Communications, Menlo Park, 1997. Corporation, 486SLC Microprocessor Data Sheet, Corporation, Essex Junction, 1993. Corporation, 486SLC2 Microprocessor Data Sheet, Corporation, Essex Junction, 1993. Corporation, 80486DX2 Processor Floating Point Instructions, Corporation, Essex Junction, 1995. Corporation, 80486DX2 Processor BIOS Writer's Guide, Corporation, Essex Junction, 1995. Corporation, Blue Lightening 486DX2 Data Book, Corporation, Essex Junction, 1994. Institute Electrical Electronics Engineers, IEEE Standard Binary Floating-Point Arithmetic, ANSI/IEEE 754-1985. xxviii Preface
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Institute Electrical Electronics Engineers, IEEE Standard Radix-Independent Floating-Point Arithmetic, ANSI/IEEE 854-1987. Muhammad Mazidi Janice Gillispie Mazidi, 80X86 Compatible Computers, Prentice-Hall, Englewood Cliffs, 1997. Hans-Peter Messmer, Indispensable Pentium Book, Addison-Wesley, York, 1995. Karen Miller, Assembly Language Introduction Computer Architecture: Using Intel Pentium, Oxford University Press, York, 1999. Stephen Morse, Eric Isaacson, Douglas Albert, 80386/387 Architecture, John Wiley Sons, York, 1987. NexGen Inc., Nx586 Processor Data Book, NexGen Inc., Milpitas, 1993. NexGen Inc., Nx686 Processor Data Book, NexGen Inc., Milpitas, 1994. Bipin Patwardhan, Introduction Streaming SIMD Extensions Pentium III, www.x86.org/articles/sse_pt1/ simd1.htm, June, 2000. Peter Norton, Peter Aitken, Richard Wilton, Programmer's Bible, Microsoft Press, Redmond, 1993. PharLap 386|ASM Reference Manual, Pharlap, Cambridge 1993. PharLap DOS-Extender Reference Manual, Pharlap, Cambridge 1995. Sen-Cuo Sheau-Chuen Her, i386/i486 Advanced Programming, Nostrand Reinhold, York, 1993. Jeffrey Royer, Introduction Protected Mode Programming, course materials onsite class, 1992. Shanley, Protected Mode System Architecture, Addison Wesley, 1996. SGS-Thomson Corporation, 80486DX Processor Programming Manual, SGS-Thomson Corporation, 1995. Walter Triebel, 80386DX Microprocessor, PrenticeHall, Englewood Cliffs, 1992. John Wharton, Complete x86, MicroDesign Resources, Sebastopol, California, 1994. sites newsgroups: Preface xxix
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www.amd.com news.comp.arch news.comp.lang.asm.x86 news.intel.microprocessors news.microsoft
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64-Bit Media Instruction Reference
This chapter describes function, mnemonic syntax, opcodes, affected flags, possible exceptions generated 64-bit media instructions. These instructions operate data located 64-bit registers. Most instructions operate parallel sets packed elements called vectors, although some operate scalars. instructions define both integer floating-point operations, include legacy MMXinstructions, 3DNow!instructions, extensions 3DNow! instruction sets. Each instruction that performs vector (packed) operation illustrated with diagram. Figure page shows conventions used these diagrams. particular diagram shows PSLLW (packed shift left logical words) instruction.
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Arrowheads going source operand indicate writing result. this case, result written first source operand, which also destination operand. First Source Operand (and Destination Operand)
Second Source Operand
mmx1
mmx2/mem64
shift left
shift left
Operation. this case, bitwise shift-left. Arrowheads coming from source operand indicate that source operand provides control function. this case, second source operand specifies number bits shift, first source operand specifies data shifted.
513-324.eps
File name this figure (for documentation control)
Ellipses indicate that operation repeated each element source vectors. this case, there elements each source vector, operation performed times, parallel.
Figure 1-1.
Diagram Conventions 64-Bit Media Instructions Gray areas diagrams indicate unmodified operand bits. Like 128-bit media instructions, many 64-bit instructions independently simultaneously perform single operation multiple elements vector thus instructions. 64-bit media instructions convert operands registers operands GPR, XMM, registers vice versa), save restore state, reset x87state. Hardware support specific 64-bit media instruction depends presence least following CPUID functions: Instructions, indicated CPUID standard function extended function 8000_0001h.
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Extensions Instructions, indicated CPUID extended function 8000_0001h. SSE, indicated CPUID standard function SSE2, indicated CPUID standard function 3DNow! Instructions, indicated CPUID extended function 8000_0001h. Extensions 3DNow! Instructions, indicated CPUID extended function 8000_0001h. FXSAVE FXRSTOR, indicated CPUID standard function extended function 8000_0001h. 64-bit media instructions used legacy mode long mode. Their long mode available following CPUID function set: Long Mode, indicated CPUID extended function 8000_0001h. Compilation 64-bit media programs execution 64-bit mode offers four primary advantages: access eight extended, 64-bit general-purpose registers (for register consisting GPR0-GPR15), access eight extended registers (for register consisting XMM0-XMM15), access 64-bit virtual address space, access RIPrelative addressing mode. further information, see: "64-Bit Media Programming" volume "Summary Registers Data Types" volume "Notation" volume "Instruction Prefixes" volume
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CVTPD2PI
Convert Packed Double-Precision Floating-Point Packed Doubleword Integers
Converts packed double-precision floating-point values register 128-bit memory location packed 32-bit signed integer values writes converted values register.
Mnemonic
Opcode
Description
CVTPD2PI mmx, xmm2/mem128
Converts packed double-precision floating-point values register 128-bit memory location packed doubleword integers values destination register.
xmm/mem128
convert
convert
cvtpd2pi.eps
result conversion inexact value, value rounded specified rounding control bits (RC) MXCSR register. floating-point value NaN, infinity, result conversion larger than maximum signed doubleword (-231 +231 instruction returns 32-bit indefinite integer value (8000_0000h) when invalid-operation exception (IE) masked. Related Instructions CVTDQ2PD, CVTPD2DQ, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI, CVTTSD2SI rFLAGS Affected None
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MXCSR Flags Affected
Note:
flag that zero (modified). Unaffected flags blank.
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception SSE2 instructions supported, indicated CPUID standard function emulate (EM) operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. memory operand aligned 16-byte boundary. page fault resulted from execution instruction. exception pending floating-point instruction. There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details.
Device available, Stack, General protection,
Page fault, floating-point exception pending, SIMD Floating-Point Exception,
CVTPD2PI
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Exception Invalid-operation exception (IE)
Real
Virtual 8086
Protected
Cause Exception source operand SNaN value, QNaN value, ±infinity. source operand large destination format. result could represented exactly destination format.
SIMD Floating-Point Exceptions
Precision exception (PE)
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CVTPI2PD
Convert Packed Doubleword Integers Packed Double-Precision Floating-Point
Converts packed 32-bit signed integer values register 64-bit memory location double-precision floating-point values writes converted values register.
Mnemonic
Opcode
Description
CVTPI2PD xmm, mmx/mem64
Converts packed doubleword integer values register 64-bit memory location packed doubleprecision floating-point values destination register.
mmx/mem64
convert convert
cvtpi2pd.eps
Related Instructions CVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI, CVTTSD2SI rFLAGS Affected None MXCSR Flags Affected None
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Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception SSE2 instructions supported, indicated CPUID standard function emulate (EM) operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. exception pending floating-point instruction. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
CVTPI2PD
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CVTPI2PS
Convert Packed Doubleword Integers Packed Single-Precision Floating-Point
Converts packed 32-bit signed integer values register 64-bit memory location single-precision floating-point values writes converted values low-order bits register. high-order bits register modified.
Mnemonic
Opcode
Description
CVTPI2PS xmm, mmx/mem64
Converts packed doubleword integer values register 64-bit memory location single-precision floating-point values destination register.
mmx/mem64
convert convert
cvtpi2ps.eps
Related Instructions CVTDQ2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI, CVTTSS2SI rFLAGS Affected None
CVTPI2PS
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MXCSR Flags Affected
Note:
flag that zero (modified). Unaffected flags blank.
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception instructions supported, indicated CPUID standard function emulate (EM) operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. exception pending floating-point instruction. unaligned memory reference performed while alignment checking enabled. There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details. result could represented exactly destination format.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check, SIMD Floating-Point Exception,
SIMD Floating-Point Exceptions Precision exception (PE)
CVTPI2PS
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CVTPS2PI
Convert Packed Single-Precision Floating-Point Packed Doubleword Integers
Converts packed single-precision floating-point values low-order bits register 64-bit memory location packed 32-bit signed integers writes converted values register.
Mnemonic
Opcode
Description
CVTPS2PI mmx, xmm/mem64
Converts packed single-precision floating-point values register 64-bit memory location packed doubleword integers destination register.
xmm/mem64
convert
convert
cvtps2pi.eps
result conversion inexact value, value rounded specified rounding control bits (RC) MXCSR register. floating-point value NaN, infinity, result conversion larger than maximum signed doubleword (-231 +231 instruction returns 32-bit indefinite integer value (8000_0000h) when invalid-operation exception (IE) masked. Related Instructions CVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI, CVTTSS2SI rFLAGS Affected None
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MXCSR Flags Affected
Note:
flag that zero (modified). Unaffected flags blank.
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception instructions supported, indicated CPUID standard function emulate (EM) operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. exception pending floating-point instruction. unaligned memory reference performed while alignment checking enabled. There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check, SIMD Floating-Point Exception,
CVTPS2PI
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64-Bit Technology
Exception Invalid-operation exception (IE)
Real
Virtual 8086
Protected
Cause Exception source operand SNaN value, QNaN value, ±infinity. source operand large destination format. result could represented exactly destination format.
SIMD Floating-Point Exceptions
Precision exception (PE)
CVTPS2PI
64-Bit Technology
26569-Rev. 3.04-September 2003
CVTTPD2PI
Convert Packed Double-Precision Floating-Point Packed Doubleword Integers, Truncated
Converts packed double-precision floating-point values register 128-bit memory location packed 32-bit signed integer values writes converted values register.
Mnemonic
Opcode
Description
CVTPD2PI mmx, xmm/mem128
Converts packed double-precision floating-point values register 128-bit memory location packed doubleword integer values destination register. Inexact results truncated.
xmm/mem128
convert
convert
cvttpd2pi.eps
result conversion inexact value, value truncated (rounded toward zero). floating-point value NaN, infinity, result conversion larger than maximum signed doubleword instruction returns 32-bit indefinite integer value (8000_0000h) when invalidoperation exception (IE) masked. Related Instructions CVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTSD2SI rFLAGS Affected None
CVTTPD2PI
26569-Rev. 3.04-September 2003
64-Bit Technology
MXCSR Flags Affected
Note:
flag that zero (modified). Unaffected flags blank.
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception SSE2 instructions supported, indicated CPUID standard function emulate (EM) operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. memory operand aligned 16-byte boundary. page fault resulted from execution instruction. exception pending floating-point instruction. There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details.
Device available, Stack, General protection,
Page fault, floating-point exception pending, SIMD Floating-Point Exception,
CVTTPD2PI
64-Bit Technology
26569-Rev. 3.04-September 2003
Exception Invalid-operation exception (IE)
Real
Virtual 8086
Protected
Cause Exception source operand SNaN value, QNaN value, ±infinity. source operand large destination format. result could represented exactly destination format.
SIMD Floating-Point Exceptions
Precision exception (PE)
CVTTPD2PI
26569-Rev. 3.04-September 2003
64-Bit Technology
CVTTPS2PI
Convert Packed Single-Precision Floating-Point Packed Doubleword Integers, Truncated
Converts packed single-precision floating-point values low-order bits register 64-bit memory location packed 32-bit signed integer values writes converted values register.
Mnemonic
Opcode
Description
CVTTPS2PI xmm/mem64
Converts packed single-precision floating-point values register 64-bit memory location doubleword integer values destination register. Inexact results truncated.
xmm/mem64
convert
convert
cvttps2pi.eps
result conversion inexact value, value truncated (rounded toward zero). floating-point value NaN, infinity, result conversion larger than maximum signed doubleword instruction returns 32-bit indefinite integer value (8000_0000h) when invalidoperation exception (IE) masked. Related Instructions CVTTPS2DQ, CVTTSS2SI rFLAGS Affected None
CVTTPS2PI
64-Bit Technology
26569-Rev. 3.04-September 2003
MXCSR Flags Affected
Note:
flag that zero (modified). Unaffected flags blank.
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception instructions supported, indicated CPUID standard function emulate (EM) operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. exception pending floating-point instruction. unaligned memory reference performed while alignment checking enabled. There unmasked SIMD floating-point exception while CR4.OSXMMEXCPT SIMD Floating-Point Exceptions, below, details.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check, SIMD Floating-Point Exception,
CVTTPS2PI
26569-Rev. 3.04-September 2003
64-Bit Technology
Exception Invalid-operation exception (IE)
Real
Virtual 8086
Protected
Cause Exception source operand SNaN value, QNaN value, ±infinity. source operand large destination format. result could represented exactly destination format.
SIMD Floating-Point Exceptions
Precision exception (PE)
CVTTPS2PI
64-Bit Technology
26569-Rev. 3.04-September 2003
EMMS
Exit Multimedia State
Clears state setting state stack registers empty (tag-bit encoding registers) indicating that contents registers available procedure, such floating-point procedure. This setting bits referred "clearing state". Because registers word shared with floating-point instructions, software should execute EMMS instruction clear state before executing code that includes floating-point instructions. functions EMMS FEMMS instructions identical. details about setting bits, "Media Processor State" volume
Mnemonic
Opcode
Description
EMMS
Clears state.
Related Instructions FEMMS 3DNow! instruction) rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) unmasked floating-point exception pending.
Device available, floating-point exception pending,
EMMS
26569-Rev. 3.04-September 2003
64-Bit Technology
FEMMS
Fast Exit Multimedia State
Clears state setting state stack registers empty (tag-bit encoding registers) indicating that contents registers available procedure, such floating-point procedure. This setting bits referred "clearing state". Because registers word shared with floating-point instructions, software should execute EMMS FEMMS instruction clear state before executing code that includes floating-point instructions. FEMMS 3DNow! instruction. functions FEMMS EMMS instructions identical. FEMMS instruction supported backward-compatibility with certain processors. Software that must both compatible with both non-AMD processors should EMMS instruction. details about setting bits, "Media Processor State" volume
Mnemonic
Opcode
Description
FEMMS
Clears state.
Related Instructions EMMS rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) 3DNow!instructions supported, indicated CPUID extended function 8000_0001h. task-switch (TS) unmasked floating-point exception pending.
Device available, floating-point exception pending,
FEMMS
64-Bit Technology
26569-Rev. 3.04-September 2003
FNSAVE (FSAVE)
Floating-Point Save No-Wait State
Stores complete state memory starting specified address reinitializes state. state requires bytes memory, depending upon whether processor operating real protected mode whether operand-size attribute 16-bit 32-bit. Because registers mapped onto bits floating-point registers, this operation also saves state. details about memory image saved FNSAVE, "Media Processor State" volume FNSAVE instruction does wait pending unmasked floating-point exceptions processed. Processor interrupts should disabled before using this instruction. Assemblers usually provide FSAVE macro that expands into instruction sequence
WAIT FNSAVE destination Opcode Opcode
WAIT (9Bh) instruction checks pending exceptions calls exception handler, necessary. FNSAVE instruction then stores state specified destination.
Mnemonic FNSAVE mem94/108env FSAVE mem94/108env
Opcode
Description Copy state mem94/108env without checking pending floating-point exceptions, then reinitialize state. Copy state mem94/108env after checking pending floating-point exceptions, then reinitialize state.
Related Instructions FRSTOR, FXSAVE, FXRSTOR rFLAGS Affected None
FNSAVE (FSAVE)
26569-Rev. 3.04-September 2003
64-Bit Technology
Condition Code
Condition Code Value Description
Exceptions
Exception Device available, Stack, General protection, Virtual Real 8086 Protected Cause Exception emulate (EM) task switch (TS) control register (CR0) memory address exceeded stack segment limit noncanonical. memory address exceeded data segment limit noncanonical. destination operand nonwritable segment. null data segment used reference memory. page fault resulted from execution instruction. unaligned memory reference performed while alignment checking enabled.
Page fault, Alignment check,
FNSAVE (FSAVE)
64-Bit Technology
26569-Rev. 3.04-September 2003
FRSTOR
Floating-Point Restore MMXState
Restores complete state from memory starting specified address, stored previous call FNSAVE. state occupies bytes memory depending whether processor operating real protected mode whether operand-size attribute 16-bit 32-bit. Because registers mapped onto bits floating-point registers, this operation also restores state. FRSTOR results exception flags loaded status word register, these exceptions unmasked control word register, floating-point exception occurs when next floating-point instruction executed (except no-wait floating-point instructions). avoid generating exceptions when loading environment, FCLEX FNCLEX instruction clear exception flags status word before storing that environment. details about memory image restored FRSTOR, "Media Processor State" volume
Mnemonic FRSTOR mem94/108env
Opcode
Description Load state from mem94/108env.
Related Instructions FSAVE, FNSAVE, FXSAVE, FXRSTOR rFLAGS Affected None
FRSTOR
26569-Rev. 3.04-September 2003
64-Bit Technology
Condition Code
Condition Code Value Loaded from memory. Loaded from memory. Loaded from memory. Loaded from memory. Description
flag cleared (modified). Unaffected flags blank. Undefined flags
Exceptions
Exception Device available, Stack, General protection, Virtual Real 8086 Protected Cause Exception emulate (EM) task switch (TS) control register (CR0) memory address exceeded stack segment limit noncanonical. memory address exceeded data segment limit noncanonical. null data segment used reference memory. page fault resulted from execution instruction. unaligned memory reference performed while alignment checking enabled. unmasked floating-point exception pending.
Page fault, Alignment check, floating-point exception pending,
FRSTOR
64-Bit Technology
26569-Rev. 3.04-September 2003
FXRSTOR
Restore XMM, MMXTM, State
Restores XMM, MMX, state. data loaded from memory state information previously saved using FXSAVE instruction. Restoring data with FXRSTOR that been previously saved with FSAVE (rather than FXSAVE) instruction results incorrect restoration. FXRSTOR results exception flags loaded status word register, these exceptions unmasked control word register, floating-point exception occurs when next floating-point instruction executed (except no-wait floating-point instructions). restored MXCSR register contains exception status flag, corresponding exception mask cleared (indicating unmasked exception), loading MXCSR register does cause SIMD floating-point exception (#XF). FXRSTOR does restore error pointers (last instruction pointer, last data pointer, last opcode), except relatively rare cases which exceptionsummary (ES) status word indicating that unmasked exception occurred. architecture supports memory formats FXRSTOR, 512-byte 32-bit legacy format 512-byte 64-bit format. Selection 32-bit 64-bit format accomplished using corresponding effective operand size FXRSTOR instruction. software running 64-bit mode executes FXRSTOR with 32-bit operand size REX-prefix operand-size override), 32-bit legacy format used. software running 64-bit mode executes FXRSTOR with 64-bit operand size (requires REX-prefix operand-size override), 64-bit format used. details about memory image restored FXRSTOR, "Saving Media Processor State" volume fast-FXSAVE/FXRSTOR (FFXSR) feature enabled EFER, FXRSTOR does restore registers (XMM0-XMM15) when executed 64-bit mode MXCSR restored whether fast-FXSAVE/FXRSTOR enabled not. Software CPUID determine whether fast-FXSAVE/FXRSTOR feature available. (See "CPUID" Volume operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared saved image XMM0-XMM15 MXCSR loaded into processor. general-protection exception occurs there attempt load non-zero value bits MXCSR that defined reserved (bits 31-16).
FXRSTOR
26569-Rev. 3.04-September 2003
64-Bit Technology
Mnemonic
Opcode
Description
FXRSTOR mem512env
Restores XMM, MMXTM, state from 512-byte memory location.
Related Instructions FWAIT, FXSAVE rFLAGS Affected None MXCSR Flags Affected
Note:
flag that zero (modified). Unaffected flags blank. Shaded fields reserved.
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception FXSAVE/FXRSTOR instructions supported, indicated CPUID standard funcion extended function 8000_0001h. emulate (EM) task-switch (TS)
Device available,
FXRSTOR
64-Bit Technology
26569-Rev. 3.04-September 2003
Exception Stack, General protection,
Real
Virtual 8086
Protected
Cause Exception memory address exceeded stack segment limit, non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. memory operand aligned 16-byte boundary. Ones were written reserved bits MXCSR. page fault resulted from execution instruction.
Page fault,
FXRSTOR
26569-Rev. 3.04-September 2003
64-Bit Technology
FXSAVE
Save XMM, MMX, State
Saves XMM, MMX, state. memory location that aligned 16byte boundary causes general-protection exception. Unlike FSAVE FNSAVE, FXSAVE does alter bits. contents saved MMX/x87 data registers retained, thus indicating that registers valid whatever other value bits indicated prior save). invalidate contents MMX/x87 data registers after FXSAVE, software must execute FINIT instruction. Also, FXSAVE (like FNSAVE) does check pending unmasked floating-point exceptions. FWAIT instruction used this purpose. FXSAVE does save pointer registers (last instruction pointer, last data pointer, last opcode), except relatively rare cases which exceptionsummary (ES) status word indicating that unmasked exception occurred. architecture supports memory formats FXSAVE, 512-byte 32-bit legacy format 512-byte 64-bit format. Selection 32-bit 64-bit format accomplished using corresponding effective operand size FXSAVE instruction. software running 64-bit mode executes FXSAVE with 32-bit operand size REX-prefix operand-size override), 32-bit legacy format used. software running 64-bit mode executes FXSAVE with 64-bit operand size (requires REX-prefix operand-size override), 64-bit format used. details about memory image restored FXRSTOR, "Saving Media Processor State" volume fast-FXSAVE/FXRSTOR (FFXSR) feature enabled EFER, FXSAVE does save registers (XMM0-XMM15) when executed 64-bit mode MXCSR saved whether fast-FXSAVE/FXRSTOR enabled not. Software CPUID determine whether fast-FXSAVE/FXRSTOR feature available. (See "CPUID" Volume operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared FXSAVE does save image XMM0-XMM15 MXCSR. details about CR4.OSFXSR bit, "FXSAVE/FXRSTOR Support (OSFXSR) Bit" volume
Mnemonic
Opcode
Description
FXSAVE mem512env
Saves XMM, MMX, state 512-byte memory location.
FXSAVE
64-Bit Technology
26569-Rev. 3.04-September 2003
Related Instructions FINIT, FNSAVE, FRSTOR, FSAVE, FXRSTOR, LDMXCSR, STMXCSR rFLAGS Affected None MXCSR Flags Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception FXSAVE/FXRSTOR instructions supported, indicated CPUID standard function extended function 8000_0001h. emulate (EM) task-switch (TS) memory address exceeded stack segment limit, non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. destination operand non-writable segment. memory operand aligned 16-byte boundary. page fault resulted from execution instruction.
Device available, Stack, General protection,
Page fault,
FXSAVE
26569-Rev. 3.04-September 2003
64-Bit Technology
MASKMOVQ
Masked Move Quadword
Stores bytes from first source operand, selected second source operand, memory location specified DS:rDI registers (except that ignored 64bit mode). first source operand register, second source operand another register. most-significant (msb) each byte second source operand specifies store store, store) corresponding byte first source operand.
Mnemonic
Opcode
Description
MASKMOVQ mmx1, mmx2
Store bytes from register, selected most-significant corresponding byte another register, DS:rDI.
mmx1
mmx2
select
select
store address Memory
DS:rDI
maskmovq.eps
mask value results following behavior: data written memory. Page faults exceptions associated with memory addressing guaranteed generated implementations. Data breakpoints guaranteed generated implementations (although code breakpoints guaranteed).
MASKMOVQ
64-Bit Technology
26569-Rev. 3.04-September 2003
MASKMOVQ implicitly uses weakly-ordered, write-combining buffering data, described "Buffering Combining Memory Writes" volume stored data shared multiple processors, this instruction should used together with fence instruction order ensure data coherency (refer "Cache Management" volume Related Instructions MASKMOVDQU Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared instructions supported, indicated CPUID standard function extensions MMXinstruction supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
MASKMOVQ
26569-Rev. 3.04-September 2003
64-Bit Technology
MOVD
Move Doubleword Quadword
Moves 32-bit 64-bit value following ways: from 32-bit 64-bit general-purpose register memory location loworder bits register, with zero-extension bits from low-order bits 32-bit 64-bit general-purpose register memory location from 32-bit 64-bit general-purpose register memory location loworder bits (with zero-extension bits) full bits register from low-order full bits register 32-bit 64-bit general-purpose register memory location.
Mnemonic
Opcode
Description
MOVD mmx, reg/mem32 MOVD mmx, reg/mem64 MOVD reg/mem32, MOVD reg/mem64,
Move 32-bit value from general-purpose register 32-bit memory location register. Move 64-bit value from general-purpose register 64-bit memory location register. Move 32-bit value from register 32-bit generalpurpose register memory location. Move 64-bit value from register 64-bit generalpurpose register memory location.
following diagrams illustrate operation MOVD instruction.
MOVD
64-Bit Technology
26569-Rev. 3.04-September 2003
reg/mem32
reg/mem64
with prefix
reg/mem32
operations "copy"
reg/mem64
with prefix
reg/mem32
reg/mem64
with prefix
reg/mem32
reg/mem64
with prefix
movd.eps
MOVD
26569-Rev. 3.04-September 2003
64-Bit Technology
Related Instructions MOVDQA, MOVDQU, MOVDQ2Q, MOVQ, MOVQ2DQ rFLAGS Affected None MXCSR Flags Affected None Exceptions (All Modes)
Exception Invalid opcode, Real Virtual 8086 Protected Description MMXinstructions supported, indicated CPUID standard function SSE2 instructions supported, indicated CPUID standard function emulate (EM) instruction used registers while CR4.OSFXSR=0. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. destination operand non-writable segment. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
MOVD
64-Bit Technology
26569-Rev. 3.04-September 2003
MOVDQ2Q
Move Quadword Quadword
Moves low-order 64-bit value register 64-bit register.
Mnemonic
Opcode
Description
MOVDQ2Q mmx,
Moves low-order 64-bit value from register destination register.
copy
movdq2q.eps
Related Instructions MOVD, MOVDQA, MOVDQU, MOVQ, MOVQ2DQ rFLAGS Affected None MXCSR Flags Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) SSE2 instructions supported, indicated CPUID standard function
MOVDQ2Q
26569-Rev. 3.04-September 2003
64-Bit Technology
Exception Device available, General protection, floating-point exception pending,
Real
Virtual 8086
Protected
Cause Exception task-switch (TS) destination operand non-writable segment. unmasked floating-point exception pending.
MOVDQ2Q
64-Bit Technology
26569-Rev. 3.04-September 2003
MOVNTQ
Move Non-Temporal Quadword
Stores 64-bit register value into 64-bit memory location. This instruction indicates processor that data non-temporal, unlikely used again soon. processor treats store write-combining (WC) memory write, which minimizes cache pollution. exact method which cache pollution minimized depends hardware implementation instruction. further information, "Memory Optimization" volume
Mnemonic
Opcode
Description
MOVNTQ mem64,
Stores 64-bit register value into 64-bit memory location, minimizing cache pollution.
mem64
copy
movntq.eps
MOVNTQ weakly-ordered with respect other instructions that operate memory. Software should SFENCE instruction force strong memory ordering MOVNTQ with respect other stores. MOVNTQ implicitly uses weakly-ordered, write-combining buffering data, described "Buffering Combining Memory Writes" volume data that shared multiple processors, this instruction should used together with fence instruction order ensure data coherency (refer "Cache Management" volume Related Instructions MOVNTDQ, MOVNTI, MOVNTPD, MOVNTPS
MOVNTQ
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) instructions supported, indicated CPUID standard function extensions MMXinstruction supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. destination operand non-writable segment. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
MOVNTQ
64-Bit Technology
26569-Rev. 3.04-September 2003
MOVQ
Moves 64-bit value:
Move Quadword
from register 64-bit memory location another register, from register another register 64-bit memory location.
Mnemonic
Opcode
Description
MOVQ mmx1, mmx2/mem64 MOVQ mmx1/mem64, mmx2
Moves 64-bit value from register memory location register. Moves 64-bit value from register register memory location.
mmx1
mmx2/mem64
copy
mmx1/mem64
mmx2
copy
movq-64.eps
Related Instructions MOVD, MOVDQA, MOVDQU, MOVDQ2Q, MOVQ2DQ rFLAGS Affected None
MOVQ
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeds stack segment limit noncanonical. memory address exceeded stack segment limit non-canonical. null data segment used reference memory. destination operand non-writable segment. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
MOVQ
64-Bit Technology
26569-Rev. 3.04-September 2003
MOVQ2DQ
Move Quadword Quadword
Moves 64-bit value from register low-order bits register, with zero-extension bits.
Mnemonic
Opcode
Description
MOVQ2DQ xmm,
Moves 64-bit value from register register.
copy
movq2dq.eps
Related Instructions MOVD, MOVDQA, MOVDQU, MOVDQ2Q, MOVQ rFLAGS Affected None MXCSR Flags Affected None
MOVQ2DQ
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) operating-system FXSAVE/FXRSTOR support (OSFXSR) cleared SSE2 instructions supported, indicated CPUID standard function task-switch (TS) unmasked floating-point exception pending.
Device available, floating-point exception pending,
MOVQ2DQ
64-Bit Technology
26569-Rev. 3.04-September 2003
PACKSSDW
Pack with Saturation Signed Doubleword Word
Converts each 32-bit signed integer first second source operands 16-bit signed integer packs converted values into words destination (first source). first source/destination operand register second source operand another register 64-bit memory location. Converted values from first source operand packed into low-order words destination, converted values from second source operand packed into high-order words destination.
Mnemonic
Opcode
Description
PACKSSDW mmx1, mmx2/mem64
Packs 32-bit signed integers register another register 64-bit memory location into 16-bit signed integers register.
mmx1
mmx2/mem64
convert
convert
convert
convert
packssdw-64.eps
each packed value destination, value larger than largest signed 16-bit integer, saturated 7FFFh, value smaller than smallest signed 16-bit integer, saturated 8000h. Related Instructions PACKSSWB, PACKUSWB
PACKSSDW
26569-Rev. 3.04-September 2003
64-Bit Technology
rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PACKSSDW
64-Bit Technology
26569-Rev. 3.04-September 2003
PACKSSWB
Pack with Saturation Signed Word Byte
Converts each 16-bit signed integer first second source operands 8-bit signed integer packs converted values into bytes destination (first source). first source/destination operand register second source operand another register 64-bit memory location. Converted values from first source operand packed into low-order bytes destination, converted values from second source operand packed into high-order bytes destination.
Mnemonic
Opcode
Description
PACKSSWB mmx1, mmx2/mem64
Packs 16-bit signed integers register another register 64-bit memory location into 8-bit signed integers register.
mmx1
mmx2/mem64
convert
convert
convert
convert
packsswb-64.eps
each packed value destination, value larger than largest signed 8-bit integer, saturated 7Fh, value smaller than smallest signed 8-bit integer, saturated 80h. Related Instructions PACKSSDW, PACKUSWB
PACKSSWB
26569-Rev. 3.04-September 2003
64-Bit Technology
rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PACKSSWB
64-Bit Technology
26569-Rev. 3.04-September 2003
PACKUSWB
Pack with Saturation Signed Word Unsigned Byte
Converts each 16-bit signed integer first second source operands 8-bit unsigned integer packs converted values into bytes destination (first source). first source/destination operand register second source operand another register 64-bit memory location. Converted values from first source operand packed into low-order bytes destination, converted values from second source operand packed into high-order bytes destination.
Mnemonic
Opcode
Description
PACKUSWB mmx1, mmx2/mem64
Packs 16-bit signed integers register another register 64-bit memory location into 8-bit unsigned integers register.
mmx1
mmx2/mem64
convert
convert
convert
convert
packuswb-64.eps
each packed value destination, value larger than largest unsigned 8-bit integer, saturated FFh, value smaller than smallest unsigned 8-bit integer, saturated 00h. Related Instructions PACKSSDW, PACKSSWB
PACKUSWB
26569-Rev. 3.04-September 2003
64-Bit Technology
rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PACKUSWB
64-Bit Technology
26569-Rev. 3.04-September 2003
PADDB
Packed Bytes
Adds each packed 8-bit integer value first source operand corresponding packed 8-bit integer second source operand writes integer result each addition corresponding byte destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PADDB mmx1, mmx2/mem64
Adds packed byte integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
paddb-64.eps
This instruction operates both signed unsigned integers. result overflows, carry ignored (neither overflow carry rFLAGS set), only low-order bits each result written destination. Related Instructions PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW rFLAGS Affected None
PADDB
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PADDB
64-Bit Technology
26569-Rev. 3.04-September 2003
PADDD
Packed Doublewords
Adds each packed 32-bit integer value first source operand corresponding packed 32-bit integer second source operand writes integer result each addition corresponding doubleword destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PADDD mmx1, mmx2/mem64
Adds packed 32-bit integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
paddd-64.eps
This instruction operates both signed unsigned integers. result overflows, carry ignored (neither overflow carry rFLAGS set), only low-order bits each result written destination. Related Instructions PADDB, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW rFLAGS Affected None
PADDD
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PADDD
64-Bit Technology
26569-Rev. 3.04-September 2003
PADDQ
Packed Quadwords
Adds each packed 64-bit integer value first source operand corresponding packed 64-bit integer second source operand writes integer result each addition corresponding quadword destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PADDQ mmx1, mmx2/mem64
Adds 64-bit integer value register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
paddq-64.eps
This instruction operates both signed unsigned integers. result overflows, carry ignored (neither overflow carry rFLAGS set), only low-order bits each result written destination. Related Instructions PADDB, PADDD, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW rFLAGS Affected None
PADDQ
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PADDQ
64-Bit Technology
26569-Rev. 3.04-September 2003
PADDSB
Packed Signed with Saturation Bytes
Adds each packed 8-bit signed integer value first source operand corresponding packed 8-bit signed integer second source operand writes signed integer result each addition corresponding byte destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PADDSB mmx1, mmx2/mem64
Adds packed byte signed integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
saturate saturate
paddsb-64.eps
each packed value destination, value larger than largest representable signed 8-bit integer, saturated 7Fh, value smaller than smallest signed 8-bit integer, saturated 80h. Related Instructions PADDB, PADDD, PADDQ, PADDSW, PADDUSB, PADDUSW, PADDW rFLAGS Affected None
PADDSB
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PADDSB
64-Bit Technology
26569-Rev. 3.04-September 2003
PADDSW
Packed Signed with Saturation Words
Adds each packed 16-bit signed integer value first source operand corresponding packed 16-bit signed integer second source operand writes signed integer result each addition corresponding word destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PADDSW mmx1, mmx2/mem64
Adds packed 16-bit signed integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
saturate saturate
paddsw-64.eps
each packed value destination, value larger than largest representable signed 16-bit integer, saturated 7FFFh, value smaller than smallest signed 16-bit integer, saturated 8000h. Related Instructions PADDB, PADDD, PADDQ, PADDSB, PADDUSB, PADDUSW, PADDW rFLAGS Affected None
PADDSW
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PADDSW
64-Bit Technology
26569-Rev. 3.04-September 2003
PADDUSB
Packed Unsigned with Saturation Bytes
Adds each packed 8-bit unsigned integer value first source operand corresponding packed 8-bit unsigned integer second source operand writes unsigned integer result each addition corresponding byte destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PADDUSB mmx1, mmx2/mem64
Adds packed byte unsigned integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
saturate
saturate
paddusb-64.eps
each packed value destination, value larger than largest unsigned 8-bit integer, saturated FFh, value smaller than smallest unsigned 8-bit integer, saturated 00h. Related Instructions PADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSW, PADDW rFLAGS Affected None
PADDUSB
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PADDUSB
64-Bit Technology
26569-Rev. 3.04-September 2003
PADDUSW
Packed Unsigned with Saturation Words
Adds each packed 16-bit unsigned integer value first source operand corresponding packed 16-bit unsigned integer second source operand writes unsigned integer result each addition corresponding word destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PADDUSW mmx1, mmx2/mem64
Adds packed 16-bit unsigned integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
saturate
saturate
paddusw-64.eps
each packed value destination, value larger than largest unsigned 16-bit integer, saturated FFFFh, value smaller than smallest unsigned 16-bit integer, saturated 0000h. Related Instructions PADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDW rFLAGS Affected None
PADDUSW
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PADDUSW
64-Bit Technology
26569-Rev. 3.04-September 2003
PADDW
Packed Words
Adds each packed 16-bit integer value first source operand corresponding packed 16-bit integer second source operand writes integer result each addition corresponding word destination (second source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PADDW mmx1, mmx2/mem64
Adds packed 16-bit integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
paddw-64.eps
This instruction operates both signed unsigned integers. result overflows, carry ignored (neither overflow carry rFLAGS set), only low-order bits result written destination. Related Instructions PADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW rFLAGS Affected None
PADDW
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PADDW
64-Bit Technology
26569-Rev. 3.04-September 2003
PAND
Packed Logical Bitwise
Performs bitwise logical values first second source operands writes result destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PAND mmx1, mmx2/mem64
Performs bitwise logical values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
pand-64.eps
Related Instructions PANDN, POR, PXOR rFLAGS Affected None
PAND
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PAND
64-Bit Technology
26569-Rev. 3.04-September 2003
PANDN
Packed Logical Bitwise
Performs bitwise logical value second source operand one's complement value first source operand writes result destination (first source). first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PANDN mmx1, mmx2/mem64
Performs bitwise logical values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
invert
pandn-64.eps
Related Instructions PAND, POR, PXOR rFLAGS Affected None
PANDN
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PANDN
64-Bit Technology
26569-Rev. 3.04-September 2003
PAVGB
Packed Average Unsigned Bytes
Computes rounded average each packed unsigned 8-bit integer value first source operand corresponding packed 8-bit unsigned integer second source operand writes each average corresponding byte destination (first source). average computed adding each pair operands, adding 9-bit temporary sum, then right-shifting temporary position. destination source operands register another register 64-bit memory location.
Mnemonic
Opcode
Description
PAVGB mmx1, mmx2/mem64
Averages packed 8-bit unsigned integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
average
average
pavgb-64.eps
Related Instructions PAVGW rFLAGS Affected None
PAVGB
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) instructions supported, indicated CPUID standard function extensions MMXinstruction supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PAVGB
64-Bit Technology
26569-Rev. 3.04-September 2003
PAVGUSB
Packed Average Unsigned Bytes
Computes rounded-up average each packed unsigned 8-bit integer value first source operand corresponding packed 8-bit unsigned integer second source operand writes each average corresponding byte destination (first source). average computed adding each pair operands, adding 9-bit temporary sum, then right-shifting temporary position. first source/destination operand register. second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PAVGUSB mmx1, mmx2/mem64
Averages packed 8-bit unsigned integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
average
average
pavgusb.eps
PAVGUSB instruction performs function identical 64-bit version PAVGB instruction, although instructions have different opcodes. PAVGUSB 3DNow! instruction. useful pixel averaging MPEG-2 motion compensation video scaling operations. Related Instructions None rFLAGS Affected None
PAVGUSB
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) 3DNow!instructions supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PAVGUSB
64-Bit Technology
26569-Rev. 3.04-September 2003
PAVGW
Packed Average Unsigned Words
Computes rounded average each packed unsigned 16-bit integer value first source operand corresponding packed 16-bit unsigned integer second source operand writes each average corresponding word destination (first source). average computed adding each pair operands, adding 17-bit temporary sum, then right-shifting temporary position. first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PAVGW mmx1, mmx2/mem64
Averages packed 16-bit unsigned integer values register another register 64-bit memory location writes result destination register.
mmx1
mmx2/mem64
average
average
pavgw-64.eps
Related Instructions PAVGB rFLAGS Affected None
PAVGW
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) instructions supported, indicated CPUID standard function extensions MMXinstruction supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PAVGW
64-Bit Technology
26569-Rev. 3.04-September 2003
PCMPEQB
Packed Compare Equal Bytes
Compares corresponding packed bytes first second source operands writes result each compare corresponding byte destination (first source). each pair bytes, values equal, result values equal, result first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PCMPEQB mmx1, mmx2/mem64
Compares packed bytes register register 64-bit memory location.
mmx1
mmx2/mem64
compare compare
pcmpeqb-64.eps
Related Instructions PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW rFLAGS Affected None
PCMPEQB
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PCMPEQB
64-Bit Technology
26569-Rev. 3.04-September 2003
PCMPEQD
Packed Compare Equal Doublewords
Compares corresponding packed 32-bit values first second source operands writes result each compare corresponding bits destination (first source). each pair doublewords, values equal, result values equal, result first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PCMPEQD mmx1, mmx2/mem64
Compares packed doublewords register register 64-bit memory location.
mmx1
mmx2/mem64
compare compare
pcmpeqd-64.eps
Related Instructions PCMPEQB, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW rFLAGS Affected None
PCMPEQD
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PCMPEQD
64-Bit Technology
26569-Rev. 3.04-September 2003
PCMPEQW
Packed Compare Equal Words
Compares corresponding packed 16-bit values first second source operands writes result each compare corresponding bits destination (first source). each pair words, values equal, result values equal, result first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PCMPEQW mmx1, mmx2/mem64
Compares packed 16-bit values register register 64-bit memory location.
mmx1
mmx2/mem64
compare compare
pcmpeqw-64.eps
Related Instructions PCMPEQB, PCMPEQD, PCMPGTB, PCMPGTD, PCMPGTW rFLAGS Affected None
PCMPEQW
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PCMPEQW
64-Bit Technology
26569-Rev. 3.04-September 2003
PCMPGTB
Packed Compare Greater Than Signed Bytes
Compares corresponding packed signed bytes first second source operands writes result each compare corresponding byte destination (first source). each pair bytes, value first source operand greater than value second source operand, result value first source operand less than equal value second source operand, result first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PCMPGTB mmx1, mmx2/mem64
Compares packed signed bytes register register 64-bit memory location.
mmx1
mmx2/mem64
compare compare
pcmpgtb-64.eps
Related Instructions PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTD, PCMPGTW rFLAGS Affected None
PCMPGTB
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PCMPGTB
64-Bit Technology
26569-Rev. 3.04-September 2003
PCMPGTD
Packed Compare Greater Than Signed Doublewords
Compares corresponding packed signed 32-bit values first second source operands writes result each compare corresponding bits destination (first source). each pair doublewords, value first source operand greater than value second source operand, result value first source operand less than equal value second source operand, result first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PCMPGTD mmx1, mmx2/mem64
Compares packed signed 32-bit values register register 64-bit memory location.
mmx1
mmx2/mem64
compare compare
pcmpgtd-64.eps
Related Instructions PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTW rFLAGS Affected None
PCMPGTD
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PCMPGTD
64-Bit Technology
26569-Rev. 3.04-September 2003
PCMPGTW
Packed Compare Greater Than Signed Words
Compares corresponding packed signed 16-bit values first second source operands writes result each compare corresponding bits destination (first source). each pair words, value first source operand greater than value second source operand, result value first source operand less than equal value second source operand, result first source/destination operand register second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PCMPGTW mmx1, mmx2/mem64
Compares packed signed 16-bit values register register 64-bit memory location.
mmx1
mmx2/mem64
compare compare
pcmpgtw-64.eps
Related Instructions PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD rFLAGS Affected None
PCMPGTW
26569-Rev. 3.04-September 2003
64-Bit Technology
Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) MMXinstructions supported, indicated CPUID standard function extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PCMPGTW
64-Bit Technology
26569-Rev. 3.04-September 2003
PEXTRW
Extract Packed Word
Extracts 16-bit value from register, selected immediate byte operand shown Table 1-1) writes low-order word 32-bit generalpurpose register, with zero-extension bits.
Mnemonic
Opcode
Description
PEXTRW reg32, mmx, imm8
Extracts 16-bit value from register writes low-order bits general-purpose register.
reg32
imm8
pextrw-64.eps
Table 1-1.
Immediate-Byte Operand Encoding 64-Bit PEXTRW
Value Field Source Bits Extracted 15-0 31-16 47-32 63-48
Immediate-Byte Field
Related Instructions PINSRW
PEXTRW
26569-Rev. 3.04-September 2003
64-Bit Technology
rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) instructions supported, indicated CPUID standard function extensions MMXinstruction supported, indicated CPUID extended function 8000_0001h. task-switch (TS) unmasked floating-point exception pending.
Device available, floating-point exception pending,
PEXTRW
64-Bit Technology
26569-Rev. 3.04-September 2003
PF2ID
Packed Floating-Point Integer Doubleword Converson
Converts packed single-precision floating-point values register 64bit memory location packed 32-bit signed integer values writes converted values another register. result conversion inexact value, value truncated (rounded toward zero). numeric range source destination operands shown Table 1-2.
Mnemonic
Opcode
Description
PF2ID mmx1, mmx2/mem64
Converts packed single-precision floating-point values register memory location doubleword integer value destination register.
mmx1
mmx2/mem64
convert convert
pf2id.eps
Table 1-2.
Numeric Range PF2ID Results
Source Source Destination Round zero (Source Round zero (Source 7FFF_FFFFh 8000_0000h Undefined
Normal, abs(Source Normal, -231 Source Normal, Source Normal, Source Normal, Source -231 Unsupported
PF2ID
26569-Rev. 3.04-September 2003
64-Bit Technology
Related Instructions PF2IW, PI2FD, PI2FW rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) 3DNow!instructions supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory. page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
Device available, Stack, General protection,
Page fault, floating-point exception pending, Alignment check,
PF2ID
64-Bit Technology
26569-Rev. 3.04-September 2003
PF2IW
Packed Floating-Point Integer Word Conversion
Converts packed single-precision floating-point values register 64bit memory location packed 16-bit signed integer values, sign-extended bits, writes converted values another register. result conversion inexact value, value truncated (rounded toward zero). numeric range source destination operands shown Table page Arguments outside range representable signed 16-bit integers saturated largest smallest 16-bit integer, depending their sign.
Mnemonic
Opcode
Description
PF2IW mmx1, mmx2/mem64
Converts packed single-precision floating-point values register memory location word integer values destination register.
mmx1
mmx2/mem64
convert convert
pf2iw.eps
PF2IW
26569-Rev. 3.04-September 2003
64-Bit Technology
Table 1-3.
Numeric Range PF2IW Results
Source Source Destination Round zero (Source Round zero (Source 0000_7FFFh FFFF_8000h Undefined
Normal, abs(Source Normal, -215 Source Normal, Source Normal, Source Normal, Source -215 Unsupported
Related Instructions PF2ID, PI2FD, PI2FW rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) extensions 3DNow!are supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory.
Device available, Stack, General protection,
PF2IW
64-Bit Technology
26569-Rev. 3.04-September 2003
Exception Page fault, floating-point exception pending, Alignment check,
Real
Virtual 8086
Protected
Cause Exception page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
PF2IW
26569-Rev. 3.04-September 2003
64-Bit Technology
PFACC
Packed Floating-Point Accumulate
Adds single-precision floating-point values first source operand adds single-precision values second source operand writes results low-order high-order doubleword, respectively, destination (first source). first source/destination operand register. second source operand another register 64-bit memory location.
Mnemonic
Opcode
Description
PFACC mmx1, mmx2/mem64
Accumulates packed single-precision floating-point values register 64-bit memory location another register writes each result destination register.
mmx1
mmx2/mem64
pfacc.eps
numeric range operands shown Table page
PFACC
64-Bit Technology
26569-Rev. 3.04-September 2003
Table 1-4.
Numeric Range PFACC Results
Source Operand Operand Operand High Operand2 Normal High Operand Normal, Undefined Unsupported High Operand Undefined Undefined
Operand1
Normal Unsupported5
Note:
Least-significant floating-point value first second source operand. Most-significant floating-point value first second source operand. sign result logical signs high operands absolute value infinitely precise result less than 2-126 (but zero), result zero with sign operand (low high) that larger magnitude. infinitely precise result exactly zero, result zero with sign operand. absolute value infinitely precise result greater than equal 2128, result largest normal number with sign operand. "Unsupported" means that exponent ones (1s).
Related Instructions PFADD, PFNACC, PFPNACC rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Device available, Stack, General protection, Virtual 8086 Protected Cause Exception emulate (EM) 3DNow!instructions supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory.
PFACC
26569-Rev. 3.04-September 2003
64-Bit Technology
Exception Page fault, floating-point exception pending, Alignment check,
Real
Virtual 8086
Protected
Cause Exception page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
PFACC
64-Bit Technology
26569-Rev. 3.04-September 2003
PFADD
Packed Floating-Point
Adds each packed single-precision floating-point value first source operand corresponding packed single-precision floating-point value second operand writes result each addition corresponding doubleword destination (first source). first source/destination operand register. second source operand another register 64-bit memory location. numeric range operands shown Table page
Mnemonic
Opcode
Description
PFADD mmx1, mmx2/mem64
Adds packed single-precision floating-point values register 64-bit memory location another register writes each result destination register.
mmx1
mmx2/mem64
pfadd.eps
PFADD
26569-Rev. 3.04-September 2003
64-Bit Technology
Table 1-5.
Numeric Range PFADD Results
Source Operand Most-Significant Doubleword Source Source Normal Source Normal, Undefined Unsupported Source Undefined Undefined
Source Destination
Normal Unsupported3
Note:
sign result logical signs source operands absolute value infinitely precise result less than 2-126 (but zero), result zero with sign source operand that larger magnitude. infinitely precise result exactly zero, result zero with sign source absolute value infinitely precise result greater than equal 2128, result largest normal number with sign source "Unsupported" means that exponent ones (1s).
Related Instructions PFACC, PFNACC, PFPNACC rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) 3DNow!instructions supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory.
Device available, Stack, General protection,
PFADD
64-Bit Technology
26569-Rev. 3.04-September 2003
Exception Page fault, floating-point exception pending, Alignment check,
Real
Virtual 8086
Protected
Cause Exception page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
PFADD
26569-Rev. 3.04-September 2003
64-Bit Technology
PFCMPEQ
Packed Floating-Point Compare Equal
Compares each packed single-precision floating-point values first source operand with corresponding packed single-precision floating-point value second source operand writes result each comparison corresponding doubleword destination (first source). each pair floatingpoint values, values equal, result values equal, result first source/destination operand register. second source operand another register 64-bit memory location. numeric range operands shown Table page 102.
Mnemonic
Opcode
Description
PFCMPEQ mmx1, mmx2/mem64
Compares pairs packed single-precision floating-point values register register 64-bit memory location.
mmx1
mmx2/mem64
compare compare
pfcmpeq.eps
PFCMPEQ
64-Bit Technology
26569-Rev. 3.04-September 2003
Table 1-6.
Numeric Range PFCMPEQ Instruction
Value Source FFFF_FFFFh1 0000_0000h 0000_0000h Normal 0000_0000h 0000_0000h FFFF_FFFFh2 0000_0000h Unsupported 0000_0000h 0000_0000h Undefined
Operand
Source Destination
Normal Unsupported3
Note:
Positive zero equal negative zero. result FFFF_FFFFh source source have identical signs, exponents, mantissas. Otherwise, result 0000_0000h. "Unsupported" means that exponent ones (1s).
Related Instructions PFCMPGE, PFCMPGT rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) 3DNow!instructions supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded data segment limit non-canonical. null data segment used reference memory.
Device available, Stack, General protection,
PFCMPEQ
26569-Rev. 3.04-September 2003
64-Bit Technology
Exception Page fault, floating-point exception pending, Alignment check,
Real
Virtual 8086
Protected
Cause Exception page fault resulted from execution instruction. unmasked floating-point exception pending. unaligned memory reference performed while alignment checking enabled.
PFCMPEQ
64-Bit Technology
26569-Rev. 3.04-September 2003
PFCMPGE
Packed Floating-Point Compare Greater Equal
Compares each packed single-precision floating-point values first source operand with corresponding packed single-precision floating-point value second source operand writes result each comparison corresponding doubleword destination (first source). each pair floatingpoint values, value first source operand greater than equal value second source operand, result value first source operand less than value second source operand, result first source/destination operand register. second source operand another register 64-bit memory location. numeric range operands shown Table page 105.
Mnemonic
Opcode
Description
PFCMPGE mmx1, mmx2/mem64
Compares pairs packed single-precision floating-point values register register 64-bit memory location.
mmx1
mmx2/mem64
compare compare
pfcmpge.eps
PFCMPGE
26569-Rev. 3.04-September 2003
64-Bit Technology
Table 1-7.
Numeric Range PFCMPGE Instruction
Value Source FFFF_FFFFh1 0000_0000h, FFFF_FFFFh3 Undefined Normal 0000_0000h, FFFF_FFFFh2 0000_0000h, FFFF_FFFFh4 Undefined Unsupported Undefined Undefined Undefined
Operand
Source Destination Normal Unsupported5
Note:
Positive zero equal negative zero. result FFFF_FFFFh, source negative. Otherwise, result 0000_0000h. result FFFF_FFFFh, source positive. Otherwise, result 0000_0000h. result FFFF_FFFFh, source positive source negative, they both negative source smaller than equal magnitude source source source both positive source greater than equal magnitude source result 0000_0000h other cases. "Unsupported" means that exponent ones (1s).
Related Instructions PFCMPEQ, PFCMPGT rFLAGS Affected None Exceptions
Exception Invalid opcode, Real Virtual 8086 Protected Cause Exception emulate (EM) 3DNow!instructions supported, indicated CPUID extended function 8000_0001h. task-switch (TS) memory address exceeded stack segment limit non-canonical. memory address exceeded dat
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