POSITIVE PSEUDO (PECL) CLOCK TERMINATION NETWORK Features St

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POSITIVE PSEUDO (PECL) CLOCK TERMINATION NETWORK Features St

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PRN299
POSITIVE PSEUDO (PECL) CLOCK TERMINATION NETWORK
Features
Stable resistor network Reduces power dissipation clock lines Ideal high-speed clock termination Reduces board space 1206 discretes component count more than PECL clock termination
Application Note
High speed microprocessors line Intels Pentium/P6®, Apple PowerPC®, SPARC® other CISC RISC based systems need well-controlled precise clock signals maintain synchronous systems. fast edge rated clock signals will exhibit transmission line effects clock lines resulting undershoots overshoots. integrated PECL termination designed suppress undershoots overshoots clock lines. PECL terminator dissipates very power compared resistor termination network. thin.film networks? PECL termination integrated network fabricated silicon substrate using advanced thin film technology. This will have fixed time constant will create additional skew clock lines. parasitic inductance compared discrete conventional thick film terminators provide effective termination high frequencies.
STANDARD VALUES 46.4
SCHEMATIC DIAGRAM
Pins
STANDARD PART ORDE RING INFORMATION Package Ordering Part Number Style Part Marking
SOT-23
When placing order please specify desired shipping: Tubes Tape Reel.
2000 California Micro Devices Corp. rights reserved. VGA200 trademark California Micro Devices Corp. 3/00
Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
ABSOLUTE MAXIMUM RATINGS Parameter VCC1, VCC2 VCC3 VCC4 supply voltage Temperature: Storage Operating Ambient Package power dissipation +150
PRN299
Unit
Rating -0.5, +6.0 -0.5, VCC1+0.5 -6.0, +6.0 -0.5, VCC2+0.5 -0.5, VCC3+0.5 -0.5, VCC4+0.5
ELECTRICAL OPERATING CHARACTERISTICS (over operating conditions unless specified other wise)
Symbol Parameter Conditions UNIT
CC2, ICC4
CC2, VCC4 supply current
VBIAS
VBIAS open circuit voltage pull-down resistor Input current inputs HSYNC, VSYNC inputs
inputs VCC2 VCC3 VCC4 SYNC inputs VCC4; PWR_UP VCC4; SYNC outputs unloaded VCC4 SYNC inputs 3.0V; PWR_UP VCC4; SYNC outputs unloaded VCC4 PWR_UP input SYNC outputs unloaded external current drawn from VBIAS 71.25 -4mA, VCC4 5.0V 4mA, VCC4 5.0V PWR_UP, VCC3 5.0V VCC2 3.0V VCC1 VCC1 VCC4 VCC4 (VCC2 VDDC_IN) 0.4V; VDDC_OUT= VCC2 (VCC2 VDDC_OUT) 0.4V; VDDC_IN= VCC2 VCC2 2.5V;
VCC4-0.8 78.75 0.15
IOFF
state leakage current, level shifting NFET Voltage drop across level shifting NFET when turned Input capacitance EO_1, EO_2, EO_3
tPLH tPHL VESD
Note Note
VCC1 2.5V; 1.25V; measured 1MHz SYNC drivers propagation delay SYNC drivers propagation delay SYNC drivers output rise fall times withstand voltage2, VCC1 VCC3 VCC4
These parameter applies only HSYNC VSYNC channels. IEC-61000-4-2 International Standard, Level contact discharge method. VCC1, VCC3 VCC4 must bypassed impedance ground plane with 0.2uF, inductance, chip ceramic capacitor each supply pin. pulse applied between applicable pins GND. pulse positive negative with respect GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 DDC_OUT2. other pins protected industry standard Human Body model (MIL-STD-883, Method 3015). This parameter guaranteed design characterization.
Note
©2000 California Micro Devices Corp. rights reserved.
Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3/00
Typical Connection Diagram
PRN299
resistor necessary between VCC3 ground protection against stream pulses required while VGA200 power-down state. value this resistor should chosen such that extra charge deposited into VCC3 bypass capacitor each pulse will discharged before next pulse occurs. maximum repetition rate specified IEC-61000-4-2 standard pulse second. When VGA200 power-up state, internal discharge resistor connected ground switch this purpose. same reason, VCC1 VCC4 also require bypass capacitor discharging resistors ground there other components system provide discharge path ground. GNDA, reference voltage resistors connected internally GNDD should ideally connected ground video
Pins
STANDARD PART ORDE RING INFORMATION Package Ordering Part Number Style Part Marking
QSOP PACVGA200Q
When placing order please specify desired shipping: Tubes Tape Reel.
2000 California Micro Devices Corp. rights reserved. 3/00
Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com

POSITIVE PSEUDO (PECL) CLOCK TERMINATION NETWORK Features St

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