High-Capacity ADPCM Processor This specification describes Bt8110
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Bt8110/8110B
High-Capacity ADPCM Processor
This specification describes Bt8110 Bt8110B multichannel ADPCM processor CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation (ADPCM) encoding decoding. fixed-rate coding algorithms include those specified ANSI Standard T1.303-1989. These algorithms identical those ITU-T Recommendations G.726 G.727. These circuits also implement variable-rate embedded codes specified ANSI Standard T1.310-1991 ITU-T Recommendation G.727. single ADPCM processor integrated circuit provide full-duplex channels ADPCM processing (encoding decoding). some applications, circuits combined provide full-duplex channels. Both A-law µ-law translations provided. Interface options such serial parallel inputs outputs, along with hardware microprocessor control modes, provided integrated circuits. separate ADPCM algorithms available given configuration per-channel basis. Bt8110 requires external lookup table ROM. Bt8110B internal lookup table ROM, external lookup table ROM. When direct framer interface mode, transparent channels Bt8110 will operate kbit/s; Bt8110B operates kbit/s. hardware control, direct framer interface mode been added Bt8110B. more details Bt8110B mode controls, refer Table Table 1-4.
Distinguishing Features
Bt8110B offers internal full-duplex channel capacity channels with processors) 5-bit quantization dynamically selectable channel-by-channel, frame-by-frame basis Transparent channel operation control modes available: microprocessor hardware. Direct framer interface both signal formats Supports optimal RESET function described algorithm standards Supports even-bit inversion A-law inputs outputs (required ITU-T Recommendations G.726, G.727) Minimum throughput delay compatible with Bt8110 per-channel, low-power CMOS
Functional Block Diagram
Applicable Standards
ANSI T1.302-1987 ANSI T1.303-1989 ANSI T1.310-1991 ITU-T G.726, G.727 ANSI T1.501-1994 ANSI T1Y1 Technical Reports
Kbit/s Input
Convert Uniform ENCODER
Input Signal
Difference Signal
Adaptive Quantizer
Signal Estimate Reconstructed Signal
Kbit/s ADPCM Output
Adaptive Predictor
Quantized Difference Signal
Inverse Adaptive Quantizer
Applications
Kbit/s Output
Kbit/s ADPCM Input
Inverse Adaptive Quantizer DECODER
Quantized Difference Signal
Reconstructed Signal Convert
Signal Estimate
Synchronous Coding Adjustment
Adaptive Predictor
T1/E1 Transcoders T1/E1 Multiplexers Personal Communications Systems: Digital European Cordless Telecommunications (DECT), Personal Access Communications System (PACS) Wireless Local Loop Voice PairGain DCME Systems Speech Processing/Recording Voice Mail/Packetization Voice over ATM/Frame Relay
Data Sheet
100060C January 2000
Ordering Information
Model Number Bt8110EPJ Bt8110EPJB Package 68-Pin Plastic Leaded Chip Carrier (PLCC) 68-Pin Plastic Leaded Chip Carrier (PLCC) Ambient Temperature Range
Revision History
Revision Level Advanced December 1996 January 2000 timing diagrams following figures have been updated: Figure 2-3, Figure 2-5, Figure 2-6, Figure 2-7, Figure 2-8, Figure A-2, Figure A-3, Figure A-4. Date Created Description
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Table Contents
List Figures List Tables Product Description
Channel Capacity Configuration Modes 1.1.1 1.1.2 1.1.3 Signal Inputs Outputs Embedded Coding Control Mode
Descriptions
Functional Description
Overview 2.1.1 2.1.2 2.1.3 2.2.1 Clocking Synchronization Microprocessor Interface Address 32-Channel Full-Duplex Interleaved Operation 2.2.1.1 Signal Inputs Outputs 2.2.1.2 Reset Control 64-Channel Encoder-Only Operation 64-Channel Decoder-Only Operation
Modes Operation
2.2.2 2.2.3 2.3.1 2.3.2 2.4.1 2.4.2
Direct Framer Interface Operation 2-11 Framer Interface 2-11 Framer Interface 2-12 Mode Pins 2-14 Control Pins 2-14
Hardware Control 2-13
Registers
0x00-0x3F-Per-Channel Control Registers (per_chan_ctrl) 0x40-Mode Control Register (mode)
100060C
Conexant
Bt8110/8110B
High-Capacity ADPCM Processor
Electrical Mechanical Specifications
Microprocessor Interface Timing 4.1.1 4.1.2 Bt8110 Timing Specifications
Absolute Maximum Ratings Characteristics Mechanical Specifications
Appendix Hardware Mode Operation
64-Channel Full-Duplex Hardware Mode Operation A.1.1 A.1.2 A.1.3 Introduction Configuration Functional Timing
Appendix Speech Compression.
Introduction B.1.1 B.1.2 B.1.3 Configuration Functional Timing Diagram Microprocessor Interface Per-Channel Configuration
Appendix Speech Compression.
Introduction C.1.1 C.1.2 C.1.3 Configuration Functional Timing Diagram Microprocessor Interface Per-Channel Configuration.
Appendix ADPCM Transcoder
Introduction D.1.1 D.1.2 D.1.3 Description Summary ADPCM Transcoder System Specifications
Appendix ADPCM Transcoder
Introduction E.1.1 E.1.2 E.1.3 Description Summary ADPCM Transcoder System Specifications
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
List Figures
List Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 4-1. Figure 4-2. Figure 4-3. Figure A-1. Figure A-2. Figure A-3. Figure A-4. Figure B-1. Figure B-2. Figure C-1. Figure C-2. Figure D-1. Figure D-2. Figure E-1. Figure E-2. Bt8110 Pinout Diagram Bt8110 Logic Diagram. Bt8110B Pinout Diagram. Bt8110B Logic Diagram Bt8110 Block Diagram. Bt8110B Block Diagram Input Output Timing 32-Channel Full-Duplex Interleaved Operation (Microprocessor Control) Input Output Timing 64-Channel Half-Duplex Encoder-Only Operation (Microprocessor Control) Input Output Timing 64-Channel Half-Duplex Decoder-Only Operation (Microprocessor Control) 2-10 Hardware Control Interleaved Timing 2-15 Hardware Control Encoder-Only Timing 2-16 Hardware Control Decoder-Only Timing 2-17 Microprocessor Interface Timing Input Output Signal Timing. 68-Pin Plastic Leaded Chip Carrier (J-Bend) 64-Channel Configuration Bt8110/8110B 64-Channel Full-Duplex Interleaved Mode Functional Timing 128-Channel Half-Duplex Encoder-Only Functional Timing. 128-Channel Half-Duplex Decoder-Only Functional Timing Speech Compression Interface Block Diagram. Speech Compression Functional Timing Diagram Speech Compression Interface Configuration Speech Compression Functional Timing Diagram Single-Board Transcoder Assembly. Single-Board Transcoder Application Single-Board Transcoder Assembly. Single-Board Transcoder Application
100060C
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List Figures
Bt8110/8110B
High-Capacity ADPCM Processor
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
List Tables
List Tables
Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table A-1. Table B-1. Table B-2. Table B-3. Table C-1. Table C-2. Table C-3. Table D-1. Table E-1. ADPCM Operational Modes. Bt8110 Descriptions Bt8110B Descriptions Bt8110/8110B Hardware Signal Definitions 1-10 Signal Connections Parallel Signal Input Parallel Signal Output Bus. Bt8110/8110B Connection Hardware Mode. 2-13 Mode Pins 2-14 Bt8110 Bt8110B with External Lookup Table Bt8110B Internal Lookup Table Interleaved Operation Encoder/Decoder-Only Operation Microprocessor Interface Timing Bt8110/8110B Hardware Mode Timing Input Output Signal Timing. System Clock Frequencies Absolute Maximum Ratings Characteristics. Mode Settings Bt8110/8110B Microprocessor Connection Microcontroller Memory Bt8110/8110B Processor Per-Channel Control Locations Bt8110/8110B Microprocessor Connection Bt8110/8110B Microprocessor Memory Bt8110/B Per-Channel Control Locations ADPCM Transcoder System Specifications ADPCM Transcoder System Specifications
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List Tables
Bt8110/8110B
High-Capacity ADPCM Processor
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Conexant
100060C
Product Description
Adaptive Differential Pulse Code Modulation (ADPCM) algorithm transcoding operation which consists encoding kbit/s Pulse Code Modulation (PCM) kbit/s ADPCM decoding from ADPCM kbit/s PCM. multichannel processor provides transcoding both A-law µ-law codes. coding rate selectable channel-by-channel basis. Bt8110/8110B maximum capacity channels ADPCM operations. configured provide full-duplex channels providing both encoding decoding. also configured provide half-duplex channels providing either encoding decoding. Bt8110/8110B consists VLSI CMOS integrated circuit ROM.
NOTE:
Bt8110, external. Additionally, Bt8110, will provide different ADPCM codes, while will provide different ADPCM codes. (See Table 3-1.). Bt8110B internal used with external ROM. Bt8110B's internal contains different ADPCM codes (see Table 3-2),
Bt8110/8110Bs single configured provide full-duplex channels operation transcoding applications. There control modes Bt8110/8110B: Hardware Microprocessor. hardware mode provides input code selection, transparency selection, algorithm reset, coding per-channel basis. microprocessor mode provided integral interface microprocessor consisting microprocessor, program data memory, desired status indicators.
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Product Description
Channel Capacity Configuration Modes
Bt8110/8110B High-Capacity ADPCM Processor
Channel Capacity Configuration Modes
There four configurations operational mode Bt8110/8110B (see Table 1-1). These configurations established setting three mode control bits ([MODE[2:0]) enable framer [EN_FRMR] Mode Control Register [mode; 0x40], microprocessor mode signal pins hardware mode (AD[2:0] CTRL[0]). Table summarizes configurations input code applied each.
Table 1-1. ADPCM Operational Modes CTRL
NOTE(S):
CTRL
Mode Control
Function
Encoder/Decoder Interleaved(1) Encoder Only Decoder Only Direct Framer Interface
Clock Rate (MHz)
6.144 6.144 6.144 12.352
Channel Capacity
Full-duplex Half-duplex Half-duplex Full-duplex
Clock Rate (MHz)
8.192 8.192 8.192 8.192
Channel Capacity
Full-duplex Half-duplex Half-duplex Full-duplex
Interleaved operation means that Bt8110/8110B alternates between encoder decoder operation consecutive inputs. This requires that inputs outputs interleaved (PCM/ADPCM/PCM, etc.) well. CTRL[1] CTRL[0] available only Bt8110B.
direct framer interface modes Bt8110/8110B connect directly framer providing full-duplex channels encoding. These configurations described detail Appendix
1.1.1 Signal Inputs Outputs
Bt8110/8110B provides both parallel serial inputs outputs. 8-bit parallel inputs selected setting input PSIGEN high. serial input multiplexed encoder/decoder input provide interleaved signals. transfer rate serial input output one-half input clock rate (CLOCK). serial output also multiplexed interleaved encoder/decoder operation. ADPCM inputs outputs appear most significant bits. serial signal input output words bits, with most significant (sign PCM) appearing first. When transparent operation selected given channel either encoder decoder, bits transferred without modification from input both serial parallel outputs.
NOTE:
exception with Bt8110 when parallel interface selected direct T1/E1 framer interface mode; then decoder path PSIG[0] must held logic level.
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Product Description
Channel Capacity Configuration Modes
1.1.2 Embedded Coding
Bt8110/8110B capability provide embedded coding according ANSI Standard T1.310-1991 ITU-T Recommendation G.727. This coding technique allows encoding performed with bits encoding information, decoding done with anywhere from input bits. coding algorithm defined that although coding distortion increases number bits decoder decreases, encoder decoder will remain synchronized. Bt8110/8110B designed that embedded coding enabled code selected. Along with four different standard (non-embedded) ADPCM codes, embedded codes provided with different embedded codes, with eight different standard (non-embedded) codes, provided with ROM. encoder always provides maximum number bits defined code selected. decoder requires ADPCM bits 2-bit encoded input that indicates many bits present decoder input. This input signal applied bits parallel input bus. embedded coding use, bits should connected ground.
1.1.3 Control Mode
Each channel four sets per-channel control inputs. These selecting coding (A-law µ-law), selecting transparent operation, selecting RESET function ADPCM coding algorithm, selecting which codes (six codes ROM) used encoding decoding. microprocessor mode selected setting input MICREN high. microprocessor address different registers. There control register each encoder decoder channel operations mode control register that sets operating mode Bt8110/8110B.
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Product Description
Descriptions
Bt8110/8110B High-Capacity ADPCM Processor
Descriptions
Bt8110 Bt8110B packaged 68-pin Plastic Leaded Chip Carriers (PLCCs). Figures illustrate pinouts Bt8110 Bt8110B, respectively. assignments listed numerical order Table Bt8110, Table Bt8110B. Figures show functionally partitioned logic diagrams Bt8110 Bt8110B. descriptions, names, assignments detailed Table 1-2.
Figure 1-1. Bt8110 Pinout Diagram
AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT AD[3] RESET SYNC MICREN AD[4] AD[5]
PSIGEN PSIG[7] PSIG[6] PSIG[5] PSIG[4] PSIG[3] PSIG[2] PSIG[1] PSIG[0] A[0] A[1] A[2]
Bt8110 ADPCM Processor
A[3] A[4] A[5] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[6] A[7] A[8]
AD[6] PCM_STB ADPCM_STB A[13] AD[12] AD[11] AD[10] A[9]
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Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Table 1-2. Bt8110 Descriptions
Product Description
Descriptions
Label
PSIG[3] PSIG[4] PSIG[5] PSIG[6] PSIG[7] (MSB) PSIGEN AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT AD[3] RESET SYNC MICREN AD[4] AD[5] AD[6] PCM_STB ADPCM_STB
Label
A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[5] A[4] A[3] A[2] A[1] A[0] PSIG[0] PSIG[1] PSIG[2]
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Product Description
Descriptions
Bt8110/8110B High-Capacity ADPCM Processor
Figure 1-2. Bt8110 Logic Diagram
Clock Sync Serial Input Reset
Clock CLOCK Serial SYNC SERIAL_IN Interface RESET PSIGEN PSIG[7] PSIG[6] PSIG[5] PSIG[4] PSIG[3] PSIG[2] PSIG[1] PSIG[0] MICREN AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
ADPCM_STB PCM_STB SERIAL_OUT
ADPCM Strobe Strobe Serial Output
Parallel Signal Enable (MSB) Parallel Signal Parallel Signal Parallel Signal Parallel Signal Parallel Signal Parallel Signal Parallel Signal Parallel Signal Microcontroller Enable Address Latch Enable Chip Select Write* Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Data Data Data Data Data Data Data Data
Parallel Input Interface
Microprocessor Interface A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Address Address Address Address Address Address Address Address Address Address Address Address Address Address
Interface
Test Interface
Parameter Parameter Parameter
Input, Output
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Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Figure 1-3. Bt8110B Pinout Diagram
Product Description
Descriptions
AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT AD[3] RESET SYNC MICREN AD[4] AD[5]
PSIGEN PSIG[7] PSIG[6] PSIG[5] PSIG[4] PSIG[3] PSIG[2] PSIG[1] PSIG[0] A[0] A[1] A[2]
Bt8110B ADPCM Processor
A[3] A[4] A[5] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[6] A[7] A[8]
AD[6] PCM_STB ADPCM_STB A[13] A[12] CTRL[1] CTRL[0] A[11] A[10] A[9]
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Product Description
Descriptions
Bt8110/8110B High-Capacity ADPCM Processor
Table 1-3. Bt8110B Descriptions
Label
PSIG[3] PSIG[4] PSIG[5] PSIG[6] PSIG[7] (MSB) PSIGEN AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT AD[3] RESET SYNC MICREN AD[4] AD[5] AD[6] PCM_STB ADPCM_STB
Label
A[13] A[12] CTRL[1] CTRL[0] A[11] A[10] A[9] A[8] A[7] A[6] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[5] A[4] A[3] A[2] A[1] A[0] PSIG[0] PSIG[1] PSIG[2]
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100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Figure 1-4. Bt8110B Logic Diagram
Product Description
Descriptions
Clock Sync Serial Input Reset
Clock CLOCK Serial SYNC SERIAL_IN Interface RESET PSIGEN PSIG[7] PSIG[6] PSIG[5] PSIG[4] PSIG[3] PSIG[2] PSIG[1] PSIG[0]
ADPCM_STB PCM_STB SERIAL_OUT
ADPCM Strobe Strobe Serial Output
Parallel Signal Enable (MSB) Parallel Signal Parallel Signal Parallel Signal Parallel Signal Parallel Signal Parallel Signal Parallel Signal Parallel Signal
Parallel Interface (ROM Interface)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Data In/PData Data In/PData Data In/PData Data In/PData Data In/PData Data In/PData Data In/PData Data In/PData
Interface
A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
Address Address Address Address Address Address Address Address Address Address Address Address Address Address
Microcontroller Enable Address Latch Enable Chip Select Write* Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Control Inputs Control Inputs
MICREN AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] CTRL[1] CTRL[0]
Microprocessor Hardware Control Interface
Test Interface
Parameter Parameter Parameter
Input, Output
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Product Description
Descriptions
Bt8110/8110B High-Capacity ADPCM Processor
Table 1-4. Bt8110/8110B Hardware Signal Definitions Label
CLOCK
Signal Name
Clock
Definition
system clock provided Bt8110/8110B. Maximum clock frequency 16.5 MHz, must have minimum high periods (duty cycle 16.5 MHz, 8.192 MHz). Provides input output synchronization. Selects algorithm reset function ANSI T1.303-1989 ITU-T G.726. Active when parallel ADPCM inputs outputs enabled interleaved mode, active both inputs ADPCM outputs encoder mode. This disabled decoder mode. Active when parallel inputs outputs enabled interleaved mode, active both ADPCM inputs outputs decoder mode. This disabled encoder mode. This multiplexed ADPCM signals interleaved mode; signals encoder mode, ADPCM signals decoder mode. This multiplexed ADPCM signals interleaved mode; ADPCM signals encoder mode, signals decoder mode. control signal that enables parallel inputs. Does affect parallel outputs (D[7:0]), which always available. Bt8110B, this signal extra functionality (see note Section 2.2.1.1). parallel input data bus. most significant (sign PCM, ADPCM) appears PSIG[7]. This input also used indicate ADPCM word length when embedded decoding performed. When serial inputs used, these inputs should left unconnected (internal pull-down resistors included) except required embedded decoding. Bt8110, these signals inputs, accepting data from external lookup table ROM. data these pins also provides parallel ADPCM output functionality Bt8110. Bt8110B, these signals outputs when internal used. D[7] most significant ADPCM data. Active high input that selects per-channel control microprocessor interface. Active high input that enables write operations Bt8110/8110B. hardware mode this enables transparent operation. Active input that performs write operation Bt8110/8110B. hardware mode this enables A-law coding (low µ-law). microprocessor-generated signal that causes Bt8110/8110B latch address address/data bus. active high with address being latched falling edge signal. hardware mode this becomes optional code input. Microprocessor 7-bit address data bus.
SYNC Clock Serial Interface RESET(1) ADPCM_STB
Synchronization Reset ADPCM Strobe
PCM_STB
Strobe
SERIAL_IN
Serial Data Input
SERIAL_OUT
Serial Data Output
PSIGEN
Parallel Signal Enable
PSIG[7:0] Parallel Interface
Parallel Signal Input
D[7:0]
Parallel Signal Output/ Data Input
MICREN(1) CS(1) Microprocessor Interface
Microprocessor Enable Chip Select
WR*(1)
Write*
ALE(1)
Address Latch Enable.
AD[6:0]
Address/Data
1-10
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100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Table 1-4. Bt8110/8110B Hardware Signal Definitions Label
A[13:0]
Product Description
Descriptions
Signal Name
Address
Definition
Bt8110, these signals ouputs driving address lines external lookup table ROM. Bt8110B, A[7:0] inputs when internal lookup table used. A[13:8] must left open when using Bt8110B with internal lookup table enabled. A[7:0] left open held normal operation when using Bt8110B with internal lookup table enabled. When using Bt8110B with internal lookup table enabled, A[0] A[3] have following functions: A[0] Disable G.726 predictor reset. This function forces output block TONE value A[3] Disable even-bit inversion A-law. This function disables even-bit inversion G.711. Signal A[0] will sampled same input times code select inputs, "disable predict reset" controlled channel-by-channel bases. A[3] timed affects every channel. A[2:0], A[5:4] used allow Bt8110B compatible with pre-Bt8110 designs. A[7:6] factory test pins Bt8110B that must always open held logic level. Bt8110B control inputs provided place GND. CTRL[1] (pin Bt8110, CTRL[0] Bt8110. modes that these control inputs implement are:
Interface CTRL[1,0]
Control Inputs
CTRL[1]
CTRL[0]
high
Mode
Internal only, interleaved, encode only decode only modes Internal only, direct framer interface. This option provides hardware-mode direct framer interface. Bt8110-compatible mode, external required used (production test only)
high high
high
Bt8110-compatible mode, existing ROMS will work. Supply Voltage Supply Ground Seven pins provided supply voltage Bt8110. pins provided Bt8110B. Nine pins provided ground Bt8110. Eight pins provided Bt8110B.
Test Signals
Parameter Parameter Parameter
serial output parameter. Used only factory test purposes should left unconnected. serial output parameter. Used only factory test purposes should left unconnected. serial output parameter. Used only factory test purposes should left unconnected.
NOTE(S):
inputs active high except which adapts type microprocessor being used. Section 2.1.2.
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1-11
Product Description
Descriptions
Bt8110/8110B High-Capacity ADPCM Processor
1-12
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100060C
Functional Description
Overview
Figure Figure illustrate block diagrams Bt8110 Bt8110B, respectively. quantizer reconstruction tables stored external (Bt8110) internal (Bt8110B) that holds fixed parameter values lookup tables specified ADPCM algorithms. Both encoder decoder paths through ADPCM processor provide conversion 64-kbps µ-law A-law channel from 16-, 24-, 32-, 40-kbit/s ADPCM channel. logic arranged serial architecture take full advantage time sharing common circuitry. encoder path, prior conversion input uniform PCM, difference signal obtained subtracting estimate input signal from input signal itself. adaptive 15-, 31-level quantizer 16-level embedded codes) used assign two, three, four, five binary digits, respectively, value difference signal transmission. inverse quantizer produces quantized difference signal from corresponding binary digits. signal estimate added this quantized difference signal produce reconstructed version input signal. Both reconstructed signal quantized difference signal operated upon adaptive predictor that produces estimate input signal, thereby completing feedback loop. decoder path includes structure identical feedback portion encoder, together with uniform µ-law A-law conversion synchronous coding adjustment. synchronous coding adjustment prevents cumulative distortion occurring synchronous tandem codings (ADPCM-PCM-ADPCM. digital connections) under certain conditions. synchronous coding adjustment achieved adjusting output codes manner that eliminates quantizing distortion next ADPCM encoding stage.
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Functional Description
Overview
Bt8110/8110B High-Capacity ADPCM Processor
Figure 2-1. Bt8110 Block Diagram
SYNC SERIAL_IN SERIAL_OUT CLOCK PSIG[7:0] Parallel Processor Quantizer Signal Memory Serial Processor Quantizer Adjustment Memory
ALE, MICREN AD[6:0]
Microprocessor Interface
Predictor Weight Memory
Parallel Signal Output D[7:0] A[13:0] Reconstruction Quantizer Table Memory ADPCM_STB PCM_STB
Memory Control
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Figure 2-2. Bt8110B Block Diagram
SYNC SERIAL_IN SERIAL_OUT CLOCK PSIG[7:0] Parallel Processor Quantizer Signal Memory Serial Processor Quantizer Adjustment Memory
ALE, MICREN AD[6:0]
Microprocessor Interface
Predictor Weight Memory
Reconstruction Quantizer Table Memory
D[7:0]
Parallel Signal Output
Memory Control
ADPCM_STB PCM_STB
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100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Functional Description
Overview
2.1.1 Clocking Synchronization
Each operating mode Bt8110/8110B requires clock synchronization inputs allow proper operation. microprocessor mode used, then synchronization signal frequency submultiple frame kHz). hardware mode used, then synchronization frequency submultiple 1/32 clock frequency; this case synchronization signal used identify consecutive inputs outputs. CLOCK signal must operate frequency 8.192 obtain frame rate signals. This clock gapped have peak rate 16.5 (maximum rate 16.384 used transcoder application). SYNC signal must operate submultiple frame rate. SYNC signal active falling edge; rising edge occur anywhere frame. direct framer interface mode, SYNC signal active rising edge.) SYNC signal synchronizes internal modulo-32 counters internal word counter. falling edge synchronizes counters, this occur submultiple kHz. ADPCM_STB PCM_STB output timing signals that used enable three-state inputs parallel input clock parallel output signals. They each clock cycles. rising edge each signal used clock parallel output data into octal register.
2.1.2 Microprocessor Interface
integral control interface Intel 8051-family microprocessor, Motorola 68HC11-family, equivalent provided. This microprocessor interface allows operation mode per-channel configuration Bt8110/8110B selected directly from software-based system. this interface optional; enabled setting MICREN control input high. When MICREN high, mode per-channel configuration done through microprocessor. microprocessor being used should connected shown Table 2-1. microprocessor interface Bt8110/8110B consists pins: enable (MICREN) address latch enable (ALE), write enable (WR*), chip select (CS), seven multiplexed address/data bits (AD[6:0]). These signals connected shown Table 2-1. microprocessor interface designed allow direct connection Intel 8051-family Motorola 68HC11 microprocessor. chip select input taken from address inputs from address decoding circuit locate Bt8110/8110B within desired memory address range. chip select input Bt8110/8110B allows control multiple circuits from single microprocessor. microprocessor interface write-only. Data read from address space Bt8110/8110B will invalid.
100060C
Conexant
Functional Description
Overview
Bt8110/8110B High-Capacity ADPCM Processor
Table 2-1. Signal Connections Bt8110/8110B
MICREN AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Function
Enable Address Latch Enable Write Enable Chip Select Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
Intel 8051
A[n] AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Motorola 68HC11
A[n] AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
interface Intel 8051 Motorola 68HC11 microprocessors comprises latch enable signal, write enable (8051) enable signal (68HC11), chip select signal (one from port 8051) seven bits 8-bit address/data (port 8051). 68HC11 microprocessor, enable signal connected write enable pin. setup hold times required latch enable write enable signals Other (much faster) processors used long multiplexed address/data feature 8051 supported. Detailed timing requirements microprocessor interface given Section 4.1.
2.1.3 Address
address controller given Register Summary, Table Table 3-4, where both interleaved encoder/decoder operations shown. internal control registers encoders decoders interleaved operation located addresses 0x00-0x3F. write address 0x40 will load Mode Control Register [mode; 0x40].
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Functional Description
Modes Operation
Modes Operation
This section details functional timing clock, synchronization, signal interfaces. data control interfaces include clock synchronization inputs, ADPCM inputs outputs, control inputs select algorithm reset, transparent operation, code type, selected coding algorithm when microprocessor interface selected. 32-channel full-duplex interleaved encoder decoder operation presented first, followed 64-channel encoder-only operation, 64-channel decoder-only operation.
2.2.1 32-Channel Full-Duplex Interleaved Operation
Figure illustrates operation Bt8110/8110B 32-channel full-duplex interleaved mode with microprocessor control. channel numbers parentheses 24-channel full-duplex mode. this diagram, inputs shown changing negative edges input clock, outputs shown changing positive edges. This recommended method operating Bt8110/8110B avoid timing problems. Detailed timing parameters given Chapter 4.0. operate Bt8110/8110B 32-channel full-duplex interleaved mode, Mode Control Register located address 0x40 should value 0x0C channels, 0x04 channels. many 24-channel configurations, gapped clock will used account frame signal; this operates correctly long there exactly clock cycles channel processed.
100060C
Conexant
Functional Description
Modes Operation
Bt8110/8110B High-Capacity ADPCM Processor
Figure 2-3. Input Output Timing 32-Channel Full-Duplex Interleaved Operation (Microprocessor Control)
Ref. Cycle 8.192 (6.144) Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] ADPCM-31 (23) RESET PCM-0 SERIAL_OUT D[7:0] ADPCM-30 (22) D[7:0] ADPCM-30 (22) PCM-29 (21) ADPCM-31 (23) PCM-29 (21) ADPCM-31 (23)
ADPCM-31 (23)
PCM-0 PCM-0 ADPCM-0
ADPCM-0 ADPCM-0
ADPCM-30 (22)
PCM-29 (21)
NOTE(S): Bt8110B only.
100060_008
2.2.1.1 Signal Inputs Outputs
Either serial parallel signal inputs used modes. When PSIGEN input tied high, parallel signal inputs both ADPCM enabled. SERIAL_IN signal contains serial encoder input, sign first, serial ADPCM input. (The ADPCM values preceded with being most significant bit.) input applied rate 4.096 Mbit/s (3.072 Mbit/s 24-channel). timing arranged shown that middle ADPCM coincident with falling edges SYNC. codes less than bits, unused serial input ADPCM bits must zero. PSIG[7:0] signal used signal input when PSIGEN high. also used ADPCM word length indication when embedded decoding performed. Table arrangement input bits bus.
NOTE:
Bt8110B only, latch been added parallel input signal enable, PSIGEN. This signal same input timing parallel input itself. This allows different inputs encoder decoder, respectively, interleaved mode, using serial input idle code insertion under control PSIGEN when normal input parallel mode, vice versa.
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Functional Description
Modes Operation
Bits decoder input used only embedded coding operation where they specify number bits applied decoder input. Unused decoder input bits must
Table 2-2. Parallel Signal Input Input
PSIG[7] PSIG[6] PSIG[5] PSIG[4] PSIG[3] PSIG[2] PSIG[1] PSIG[0]
Encoder
Sign
Decoder
bits, bits bits, bits
PSIGEN low, only PSIG[7:0] inputs used PSIG[2] PSIG[1]. These used inputs embedded decoding. other PSIG inputs should held logic level; these inputs have internal pull-down circuits. Driving these inputs when only serial inputs enabled will induce test modes part that will interfere with proper operation. SERIAL_OUT represents timing serial ADPCM signals shown Figure 2-3. ADPCM output from channel whose signal applied clock cycles previously. output from channel whose ADPCM input applied clock cycles previously. Unused ADPCM output bits D[7:0] outputs output bits used parallel signal outputs indicated time. Table gives arrangement output bits bus.
NOTE:
Bt8110B only, when internal used, bidirect outputs D[7:0] will contain PCM/ADPCM output values, D[7]. Each output word will latched simultaneously with falling edge ADPCM strobe signals. interleaved mode, output timing will appear shown signal D[7:0] Figure 2-3.
delay parallel outputs observed Figure 2-3. When parallel inputs used, ADPCM output encoder operations available clock cycles after input applied. output decoder operations available clock cycles after input applied. When channel control transparent operation, 8-bit output field exactly same 8-bit input field either parallel serial inputs. delay kept same coding operations.
100060C
Conexant
Functional Description
Modes Operation
Bt8110/8110B High-Capacity ADPCM Processor
Table 2-3. Parallel Signal Output Output
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Decoder
Sign
Encoder
2.2.1.2 Reset Control
RESET signal used reset algorithm according ANSI T1.303-1989 ITU-T G.726 when microprocessor operation mode used; reset control [EN_RST; per_chan_ctrl.5] also this function. real-time algorithm reset function useful Digital Circuit Multiplication Equipment (DCME), packet-voice, speech storage applications. RESET input active during time interval shown Figure 2-3.
2.2.2 64-Channel Encoder-Only Operation
Figure shows functional timing 64-channel half-duplex encoder-only operation. channel numbers parentheses 48-channel encoder-only mode. timing generally same interleaved timing, inputs encoding, outputs ADPCM. this mode operation, ADPCM_STB signal occurs once every clock cycles PCM_STB signal active. This keeps ADPCM_STB signal periodic with both inputs outputs when parallel input interface used. operate Bt8110/8110B channel encoder-only mode, Mode Control Register should value 0x0D channels 0x05 channels. many 48-channel configurations, gapped clock will used account frame signal; this operates correctly long there exactly clock cycles channel processed. address table microprocessor per-channel controls (encoder/decoder operation only) given Register Summary, Table 3-4.
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Functional Description
Modes Operation
Figure 2-4. Input Output Timing 64-Channel Half-Duplex Encoder-Only Operation (Microprocessor Control)
Ref. Cycle 8.192 (6.144) Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] PCM-63 (47) RESET PCM-0 SERIAL_OUT D[7:0] ADPCM-60 (44) D[7:0] ADPCM-60 (44) ADPCM-61 (45) ADPCM-62 (46) ADPCM-61 (45) ADPCM-62 (46)
PCM-63 (47)
PCM-0 PCM-0 PCM-1
PCM-1 PCM-1
ADPCM-60 (44)
ADPCM-61 (45)
NOTE(S): Bt8110B only.
100060_009
2.2.3 64-Channel Decoder-Only Operation
Figure shows functional timing 64-channel decoder-only operation. channel numbers parentheses 48-channel mode. Again, timing generally same interleaved timing, inputs ADPCM outputs PCM. Here, PCM_STB active every clock cycles, ADPCM_STB active. operate Bt8110/8110B 64-channel decoder-only, Mode Control Register should value 0x0E channels 0x06 channels. address table microprocessor per-channel controls (encoder/decoder-only operation) same encoder-only operation given Register Summary, Table 3-4.
100060C
Conexant
Functional Description
Modes Operation
Bt8110/8110B High-Capacity ADPCM Processor
Figure 2-5. Input Output Timing 64-Channel Half-Duplex Decoder-Only Operation (Microprocessor Control)
Ref. Cycle 8.192 (6.144) Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] ADPCM-63 (47) RESET ADPCM-0 SERIAL_OUT D[7:0] PCM-58 (42) D[7:0] PCM-58 (42) PCM-59 (43) PCM-60 (44) PCM-59 (43) PCM-60 (44)
ADPCM-63 (47)
ADPCM-0 ADPCM-0 ADPCM-1
ADPCM-1 ADPCM-1
PCM-58 (42)
ADPCM-59 (43)
NOTE(S): Bt8110B only.
100060_010
2-10
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Functional Description
Direct Framer Interface Operation
Direct Framer Interface Operation
direct framer interface operation modes intended voice compression storage applications such voice mail, voice message store forward, voice response. more details, Speech Compression Interface application notes, Appendix this specification.
2.3.1 Framer Interface
this configuration, address 0x40 must value 0x14 properly Bt8110/8110B mode. per-channel control registers given Table must configured appropriate code selection, coding type, transparency. Bt8110 allows only kbit/s data rate transparent mode. Bt8110B operates full kbit/s data rate. full-rate signals serial connected directly SERIAL_IN SERIAL_OUT pins. this application, PSIGEN input must held low, thus enabling parallel interface ADPCM inputs PSIG[7:0] outputs D[7:0]. ADPCM inputs outputs timed signal ADPCM_STB. ADPCM input Bt8110/8110B applied parallel input PSIG[7:3] with most significant PSIG[7]. ADPCM output obtained from Parallel Signal Output D[7:0] with most significant D[7]. Bt8110/8110B interfaces framer, which used transmit receive digital line 1.544 Mbit/s rate. slip buffer framer frame-synchronizes receive signal transmit signal that Bt8110/8110B operate synchronously both signals. ADPCM input data must valid positive edge ADPCM_STB; ADPCM output data valid positive edge. processing delay Bt8110/8110B, there five-channel offset between timing ADPCM input output. ADPCM output always bits (for kbit/s coding embedded codes) less. ADPCM input includes ADPCM input bits bits indicate number bits decoder input when embedded encoding used. Bt8110 only, input PSIG[0], least significant bit, must left open held logic level (this internal pull-down resistor). 6.144 clock obtained internally dividing gapping 12.352 input clock Bt8110. required 12.352 signal source should phase-locked incoming data. complete implementation 48-channel speech compression interface utilizing Conexant Bt8300 Dual T1-Framer Bt8110/8110B detailed Appendix Speech Compression Interface.
100060C
Conexant
2-11
Functional Description
Direct Framer Interface Operation
Bt8110/8110B High-Capacity ADPCM Processor
2.3.2 Framer Interface
this configuration, address 0x40 must value 0x1C properly Bt8110/8110B mode. per-channel control registers given Table must configured appropriate code selection, coding type, transparency. Bt8110 allows only kbit/s data rate transparent mode. Bt8110B operates full kbit/s data rate. full-rate signals serial connected directly SERIAL_IN SERIAL_OUT pins. this application PSIGEN input must held low, thus enabling parallel interface ADPCM inputs PSIG[7:0] outputs D[7:0]. ADPCM inputs outputs timed signal ADPCM_STB. input each Bt8110 applied parallel input PSIG[7:0] with most significant PSIG[7]. output obtained from data D[7:0] with most significant D[7]. Bt8110/8110B interfaces framer which transmits receives digital line 2.048 Mbit/s primary rate. slip buffer framer frame-synchronizes receive signal transmit signal allowing Bt8110/8110B operate synchronously both signals. ADPCM input data must valid positive edge ADPCM_STB; ADPCM output data valid positive edge. processing delay Bt8110/8110B, there five-channel offset between timing ADPCM input output. ADPCM output always bits (for kbit/s coding embedded codes) less. ADPCM input includes ADPCM input bits bits indicate number bits decoder input when embedded encoding used. Bt8110 only, input PSIG[0], least significant bit, must left open held logic level (this internal pull-down resistor). required 8.192 clock source should phased-locked incoming data. complete implementation 60-channel speech compression interface utilizing Bt8510 Framer Bt8110/8110B detailed Appendix Speech Compression Interface.
2-12
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Functional Description
Hardware Control
Hardware Control
Some applications require precise timing modification code selected, transparent operation, coding law. these cases, control signals provided hardware updated each time encoder input ADPCM decoder input applied. Serial parallel inputs used. Table 2-4. defines functions inputs control pins hardware control.
Table 2-4. Bt8110/8110B Connection Hardware Mode Bt8110/8110B
MICREN AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Function
Enable Optional Coding Enable A-Law Enable Transparent Mode Mode Mode 32-Channel Operation Code Code Embedded Coding
Hardware Mode
(CODE[3]) A-LAW TRNSPT MODE[0] MODE[1] MODE[2] CH32 CODE[0] CODE[1] (CODE[2])
NOTE(S): four CODE[n] pins (24, address code locations
when using hardware control mode.
100060C
Conexant
2-13
Functional Description
Hardware Control
Bt8110/8110B High-Capacity ADPCM Processor
2.4.1 Mode Pins
Mode Control (AD[2:0]) Enable 32-Channel Operation (AD[3]) control pins fixed given operational configuration subject timing specifications. Mode control operation pins defined Table 2-5. enable 32-channel operation input high 64-channel operation 48-channel operation.
Table 2-5. Mode Pins AD[2]
NOTE(S):
AD[1]
AD[0]
Source
Interleaved Encoder Decoder Only used pre-Bt8110 design compatibility. Interleaved Processor 48/64(1) Interleaved Processor 48/64(1) Encoder Processor 48/64(1) Encoder Processor 48/64(1) Decoder Processor 48/64(1) Decoder Processor 48/64(1)
Appendix additional information.
2.4.2 Control Pins
Four pins control coding (AD[6:4], ALE), selects coding (WR*), selects transparent operation (CS). Figure illustrates functional timing these inputs. Figure Figure detail encoder-only operation decoder-only operation, respectively. code select input pins have same timing requirement parallel signal inputs PSIGEN. transparent enable A-law enable controls applied clock cycles after reset input clock cycles before coding input. Detailed timing requirements provided Chapter 4.0.
2-14
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Figure 2-6. Hardware Control Interleaved Timing
Ref. Cycle 8.192 (6.144) Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] CODE[1], CODE[0] OPT, RESET PCM-0 SERIAL_OUT D[7:0] ADPCM-30 (22) D[7:0] ADPCM-30 (22) PCM-29 (21) PCM-29 (21)
Functional Description
Hardware Control
ADPCM-31 (23)
PCM-0
ADPCM-0
ADPCM-31 (23)
PCM-0
ADPCM-0
ADPCM-0
ADPCM-30 (22)
PCM-29 (21) ADPCM-31 (23) ADPCM-31 (23)
NOTE(S): Bt8110B only.
100060_011
100060C
Conexant
2-15
Functional Description
Hardware Control
Bt8110/8110B High-Capacity ADPCM Processor
Figure 2-7. Hardware Control Encoder-Only Timing
Ref. Cycle 8.192 (6.144) Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] CODE[1], CODE[0] OPT, RESET PCM-0 SERIAL_OUT D[7:0] ADPCM-60 (44) D[7:0]
PCM-63 (47)
PCM-0
PCM-1
PCM-63 (47)
PCM-0
PCM-1
PCM-1
ADPCM-60 (44)
ADPCM-61 (45) ADPCM-61 (45) ADPCM-61 (45) ADPCM-62 (46) ADPCM-62 (46)
ADPCM-60 (44)
NOTE(S): Bt8110B only.
100060_012
2-16
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Figure 2-8. Hardware Control Decoder-Only Timing
Functional Description
Hardware Control
Ref. Cycle 8.192 (6.144) Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] CODE[1], CODE[0] OPT, RESET
ADPCM-63 (47)
ADPCM-0
ADPCM-1
ADPCM-63 (47)
ADPCM-0
ADPCM-1
ADPCM-0 SERIAL_OUT D[7:0] PCM-58 (42) D[7:0] PCM-58 (42) PCM-59 (43)
ADPCM-1
PCM-58 (42)
ADPCM-59 (43) PCM-60 (44) PCM-59 (43) PCM-60 (44)
NOTE(S): Bt8110B only.
100060_013
100060C
Conexant
2-17
Functional Description
Hardware Control
Bt8110/8110B High-Capacity ADPCM Processor
2-18
Conexant
100060C
Registers
NOTE:
summary registers refer Register Summary section this chapter.
0x00-0x3F-Per-Channel Control Registers (per_chan_ctrl)
Per-channel Control Registers used microprocessor code selection, transparency, algorithm reset, coding type per-channel basis. This capability allows each channel configuration without having generate input control signals hardware each channel. Per-channel control registers write-only. attempt microprocessor read these registers will result erroneous data. Four code select bits (CODE[3:0]) select different codes from ROM. This allows single Bt8110/8110B realize ADPCM coding algorithms contained ANSI standards ITU-T recommendations ADPCM coding. Maximum flexibility achieved with single device ADPCM applications. Specific code assignments depend coding that part Bt8110/8110B set. standard codes that provided kbit/s code ITU-T Recommendation G.726 ANSI Standard T1.303-1989, kbit/s codes given ANSI Standard T1.303-1989, embedded codes ANSI Standard T1.310-1991 ITU-T Recommendation G.727. Only codes embedded codes.
EN_ALAW EN_RST EN_TRPT CODE[3] CODE[2] CODE[1] CODE[0]
EN_ALAW
Enable A-Law Coding-Sets encoder input decoder output coding A-law. this control set, coding µ-law. Enable Reset-Causes algorithm reset input continuously applied long set. This function according ANSI Standard T1.303-1989 useful Digital Circuit Multiplexing Equipment (DCME) functions. Enable Transparent Operation-Uses Bt8110/8110B transfer 8-bit input output without modifications both encoder decoder channels. delay Bt8110/8110B same transparent operation coded (normal) operation. Code Select-Selects among codes contained lookup table. Bt8110 this table provided Conexant ROM, upon request. Each code block 1024 bytes reorganized user, except blocks which reserved.
EN_RST
EN_TRPT
CODE[3:0]
100060C
Conexant
Registers
0x00-0x3F-Per-Channel Control Registers (per_chan_ctrl)
Bt8110/8110B
High-Capacity ADPCM Processor
Table 3-1. Bt8110 Bt8110B with External Lookup Table CODE[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 kbit/s G.726 kbit/s G.726 kbit/s G.726/G.727 kbit/s G.726 Unused Unused Reserved Reserved kbit/s Conexant (data optimized) kbit/s Tellabs kbit/s Alternate (3-level) kbit/s Alternate (4-level) G.727 (5,5)-Embedded Code G.727 (x,4)-Embedded Code G.727 (x,3)-Embedded Code G.727 (x,2)-Embedded Code
Code Table
NOTE(S): Section 4.1.2, Specification Section.
Table 3-2. Bt8110B Internal Lookup Table CODE[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 kbit/s G.726 kbit/s G.726 kbit/s G.726/G.727 kbit/s G.726 kbit/s G.721-1984 (16-level) kbit/s Tellabs kbit/s Alternate (4-level) available kbit/s Conexant (data optimized) available kbit/s Alternate (3-level) kbit/s Alternate (4-level)
Internal Code Table
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Registers
0x40-Mode Control Register (mode)
Table 3-2. Bt8110B Internal Lookup Table CODE[3:0]
1100 1101 1110 1111
Internal Code Table
G.727 (5,5)-Embedded Code G.727 (x,4)-Embedded Code G.727 (x,3)-Embedded Code G.727 (x,2)-Embedded Code
0x40-Mode Control Register (mode)
write address 0x40 will address mode control registers channels. Five bits used control mode operation Bt8110/8110B. This register write-only.
RSVD RSVD EN_FRMR EN_32CH MODE[2] MODE[1] MODE[0]
RSVD EN_FRMR EN_32CH
Reserved-Unused; should logic low. Enable Direct T1/E1 Framer Interface-Set direct connection framer circuit. Enable 32-Channel Operation-Set 32-channel full duplex 64-channel half-duplex operation. set, 24-channel full-duplex 48-channel half-duplex operation obtained. Mode Control-Set values required obtain desired operating mode configuration follows:
Source Interleaved Encoder Decoder Used
MODE[2:0]
100060C
Conexant
Registers
0x40-Mode Control Register (mode)
Bt8110/8110B
High-Capacity ADPCM Processor
Conexant
100060C
100060C
Read/ Write
RSVD RSVD RSVD RSVD RSVD RSVD
Register Summary
Bt8110/8110B
Table 3-3. Interleaved Operation Number
EN_ALAW EN_ALAW EN_ALAW EN_ALAW EN_ALAW EN_ALAW EN_RST EN_TRPT CODE[3] EN_RST EN_TRPT CODE[3] EN_RST EN_TRPT CODE[3] EN_RST EN_TRPT CODE[3] CODE[2] CODE[2] CODE[2] CODE[2]
ADDR (hex)
EN_RST EN_RST EN_TRPT CODE[3] CODE[2] EN_TRPT CODE[3] CODE[2]
Register Label
CODE[1] CODE[1] CODE[1] CODE[1] CODE[1] CODE[1]
CODE[0] CODE[0] CODE[0] CODE[0] CODE[0] CODE[0]
High-Capacity ADPCM Processor
Conexant
RSVD RSVD RSVD EN_ALAW EN_RST RSVD RSVD EN_ALAW EN_RST RSVD EN_ALAW EN_RST RSVD EN_ALAW EN_RST EN_TRPT EN_TRPT EN_TRPT EN_TRPT EN_FRMR
0x3C
CODE[3] CODE[3] CODE[3] CODE[3] EN_32CH
CODE[2] CODE[2] CODE[2] CODE[2] MODE[2]
CODE[1] CODE[1] CODE[1] CODE[1] MODE[1]
CODE[0] CODE[0] CODE[0] CODE[0] MODE[0]
0x3D
0x3E
0x3F
0x40
MODE
Read/ Write
RSVD RSVD RSVD
Table 3-4. Encoder/Decoder-Only Operation Number
EN_ALAW EN_ALAW EN_ALAW EN_RST EN_TRPT CODE[3] CODE[2] EN_RST EN_TRPT CODE[3] CODE[2] CODE[1] CODE[1]
ADDR (hex)
EN_RST EN_TRPT CODE[3] CODE[2] CODE[1]
Register Label
ENC/DEC
CODE[0] CODE[0] CODE[0]
ENC/DEC
ENC/DEC
0x3E RSVD RSVD RSVD EN_FRMR EN_32CH RSVD EN_ALAW EN_RST EN_TRPT CODE[3]
ENC/DEC
RSVD
EN_ALAW
EN_RST
EN_TRPT
CODE[3]
CODE[2] CODE[2] MODE[2]
CODE[1] CODE[1] MODE[1]
CODE[0] CODE[0] MODE[0]
0x3F
ENC/DEC
0x40
MODE
Conexant
High-Capacity ADPCM Processor
Bt8110/8110B
100060C
Electrical Mechanical Specifications
Microprocessor Interface Timing
enable microprocessor interface, MICREN must logic high level. pinouts controller interface connected given Table either 8051 68HC11 controller. Figure illustrates timing requirements microprocessor interface inputs. control active (write) 8051 latches data rising edge control active high (write) 68HC11. appropriate input identified write enable signal. input active high. Address data latched falling edge independent input. write cycle time equal system clock cycles, varies from 16.384 clock 6.144 clock. write cycle time measured from write cycle (rising edge WR*) beginning edge next write cycle.
Table 4-1. Microprocessor Interface Timing Parameter
TADWRH TADRDL TWRW TCLCL TDH(1)
NOTE(S):
Description
Select Write High Select Read Write Pulse Width Address Setup before Address Hold after Write/Read Write Data Stable before Write High Write Data Hold after Write High Write Cycle Time
ns(2)
external address/data capacitance will increase data hold time remains undriven. Time given nominal 8.192 input clock frequency. minimum time allowed should times input clock period. write cycle time measured from write cycle (rising edge WR*) beginning edge next write cycle.
100060C
Conexant
Electrical Mechanical Specifications
Microprocessor Interface Timing
Bt8110/8110B High-Capacity ADPCM Processor
Figure 4-1. Microprocessor Interface Timing
TADWRH TADRDL (8051) (68HC11) TWRW
AD[6:0]
100060_014
TCLCL
4.1.1 Bt8110 Timing
Bt8110/8110B fully static synchronous digital processor. inputs MICREN, PSIGEN, hardware mode AD[3:0] configuration inputs fixed given operating mode. other inputs sampled positive clock transitions. SERIAL_IN D[7:0] inputs sampled every other clock cycle; other inputs sampled every clock cycles. setup hold times data controlled internal circuits Bt8110/8110B allow operation using with hold time. Tables give setup hold times inputs reference clock cycle relative SYNC signal input given channel during hardware mode operation. outputs settle within (TPDmax) corresponding clock positive transition less than logic outputs greater than -0.5 logic high outputs into load (see Figure 4-2).
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Electrical Mechanical Specifications
Microprocessor Interface Timing
Table 4-2. Bt8110/8110B Hardware Mode Timing Signal Name
SYNC SERIAL_IN RESET PSIG[7:0] AD[6] AD[5] AD[4]
Functions
Multiframe SYNC Serial PCM/ADPCM Input Enable Algorithm Reset Enable Transparent Operation Enable A-Law Coding Parallel PCM/ADPCM Input Optional Code Input, CODE[3] Optional Code Input, CODE[2] Optional Code Input, CODE[1] Optional Code Input, CODE[0]
Reference Cycle
Setup Time (TSU)
Hold Time (THD)
Table 4-3. Input Output Signal Timing Parameter
Description
Input Setup Time Input Hold Time Output Setting Time
Figure 4-2. Input Output Signal Timing
Clock Output Signal Input Clock Input Signal
100060_015
100060C
Conexant
Electrical Mechanical Specifications
Microprocessor Interface Timing
Bt8110/8110B High-Capacity ADPCM Processor
4.1.2 Specifications
used part Bt8110/8110B requires access time less than clock cycles. worst-case internal propagation delays total requiring access time less than clock periods. Recommended access times system clock frequencies shown Table 4-4.
Table 4-4. System Clock Frequencies Clock Frequency
6.144 8.192 12.288 16.384
Access Time
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Electrical Mechanical Specifications
Absolute Maximum Ratings
Absolute Maximum Ratings
power consumption proportional internal Bt8110/8110B system clock rate shown Table 4-5; however, power included. Stresses above those listed Absolute Maximum Ratings cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated other sections this document implied. Exposure absolute maximum rating conditions extended periods affect device reliability. This device should handled ESD-sensitive device. Voltage signal that exceeds power supply voltage more than +0.5 induce destructive latchup.
Table 4-5. Absolute Maximum Ratings Parameter
Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Operating Supply Voltage Bt8110: Maximum Current 8.192 (internal clk) Bt8110B: Maximum Current 8.192 (internal clk)
Symbol
VOUT TSTG
Value
-0.5 +7.0 -0.5 +0.5 -0.5 +0.5 +150 +4.75 +5.25
Unit
Volts Volts Volts Volts
100060C
Conexant
Electrical Mechanical Specifications
Characteristics
Bt8110/8110B High-Capacity ADPCM Processor
Characteristics
inputs Table have input thresholds compatible with drive levels. Leakage current each less than state. outputs have drive current outputs CMOS drive levels used with CMOS logic.
Table 4-6. Characteristics Parameter
COUT
Description
Supply Voltage Outputs, AD[6:0] Outputs, AD[6:0] Input Voltage High Input Voltage Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Protection Latch-up Input
Conditions
4.75
5.00
5.25 0.45 1.35
Units
Volts Volts Volts Volts Volts kVolts
Inputs AD[6:0] Outputs MIL-STD-883C, Method 3015 JEDEC JC-40.2 8.192 8.192
3.15
Bt8110: Bt8110B:
Supply Current Supply Current
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Electrical Mechanical Specifications
Mechanical Specifications
Mechanical Specifications
Figure 4-3. 68-Pin Plastic Leaded Chip Carrier (J-Bend)
PLCC
.042" .048" .042" .056" DETAIL
IDENTIFIER
.050" BSC.
INCHES
MILLIMETERS MAX. .200 .130 .995 .958 .465 .995 .958 .465 MIN. 4.20 2.29 25.02 24.13 11.30 25.02 24.13 11.30 20.32 REF. NOM. MAX. 5.08 3.30 25.27 24.33 11.81 25.27 24.33 11.81
.025"/.045"
MIN. .165 .090 .985 .950 .445 .985 .950 .445
NOM.
.026" .032"
.800 REF.
20.32 REF.
.013" .021" .020" MIN.
.800 REF.
DETAIL
100060_016
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Conexant
Electrical Mechanical Specifications
Mechanical Specifications
Bt8110/8110B High-Capacity ADPCM Processor
Conexant
100060C
Appendix Hardware Mode Operation
64-Channel Full-Duplex Hardware Mode Operation
A.1.1 Introduction
This appendix details Bt8110/8110B ADPCM Processor 64-channel operation. This configuration used conjunction with Bt8200 ADPCM Line Formatter build ADPCM transcoder. interface nomenclature Figure corresponds that used with transcoder evaluation boards (Bt8200EVM-T1 Bt8200EVM-E1). Appendix Bt8110/8110B 32-channel processors (combined with single external Bt8110) will process either full-duplex channels using interleaved encoder/decoder processing. This combination also programmed alternately process encode-only decode-only channels.
A.1.2 Configuration
block diagram showing configuration Bt8110/8110B 64-channel operation shown Figure A-1. Bt8110/8110Bs share input output signals external appear external interfaces single functional device, each takes turns reading obtain required outputs.
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Conexant
Appendix Hardware Mode Operation
64-Channel Full-Duplex Hardware Mode Operation
Bt8110/8110B
High-Capacity ADPCM Processor
Figure A-1. 64-Channel Configuration Bt8110/8110B
CLOCK SYNC CHANNEL SERIAL_IN CNTRL CODE12 CODE13
CLOCK SYNC AD[3] SERIAL_IN RESET, AD[4] AD[5] D[7:0] ADPCM Processor Bt8110/8110B SERIAL_OUT A[13:0] SERIAL_OUT
External CLOCK SYNC CHANNEL SERIAL_IN CNTRL CODE12 CODE13 CLOCK SYNC AD[3] SERIAL_IN RESET, AD[4] AD[5] D[7:0]
ADPCM Processor Bt8110/8110B A[13:0] SERIAL_OUT
100060_017
Bt8110/8110Bs need have three mode control pins enable interleaved, encoder, decoder modes; processor number. interleaved mode, circuit will realize full-duplex channels ADPCM coding. encoder mode, encoders realized. decoder mode, decoders realized. modes, inputs AD[2], AD[1], AD[0] need shown Table A-1.
Table A-1. Mode Settings Name
Interleaved Mode Encoder Mode Decoder Mode
Processor Number AD[2] AD[1] AD[0]
Processor Number AD[2] AD[1] AD[0]
Processor Number Processor Number must designated such because, this configuration, each Bt8110/8110B responds alternate groups clock cycles (12.288 16.384 MHz). Number Number designation arbitrary influenced other part circuitry.
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Appendix Hardware Mode Operation
64-Channel Full-Duplex Hardware Mode Operation
addition, MICREN PSIGEN must held serial inputs used. However, Bt8110/8110B parallel signal input capability. PSIGEN connected supply voltage, parallel signal input enabled. Note that CNTRL input connected both RESET inputs (pins 22). RESET input controls algorithm reset function according ANSI Standard T1.303-1989/ITU-T G.7.26 input controls transparency (the passthrough 8-bit input without encoding decoding).
A.1.3 Functional Timing
Functional timing diagrams given Figure through Figure interleaved operation, encoder-only operation, decoder-only operation, respectively. CLOCK signal frequency 16.384 64-channel full-duplex 128-channel half-duplex operation, 12.288 48-channel 96-channel half-duplex operation. SYNC signal used identify channel required multiple clock periods. Details timing given Chapter 4.0. each mode, channels numbered. numbers parentheses 48-channel full-duplex operation 96-channel half-duplex (encoder- decoder-only) operation.
Figure A-2. 64-Channel Full-Duplex Interleaved Mode Functional Timing
Ref. Cycle 16.384 (12.288) CLOCK SYNC ADPCM_STB PCM_STB 8.192 (6.144) Mbit/s SERIAL_IN PSIG[7:0] ADPCM-63 (47) RESET,CS PCM-0 SERIAL_OUT D[7:0] ADPCM-62 (46) D[7:0] ADPCM-62 (46) PCM-61 (45) ADPCM-63 (47) PCM-61 (45) ADPCM-63 (47)
ADPCM-63 (47)
PCM-0 PCM-0 ADPCM-0
ADPCM-0 ADPCM-0
ADPCM-62 (46)
PCM-61 (45)
NOTE(S): Bt8110B only.
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Conexant
Appendix Hardware Mode Operation
64-Channel Full-Duplex Hardware Mode Operation
Bt8110/8110B
High-Capacity ADPCM Processor
Figure A-3. 128-Channel Half-Duplex Encoder-Only Functional Timing
Ref. Cycle 16.384 (12.288) CLOCK SYNC ADPCM_STB PCM_STB 8.192 (6.144) Mbit/s SERIAL_IN PSIG[7:0] PCM-127 (95) RESET,CS PCM-0 SERIAL_OUT D[7:0] ADPCM-124 (92) D[7:0] ADPCM-124 (92) ADPCM-125 (93) ADPCM-126 (94) ADPCM-125 (93) ADPCM-126 (94)
PCM-127 (95)
PCM-0
PCM-1
PCM-0 PCM-1
PCM-1
ADPCM-124 (92)
ADPCM-125 (93)
NOTE(S): Bt8110B only.
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Conexant
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Bt8110/8110B
High-Capacity ADPCM Processor
Appendix Hardware Mode Operation
64-Channel Full-Duplex Hardware Mode Operation
Figure A-4. 128-Channel Half-Duplex Decoder-Only Functional Timing
Ref. Cycle 16.384 (12.288) CLOCK SYNC ADPCM_STB
PCM_STB 8.192 (6.144) Mbit/s SERIAL_IN PSIG[7:0] ADPCM-127 (95) RESET,CS ADPCM-0 SERIAL_OUT D[7:0] PCM-122 (90) D[7:0] PCM-122 (90) PCM-123 (91) PCM-124 (92) PCM-123 (91) PCM-124 (92)
ADPCM-127 (95)
ADPCM-0 ADPCM-0 ADPCM-1
ADPCM-1 ADPCM-1
PCM-122 (90)
ADPCM-123 (91)
NOTE(S): Bt8110B only.
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Conexant
Appendix Hardware Mode Operation
64-Channel Full-Duplex Hardware Mode Operation
Bt8110/8110B
High-Capacity ADPCM Processor
Conexant
100060C
Appendix Speech Compression
Introduction
This appendix details operation Bt8110/8110B ADPCM Processor with Bt8300 Dual Framer application speech compression. This operation mode used provide full-duplex speech compression kbit/s using variety embedded non-embedded codes. Bt8110/8110B provides coding algorithms specified ITU-T Recommendation G.726 ANSI Standard T1.303-1989 kbit/s. also provides embedded codes ANSI Standard T1.310-1991 ITU-T Recommendation G.727. kbit/s ADPCM algorithm also specified AMIS version digital messaging protocol. speech compression application channels uses Bt8300 with associated RAM; Bt8110/8110Bs, (each with associated Bt8110); microprocessor configuration control. separate coding algorithms selected microprocessor. evaluation board available this configuration (part number Bt8113EVM). Although this application note Bt8113EVM both Bt8300 Dual Framer (with external RAM), Bt8360 Single Framers (with internal RAM) used with Bt8110/8110Bs voice channels, respectively. Bt8360 newer generation product offers more voiceand signaling-related features than Bt8300. even higher level integration functionality, Bt8370 framer with integral used.
B.1.1 Configuration
configuration Bt8110/8110B Bt8300 shown Figure B-1. Bt8300 used transmit receive lines. slip buffers Bt8300 used synchronize transmit receive signals both Bt8110/8110B.
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Conexant
Appendix Speech Compression
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
Figure B-1. Speech Compression Interface Block Diagram
ADPCM Processor Bt8110/8110B CLOCK PSIG[7:0] SYNC PSIGEN SERIAL_IN 1.544 SYNC SYNC SLIP BUFF SLIP BUFF SERIAL_OUT D[7:0] PSIG[0] ADPCM_STB PCM_STB
12.352 Oscillator
PSIG (ADPCM Input)
(ADPCM Output)
Dual Framer Bt8300
ADPCM Processor Bt8110/8110B CLOCK SYNC SERIAL_IN SERIAL_OUT PSIG[7:0] PSIGEN PSIG[0] D[7:0] PSIG (ADPCM Input) ADPCM_STB PCM_STB
Microprocessor
(ADPCM Output)
100060_021
single microprocessor used control Bt8300 Bt8110/8110Bs. only requirement Bt8110/8110B control configure operating mode per-channel control registers that code rate A-law/µ-law, reset algorithm each channel, desired. 12.352 signal source required Bt8300 also used Bt8110 clock. maintain proper synchronization Bt8110/8110B, exact 12.352 source that eight times slip-buffer clock rate (which same transmit clock) must used. This source phase-locked received clocks from line local clock source. slip-buffer clock transmit clock side framer then obtained from 1.544 clock output from Bt8300. 12.352 clock source locked line, then encoder buffer will have frame slips where sample either repeated deleted before encoding ADPCM. speech signals, this impairment insignificant. full-rate inputs outputs Bt8110/8110B serial configured connect directly Bt8300. SERIAL_IN SERIAL_OUT signals Bt8110/8110B connect directly slip buffer output transmit input framer, respectively. frame synchronization determined SYNC input, which obtained from
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Appendix Speech Compression
Introduction
free-running synchronization signal SYNC Bt8300 (this signal must also connected SYNC synchronize side transmitter). Bt8110/8110B clock 6.144 obtained internally dividing gapping 12.352 input clock Bt8110/8110B. ADPCM inputs outputs timed signal ADPCM_STB. This signal will identical both Bt8110/8110Bs. input each applied parallel input PSIG[7:0], with most significant PSIG[7]. output obtained from parallel signal output D[7:0], with most significant D[7]. input data must valid positive edge ADPCM_STB output data valid positive edge. processing delay Bt8110/8110B, there five-channel offset between timing ADPCM input output. ADPCM output always bits less (for kbit/s coding embedded codes). ADPCM input includes ADPCM input bits bits indicate number bits decoder input when embedded encoding used. MICREN input must connected supply voltage enable microprocessor interface. PSIGEN must held low. RESET input used reset algorithm externally, should held low; otherwise should generated. RESET input active high.
B.1.2 Functional Timing Diagram
timing speech compression interface circuit given Figure B-2. clock signal 12.352 applied Bt8300 both Bt8110/8110Bs. SYNC signal Bt8110/8110B multiframe synchronization output Bt8300. This signal provides channel synchronization Bt8110/8110Bs. SYNC signal period timing diagram shows beginning frame period. ADPCM_STB signal enable clock output Bt8110/8110Bs. positive edge occurs when ADPCM input clocked into circuit ADPCM output available from data pins. frame-bit location identified from wide interval this signal, which occurs once frame. serial input output timing determined Bt8300 synchronization. parts designed that long clocks synchronization signals provided shown Figure B-1, serial interface will operate properly. Each signals clocked respective input circuitry near middle signaling interval, interconnection circuitry critical. This makes possible, instance, drop-and-insert other processing functions interface.
NOTE:
ADPCM inputs taken from parallel input PSIG[7:0] Bt8110B, PSIG[7:1] Bt8110. outputs available data output D[7:0] Bt8110B, D[7:1] Bt8110. Note that encoding provided timeslots that normally carry framing signaling information.
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Conexant
Appendix Speech Compression
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
There offset timing between input output signals caused processing delay Bt8110/8110B. Figure B-2, ADPCM-3 encoded output from PCM-3 ADPCM-22 results decoded PCM-22. This offset must accounted processing speech signals eliminated delaying encoded output channel counts. RESET input used reset ADPCM algorithm according ANSI Standard T1.303-1989 ITU-T G.726, timing shown Figure B-2. Note that RESET input applied approximately before corresponding ADPCM input; possible PCM_STB signal latch reset inputs ADPCM signal stream ADPCM_STB signal latch reset inputs input stream. 48-channel designs, helpful have single interleaved parallel bus. signal PCM_STB, which also output from each Bt8110/8110B, used clock inputs outputs single parallel bus.
Figure B-2. Speech Compression Functional Timing Diagram
12.352 CLOCK 6.176 INT. SYNC ADPCM_STB 1.544 Mbit/s SERIAL_IN 1.544 Mbit/s SERIAL_OUT PSIG[7:0] ADPCM-3 D[7:0] ADPCM-22 PCM_STB RESET PCM-1 D[7:0] ADPCM-22 PCM-1 ADPCM-23 PCM-2 ADPCM-24 ADPCM-4 PCM-2 ADPCM-5 PCM-3 PCM-1 ADPCM-23 PCM-2 ADPCM-24 ADPCM-4 ADPCM-5
PCM-24
PCM-1
PCM-2
PCM-24
PCM-1
PCM-2
NOTE(S): Bt8110B only.
100060_022
Conexant
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Bt8110/8110B
High-Capacity ADPCM Processor
Appendix Speech Compression
Introduction
B.1.3 Microprocessor Interface Per-Channel Configuration
microprocessor interface Bt8300 provides control status functions lines; also used insert extract signaling this application. Table lists connections Bt8110/8110B. Only bits address/data required. Bt8110/8110B operated either 8051-type 68HC11-type interface. Only 8051-type connections given here, since Bt8300 requires this interface. 68HC11 microprocessor used well; gates required derive read write control signals needed emulate 8051. Bt8360 Framer Bt8370 T1/E1 Framer/LIU interface directly with either 8051-type 68HC11-type microprocessor.
Table B-1. Bt8110/8110B Microprocessor Connection ADPCM Processor
MICREN AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Function
Enable Address Latch Enable Write Enable Chip Select Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
Intel 8051
AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Table lists address interpretations control fields. this application address 0x40 must value 0x14 properly mode Bt8110/8110B. write address range 0x40-0x3F will cause mode Bt8110/8110B set. Table also provides per-channel control register interpretations. Bits D[3:0] each encoder decoder channel control select particular ADPCM code used; note that values invalid these positions. codes available from Conexant with evaluation board. D[6] enables A-law coding when set. D[5] enables algorithm RESET function. This operation sets internal parameters Bt8110/8110B fixed values, specified ANSI Standard T1.303-1989 ITU-T G.726. D[4] enables transparent operation. encoder channels, when transparent bits transferred output with same delay when ADPCM encoding taking place. Full 8-bit kbit/s) transparent operation valid option speech compression interface configuration using Bt8110/8110B. kbit/s transparent operation valid with Bt8110/8110BB. decoder, five ADPCM inputs embedded encoding inputs transferred
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Conexant
Appendix Speech Compression
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
serial output with same delay when ADPCM decoding taking place. input PSIG[0], LSB, must held logic level this application.
Table B-2. Microcontroller Memory Address (hex)
Interleaved Operation 0x3E 0x3F 0x40 Encoder/Decoder-Only Operation 0x3E 0x3F 0x40
Function
Encoder Control Decoder Control Encoder Control Encoder Control Decoder Control Mode Control Encoder/Decoder Control Encoder/Decoder Control Encoder/Decoder Control Encoder/Decoder Control Encoder/Decoder Control Mode Control
Mode Control Register D[2:0] D[3] D[4]
Function
Operation Mode 32/64-Channel Operation Serial PCM, Parallel ADPCM Mode
Encoder/Decoder Control Register
D[3:0] D[4} D[5] D[6]
Code Select (codes invalid) Encoder/Decoder Transparent Reset Encoder/Decoder Encoder/Decoder A-Law
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Appendix Speech Compression
Introduction
Table shows encoder decoder locations each channel. This table cross-reference between encoder decoder addresses channel timeslots.
Table B-3. Bt8110/8110B Processor Per-Channel Control Locations Channel
Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel
Encoder
Decoder
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Conexant
Appendix Speech Compression
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
Conexant
100060C
Appendix Speech Compression
Introduction
This appendix details operation Bt8110/8110B ADPCM Processor with Bt8510 Framer/LIU Bt8370 T1/E1 Framer/LIU) application speech compression. This mode used provide full-duplex speech compression kbit/s using number embedded non-embedded codes. Bt8110/8110B provides coding algorithms specified ITU-T Recommendation G.726 ANSI Standard T1.303-1989 kbit/s. also provides embedded codes ITU-T Recommendation G.727 ANSI Standard T1.310-1991. kbit/s ADPCM algorithm also used AMIS version digital messaging protocol. speech compression application channels requires Bt8510 Framer circuit, Bt8110/8110B (with associated Bt8110), microprocessor configuration control. separate coding algorithms selected controller channel-by-channel basis. This application requires approximately square inches approximately Watts power from supply.
C.1.1 Configuration
Figure illustrates configuration Bt8110/8110B Bt8510. Bt8510 transmits receives digital line 2.048 Mbit/s primary rate. slip buffer Bt8510 frame-synchronizes receive signal transmit signal that Bt8110/8110B operate synchronously both signals. single microprocessor used control Bt8510 Bt8110/8110B. only control requirement microprocessor configure operating mode per-channel control registers that code rate reset algorithm each channel, desired. Bt8510 Bt8110/8110B each have chip select input that used select desired device. Bt8510 includes integral digital timing recovery circuit analog interface that compatible with either cable twisted-pair wire meets requirements ITU-T Recommendation G.703. timing recovery circuit requires 32.768 clock signal. Bt8510 provides 16.384 output which divided provide 8.192 clock required Bt8110/8110B also provided system clock input.
100060C
Conexant
Appendix Speech Compression
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
2.048 clock then provided BITCKO. This clock used clock input both transmitter circuit slip buffer circuit. This procedure ensures proper alignment Bt8110/8110B system clocks.
Figure C-1. Speech Compression Interface Configuration
32.768 VCXO
CK160 SYSCKI SLPSYNCI XYSNCO SLPPCMO Framer Bt8510 XPCMI BITCKO XCKI SLPCKI XSYNCI
CLOCK
PSIG[7:0]
ADPCM_Input ADPCM_STB PCM_STB
SYNC SERIAL_IN SERIAL_OUT A[13:0]
ADPCM Processor Bt8110/B
MICREN RESET PSIGEN PSIG[0]
D[7:0]
(ADPCM Output)
Microprocessor
100060_023
32.768 signal source then phase-locked received clock phase-locking slip buffer sync output receive sync output) then transmit receive clocks will synchronized frame slips will appear receiver. full-rate inputs outputs Bt8110/8110B serial configured connect directly Bt8510. SERIAL_IN SERIAL_OUT signals Bt8110/8110B connect directly slip buffer output transmit input framer, respectively. Bt8110/8110B frame synchronization determined SYNC input, which obtained from free-running synchronization signal XSYNCO from Bt8510 (this signal must also connected SLPSYNCI synchronize receive slip buffer). ADPCM inputs outputs timed signal ADPCM_STB. input Bt8110/8110B applied parallel input PSIG[7:0], with most significant PSIG[7]. output obtained from data D[7:0], with most significant D[7]. input data must valid positive edge ADPCM_STB output data valid positive edge. processing delay Bt8110/8110B, there five-channel offset between timing ADPCM input output. ADPCM output always bits (for kbit/s coding embedded codes) less. input includes ADPCM input bits bits indicate number bits decoder input when embedded encoding used.
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Appendix Speech Compression
Introduction
MICREN input must connected supply voltage enable microprocessor interface. PSIGEN must held logic level. RESET input used reset algorithm externally, should connected ground shown Figure C-1; otherwise should generated. RESET input active high.
C.1.2 Functional Timing Diagram
Figure illustrates timing Bt8110/8110B circuit. CLOCK signal 8.192 applied Bt8110/8110B. SYNC signal Bt8110/8110B multiframe synchronization output Bt8510. This signal provides channel synchronization Bt8110/8110B. SYNC signal period timing diagram shows beginning frame period. ADPCM_STB signal enable clock output Bt8110/8110B. positive edge occurs when ADPCM input clocked into circuit ADPCM output available from data pins. serial input output timing determined Bt8510 synchronization. parts designed that long clocks synchronization signals provided shown Figure C-1, serial interface will operate properly. Each signals clocked respective input circuitry near middle signaling interval, interconnection circuitry critical. This makes possible drop-and-insert other processing functions serial interface.
NOTE:
ADPCM inputs taken from parallel input PSIG[7:0] Bt8110B, PSIG[7:1] Bt8110. outputs available data output D[7:0] Bt8110B, D[7:1] Bt8110. Note that encoding provided timeslots that normally carry framing signaling information.
There offset timing between input output signals caused processing delay Bt8110/8110B. Figure C-2, ADPCM-3 encoded output from PCM-3 ADPCM-30 results decoded PCM-30. This offset must accounted processing speech signals, eliminated delaying encoded output channel counts. RESET input used reset ADPCM algorithm according ANSI Standard T1.303-1989 ITU-T G.726, timing shown Figure C-2. Note that RESET input applied approximately before corresponding ADPCM input; possible PCM_STB signal latch reset inputs ADPCM signal stream ADPCM_STB signal latch reset inputs input stream.
100060C
Conexant
Appendix Speech Compression
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
Figure C-2. Speech Compression Functional Timing Diagram
8.192 CLOCK SYNC ADPCM_STB 2.048 Mbit/s SERIAL_IN 2.048 Mbit/s SERIAL_OUT PSIG[7:0], CODE[1,0], OPT, D[7:0] ADPCM-29 PCM_STB RESET PCM-0 D[7:0] ADPCM-29 PCM-0 ADPCM-30 PCM-1 ADPCM-31 ADPCM-3 PCM-1 ADPCM-4 PCM-2 PCM-0 ADPCM-30 PCM-1 ADPCM-31
PCM-31 (Frame
PCM-0 (Frame
PCM-1
PCM-31
PCM-0
PCM-1
ADPCM-2
ADPCM-3
ADPCM-4
NOTE(S): Bt8110B only.
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Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Appendix Speech Compression
Introduction
C.1.3 Microprocessor Interface Per-Channel Configuration
microprocessor interface Bt8510 provides control status functions lines; also used insert extract signaling this application. connections Bt8110/8110B given Table C-1. Only bits address/data required. upper address bits, A[13:8], microprocessor used chip select signal. Bt8110/8110B operated either 8051-type 68HC11-type interface. Only 8051-type connections given Table C-1. 68HC11, signal must connected signal ALE. other connections same.
Table C-1. Bt8110/8110B Microprocessor Connection ADPCM Processor
MICREN AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Function
Enable Address Latch Enable Write Enable Chip Select Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
Intel 8051
A[n] AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Table gives address interpretations control fields. this application address 0x40 must value 0x1C properly mode Bt8110/8110B. write address 0x40 will cause mode Bt8110/8110B set. least must allowed between consecutive write operations Bt8110/8110B. Table also provides Per-Channel Control Register interpretations. Bits D[3:0] each encoder decoder channel control select particular ADPCM code used; note that values invalid these positions. codes available from Conexant. D[6] enables A-law coding when D[5] enables algorithm RESET function when This operation sets internal parameters Bt8110/8110B fixed values, specified ITU-T Recommendation G.726 ANSI Standard T1.303. D[4] enables transparent operation when encoder channels, when transparent set, bits transferred output with same delay when ADPCM decoding taking place. decoder, five ADPCM inputs embedded-encoding inputs transferred serial output with same delay when ADPCM decoding taking place. Bt8110 only, input PSIG[0], least significant bit, must held logic level this application (this internal pull-down resistor).
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Conexant
Appendix Speech Compression
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
Table C-2. Bt8110/8110B Microprocessor Memory Address
Interleaved Operation 0x3E 0x3F 0x40 Encoder/Decoder-Only Operation 0x3E 0x3F 0x40
Function
Encoder Control Decoder Control Encoder Control Encoder Control Decoder Control Mode Control Encoder/Decoder Control Encoder/Decoder Control Encoder/Decoder Control Encoder/Decoder Control Encoder/Decoder Control Mode Control
Mode Control Register D[2:0] D[3] D[4] D[3:0] D[4] D[5] D[6]
Function
Operation Mode: speed, Interleaved 32/64-Channel Operation: Serial PCM, Parallel ADPCM Mode: Code Select (codes invalid) Encoder/Decoder Transparent Reset Encoder/Decoder Encoder/Decoder A-Law
Encoder/Decoder Control Register
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Appendix Speech Compression
Introduction
Table gives encoder decoder locations each channel control word. This table cross-reference between encoder decoder addresses channel timeslots.
Table C-3. Bt8110/B Per-Channel Control Locations Timeslot
Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot Timeslot
Encoder
Decoder
100060C
Conexant
Appendix Speech Compression
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
Conexant
100060C
Appendix ADPCM Transcoder
Introduction
This appendix describes assembly Bt8110/B ADPCM Processor, Bt8200 ADPCM Line Formatter, Bt8300 (dual), Bt8360 (single) Clear-Channel Framers, Bt8370 T1/E1 Framer/LIU that realizes single-board transcoder meeting interface requirements given ANSI Standard T1.302-1989. evaluation board available this configuration (Bt8200EVM-T1). T1.302-1989 line format standard kbit/s ADPCM compression voice-band signals. specifies three signaling methods transcoders: Bundle Format-Provides voice-band channels along with four signaling alarm overhead channels. Transition Signaling-Provides channels with kbit/s ADPCM allows switching ADPCM DS0s systems network managers thus compatible with fractional services. Robbed-Bit Signaling-Provides channels with kbit/s with kbit/s used every sixth frame provide bandwidth signaling bits. T1.303-1989/G.726 specifies 24-kbit/s ADPCM algorithm used signaling frames.
D.1.1 Description
transcoder meeting requirements these standards providing option three methods signaling developed with three Conexant products: Bt8110/B, Bt8200, Bt8300 Bt8360 Bt8370 place Bt8300). Bt8110/Bs provide transcoding channels; code rate adjusted from kbit/s kbit/s channel-by-channel, frame-by-frame basis. Bt8200 buffers synchronizes transcoded ADPCM signals obtain required line formats translates signaling bits required. Three framers used. framers synchronize (PCM) ports; third framer provides frame synchronization frame generation interface that carries compressed voice channels kbit/s.
100060C
Conexant
Appendix ADPCM Transcoder
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
Figure shows transcoder assembly. Circuit elements required include microprocessor; 12.352 timing oscillator that synchronized signals synchronized externally; line interface units, used generate recover pulses from lines; optional RS-232C interface supervisory data link.
Figure D-1. Single-Board Transcoder Assembly
UART Link
RS-232C
Microcontroller
Bt8300 Bt8360s, Bt8370s) PORT Dual Framer PORT
Bt8200 PORT
Bt8300 Bt8360, Bt8370) Framer
ADPCM Line Formatter
ADPCM Processors Bt8110/B
100060_025
microprocessor sets configuration transcoder monitors status alarm indications. also send receive messages data links, required. Optional status (LED) indicators also microprocessor. UART link RS-232C interface used transfer supervisory signaling from Bt8200 ports, idle transparent (uncoded data) channels, provide optional templates bundle transmission AT&T 54070 Bellcore TR-TSY-000210. ADPCM processor consists 68-pin PLCC integrated circuits (and Bt8110). Bt8300 consists 84-pin PLCC external RAM; Bt8360 68-pin PLCC with internal RAM; Bt8370 80-pin PLCC with internal integral LIU; Bt8200 consists 84-pin PLCC integrated circuit external RAM. microprocessor provided several different configurations, typically Intel 8051-family part program memory used. Only supply required; power consumption assembly totals less than Watts. entire transcoder approximately square inches (194 square centimeters) circuit-board area, allowing development single-board wall-mount unit. compact size power consumption also permits development built-in units channel banks customer-premise multiplexers. evaluation board transcoder configuration available. This board uses Bt8110/Bs, Bt8200, three Bt8360s. microprocessor programmed obtain maintenance status information, template configurations, perform diagnostic tests Bt8110/Bs.
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Appendix ADPCM Transcoder
Introduction
D.1.2 Summary
transcoder assembly used double voice-channel capacity line, shown Figure D-2. full-rate come from systems, channel banks, PBXs, other stream signal sources. ADPCM transcoder used interface AT&T's multiplexing service when bundle format used. When transition signaling used, channels provided. Also, transition signaling compatible with fractional services. software listing program used Bt8200EVM-T1 available upon request.
Figure D-2. Single-Board Transcoder Application
Transcoder Transcoder
100060_026
Kbit/s ADPCM
100060C
Conexant
Appendix ADPCM Transcoder
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
D.1.3 ADPCM Transcoder System Specifications
Table D-1. ADPCM Transcoder System Specifications Name
Channel Capacity ADPCM Coding channels, full-duplex. ANSI Standard T1.303-1989 ITU-T G.726 kbit/s bundle format transition signaling kbit/s kbit/s robbed-bit signaling. Both ANSI standard proprietary robbed-bit signaling algorithms supported. Bundle format transition signaling ANSI Standard T1.302-1989 kbit/s (bundle) basis. Robbed-bit signaling ANSI Standard T1.302.1989. ESF, SLC® options T1s. ZBTSI and/or B8ZS selected processor control auto-selected based far-end format. Both bit-oriented message-oriented signaling supported ports. built-in kbit/s serial port data link integral microprocessor. outputs synchronized received external timing reference. bundle, transition signaling alarms available microprocessor. Indicators provided required. Looping each available microprocessor control. channels selected transparent kbit/s boundaries. This allows transmission digital data increments kbit/s. Full-time in-service diagnostic test ADPCM coding processor channels using idle channel channel used bundle delta channel. Storage configuration data during power outage nonvolatile EEROM memory. Per-channel optional insertion selectable code signaling states idle channels. 0-250 ports. Less Watts system Approximately (12.7 20.3 cm).
Description
Signaling Modes
Framing Clear Channel Data Link Configuration Control Synchronization Alarms Self-Test Transparent Channels
Diagnostic Test
Program Storage Idle Channel Control Slip Buffer Power Requirement Board Dimensions
Conexant
100060C
Appendix ADPCM Transcoder
Introduction
This appendix describes assembly Bt8110/B ADPCM Processor, Bt8200 ADPCM Line Formatter, Bt8510 Framer Bt8370 T1/E1 Frame/LIU that realizes single-board transcoder meeting transcoding requirements ITU-T Recommendation G.726 interface requirements given ITU-T Recommendation G.761. evaluation board available this configuration (Bt8200EVM-E1). G.726 transcoding algorithm between kbit/s kbit/s ADPCM. G.761 line format kbit/s ADPCM compression voice-band signals 2.048 Mbit/s primary-rate digital streams. Signaling conversion from full-rate source streams compressed digital stream specified G.761 well. This signaling conversion requires processing signaling history with scrambling algorithm ensure that multiframe alignment signal emulation occur compressed stream.
E.1.1 Description
Bt8200EVM-E1 transcoder meeting requirements G.761 developed with three Conexant products: Bt8110/B, Bt8200, Bt8510. Bt8110/B ADPCM processors provide transcoding channels. Bt8200 ADPCM Line Formatters buffer synchronize encoded decoded ADPCM signals, respectively, obtain required line formats. Three Bt8510 Framers used, each full-rate ports compressed port. Figure shows transcoder assembly. Circuit elements required include microprocessor; 16.384 timing oscillators that synchronized signals synchronized externally; optional RS-232C interface supervisory data link. encoder decoder operate with separate time bases; normally decoder synchronized incoming clock port meet synchronization requirements G.761. microprocessor sets configuration transcoder monitors status alarm indications. Optional status (LED) indicators also microprocessor. UART link RS-232C interface used transfer supervisory signaling from Bt8200 ports, idle transparent (uncoded data) channels, provide signaling conversion (G.761 signaling performed microprocessor external hardware) between
100060C
Conexant
Appendix ADPCM Transcoder
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
full-rate compressed ports required G.761, enter, implement, monitor diagnostic tests Bt8110/B. Bt8510 framers include analog line interfaces that compatible with cable wire-pair lines, digital timing-recovery circuit, slip buffers. This allows circuit provide termination synchronization functions required transcoding. ADPCM processors operate time-shared-logic principle, that circuit elements shared channels. This characteristic makes possible provide full-time diagnostic test both Bt8110/Bs framing signaling timeslots without disturbing active traffic.
Figure E-1. Single-Board Transcoder Assembly
RS-232C
UART Link
Bt8110/B ADPCM Processor
Microprocessor Bt8200 Bt8510 Framer/LIU ADPCM Line Formatter Framer/LIU
Bt8200
Framer/LIU
ADPCM Line Formatter
Bt8110/B
ADPCM Processor
100060_027
Each ADPCM processor consists 68-pin PLCC integrated circuit (and Bt8110). Each Bt8510 consists 68-pin PLCC circuit. Each Bt8200 consists 84-pin PLCC integrated circuit RAM. microprocessor provided several different configurations, typical configuration includes Intel 80C188 processor program memory. Only supply required; power consumption assembly totals less than Watts. entire transcoder approximately square inches (260 square centimeters) circuit-board area, allowing development single-board wall-mount unit. compact size power consumption also permits development built-in units channel banks customer-premise multiplexers. evaluation board constructed this configuration available. microprocessor programmed obtain maintenance status information, provide signaling conversion between full-rate compressed streams, perform diagnostic tests Bt8110/Bs. software listing program used Bt8200EVM-E1 available upon request.
Conexant
100060C
Bt8110/8110B
High-Capacity ADPCM Processor
Appendix ADPCM Transcoder
Introduction
E.1.2 Summary
transcoder assembly used double voice-channel capacity line, shown Figure E-2. full-rate come from systems, channel banks, PBXs, other stream signal sources.
Figure E-2. Single-Board Transcoder Application
Transcoder Transcoder
100060_028
Kbit/s ADPCM
E.1.3 ADPCM Transcoder System Specifications
Table E-1. ADPCM Transcoder System Specifications Name
Channel Capacity ADPCM Coding Signaling Modes Framing Line Interface Unit Configuration Control Synchronization
Description
channels, full-duplex. kbit/s ADPCM ITU-T Recommendation G.726. Signaling ITU-T Recommendation G.761. ITU-T Recommendation G.704, G.706, G.732. Integral analog line interface unit Bt8510 Framer. built-in kbit/s serial port. outputs synchronized received output synchronized input external timing reference. alarms available microprocessor. Indicators provided required. Looping each available microprocessor control. channels selected transparent according requirements recommendation G.761. Full-time in-service diagnostic test ADPCM processor channels using timeslot timeslot Storage configuration data during power outage nonvolatile EEROM NOVRAM memory. Per-channel optional insertion selectable code signaling states idle channels. 0-250 ports. Less then Watts system 4.75-5.25 Volts. Approximately (12.7 20.3 cm).
Alarms Self-Test Transparent Channels Diagnostic Test Program Storage Idle Channel Control Slip Buffer Power Requirement Board Dimensions
100060C
Conexant
Appendix ADPCM Transcoder
Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
Conexant
100060C
Sales Offices
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