MirrorBitRELIABILITY STUDY OVERVIEW MirrorBitcell breakthrou

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Reliability Study
MirrorBitRELIABILITY STUDY
OVERVIEW
MirrorBitcell breakthrough Flash memory cell architecture that enables Flash memory product hold twice much data standard Flash, without compromising device endurance, performance reliability. MirrorBit architecture result years research development design, processing, testing characterization multi-bit cells that culminated AMD's patented MirrorBit architecture. MirrorBit memory cells, which store full charge each physically distinct locations, offer many advantages over MLCs that store fractional levels charge location. Since each MirrorBit memory cell physically different location, bits independent interact with each other, allowing offer same performance reliability standard single-bit Flash memory products. Over billion MirrorBit memory bits have been tested studied since inception this technology. Over thousand devices packages were subjected extensive tests qualification MirrorBit technology. This extensive testing testament AMD's commitment delivering highly reliable worldclass quality products. Over billion bits have also been characterized through 100,000 readprogram-erase cycles. Reliability testing allows offer MirrorBit devices that designed deliver 100,000 program/erase cycles, well years data retention 125°C. Testing shows that failure rates consistent with AMD's standard floating gate technology. Furthermore, expect complete characterization endurance cycle level near future. focus this article explain methodology testing employed characterize qualify reliability MirrorBit based Flash products.
Publication 26203A Rev: Amendment/0 Issue Date: November 2002
RELIABILITY TESTING
WHAT RELIABILITY?
Reliability defined ability product perform stated functions predictable length time. Failure loss ability device perform required functions. There basic categories device failure that affect reliability. Hard failures, complete unrecoverable faults device, arise from defects that occur during manufacturing process. Once there hard failure, device fails cannot recovered. other hand, soft failures occur over time result operating device caused physical degradation device. These types failures recovered. However, either type failure results reduced reliability. Reliability tested ensured accelerated stress tests. well-designed stress test quickly identifies relevant failure mechanism. advantages accelerated stress testing that these tests stress device order bring low-rate failures. They also make possible replicate failures that would occur over many years device operation large population using smaller sample population over shorter time with accelerated stress. Once problem identified, either root-cause Reliability Testing eliminated screen implemented ensure that failure contained.
Accelerated Stress Tests
number different stress tests have been used help ensure that MirrorBit products offer high levels endurance, reliability data retention. attached flowchart (Figure summarizes reliability stress tests (product package tests) performed qualify MirrorBit technology. Test results summarized this study included Am29LV640MU/Am29LV641MH/L Qualification Summary.
Product Testing
Thermal Tests High Temperature Operating Life (HTOL) Tests
Package Testing
Moisture Tests [FBGA TSOP] Steam Pressure (SPP)
HTOL 150C
Process Characterization Tests Program/Erase Endurance Cycles 100K Cycles
Highly Accelerated Stress Test (HAST)
Thermo-Mechanical Tests [FBGA TSOP] Temperature Cycling (T/C) Cycles
Data Retention Bake (DRB) 250C
Electrostatic Discharge (ESD) Sensitivity Latch-Up Tests [FBGA TSOP] Sensitivity Human Body Model (HBM)
Latch-Up Sensitivity
Figure
MirrorBit
DEVICE TESTING RELIABILITY
Reliability Testing
Accelerated Stress Tests
Product Testing
Thermal Tests High Temperature Operating Life (HTOL) Tests
Package Testing
Moisture Tests [FBGA TSOP] Steam Pressure (SPP)
HTOL 150C
Process Characterization Tests Program/Erase Endurance Cycles 100K Cycles
Highly Accelerated Stress Test (HAST)
Thermo-Mechanical Tests [FBGA TSOP] Temperature Cycling (T/C) Cycles
Data Retention Bake (DRB) 250C
Electrostatic Discharge (ESD) Sensitivity Latch-Up Tests [FBGA TSOP] Sensitivity Human Body Model (HBM)
Latch-Up Sensitivity
Flash memory device testing comprises tests such High Temperature Operating Lifetest (HTOL) Program/Erase Cycling (Endurance) Data Retention Bake (DRB) tests
These tests help ensure that devices shipped will fail field unacceptable rates devices shipped will meet industry's highest endurance specification 1,000,000 program/erase cycles (100,000 initially) devices shipped will retain data more than years 125°C
MirrorBit
THERMAL TESTS
High Temperature Operating Life (HTOL) tests help ensure that product performs reliably, both upon receipt shipment well system. Accelerated thermal tests used Ensure that rate failure field very within acceptable levels Provide estimate operating life field failure rate device
Thermal tests performed qualify MirrorBit devices are: High Temperature Operating Life (HTOL) hours 150°C data MirrorBit technology achieves same results AMD's standard floating gate technology
Reliability Testing
Accelerated Stress Tests
Product Testing
Thermal Tests High Temperature Operating Life (HTOL) Tests
Package Testing
Moisture Tests [FBGA TSOP] Steam Pressure (SPP)
HTOL 150C
Process Characterization Tests Program/Erase Endurance Cycles 100K Cycles
Highly Accelerated Stress Test (HAST)
Thermo-Mechanical Tests [FBGA TSOP] Temperature Cycling (T/C) Cycles
Data Retention Bake (DRB) 250C
Electrostatic Discharge (ESD) Sensitivity Latch-Up Tests [FBGA TSOP] Sensitivity Human Body Model (HBM)
Latch-Up Sensitivity
MirrorBit
HTOL 150°C
Reliability studies have shown that probability generic device failure field shown Figure
HTOL test comprises tests check Early Life/Infant Mortality, Inherent Life Wearout Region functionality MirrorBit devices. Early Life Infant Mortality HTOL test used weed failures early device's life. purpose Early Life (EL) test detect quantify presence failure mechanisms that occur "defective subpopulation". This portion total device population generally been affected some anomalous condition during manufacturing. early life failure rate enables estimate time first failure this product. This test also helps implement screens prevent early life fallout future (e.g., screen repair slow erase bits population).
Probability Failures
Early Failures
Constant Failure Rate
Wearout
Early Life
Inherent Life
Insert tests screens prevent these devices from reaching customer
Time
accelerated tests determine operating life help ensure that devices meet published specifications
Figure Bathtub Curve Operating life tests performed while device under power functioning intended, used elucidate various failure mechanisms intrinsic manufacturing process.
High Temp. Operating Life (HTOL) hrs.
1600 1400
Early Life/Infant Mortality Test Temperature Duration Voltage Number lots tested Devices tested Maximum estimated failure rate Calculated failure rate Failures Pass/Fail 150°C hours 3.6V 1443 FITS FITS PASS
Sample Size
1200 1000 0.32µm 0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Minimum Sample Size
MirrorBit
HTOL 150°C
Inherent Life (Constant Failure Rate) test designed detect failure mechanisms that intrinsic entire population devices. This test provides estimate failure rate beyond early life period. Bathtub curve (Figure shows this constant failure rate region used determine "useful working life" devices.
Results from accelerated conditions translated standard application conditions using appropriate data models activation energies order estimate field reliability FITS (Failures Time)1 product. Wearout Region HTOL test demonstrates rapidly increasing failure rate. generally observed today's integrated devices (obsolescence).
High Temp. Operating Life (HTOL) hrs.
Inherent Life /Constant Failure Rate Temperature Duration Voltage Number lots tested Devices tested Maximum estimated failure rate Calculated failure rate Failures Pass/Fail 150°C hours 3.6V FITS FITS PASS
Sample Size
0.32µm 0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Minimum Sample Size
High Temp. Operating Life (HTOL) 1000 hrs.
Inherent Life /Constant Failure Rate Temperature Duration Voltage Number lots tested Devices tested Maximum estimated failure rate Calculated failure rate Failures Pass/Fail MTTF (Mean time failure) 150°C 1000 hours 3.6V FITS FITS PASS 19,026 years
Sample Size
0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Minimum Sample Size
Note: failure rate expressed number failures billion hours.
MirrorBit
MirrorBit
PROCESS CHARACTERIZATION TESTS
Process Characterization tests confirm that process device have been characterized over specified range process variations, using silicon from production Fab. These tests performed help ensure that: Devices shipped will meet industry's highest endurance specification 1,000,000 program/erase cycles (100,000 initially) Devices shipped will retain data more than years 125°C
Tests performed qualify MirrorBit devices are: Program/Erase Endurance Cycles 100K cycles data (Further testing underway cycles) Data Retention Bake (DRB) hours 250°C data MirrorBit products exhibit same high levels endurance data retention standard Flash.
Reliability Testing
Accelerated Stress Tests
Product Testing
Thermal Tests High Temperature Operating Life (HTOL) Tests
Package Testing
Moisture Tests [FBGA TSOP] Steam Pressure (SPP)
HTOL 150C
Process Characterization Tests Program/Erase Endurance Cycles 100K Cycles
Highly Accelerated Stress Test (HAST)
Thermo-Mechanical Tests [FBGA TSOP] Temperature Cycling (T/C) Cycles
Data Retention Bake (DRB) 250C
Electrostatic Discharge (ESD) Sensitivity Latch-Up Tests [FBGA TSOP] Sensitivity Human Body Model (HBM)
Latch-Up Sensitivity
MirrorBit
ENDURANCE
addition data retention, other important requirement Flash memory integrity endurance. Endurance, ability repeatedly program erase memory cell, closely connected with reliability cell. Program/Erase endurance cycling tests performed help ensure that device able sustain repeated data changes (P/E cycles). MirrorBit Flash devices were placed boards biased thermal chambers high temperatures. components were cycled repeatedly through programming erase conditions. Margin verification automatically performed after each cycle.
Endurance failures caused predominantly charge trapping oxide rupturing occurring charge transfer dielectric (e.g., tunneling, electrons) during program/erase cycles [1]. test also used check charge loss/gain issues erase time degradation issues with device. These tests help make sure that MirrorBit devices currently meet 100,000 cycles threshold, that they eventually meet industry's highest endurance specification 1,000,000 program/erase cycles AMD.
Program/Erase Endurance 100K cycles Matrix1
Endurance Temperature Duration Number lots tested Devices tested Failures Pass/Fail Specified Endurance -40°/25°/90°C 100K cycles PASS 100K cycles2
Sample Size
0.32µm 0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Minimum Sample Size
Note: Tempture/Voltage stress conditions used test MirrorBit devices included Am29LV640MU/Am29LV641MH/L Qualification Summary. Units undergoing further testing cycles.
MirrorBit
DATA RETENTION CHARACTERIZATION
most fundamental requirement Flash memory, non-volatile memory, that data retention. Flash memory solution should guarantee period over which data will retained device. important realize that data retention strongly dependent temperature. Flash memory devices, including MirrorBit Flash devices, specified retain data years 125°C. Data retention essentially process trapping confining electrons charge storage medium. Mechanisms electron gain/loss, (i.e., transport to/from dielectric), follow basic chemical kinetics. rate these phenomena described Arrhenius equation1 exponentially dependent temperature. result, explicitly states both time temperature while specifying data retention.
Data Retention Bake (DRB) test used characterize ability Flash memory device retain appropriate level charge. charge gain/loss caused defects either charge storage material select gate oxide. Abnormal levels charge gain/loss result change number electrons storage dielectric, therefore compromise data integrity. AMD's data retention bake test helps ensure that devices shipped customer offer highest levels data integrity. testing performed loading test pattern into wafer then baking wafer hours 250°C. baked devices submitted number electrical tests, post-test memory pattern must identical pre-test pattern, devices pass. Testing data retention baked hrs. 250°C equates lifetime more than years 125°C.
Wafer Level Data Retention Bake (DRB) 168hrs. 250°C
3000 2500
Data Retention Bake (DRB) Temperature Duration Number lots tested Devices tested Failures Pass/Fail Specified Data Retention 250°C hours 2603 PASS years 125°C
Sample Size
2000 1500 1000 0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Minimum Sample Size
Note: Arrhenius equation expressed R1=R0exp(-Ea/kT1) Where: Reaction Rate Constant Activation energy Boltzman's Constant (8.62x10-5eV/°K) Reaction Temperature (°K)
MirrorBit
MirrorBit
PACKAGE LEVEL RELIABILITY
Reliability Testing
Accelerated Stress Tests
Product Testing
Thermal Tests High Temperature Operating Life (HTOL) Tests
Package Testing
Moisture Tests [FBGA TSOP] Steam Pressure (SPP)
HTOL 150C
Process Characterization Tests Program/Erase Endurance Cycles 100K Cycles
Highly Accelerated Stress Test (HAST)
Thermo-Mechanical Tests [FBGA TSOP] Temperature Cycling (T/C) Cycles
Data Retention Bake (DRB) 250C
Electrostatic Discharge (ESD) Sensitivity Latch-Up Tests [FBGA TSOP] Sensitivity Human Body Model (HBM)
Latch-Up Sensitivity
PACKAGE LEVEL TESTING INCLUDES:
Package level tests check issues such
Steam Pressure (SPP) test Highly Accelerated Stress Test (HAST) Temperature Cycling (T/C) Electrostatic Discharge (ESD) Latch-up sensitivity tests
molding problems chemical/galvanic corrosion metallization moisture penetration temperature induced stress cycles cracking die/package electrostatic shocks
MirrorBit
MOISTURE TESTS
Moisture tests designed assess ability packaged parts withstand moisture contamination. These tests reveal: Problems with die/package combination Problems with molding process chemical galvanic corrosion metallization Other moisture contamination related failure mechanisms
moisture tests used help ensure that MirrorBit devices used system that powered high humidity environment are: Steam Pressure (SPP) hours data Highly Accelerated Stress Test (HAST) hours data Results from above tests show that packaged MirrorBit products have same level reliability standard Flash.
Reliability Testing
Accelerated Stress Tests
Product Testing
Thermal Tests High Temperature Operating Life (HTOL) Tests
Package Testing
Moisture Tests [FBGA TSOP] Steam Pressure (SPP)
HTOL 150C
Process Characterization Tests Program/Erase Endurance Cycles 100K Cycles
Highly Accelerated Stress Test (HAST)
Thermo-Mechanical Tests [FBGA TSOP] Temperature Cycling (T/C) Cycles
Data Retention Bake (DRB) 250C
Electrostatic Discharge (ESD) Sensitivity Latch-Up Tests [FBGA TSOP] Sensitivity Human Body Model (HBM)
Latch-Up Sensitivity
MirrorBit
STEAM PRESSURE TEST
Steam Pressure (SPP) testing used evaluate plastic package survivability when moisture forced through encapsulant surface. Packaged MirrorBit devices were placed pressurized chambers exposed saturated steam 121°C pressure psig hours.
This test designed indicator gross problems with die/package combination with molding process. test primarily used check moisture contamination related failure mechanisms. test also checks chemical galvanic corrosion1 metallization.
FBGA Package
Steam Pressure (FBGA) Temperature Duration Humidity Pressure Number lots tested Devices tested 121°C hours Saturated Steam psig PASS
Sample Size
0.23µm 0.17µm
MirrorBit (0.23
Failures Pass/Fail
Technology
Sample Size Failures Minimum Sample Size
TSOP Package
Steam Pressure (TSOP) Temperature Duration Humidity Pressure Number lots tested Devices tested 121°C hours Saturated Steam psig PASS
Sample Size
0.23µm 0.17µm
MirrorBit (0.23
Failures Pass/Fail
Technology
Sample Size Failures Minimum Sample Size
Note: Galvanic couple formed gold ball bond aluminum provides driving force accelerate corrosion.
MirrorBit
HIGHLY ACCELERATED STRESS TEST
Highly Accelerated (Temperature Humidity) Stress Test (HAST) performed purpose evaluating reliability non-hermetic packaged solid-state devices humid environments [2]. employs severe conditions temperature, humidity bias, which accelerate penetration moisture through external protective material (encapsulant seal) well interface between encapsulant/seal metallic conductors. MirrorBit Flash devices were mounted boards with bias applied parts. boards were placed pressurized test chamber
relative humidity temperatures between 110°C 150°C. Intermediate electrical test readouts were taken with final readout hours. stress usually activates same failure mechanisms "85/85" Steady-State humidity Life Test (JEDEC Standard 22-A101).The test assumes moisture penetration surface that primary failure mechanism will electrolytic corrosion metallization1. Other moisture contamination related failure mechanisms might also observed. test intended evaluate molding compound purity, well quality passivation glassivation processes.
HAST FBGA Package
Highly Accelerated Stress Test (FBGA) Temperature Duration Relative Humidity Number lots tested Devices tested 110-150°C hours PASS
Sample Size
0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Minimum Sample Size
Failures Pass/Fail
HAST TSOP Package
Highly Accelerated Stress Test (TSOP) Temperature 110-150°C hours PASS Duration Relative Humidity Number lots tested Devices tested Failures Pass/Fail
Sample Size
0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Minimum Sample Size
Note: electrochemical reaction that consumes metallization results loss contact function.
MirrorBit
MirrorBit
THERMO-MECHANICAL TESTS
Thermo-Mechanical Tests: Cycle package between high temperature extremes, causing mechanical stresses packaged device used help ensure that there failures mismatch coefficients thermal expansion, mechanical manufacturing defects
Test performed qualify MirrorBit devices: Temperature Cycling (T/C) cycles data Results show that packaged MirrorBit devices demonstrate same levels reliability standard flash.
Reliability Testing
Accelerated Stress Tests
Product Testing
Thermal Tests High Temperature Operating Life (HTOL) Tests
Package Testing
Moisture Tests [FBGA TSOP] Steam Pressure (SPP)
HTOL 150C
Process Characterization Tests Program/Erase Endurance Cycles 100K Cycles
Highly Accelerated Stress Test (HAST)
Thermo-Mechanical Tests [FBGA TSOP] Temperature Cycling (T/C) Cycles
Data Retention Bake (DRB) 250C
Electrostatic Discharge (ESD) Sensitivity Latch-Up Tests [FBGA TSOP] Sensitivity Human Body Model (HBM)
Latch-Up Sensitivity
MirrorBit
TEMPERATURE CYCLING TEST
Temperature Cycling (T/C) testing cycles package between high temperature extremes. Through continuous cycling from high temperatures, structure expands contracts, causing mechanical stresses packaged device.
MirrorBit devices were placed chambers that automatically cycle between temperatures -40°C high 150°C. Standard temperature ranges well dwell times followed JEDEC Standards. final readpoint this test cycles. This test especially useful detecting stressinduced failures from mismatch coefficients thermal expansion die/package structure.
Temp Cycling FBGA Package
Temperature Cycling (FBGA) Temperature Cycles Number lots tested Devices tested Failures -40°C 150°C 1000 PASS
Sample Size
0.32µm 0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Mimimum Sample Size
Pass/Fail
Temp Cycling TSOP Package
Temperature Cycling (TSOP) Temperature -40°C 150°C 1000 PASS Cycles Number lots tested Devices tested Failures
Sample Size
0.32µm 0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Mimimum Sample Size
Pass/Fail
MirrorBit
SENSITIVITY LATCH-UP TESTS
(Electrostatic Discharge) sensitivity testing helps ensure that product robust enough survive normal assembly handling customer. objective minimize failures resulting from human equipment handling Latch-Up (LU) evaluation minimize (electrical overstress) failures latch-up during test, burn-in end-use systems
Sensitivity Latch-up Tests: Sensitivity Human Body Model (HBM) Passes 4000V Latch-Up Sensitivity Results: Pass MirrorBit products exhibit equivalent better Latch-up characteristics than standard Flash.
Reliability Testing
Accelerated Stress Tests
Product Testing
Thermal Tests High Temperature Operating Life (HTOL) Tests
Package Testing
Moisture Tests [FBGA TSOP] Steam Pressure (SPP)
HTOL 150C
Process Characterization Tests Program/Erase Endurance Cycles 100K Cycles
Highly Accelerated Stress Test (HAST)
Thermo-Mechanical Tests [FBGA TSOP] Temperature Cycling (T/C) Cycles
Data Retention Bake (DRB) 250C
Electrostatic Discharge (ESD) Sensitivity Latch-Up Tests [FBGA TSOP] Sensitivity Human Body Model (HBM)
Latch-Up Sensitivity
MirrorBit
SENSITIVITY
historic method classifying components Susceptibility uses Human Body Model. discharge waveform intended approximate event from human finger component while other pins ground potential. Products must display Withstand Voltage 2000 volts nominal pass qualification requirements.
charging voltage 1000, 2000, 3000, 4000 volts nominal applied device discharged separately each pin-pair combination. stress applied consisted positive pulses followed negative pulses. test procedure discharge waveform specified ANSI/ESD S-5.1. This test checks electrical failures such increased leakage currents well damage I/O's core.
Sensitivity- FBGA Package
Sensitivity (FBGA) Temperature Voltage applied each pair Actual test voltage passed Number lots tested Devices tested Failures Pass/Fail Minimum voltage required pass test Ambient 1kV, 2kV, 3kV, 2000V >4000V PASS
Passed Voltage
0.23µm 0.17µm
MirrorBit (0.23
Technology
Passed Voltage Minimum Passed Voltage
Sensitivity- TSOP Package
Sensitivity HBM(TSOP) Temperature Minimum voltage required pass test Actual test voltage passed Number lots tested Devices tested Ambient 2000V >4000V PASS Voltage applied each pair 1kV, 2kV, 3kV,
Passed Voltage
0.32µm 0.23µm 0.17µm
MirrorBit (0.23
Failures Pass/Fail
Technology
Passed Voltage Minimum Passed Voltage
Note: Results show greater than 100% improvement sensitivity when compared standard floating gate technology.
MirrorBit
LATCH-UP SENSITIVITY STATIC LATCH-UP (SLU)
Latch-up occur when sustained impedance path created between power supply rails. This caused triggering parasitic layer bipolar structures (SCR) current generated from various sources. test method used assess product susceptibility latch-up. over-voltage forced each supply trigger current forced pins valid logic states 125°C. Trigger polarity chosen result overstress condition. long slow trigger pulse conforms JEDEC Std-17 eliminate transient effects.
qualification, products were required display Withstand Voltage volts power supply pins. Withstand Currents greater than +100ma volts greater than -100ma volts. This test used detect failures caused electrical failure Latch-up condition. form EOS1 damage package detected.
Latch-Up Test-FBGA Package
Static Latch-up Sensitivity (FBGA) Temperature Voltage applied Minimum current allowed pass test Number lots tested Devices tested Failures 125°C 5.6V 100mA PASS
Sample Size
0.32µm 0.23µm 0.17µm
MirrorBit (0.23
Technology
Sample Size Failures Minimum Sample Size
Pass/Fail
Latch-Up Test-TSOP Package
Static Latch-up Sensitivity (TSOP) Temperature Voltage applied Minimum current allowed pass test Number lots tested Devices tested Failures 125°C 5.6V 100mA PASS
Sample Size
0.32µm 0.23µm 0.17µm
MirrorBit (0.23
Pass/Fail
Technology
Sample Size Failures Minimum Sample Size
Note: Electrical Overstress
MirrorBit
REFERENCES
[1]: Jedec Standard EEPROM Program/Erase Endurance Data Retention Test JESD22-A117 [2]: EIA/Jedec Standard Test Method JESD22 A110-B; Highly Accelerated Temp. Humidity Stress Test (HAST)
MirrorBit
MirrorBit
Sales Offices Representatives
North America
ALABAMA ARIZONA CALIFORNIA, West Lake Village Irvine Angeles Pleasanton Sacramento (Cool) Diego Jose CANADA (Toronto) COLORADO CONNECTICUT FLORIDA, Clearwater Miami (Lakes) GEORGIA ILLINOIS, Chicago Mundelein MASSACHUSETTS MICHIGAN MINNESOTA JERSEY, Chatham Cherry Hill Parsippany YORK NORTH CAROLINA OREGON PENNSYLVANIA SOUTH DAKOTA TEXAS, Austin Dallas Houston VIRGINIA .(256)830-9192 .(602)242-4400 .(805)496-3992 .(949)450-7500 .(805)496-3992 .(925)416-8150 .(530)886-0945 .(858)566-6414 .(408)922-0300 .(905)831-6226 .(203)264-7800 .(727)793-0055 .(305)820-1113 .(770)814-0224 .(630)773-4422 .(847)837-0439 .(781)213-6400 .(248)471-6294 .(973)701-1777 .(856)662-2900 .(973)299-0002 .(716)425-8050 .(919)840-8080 .(503)245-0080 .(215)340-1187 .(605)692-5777 .(512)346-7830 .(972)985-1344 .(703)736-9568
Representatives U.S. Canada
ARIZONA, Tempe Centaur CALIFORNIA, Calabasas Centaur Irvine Centaur Diego Centaur. Santa Clara Fourfront. CANADA, Burnaby, B.C. Davetek Marketing. Calgary, Alberta Davetek Marketing. Kanata, Ontario J-Squared Tech. Mississauga, Ontario J-Squared Tech. Laurent, Quebec J-Squared Tech. COLORADO, Golden Compass Marketing FLORIDA, Melbourne Marathon Technical Sales Lauderdale Marathon Technical Sales Orlando Marathon Technical Sales Petersburg Marathon Technical Sales GEORGIA, Duluth Quantum Marketing ILLINOIS, Skokie Industrial Reps, Inc. INDIANA, Kokomo IOWA, Cedar Rapids Lorenz Sales KANSAS, Lenexa Lorenz Sales MASSACHUSETTS, Burlington Synergy Associates MICHIGAN, Brighton MINNESOTA, Paul Cahill, Schmitz Cahill, Inc. MISSOURI, Louis Lorenz Sales JERSEY, Laurel Associates YORK, Buffalo Nycom, Inc. East Syracuse Nycom, Inc. Pittsford Nycom, Inc. Rockville Centre Associates NORTH CAROLINA, Raleigh Quantum Marketing OHIO, Middleburg Dolfuss Root Powell Dolfuss Root Vandalia Dolfuss Root Westerville Dolfuss Root OREGON, Lake Oswego Squared, Inc. UTAH, Murray Front Range Marketing VIRGINIA, Glen Burnie Coherent Solution, Inc. WASHINGTON, Kirkland Squared, Inc. WISCONSIN, Pewaukee Industrial Representatives
International
AUSTRALIA, North Ryde BELGIUM, Antwerpen BRAZIL, Paulo CHINA, Beijing Shanghai Shenzhen FINLAND, Helsinki FRANCE, Paris GERMANY, Homburg Munich HONG KONG, Causeway ITALY, Milan INDIA, Delhi JAPAN, Osaka Tokyo KOREA, Seoul SINGAPORE, Singapore SWITZERLAND, Geneva SWEDEN, Stockholm TAIWAN, Taipei UNITED KINGDOM, Frimley Haydcock
Representatives Latin America
ARGENTINA, Capital Federal. Argentina- Rep. .(+54-11)4373-0655 CHILE, Santiago LatinRep/WWRep. COLUMBIA, Bogota Dimser. MEXICO, Guadalajara LatinRep/WW Rep. Mexico, City LatinRep/WW Rep. Monterrey LatinRep/WW Rep. PUERTO RICO, Boqueron Infitronics.
Advanced Micro Devices reserves right make changes product without notice order improve design performance characteristics. performance characteristics listed this document guaranteed specific tests, guard banding, design other practices common industry. specific testing details, contact your local sales representative. company assumes responsibility circuits described herein.
Advanced Micro Devices, Inc. rights reserved. AMD, Arrow logo combination thereof, MirrorBit, trademarks Advanced Micro Devices, Inc. Other product names informational purposes only trademarks their respective companies. 2002 Advanced Micro Devices, Inc. LYX-3.5M-11/02-0 11/02 26203A Printed
Place, P.O. 3453, Sunnyvale, 94088-3453 408-732-2400 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com

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