µPD9930 LINEAR CODEC DIGITAL CELLULAR TELEPHONE µPD9930 sing

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µPD9930 LINEAR CODEC DIGITAL CELLULAR TELEPHONE µPD9930 sing

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INTEGRATED CIRCUIT
µPD9930
LINEAR CODEC DIGITAL CELLULAR TELEPHONE
µPD9930 single power operation, power consumption linear CODEC developed digital cellular telephone use. CODEC wide dynamic use. This also features microphone/receiver amplifier, tone generator, (Digital Audio Interface: conforming GSM11.10), power-saving function. These functions controlled microcontroller. addition, (TYP.) power consumption enabled during operation.
FEATURES
single power supply power consumption operation: (TYP.) (VDD stand-by mode: (TYP.) (VDD CODEC 13-bit precision linear coding Transmission level controlled microcontroller. Analog input/output funciton noise microphone amplifier High output receiver amplifier Piezo-electric receiver directly driven. Gain canbe controlled microcontroller. On-chip amplifier accessory input/output Tone generator Frequency, generating pattern gain controlled microcontroller. DTMF generation function Various service tone generation function triple tone generation function Desired tone frequency registered (0.3 kHz) Conforming GSM11.10 Test mode terminal microcontroller command. Stand-by mode Rise time time stand-by clearing: 30.5 (TYP.) Master clock generation (external clock input: kHz) Tone interrupt pattern output function Ringer output function
ORDERING INFORMATION
Part Number µPD9930G-22 Package 44-pin plastic
information this document subject change without notice. Document S11616EJ2V0DS00 (2nd edition) (Previous IC-3342) Date Published November 1996 Printed Japan mark shows major revised points.
1994,1996
RESETB MIXI MICO MICI- MICI+ Microphone amplifier Digital signal processor Pre-Filter Mixer
Voice send Digital Gain Cont. -2.8 (0.4 steps)
BLOCK DIAGRAM
REQB FSYNC kHz)
Transmit
XACOMO) XAUXO XAUXI-
SCLK (256 kHz) INTERFACE
Accessory input amplifier Vref
Post Filter (Accessory output amplifier)
RAUXO
REC1O
Post Filter (Receiver amplifier steps)
Receive
Voice receive Digital Gain Cont. -2.4 (0.8 steps)
DSPSEL
REC2I- REC2O-
Receiver drive amplifier (Receiver amplifier
MICROCONTROLLER INTERFACE Sign code output
Tone Gain Cont. steps) -38.5 Tone Generator
MCLK MSTR MDAT
Vref
REC2O+
Vref (GSM11.
DCLK DRSTB Tone Interval Generation
XACOMI XACOMO Vcombuff RACOMO RACOMI Vref
TIMER
RINGER
Low-current drive
µPD9930
µPD9930
CONFIGURATION (Top View) 44-pin plastic
RACOMO
XACOMO
REC2O+
REC2O-
RACOMI
XACOMI
XAUXI-
XAUXO
REC2I-
ICNote
REC1O RAUXO AVDD1 AVDD2 DVDD SCLK TEST MSTR
MICO MICI- MICI+ AGND4 AGND3 AGND2 AGND1 DGND FSYNC RESETB REQB
TIMER
RINGER
MDAT
DRSTB
MCLK
DCLK
Note Internal connection; leave unconnected
DSPSEL
MIXI
µPD9930
Name
AGND1-AGND4 DD1, DCLK DGND DRSTB DSPSEL FSYNC MCLK MDAT MICI+ MICI- MICO MIXI MSTR RACOMI RACOMO RAUXO REC1O REC2I- REC2O+ REC2O- REQB RESETB RINGER SCLK TC1, TEST TIMER XACOMI XACOMO XAUXI- XAUXO Analog Ground Analog Power Supply (Digital Audio Interface) Clock Output Digital Ground Serial Input Serial Output Reset Digital Signal Processor Select Digital Power Supply Frame Synchronization Signal Input Internally Connected Microcontroller Synchronous Clock Microcontroller Serial Data Microphone Amplifier Input Non-Inverted Microphone Amplifier Input Inverted Microphone Amplifier Output Mixer Input Microcontroller Strobe Receive Common Reference Voltage Input Receive Common Reference Voltage Output Receive Auxiliary Amplifier Output Receive Amplifier Output Receive Amplifier Input Inverted Receive Amplifier Output Non-Inverted Receive Amplifier Output Inverted Request Reset Ringer Serial Data Synchronous Clock Output Serial Data Output Enable Serial Data Input Serial Data Output Mode Control Test Timer Transmit Common Reference Voltage Input Transmit Common Reference Voltage Output Transmit Auxiliary Amplifier Input Inverted Transmit Auxiliary Amplifier Output
µPD9930
CONTENTS
FUNCTIONS
LIST FUNCTIONS EQUIVALENT CIRCUIT
BLOCK FUNCTIONS
CODEC 2.1.1 Audio Codec 2.1.2 Audio Analog Input 2.1.3 Audio Analog Output 2.1.4 Audio Digital Accessory Output 2.1.5 Audio Digital Signal Processor 2.1.6 Power Up/Down Control 2.1.7 Microcontroller Interface 2.1.8 Interface 2.1.9 (Digital Audio Interface)
TONE INTERVAL OUTPUT FUNCTION (TIMER TERMINAL) INTERNAL CONTROL FUNCTIONS
SEND/RECEIVE GAIN CONTROL 4.1.1 Voice Send Analog Gain/Receiver Amplifier Control Register (TXGCR) 4.1.2 Voice Receive Analog Gain Control Register (RXGCR) 4.1.3 Voice Send/Receive Digital Gain Control Register (DGGSR) DIGITAL INPUT/OUTPUT CONTROL 4.2.1 Digital Signal Processing Control Register (DSPCR) TONE CONTROL 4.3.1 Tone Frequency Selection Register (FRQSR) 4.3.2 Expanded Tone Registers (EXPR1, EXPR2) 4.3.3 Tone Control Register (TONCR) 4.3.4 Tone Gain Control Register (TNGCR) TEST MODE CONTROL 4.4.1 Test Control Register (TSTCR)
ELECTRICAL CHARACTERISTICS APPLIED CIRCUIT EXAMPLE PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS
µPD9930
FUNCTIONS
LIST FUNCTIONS Table List Functions (1/2)
Name MDAT MCLK DRSTB Input/Output Input Input Input Input Output Microcontroller interface serial input Microcontroller interface clock input (Digital Audio Interface) reset input This reset level. Internally pulled high. serial input Internally pulled high. serial output Hi-Z normal operation (TC1 level) DCLK Output Input clock output (104 kHz) Hi-Z normal operation mode control Selection test mode specified GSM11.10 combination with level High level Test mode specification Normal operation Speech encoder test mode Speech decoder test mode Acoustic device test mode Function
Input
pins internally pulled down. TIMER RINGER DSPSEL Output Output Input Timer output. Output rectangular wave synchronized with tone intermittent pattern. Ringer tone output. Output rectangular wave synchronized with tone frequency. Selection interface input/output timing mode. Connect GND. (VDD mode mode Input interface data transmit request signal. Serial data input/output level. System reset input. This reset level. Initializes control registers. Reset when turning power Send/receive frame synchronization signal kHz) input Digital ground. Connect digital ground line near µPD9930 pins. Analog ground. Connect analog ground line near µPD9930 pins.
REQB RESETB FSYNC DGND AGND1 AGND2 AGND3 AGND4 MICI+ MICI- MICO MIXI XAUXO
Input Input Input Input Input Output Input Output
Microphone amplifier non-inverted input Microphone amplifier inverted input Microphone amplifier output. Connect microphone amplifier gain adjust resistor. Outputs sidetone signal REC2I- pin. Pre-filter mixer input Accessory input amplifier output. Connect accessory input amplifier gain adjust resistor.
µPD9930
Table List Functions (2/2)
Name XAUXI- XACOMI XACOMO RACOMO RACOMI REC2O+ REC2O- REC2I- REC1O RAUXO AVDD1 AVDD2 DVDD SCLK TEST MSTR Input/Output Input Input Output Output Input Output Output Input Output Output Output Input Output Output Input Input Digital power. Connect digital power supply line near µPD9930 pins. interface enable signal output interface serial input interface serial output interface clock output (256 kHz) high level Microcontroller interface strobe signal input Function Accessory input amplifier inverted input Voice send internal reference voltage input Voice send internal reference voltage (1.2 output Voice receive internal reference voltage (1.2 output Voice receive internal reference voltage input Receiver amplifier non-inverted output Receiver amplifier inverted output Internal connection; leave unconnected Receiver amplifier inverted input Connect sidetone gain adjust resistor. Receiver amplifier output Accessory output amplifier output Analog power. Connect analog power supply line near µPD9930 pins.
Caution Short-circuit XACOMI XACOMO pins location close pins µPD9930 possible. Connect capacitor (chip capacitor electrolytic capacitor) between this short-circuited portion analog ground. same applies RACOMI RACOMO pins. transmission/reception level determined these reference pins. Therefore, make sure that these pins affected noise fluctuation ground potential current.
µPD9930
EQUIVALENT CIRCUIT
Type AVDD Type AVDD
Analog input internal circuit
Analog input internal circuit
AGND Name MICI+, MICI-, XAUXI-, REC2I- Type AVDD
AGND Name MIXI, XACOMI, RACOMI Type DVDD
Analog output From internal circuit
CMOS input internal circuit
AGND Name MICO, XAUXO, XACOMO, RACOMO, REC2O+, REC2O-, REC1O, RAUXO Type DVDD Mask input CMOS input internal circuit CMOS input
DGND Name MDAT, MCLK, DSPSEL, REQB, RESETB, FSYNC, TEST, MSTR Type
Note
DVDD
internal circuit
DGND DGND Name Type Note DVDD DVDD Name TC1, Type CMOS input internal circuit CMOS output From internal circuit DGND Name TIMER, RINGER, SEN, SCLK DVDD CMOS output From internal circuit DGND Name DCLK Enable signal DVDD
DGND Name DRSTB, Type
Note normal mode, output drive side high impedance reducing power consumption.
µPD9930
BLOCK FUNCTIONS
CODEC 2.1.1 Audio Codec Audio analog signal linear code conversion. Input/output format: bits (2's complement) Accuracy: bits 2.1.2 Audio Analog Input Includes microphone input accessory input. Microphone amplifier Amplifiers differential input signals from microphone required gain. Accessory input amplifier Amplifiers accessory input signal required gain. Pre-filter mixer Selects output signal microphone amplifier accessory input amplifier, inputs these converter after controlled gain. Table Analog Input Function
Amplifier Function Gain setting method Gain setting range
Microphone Amplifier External resistor (dB) (Including gain setting resistance) V0-p
Accessory Input Amplifier External resistor (dB) (Including gain setting resistance) V0-p
Pre-filter Mixer Microcontroller command
Minimum resistive load Maximum capacitive load Maximum output level
Figure Analog Input Block
MIXI MICO XACOMO) Vref XAUXO XAUXI- MICI- MICI+
Microphone amplifier
Pre-filter mixer
Accessory input amplifier
µPD9930
2.1.3 Audio Analog Output Includes receiver output accessory output. Sidetone addition also possible. Post filter (receiver amplifier This circuit adjusts gain differential output signal (volume control), then converts single output signal. Receiver drive amplifier (receiver amplifier This differential output amplifier that directly drive piezo-electric receiver (when using dynamic receiver, additional external amplifier necessary). sidetone added this circuit. Post filter (accessory output amplifier) This circuit converts differential output signal single output signal. Connected earphone head (capacitance load), etc. Table Analog Output Functions
Amplifier Function Gain setting method Gain setting range
Receiver Amplifier Microcontroller command steps)
Receiver Amplifier External resistor Voice receive signal gain: (dB) dBNote Sidetone signal gain: (dB) dBNote
Accessory Output Amplifier
Minimum resistive load Maximum capacitive load Maximum output level
V0-p
Vp-p (Differential output)
V0-p
Note Conversion result (single output differential output) Figure Analog Output Block
RAUXO
Post filter (accessory output amplifier) Post filter (receive amplifier steps) Receiver drive amplifier (receiver amplifier
REC1O
Sidetone signal REC2I- REC2O-
Vref
REC2O+
Vref
µPD9930
2.1.4 Audio Digital Accessory Output Ringer output (RINGER pin) Outputs rectangular waves same signal frequency tone signal frequency. output controlled turning power output buffer with control register. Figure RINGER Output
RAUXO (Tone output)
RINGER
RINGER signal tends bounce when tone output (RAUXO) signal crosses zero level, this tendency increases tone output gain decreases (lower than dB). When using RINGER pin, tune tone output gain TNGCR (Tone gain control register) Timer (tone interval) output (TIMER pin) Outputs rectangular waves same pattern tone signal interrupt pattern. This used make blink synchronization with ringer tone. Figure Digital Accessory Output Waveform
REC10 RAUXO (Tone output)
RINGER
TIMER
2.1.5 Audio Digital Signal Processor Send signal digital processing, receive signal digital processing, transmission level (digital gain) control, tone generation processing. Voice send signal digital gain fine adjustment function Performs gain fine adjustment voice send signal digital coefficient multiplication. Together with prefilter gain adjustment, fine adjustment possible width Voice receive signal digital gain fine adjustment function Performs fine adjustment gain voice receive signal digital coefficient multiplication. Tone generation function Generates single-tone dual-tone audible signals. Tone frequency, interrupt pattern, gain, generation/stop controlled microcontroller command. triple tone generated special command.
µPD9930
Table Digital Gain Control Functions
Voice Send Signal Gain Control Voice Receive Signal Gain Control Gain setting method Gain setting range Microcontroller command -2.8 (0.4 steps) Microcontroller command -2.4 (0.8 steps) Tone Gain Control Microcontroller command steps), -38.5
2.1.6 Power Up/Down Control PD9930 includes power down function reducing power consumption. Power down control methods described below. Input/output amplifier power up/down control Power up/down both input output amplifiers controlled. When power down function used input amplifiers, both pre-filter enter power down state. When power down function used accessory output amplifier receiver amplifier, also enters power down state. Stand-by mode power consumption realized mode which chip operation stopped. stand-by mode power down command. Operation restarts power command. following control registers used enable control described above.
Control Method Power up/down control input/output amplifier (not including receiver amplifier Power up/down control receiver amplifier Set/clear standby mode Registers Used Input/output amplifier control register (AMPCR) Send analog gain/receiver amplifier control register (TXGCR) Power control command (PUPCMD) Power down control command (PDWCMD)
outline diagram power down control shown Figure 2-5.
µPD9930
Figure Power Down Control
Register address
AMPCR MICPDB XAUXPDB REC1PDB RAUXPDB RINGPDB TXGCR REC2PDB TXAG
HEXNote
Register address
Power command
Power down command
HEXNote
Note value with first value with first
Microphone input Stand-by Stand-by Power MICPDB Pre-filter mixer
XACOMI Accessory input Vref When input amplifiers power down state, these also enter power down state.
Power XAUXPDB
Digital signal processor
Accessory output Power RAUXPDB Receiver Power REC1PDB Receiver Vref
Stand-by
Stand-by When both accessory output receiver amplifiers power down state, these also enter power down state. Stand-by Power Vref REC2PDB
Ringer output Stand-by Ringer output RINGPDB
Caution MICPDB XAUXPDB cannot enter power state same time (MICPDB XAUXPDB "1").
µPD9930
Input/output amplifier control register (AMPCR) This 5-bit register power up/down control each input/output amplifier (not including receiver amplifier ringer output ON/OFF control. Remark information power up/down control receiver amplifier refer 4.1.1 Voice Send Analog Gain/ Receiver Amplifier Control Register (TXGCR). Figure Input/Output Amplifier Control Register
Register address AMPCR
MICPDB XAUXPDB REC1PDB RAUXPDB RINGPDB
MICPDB
Microphone amplifier power control Power down Power
XAUXPDB Accessory input amplifier power control Power down Power
REC1PDB Receiver amplifier power control Power down Power
RAUXPDB Accessory output amplifier power control Power down Power
RINGPDB Ringer output control Sets output level. Output enable
Remarks stand-by mode, amplifiers enter power down state regardless input/output control register settings. However, register contents held unless reset written, when stand-by mode cleared power command, command prior stand-by mode resumed. microphone accessory amplifiers cannot enter power "1") state same time.
µPD9930
Table Function Specification Input/Output Amplifier Control Register
Register address AMPCR Microphone Accessory Receiver Accessory amplifier input amplifier amplifier output amplifier Ringer output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output Stop Output HEXNote Remarks reset
Note value with first value with first Remark Power Power down
µPD9930
Power up/down command (PUPCMD/PDWCMD) stand-by mode cleared following special commands. When resetting, stand-by mode set. Figure Power Down Command (Sets stand-by mode)
PDWCMD
Remark Don't Care Figure Power Command (Clears stand-by mode)
PUPCMD
Remark Don't Care Power up/down timing
Power command FSYNC Power down command
COUNT
ANAPWD
CLKPWD
DSPPWD
Remarks COUNT:
Internal counter (counts with 8-kHz internal clock)
ANAPWD: Analog power down (power down when high) CLKPWD: Clock power down (power down when high) DSPPWD: Signal processing power down (power down when high)
µPD9930
Power up/down sequence Power down sequence
Power down command execution
Digital signal processing (filter operation, tone generation operation) operation stop
Clock (internal clock, serial clock) power down
Analog (PLL, amplifiers) power down
Power sequence
Power command execution
Analog operation start
clock stabilization
Clock operation start
Digital signal operation start
Remarks interface serial input/output operation does stop start when switching power up/down. Rising time from standby mode normal operation mode about 30.5 after execution power command. FSYNC stopped power down. However, input FSYNC clock necessary during operation above sequence.
µPD9930
2.1.7 Microcontroller Interface PD9930 control internal functions microcontroller command. clock synchronous serial incorporated receive command. clocked serial interface provided receive microcontroller commands. microcontroller connection example shown Figure 2-9. 8-bit length data received serial clock (MCLK), serial input (MDAT), strobe input (MSTR) lines Note. timing chart shown Figure 2-10. reading data internal shift register setting MSTR high level MCLK rising point, latched internal control register. Data transfer must made with first. Note When bits more MCLK clocks more) data input, last 8-bit which input immediately before active edge MSTR recognized control command. Figure Example Connection with Microcontroller
Microcontroller Serial PORT
PD9930
Microcontroller MDAT MCLK MSTR
Figure 2-10 Microcontroller Interface Timing Chart
MCLK
MDAT
MSTR
µPD9930
2.1.8 Interface clock synchronous serial built-in exchange voice send/receive coding data with external DSP. 16-bit data transferred serial clock (SCLK kHz), serial input (SI), serial output (SO), enable output (SEN) lines. REQB terminal allowing/inhibiting data transmission. There modes data input output timing, either selected DSPSEL terminal. Select mode matching serial interface input/output timing. Data format follows: Both output input complement format with first. Figure 2-11 Data Format Interface
output
Coding data bits) Sign Invalid data
Remark full code output when +3.17 dBm0 (A/D Vp-p).
input
Coding data bits) Sign
Remark When full code input pin, accessory output Vp-p. Table Input/Output Timing Mode Selection
input DSPSEL MODE1 MODE2
Mode
Table Allowing Data Transmission
REQB Input Data Transmission Data transmission allowed. Enable signal (SEN) output rising edge FSYNC kHz), data input/output started. Enable signal output data input output.
µPD9930
Figure 2-12 Example Connection with (Mode
Serial enable PORT DSPSEL Note
PD9930
SCLK REQB FSYNC
Note When using with mode connect DSPSEL GND.
µPD9930
Figure 2-13 Interface Timing Chart Mode (DSPSEL VDD)
REQB
FSYNC kHz)
SCLK (256 kHz)
don't care
don't care
Mode (DSPSEL GND)
REQB
FSYNC kHz)
SCLK (256 kHz)
don't care
don't care
µPD9930
2.1.9 (Digital Audio Interface) on-chip circuit enabling functions specified GSM11.10. receive system on-chip only. necessary, should mounted externally. System configuration time test mode shown Figure 2-15. terminal connected system simulator DSUB socket. test mode selected terminals TC2, microcontroller command. mode should after completing power-up operation (30.5 after executing power-up command). When changing modes from normal, either following operations should executed. After specifying normal mode, input reset signal (DRSTB low). Input reset signal (RESETB low). When specifying command, test control register mode specification bits (ITC1, ITC2) used (Refer 4.4.1 Test Control Register (TSTCR).). Timing each mode shown Figures 2-16 through 2-20. operation time each mode, refer Figure 4-13 Test Mode Operation. Table Test Mode Specification
(ITC2) (ITC1) Test mode specification Normal operationNote Function
Normal operation. This mode system reset (when RESETB low) regardless status TC2. Outputs data input from (speech encoder) from pin. Input started rising edge first FSYNC (8-kHz external clock input) after execution mode specification, outputting data started next rising edge FSYNC. Outputs speech decoder output data input from from pin. Inputting data from started rising edge first FSYNC (8-kHz external clock input) after execution mode specification, data output from next rising edge FSYNC.
Speech encoder test mode
Speech decoder test mode
Acoustic device, A/D, Outputs audio data converted into digital signal from pin. test mode Also inputs audio data input from converter. Inputting/outputting data started rising edge first FSYNC (8-kHz external clock input) after execution mode specification. this time, clock output (SCLK) stopped.
Note normal mode, DRSTB level (during period, serial interface with disabled). well, output pins driver high-impedance state, because DRSTB input connected with pull-up resistor. Remark Analog loop back mode test mode cannot specified same time. test mode with TC1, ITC1, ITC2) DRSTB pins. test mode entered rising edge DRSTB signal when both pins ITC1 ITC2 pins) shown Figure 2-14.
µPD9930
Figure 2-14 Latch Timing TC1, ITC1, ITC2)
(ITC1) (ITC2)
DRSTB
Figure 2-15 Example System Configuration Time Test Mode
Mobile equipment
PD9930
System simulator
25-Pin DSUB socket DCLK
FSYNC MCLK MSTR MDAT
Test command Microcontroller
DRSTB SCLK REQB (SP-CODEC)
Remark acoustic device test mode, REQB ignored (both high levels). When DSPSEL (mode SCLK fixed low, when DSPSEL (mode fixed high.
(ITC1) (ITC2) DRSTB REQB FSYNC kHz) DCLK (104 kHz) don't care SCLK (256 kHz)
Figure 2-16 Speech Encoder Test Mode (DSP Interface MODE (TC1
µPD9930
Figure 2-17 Speech Encoder Test Mode (DSP Interface Mode (TC1
(ITC1)
(ITC2)
DRSTB
REQB
FSYNC kHz)
DCLK (104 kHz)
don't care
SCLK (256 kHz)
µPD9930
(ITC1) (ITC2) DRSTB REQB FSYNC kHz) SCLK (256 kHz) DCLK (104 kHz)
Figure 2-18 Speech Decoder Test Mode (DSP Interface Mode (TC1
µPD9930
Figure 2-19 Speech Decoder Test Mode (DSP Interface Mode (TC1
(ITC1)
(ITC2)
DRSTB
REQB
FSYNC kHz)
SCLK (256 kHz)
DCLK (104 kHz)
µPD9930
(ITC1) (ITC2) DRSTB REQB FSYNC kHz) SCLK (256 kHz) DCLK (104 kHz)
Figure 2-20 Acoustic Device Test Mode (DSP Interface Mode (TC1
Note
µPD9930
Note Interface Mode SCLK fixed high.
µPD9930
TONE INTERVAL OUTPUT FUNCTION (TIMER TERMINAL)
When tone generated, interval signal that indicates tone intermittent state output. function used, example, make blink synchronization with ringer tone. Figure Tone Interval Output Waveform
Tone generation
Continuous tone
Tone generation Tone stop (31.25 (31.25
Intermittent tone (when 31.25 on/off)
Tone generation (200
One-shot tone (200 one-shot)
Tone generation Tone stop
triple tone
µPD9930
INTERNAL CONTROL FUNCTIONS
PD9930 control internal functions commands from microcontroller. Commands consist 8bit data consisting register address setting data, written following internal registers.
Register name Voice send analog gain/receiver amplifier control register (TXGCR) Voice receive analog gain control register (RXGCR) Voice send/receive digital gain control register (DGGSR) Digital signal processing control register (DSPCR) Tone frequency selection register (FRQSR) Expanded tone register (EXPR1/EXPR2) Tone control register (TONCR) Tone gain control register (TNGCR) Power up/down control Control Voice send/receive gain control
Digital input/output control Tone control
Input/output amplifier control register (AMPCR) (10) Power control command (PUPCMD) (11) Power down control command (PDWCMD) (12) Test control register (TSTCR)
Test mode control
Remarks case registers (1), (2), (11), written contents executed instantly. registers (12), since fetch execution made internal clock (125 interval), keep more interval write-in same register. write-in same register executed continuously, previous command ignored. Even when stand-by mode, write-in each internal register possible (can held), command written register executed only after clearing stand-by mode. SEND/RECEIVE GAIN CONTROL outline send/receive gain control shown Figure 4-1. With PD9930, following send receive gain control possible.
Send/receive gain control Voice send gain control Pre-filter analog gain adjustment Digital gain fine adjustment -2.8 steps) Voice receive gain control Receiver amplifier analog gain adjustment (volume control) steps) Digital gain fine adjustment -2.4 steps) Register used Voice send analog gain/receiver amplifier control register (TXGCR) Voice send/receive digital gain control register (DGGSR) Voice receive analog gain control register (RXGCR) Voice send/receive digital gain control register (DGGSR)
µPD9930
Figure Send/Receive Gain Control
Register address
TXGCR REC2PDB TXAG
Digital signal-processor -2.8 (0.4 steps) Voice send digital gain control
Pre-filter/mixer Microphone input Accessory input Voice send analog gain control
Register address RXDG1 RXDG0
DGGSR TXDG2 TXDG1 TXDG0
Receiver amplifier Voice receive analog gain control steps) Voice receive digital gain control -2.4 (0.8 steps)
Receiver output
Register address RXAG4 RXAG3
RXGCR RXAG2 RXAG1 RXAG0
µPD9930
4.1.1 Voice Send Analog Gain/Receiver Amplifier Control Register (TXGCR) This register controls pre-filter gain. also controls receiver amplifier power up/down shown Table (Refer 2.1.6 Power Up/Down Control). When power down, contents register area retained. After power control continues before power down. Figure Voice Send Analog Gain/Receiver Amplifier Control Register
Register address TXGCR REC2PDB TXAG
REC2PDB
Receiver amplifier power up/down specification Power down Power
TXAG
Pre-filter analog gain specification Sets Sets
Table Function Specification Send Analog Gain/Receiver Amplifier Control Register
Register address TXGCR Receiver amplifier Power down Power down Power Power Voice send analog gain HEXNote Remarks reset
Note value with first value with first
µPD9930
4.1.2 Voice Receive Analog Gain Control Register (RXGCR) This 5-bit register controlling analog gain (volume) receiver amplifier Figure Voice Receive Analog Gain Control Register
Register address RXAG4 RXAG3 RXGCR RXAG2 RXAG1 RXAG0
RXAG4 RXAG0 Receiver amplifier gain specification 00000 11111 steps)
µPD9930
Table Function Specifications Voice Receive Analog Gain Control Register
Register address RXGCR Voice receive analog gain HEXNote Remarks
reset
Note value with first value with first
µPD9930
4.1.3 Voice Send/Receive Digital Gain Control Register (DGGSR) This 5-bit register adjusting gain digital signal processor. gain send system receive system fine-adjusted independently. Figure Send/Receive Digital Gain Control Register
Register address RXDG1 RXDG0
DGGSR TXDG2 TXDG1 TXDG0
RXDG1 RXDG0 Receive digital gain specification -2.4 (0.8 steps)
TXDG2 TXDG0 Send digital gain specification -2.8 (0.4 steps)
µPD9930
Table Function Specifications Voice Send/Receive Digital Gain Control Register
Register address DGGSR Voice receive digital gain -0.8 -0.8 -0.8 -0.8 -0.8 -0.8 -0.8 -0.8 -1.6 -1.6 -1.6 -1.6 -1.6 -1.6 -1.6 -1.6 -2.4 -2.4 -2.4 -2.4 -2.4 -2.4 -2.4 -2.4 Voice send digital gain -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 HEXNote Remarks reset
Note value with first value with first
µPD9930
DIGITAL INPUT/OUTPUT CONTROL outline digital input/output control shown Figure 4-5. PD9930 control input output digital signal processor follows.
Digital input/output control Voice send data operation processing execution/stop Connection disconnection tone output Voice send/ receive system Serial output terminal (SO) control Serial input terminal (SI) control Digital signal processing control register (DSPCR) Registers used
Caution must connect disconnect tone output voice send/receive system tone operation. causes malfunction. Figure Digital Input/Output Control
Register address TXACT
DSPCR TNACT SOACT SIACT
Digital signal processor
TXACT
SOACT DGND SIACT
Note TNACT
DGND
Tone generator
Note Connected when TXACT TNACT
µPD9930
4.2.1 Digital Signal Processing Control Register (DSPCR) This 4-bit register controlling digital signal processor input/output. Figure Digital Signal Processing Control Register
Register address TXACT DSPCR TNACT SOACT SIACT
TXACT
Voice send data processing control Stops voice send data digital processing. Executes voice send data digital processing.
TNACT
Tone output control Disconnects tone output from voice send/receive systems. Connects tone output voice send/receive systems.
SOACT
interface output control Sets serial output (SO) level
Note
Outputs send data tone data) serial output (SO).
SIACT
interface input control Sets serial input (SI) level
Note
Inputs receive data serial input (SI).
Note Test Control Register serial input/output terminal level, (refer 4.4.1 Test Control Register (TSTCR)). Caution Before specification SOACT bit, sure write SIOOFF Test Control Register. isn't written SIOOFF bit, serial output terminal level, regardless SOACT bit.
µPD9930
Table Function Specification Digital Signal Processing Control Register
Register address DSPCR Serial output control Note Note Control output Note Voice receive signal output Inhibiting command Inhibiting command Note Note Tone output Tone output Tone output HEXNote Remarks reset
Voice receive signal tone output Tone output
Voice receive signal tone output Inhibiting command Inhibiting command Note Voice receive signal output
Voice send signal output Voice send signal output
Inhibiting command Inhibiting command Voice send signal output Voice send signal output Tone output
Voice receive signal tone output
Notes value with first value with first Stops voice send data processing serial output. Stops voice receive data serial input tone output.
µPD9930
TONE CONTROL outline diagram tone generator shown Figure 4-7. Tone generation tone oscillation circuit tone oscillation circuit. tone oscillation circuit generates high group frequency DTMF four types single tones (tone frequency). tone oscillation circuit generates group frequency (tone frequency) DTMF. Dual tone output adding tone frequency. addition registered tones, other frequencies registered. Also, triple tone generated special command. Examples tone generation shown Figure 4-8. Tone control items shown below.
Tone control Tone frequency Registered tone Specification DTMF Single tone: kHz, Selection triple tone User registration tone Registration desired tone range. (Single tone, dual tone) Registers used Tone frequency selection register (FRQSR) Tone control register (TONCR) Tone frequency selection register (FRQSR) Expanded tone register (EXPR1) Expanded tone register (EXPR2) Generation pattern Registered pattern Desired pattern Gain 31.25 intermittence, intermittence, intermittence, intermittence, intermittence, one-shot tone Interrupted desired interval START/STOP command Tone gain control register (TNGCR) Tone control register (TONCR)
Control tone output gain steps), -38.5
Figure Tone Control
Register address
FRQSR FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
Register address Tone oscillation circuit Tone frequency 1209 1336 1477 1633 2000 2600
TNGCR TNGAIN4 TNGAIN3 TNGAIN2 TNGAIN1 TNGAIN0
dBm0
(1-dB steps) -38.5 output (receive signal) (Only sign code) Ringer output
Expanded tone register
Expanded tone frequency
TNACTNote START/ STOP Serial output
Tone oscillation circuit Tone frequency dBm0 Expanded tone register Expanded tone frequency Tone interval generation
Timer output
Note Digital signal processing control register (Refer Figure 4-6).
µPD9930
Register address TNMODE TNP2
TONCR TNP1 TNP0 START/ STOP
µPD9930
Figure Tone Generation Examples When generating busy tone (400 single tone, intermittence)
Busy tone generation DTMF generation
When generating DTMF with continuous tone
Tone gain control register tone gain.
Tone gain control register tone gain.
Tone frequency selection register frequency
Tone frequency selection register frequency DTMF "7".
Tone control register Select single tone Select intermittent pattern. START/STOP (start)
Tone control register Select dual tone. Select continuous tone. START/STOP (start)
When generating triple tone
When generating intermittent user register tone (480 single tone; coefficient 0111011100B)
triple tone generation
User register tone generation
Tone gain control register tone gain.
Tone gein control register tone gain.
Tone control register Select single tone Select triple tone START/STOP (start)
Tone frequency selection register Specify "user register"
Expanded tone register "100110" (registration command) registration data (lower order bits) setting
Expanded tone register Registration data (higher-order bits) setting
Tone control register Select single tone. Select intermittent pattern. START/STOP (start)
µPD9930
4.3.1 Tone Frequency Selection Register (FRQSR) This 5-bit register specifying tone (high group frequency DTMF four types single tones) tone (low group frequency DTMF) frequency combinations. Figure Tone Frequency Selection Register
Register address FRQSR
FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
FRQSEL4 FRQSEL0 00000 10100
Tone frequency selection Refer Table Function Specification Tone Frequency Selection Register.
Write operation this register instantaneously executed retained when command received, change tone generation generating tone executed only when written START/STOP control tone control register (refer Figure 4-11 Tone Control Register). When user registration tone selected, tone specified expanded tone register (refer Figure 4-10 Expanded Tone Frequency Registration Procedure) generated. Caution input command that sets tone oscillation frequency after inputting tone oscillation command (writing START/STOP control tone control register).
µPD9930
Table Function Specification Tone Frequency Selection Register
Register address FRQSR DTMF function DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF DTMF Tone frequency 1209 1336 1477 1633 1209 1336 1477 1633 1209 1336 1477 1633 1209 1336 1477 1633 HzNote HzNote
Note
HEXNote Tone frequency Indefinite value Indefinite value Indefinite value Indefinite value User registration Remarks
reset
kHzNote User registration Inhibiting command Inhibiting command Inhibiting command
Notes value with first value with first This single tone. When specifying this tone, sure specify tone control register single tone mode (refer Figure 4-11 Tone Control Register). Remark DTMF tone generation, specify tone control register dual tone mode (refer Figure 4-11 Tone Control Register). register specified single tone mode, only high group tone (tone frequency) generated.
µPD9930
4.3.2 Expanded Tone Registers (EXPR1, EXPR2) Expanded Tone Frequency Registration Procedure µPD9930 register desired tone frequencies (expanded tone frequencies) range. Expanded tone register (EXPR1) registering expanded tone frequency (high group frequency DTMF single tone). Expanded tone register (EXPR2) registering expanded tone frequency (low frequency DTMF). frequency must specified 10-bit coefficient (2's complement). Registration single tone done with EXPR1 (single-tone generation impossible EXPR2) (refer Figure 4-10 (a)). When registering dual tone, high group EXPR1 group EXPR2. Write operation this register executed continuously writing expanded tone registration command expanded tone data command (refer Figure 4-10). Once registered, frequency valid until reset updated. Figure 4-10 Expanded Tone Frequency Registration Procedure Expanded tone frequency registration procedure expanded tone registration command EXPR1. Expanded tone registration command EXPR1
higher-order bits expanded tone coefficient (expanded tone data command) EXPR1. Expanded tone data command EXPR1
Remark EA0: Tone frequency 10-bit coefficient Expanded tone frequency registration procedure expanded tone registration command EXPR2. Expanded tone registration command EXPR2
higher-order bits expanded tone coefficient (expanded tone data command) EXPR2. Expanded tone data command EXPR2
Remark EB0: Tone frequency 10-bit coefficient Caution After executing expanded tone registration command, next command written expanded tone data, continuously execute expanded tone data command.
µPD9930
Expanded Tone Data Determination Method coefficient tone frequency (0.3 kHz) generated determined following formula. fe/fs)
Coefficient Sign bits below decimal point (Coefficient: complement) Example When specifying single tone 400/8000) 0.1) (0.3141592653.) 0.951056516. (0.11110011X) Next, least significant determined. When (0.111100110) 0.94921875 COS-1 (0.94921875) 0.320052983 0.320052983 fs/(2) 407.504115 When (0.111100111) 0.951071875 COS-1 (0.951071875) 0.314109559 0.314109559 fs/(2) 399.524415 Since nearest coefficient registered (0.111100111) (1E7) (Higher-order bits determined.)
error oscillation frequency rounding 10-bit coefficient below (MAX. ±1.7 frequencies. About ±1.67 near About ±1.00 near About ±0.40 near About ±0.25 near About ±0.16 near Coefficient negative number kHz.
µPD9930
4.3.3 Tone Control Register (TONCR) This 5-bit register controlling single tone/dual tone specification, generation pattern selection, generation stopping. Figure 4-11 Tone Control Register
Register address TNMODE TNP2 TONCR TNP1 TNP0 START /STOP
TNMODE Single tone/dual tone specification Single tone mode Dual tone mode
Remarks reset
TNP2
TNP1
TNP0 Generation pattern selection Continuous tone generation 31.25 tone, 31.25 tone repeated tone, tone repeated tone, tone repeated tone, tone repeated tone, tone repeated triple tone generated Note interval tone generated (one shot tone)
Remarks reset
START/STOP Tone generation/stop control Stop ("1" "0", both valid) Note Validation tone ferquency selection register setting data, start generation ("1" "1", both valid)
Remarks reset
Notes tone 1400 tone 1800 tone tone repeated. input command that sets tone oscillation frequency after inputting tone oscillation command (writing START/STOP control tone control register). Remark When regeneration pattern specified "110", becomes triple tone command, tone generation forcibly enters single tone mode. Tone generation change tone that being generated executed only when written START/ STOP control bit) (refer Figure 4-11 Table 4-6).
µPD9930
Table Function Specification Tone Control Register
Register address TONCR Tone control conditions Tone stop Continuous single tone generation 31.25 intermittent single tone generation intermittent single tone generation intermittent single tone generation intermittent single tone generation intermittent single tone generation triple tone generation one-shot single tone generation Continuous dual tone generation 31.25 intermittent dual tone generation intermittent dual tone generation intermittent dual tone generation intermittent dual tone generation intermittent dual tone generation one-shot dual tone generation HEXNote
Note value with first Remark Don't care
value with first
4.3.4 Tone Gain Control Register (TNGCR) This 5-bit register controlling tone output gain. Figure 4-12 Tone Gain Control Register
Register address TNGCR
TNGAIN4 TNGAIN3 TNGAIN2 TNGAIN1 TNGAIN0
TNGAIN4 TNGAIN0 00000 11111
Tone gain selection (Refer Table Function Specification Tone Gain Control Register). steps), -38.5
µPD9930
Table Function Specification Tone Gain Control Register
Register address TNGCR Tone gain -38.5 HEXNote Remarks
reset
Note value with first value with first
µPD9930
TEST MODE CONTROL PD9930 following test functions.
Test function test function This test function stipulated GSM11.10. Test mode selection controlled external terminal (TC1 TC2) internal register (ITC1, ITC2). Send data after processing input LPF. SCLK terminals level. Registers used Test control register (TSTCR)
Analog loopback function interface input/ output control function
outline test mode control shown Figure 4-13.
µPD9930
Figure 4-13 Test Mode Operation
(speech encoder test mode)
(speech decoder test mode)
Mobile Station
Mobile Station
PD9930
PD9930
speech encoder
speech decoder
System simulator
System simulator
(A/D, test mode)
Analog loopback mode
Mobile Station
PD9930
PD9930
System simulator
µPD9930
4.4.1 Test Control Register (TSTCR) This 5-bit control register selecting test mode. ITC1, ITC2 become valid rising edge DRSTB. precautions when using DAI, refer 2.1.9 (Digital Audio Interface). Figure 4-14 Test Control Register
Register address TCMODE ITC2 TSTCR ITC1 LOOPBK SIOOFF
TCMODE test mode control method selection
Remarks
Specification test mode external terminals reset Specification test mode test control registers ITC1 ITC2
ITC2
ITC1
test mode specification Normal operation Speech encoder test mode Speech decoder test mode Acoustic device, A/D, test mode
Remarks reset
LOOPBK
Analog loopback specification Normal operation Analog loopback
Remarks reset
SIOOFF
interface input/output terminal control Normal operation
Remarks
Setting terminals SCLK, level reset
Remark analog loopback mode test mode cannot specified same time.
µPD9930
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS 25°C, DGND AGND1 AGND4
Item Supply Voltage Analog Input Voltage Digital Input Voltage Analog Output Applied Voltage Digital Output Applied Voltage Operating Ambient Temperature Storage Temperature Symbol VAIN VDIN VAOUT VDOUT Tstg Conditions AVDD1, AVDD2, DVDD analog input pins digital input pins analog output pins digital output pins Ratings -0.3 +5.5 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 +150 Unit
Cautions Connect AGND1 through AGND4 pins DGND analog ground line near µPD9930 pins. Connect DVDD, AVDD1, AVDD2 pins analog power supply line near µPD9930 pins. connect output (and bidirectional) pins each other. connect output bidirectional) pins directly VDD, VCC, line. However, open drain open collector directly connected VDD, VCC, line. timing design made that signal conflict occurs, three-state pins also connected directly three-state pins external circuit. Exposure Absolute Maximum Ratings extended periods affect device reliability; exceeding ratings could cause permanent damage. parameters apply independently. device should operated within limits specified under Characteristics.
µPD9930
RECOMMENDED OPERATING RANGE +85°C) Condition
Item Supply Voltage High Level Input Voltage Level Input Voltage Analog Input Voltage Microphone Input Analog Input Voltage Gain Setting Range Load Resistance Load Capacitance Accessory Input Analog Input Voltage Gain Setting Range Load Resistance Load Capacitance Pre-filter Mixer Input Analog Input Voltage Accessory Output Load Resistance Load Capacitance Receiver Output Load Resistance Load Capacitance Receiver Output Analog Input Voltage Gain Setting Range Load Resistance Load Capacitance Reference Voltage Output Load Capacitance CLACOM XACOMO, RACOMO VREC2 GREC2 RLREC2 CLREC2 REC2ISet with external resistor series series Vp-p RLREC1 CLREC1 RLAUXO CLAUXO VMIXI MIXI Vp-p VAUXI GAUXI RLAUXI CLAUXI XAUXI- with external resistor Includes gain setting resistance Vp-p VMIC GMIC RLMIC CLMIC Differential: MICI+, MICI- with external resistor Includes gain setting resistance Vp-p Symbol Conditions AVDD1, AVDD2, DVDD digital input pins digital input pins analog input pins MIN. TYP. MAX. Unit
Frame Signal (FSYNC) Reset Signal (RESETB)
Item FSYNC Frequency FSYNC High Level Width FSYNC Level Width FSYNC Rise Time FSYNC Fall Time RESETB Level Width Symbol tWHS tWLS tRSL Conditions MIN. 7.995 TYP. 8.000 MAX. 8.005 Unit
µPD9930
Microcontroller Interface
Item MCLK Cycle Time MCLK High Level Width MCLK Level Width MCLK Rise Time MCLK Fall Time MDAT Setup Time MSTR MDAT Hold Time from MCLK MSTR High Level Width MCLK Setup Time MSTR MSTR Setup Time MCLK Symbol tMCY tMCH tMCL tSUMDA tHMDA Conditions MIN. TYP. MAX. Unit
tWMST tSUMCK tSUMST
Interface
Item Setup Time SCLK Hold Time from SCLK Symbol tSUSI tHSI Conditions MIN. TYP. MAX. Unit
Item Setup Time DCLK Hold Time from DCLK TC1, Rise Time TC1, Fall Time DRSTB Level Width DRSTB Rise Time DRSTB Fall Time Mode Setting Time Mode Setting Time REQB Level Width REQB High Level Width REQB Rise Time REQB Fall Time Symbol tSUDI tHDI tDRSL tDRR tDRF tTCF tTCR tDRQL tDRQH tDRQR tDRQF Conditions MIN. TYP. MAX. Unit
µPD9930
CAPACITANCE 25°C)
Item Digital Output Capacitance Digital Input Capacitance Symbol Conditions MIN. TYP. MAX. Unit
CHARACTERISTICS 25°C, Current Consumption
Item Circuit Current Normal Mode Symbol IDD1
(GND standard))
Conditions Microphone input (1020 dBm0) Accessory input: Power down serial input (1020 dBm0) Accessory output: Power Receiver Power Microphone input (1020 dBm0) Accessory input: Power down serial input (1020 dBm0) Accessory output: Power Receiver Power DRSTB, TC1, TC2: Open FSYNC: Other digital input pins:
MIN.
TYP.
MAX.
Unit
Circuit Current Operation
IDD2
10.0
Circuit Current Standby Mode
IDD3
Digital Part
Item Digital Input Leak Current Symbol Pull-Up/Down Current Level Output Voltage High Level Output Voltage -2.0 -1.0 Conditions MIN. TYP. MAX. Unit
µPD9930
Analog Part
Item Pre-filter Mixer Volume Range Volume Accuracy Cross-Talk between Input Channels GPRF GPRF CTIN1 Volume standard Microphone input amplifier: Power down MICI Vp-p XAUXI- Vp-p Accessory input gain setting: Accessory input amplifier: Power down MICI Vp-p XAUXI- Vp-p Accessory input gain setting: -3.2 -3.0 -2.8 Symbol Conditions MIN. TYP. MAX. Unit
Cross-Talk between Input Channels
CTIN2
Accessory Output Maximum Output Voltage Receiver Output Maximum Output Voltage Volume Range Volume Accuracy VR1MAX Vp-p VAMAX Vp-p
GREC1 GREC1 Volume: VolumeNote:
-1.5 -2.0 -1.0 -1.0
-0.5
Receiver Output Maximum Output Voltage Reference Voltage Output Output Voltage VACOM XACOMO, RACOMO VR2MAX Distortion factor (MAX.) Vp-p
Note Simple decrease gain drop volume guaranteed. Tone Generator
Item Output Signal Level Symbol VTN1 VTN2 Frequency Deviation Distortion Factor Tone Volume Range Tone Volume Accuracy TNSD Volume: steps) Tone Tone Accessory output Conditions MIN. -2.93 -5.93 -38.5 -1.4 -1.0 -0.8 TYP. MAX. -2.73 -5.73 Unit dBm0
µPD9930
CHARACTERISTICS Interface +85°C,
Item SCLK Cycle Time SCLK High Level Width SCLK Level Width SCLK Rise Time SCLK Fall Time SCLK Delay Time from FSYNC Delay Time from FSYNC Delay Time from SCLK Mode Delay Time from SCLK Mode Output Delay Time from SCLK Mode Output Delay Time from SCLK Mode Symbol tSCY tSCH tSCL tDSCLK
Conditions MIN. TYP. 3906 1953 1953 MAX. Unit
tDSENR
tDSENF
tDSO
+85°C,
Item DCLK Cycle Time DCLK High Level Width DCLK Level Width DCLK Rise Time DCLK Fall Time DCLK Delay Time from FSYNC Output Delay Time from DCLK
Conditions MIN. TYP. 9615 4808 4808 MAX. Unit
Symbol tDCY tDCH tDCL tDDCLK
tDDO
Others (Digital Output) +85°C,
Item TIMER/RINGER Rise Time TIMER/RINGER Fall Time Symbol tDDR tDDF
MIN. TYP. MAX. Unit
Conditions TIMER RINGER TIMER RINGER
µPD9930
Frame signal (FSYNC)
1/fs tWHS
FSYNC
tWLS
Remark During normal operation power up/down sequence, sure input frame signal. Reset signal (RESETB)
RESETB
tRSL
Remarks reset signal input without shaping, take full precautions against noise. power reset circuit incorporated, sure RESET after turning power Microcontroller interface timing
tWMST
MSTR
tMCY
tMCH
tSUMCK
tSUMST
MCLK
tSUMDA tHMDA
tMCL
MDAT
Remark Microcontroller command (LSB first)
µPD9930
interface timing (mode
SCLK
tDSCLK
tSCY
tSCL
tSCH
FSYNC
tDSENR
tDSENF
tDSO
tSUSI
tHSI
don't care
don't care
interface timing (mode
SCLK
tDSCLK
tSCY
tSCH
tSCL
FSYNC
tDSENF
tDSENR
tDSO
tSUSI
tHSI
don't care
don't care
µPD9930
input timing
FSYNC
tDDCLK
tDCY
tDCH
DCLK
tSUDI
tHDI
tDCL
Remark Input data (MSB first) output timing
FSYNC
tDDCLK
tDCY
tDCH
DCLK
tDDO
tDCL
Remark Output data (MSB first)
µPD9930
TC1, TC2, DRSTB input timing
TC1,
tTR,
tTCF tDRF
tTCR tDRR
tTR,
DRSTB
tDRSL
TIMER, RINGER output timing
tDDR
tDDF
TIMER, RINGER
REQB input timing
tDRQF
tDRQR tDRQH
REQB
tDRQL
µPD9930
TRANSMISSION CHARACTERISTICS Transmission characteristics indicated below unless otherwise specified. Analog input Analog input signal (-10 dBm0, 1020 accessory input part Accessory input: gain Microphone input: Power down Pre-filter mixer: gain Analog output Analog output signal accessory output part Receiver output: Power down Digital gain Send receive: Digital input signal level: dBm0 25°C,
(GND standard)
Send/Receive Zero Transmission Level dBm0 level)
Item Send Zero Transmission Level Receive Zero Transmission Level Symbol V0TLPX standard standard Conditions MIN. TYP. -8.4 MAX. Unit
V0TLPR
-8.4
Gain Characteristics
Item Send Gain Deviation Receive Gain Deviation Send Gain Deviation Temperature Power Fluctuation Receive Gain Deviation Temperature Power Fluctuation Symbol Conditions MIN. -0.5 -0.5 -0.4 TYP. MAX. +0.5 +0.5 +0.4 Unit
-0.4
+0.4
Transmission Loss Level
Item Send Transmission Loss Level Symbol dBm0 dBm0 dBm0 Receive Transmission Loss Level dBm0 dBm0 dBm0 Conditions MIN. -0.4 -0.6 -1.2 -0.4 -0.6 -1.2 TYP. MAX. +0.4 +0.6 +1.2 +0.4 +0.6 +1.2 Unit
µPD9930
Transmission Gain Frequency Characteristics
Item Send Transmission Gain Frequency Characteristics Symbol GRX1 GRX2 GRX3 GRX4 GRX5 GRX6 GRX7 Receive Transmission Gain Frequency Characteristics GRR3 GRR4 GRR5 GRR6 GRR7 more more -0.3 -0.65 -0.8 -2.5 -0.3 -0.65 -0.8 Conditions MIN. TYP. MAX. +0.3 +0.3 +0.3 +0.3 Unit
Noise Characteristics
Item Send Noise Symbol Conditions Microphone power down, XAUXI- ACOM, gain message filter message filter, input code from MIN. TYP. MAX. Single Frequency Noise Cross-Talk between Send Receive Channels CTTR Send input Receive output sidetone pass, microphone power down input dBm0 1020 from XAUXI- input code from sidetone pass, microphone power down XAUXI- ACOM input dBm0 1020 from ±100 mV0-p signal application Unit dBrnc0 dBm0c dBrnc0 dBm0c dBm0
Receive Noise
NRC1
Cross-Talk between Receive Send Channels
CTRT
Power Supply Voltage Variation Rejection
PSRR
µPD9930
Distortion Factor Characteristics
Item Send Channel Total Power Distortion Factor
Symbol dBm0 dBm0 dBm0
Conditions
MIN.
TYP.
MAX.
Unit
Receive Channel Total Power Distortion Factor
dBm0 dBm0 dBm0
Absolute Delay Delay Distortion Frequency Characteristics
XAUXI- RAUXO XAUXI- RAUXO
1.40 0.70 0.20 0.20 1.40
Send Transmission Gain Frequency Characteristics (GRX)
Send transmission gain (dB)
Frequency (kHz)
µPD9930
Send Transmission Gain Frequency Characteristics (GRX)
-0.1
-0.2
Send transmission gain (dB)
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
Frequency (kHz)
Receive Transmission Gain Frequency Characteristics (GRR)
Receive transmission gain (dB)
Frequency (kHz)
µPD9930
Receive Transmission Gain Frequency Characteristics (GRR)
-0.1
-0.2
Receive transmission gain (dB)
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
Frequency (kHz)
µPD9930
Send/receive zero transmission level dBm0 level) explained below your reference. Send zero transmission level Analog output signal level which digital input signal level converter becomes dBm0. Receive zero transmission level Analog input signal level which digital output signal level converter becomes dBm0. Analog signal level (dBm) conversion expression amplitude voltage signal analog signal level follows: logW analog signal level (dBm) analog signal power (mW) (V2/R) effective value analog signal (AC) (Vrms) resistance With µPD9930, signal voltage (effective value) calculated -8.4 substituted. 0.1445 (mW) 0.294 (Vrms) calculate V0-p, multiply signal voltage (effective value) V0-p 0.416 Digital signal level (dBm0) Signal level where level full swing digital output value converter digital input value converter considered 3.17 dBm0 (the amplitude analog signal Vp-p where gain microphone input accessory input dB). <Level diagram> This diagram indicates range which adjustments made using each amplifier gain control function. Example: Input level which digital output linear codec dBm0 dBm. (Conditions) Microphone amplifier gain during microphone input: Analog gain control: Digital gain control: Output level which digital input linear codec dBm0 -18.4 dBm. (Conditions) During receiver output Analog gain control: Digital gain control:
µPD9930
Voice send level diagram (microphone input)
Vref [dBm]
Analog gain control
Digital gain control
[dBm0] -2.8 (0.4 steps) dBm0 -33.4 -15.8 dBm0
-41.4
Remarks Thick line: Indicates case where gain microphone amplifier gain analog gain control gain digital gain control Thin line: Indicates case where gain microphone amplifier gain analog gain control gain digital gain control -2.8 Overload level: 3.17 dBm0.
µPD9930
Voice receive level diagram (receiver output)
Receiver [dBm]
Analog gain control
Digital gain control -2.4 (0.8 steps)
steps)
[dBm0]
-18.4 dBm0
-51.8
Remarks Thick line: Indicates case where gain analog gain control gain digital gain control Thin line: Indicates case where gain analog gain control gain digital gain control -2.4 Overload level: 3.17 dBm0.
µPD9930
Voice send level diagram (accessory input)
Vref [dBm]
Analog gain control
Digital gain control
[dBm0] -18.4 -15.8 dBm0 -28.4 -2.8 (0.4 steps) dBm0
Remarks Thick line: Indicates case where gain microphone amplifier gain analog gain control gain digital gain control Thin line: Indicates case where gain microphone amplifier gain analog gain control gain digital gain control -2.8 Overload level: 3.17 dBm0.
µPD9930
Voice receive level diagram (accessory output)
[dBm]
Accessory output (fix)
Digital gain control -2.4 (0.8 steps)
[dBm0]
-18.4 -20.8 dBm0
Remarks Thick line: Indicates case where gain digital gain control Thin line: Indicates case where gain digital gain control -2.4 Overload level: 3.17 dBm0.
APPLIED CIRCUIT EXAMPLE
MICO MICI- MICI+
From RESET circuit
From
AGND4
AGND3
AGND2
AGND1
DGND
FSYNC
RESETB
REQB
MIXI Accessory input XAUXI- XACOMI XACOMO RACOMO Note RACOMI REC2O+ REC2O- REC2I- RAUXO REC1O XAUXO
DSPSEL
(mode (mode
RINGER Low-current drive TIMER
Microcontroller DSUB socket pin)
PD9930G-22
DCLK DRSTB MCLK MDAT
MSTR
SCLK
AVDD1
AVDD2
TEST
DVDD
µPD9930
Accessory output
REQB
Note When connecting dynamic receiver, drive amplifier.
µPD9930
PACKAGE DRAWINGS PLASTIC
detail lead
5°±5°
P44G-80-22-2 ITEM MILLIMETERS 13.6 10.0 10.0 13.6 0.35 0.10 0.15 (T.P.) 0.15+0.10 -0.05 0.15 1.45 0.05 0.05 1.65 MAX. INCHES 0.535+0.017 -0.016 0.394+0.008 -0.009 0.394+0.008 -0.009 0.535+0.017 -0.016 0.039 0.039 0.014+0.004 -0.005 0.006 0.031 (T.P.) 0.071+0.008 -0.009 0.039+0.009 -0.008 0.006+0.004 -0.003 0.006 0.057+0.005 -0.004 0.002 0.002 0.065 MAX.
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
µPD9930
RECOMMENDED SOLDERING CONDITIONS
following conditions must soldering conditions µPD9930. more details, refer document "Semiconductor Device Mounting Technology Manual" (C10535E). Please consult with sales offices case other soldering process used, case soldering done under different conditions. Type Surface Mount Device
µPD9930G-22: 44-pin plastic
Soldering process Infrared reflow Soldering conditions Peak temperature package surface: 235°C below, Reflow time: seconds below (210°C higher), Number reflow processes: MAX. Exposure limitNote: days hours pre-baking required 125°C afterwards) Peak temperature package surface: 215°C below, Reflow time: seconds below (200°C higher), Number reflow processes: MAX. Exposure limitNote: days hours pre-baking required 125°C afterwards) Wave soldering Soldering bath temperature: 260°C below, Reflow time: seconds below, Number reflow processes: Preheating temperature: 120°C MAX. (package surface temperature) Exposure limitNote: days hours pre-baking required 125°C afterwards) WS60-107-1 Symbol IR35-107-2
VP15-107-2
Partial heating method Terminal temperature: 300°C below, Time: seconds below (Per side device).
Note Exposure limit before soldering after dry-pack package opened. Storage conditions: 25°C relative humidity less. Caution apply more than soldering method time, except "Partial heating method".
µPD9930
[MEMO]
µPD9930
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD9930
[MEMO]
export this product from Japan prohibited without governmental license. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
application circuits their parameters reference only intended actual design-ins.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD9930 LINEAR CODEC DIGITAL CELLULAR TELEPHONE µPD9930 sing

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