µPD78P4916 16-BIT SINGLE-CHIP MICROCONTROLLER µPD78P4916 µPD

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µPD78P4916 16-BIT SINGLE-CHIP MICROCONTROLLER µPD78P4916 µPD

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INTEGRATED CIRCUIT
µPD78P4916
16-BIT SINGLE-CHIP MICROCONTROLLER
µPD78P4916 µPD784915 subseries 78K/IV Series microcontrollers which incorporate high-speed high-performance 16-bit CPU. µPD78P4916 replaces mask with one-time PROM increases on-chip capacity compared µPD784915. suitable evaluation system development small quantity production. Detailed descriptions functions provided following user's manuals. sure read these documents when designing.
µPD784915 Subseries User's Manual Hardware U10444E
78K/IV Series User's Manual Instruction U10905E
FEATURES
High-speed instruction execution using 16-bit core Minimum instruction execution time: 8-MHz internal clock) On-chip high capacity memory PROM Kbytes Note Note 2048 bytes Note
possible change capacity internal PROM internal specifying internal memory capacity select (IMS) register.
ORDERING INFORMATION
Part Number Package 100-pin plastic
µPD78P4916GF-3BA
information this document subject change without notice. Document U11045EJ1V0DS00 (1st edition) Date Published April 1996 Printed Japan
mark
shows major revised points.
1996
µPD78P4916
78K/IV Series Products
78K/IV Series
mPD784915 Subseries Subseries
78K/I Series
High-performance 16-bit core High-speed operation On-chip analog circuit
µPD78148 Subseries µPD78138 Subseries
Enhanced peripheral hardware
µPD78P4916
Function List (1/2)
Item Internal PROM capacity Internal capacity Operation clock Kbytes
Note
Function
2048 bytes Note (Internal clock: MHz) frequency oscillation mode: (Internal clock: MHz) power consumption mode: 32.768 (Subsystem clock) 8-MHz internal clock) Total: Input: I/O:
Minimum instruction execution time ports
Real-time output port
(including outputs each Pseudo-VSYNC Head amplifier switch, Chrominance rotate) Timer/counter (16-bit) (16-bit) (22-bit) (16-bit) (5-bit) (8-bit) (8-bit) Compare register Number bits Capture register Measurement cycle 65.5 65.5 Remark
Super timer unit
Timer/counter
Generates signal Divides signal Operation edge
Capture register
Input signal VSYNC TREEL SREEL
Special circuit
VSYNC separator, HSYNC separator VISS detector, Wide-aspect detector Field identifier Head amplifier switch/chrominance rotate output circuit Timer (16-bit) (16-bit) (16-bit) Compare register (Capture/compare) Capture register
General purpose timer
output
16-bit precision: channels (Carrier frequency: 62.5 kHz) 8-bit precision: channels (Carrier frequency: 62.5 kHz) 3-wire serial I/O: channels BUSY/STRB control available (only channel) 8-bit resolution channels, conversion time:
Serial interface
converter
Note
possible change capacity internal PROM internal specifying internal memory capacity select (IMS) register.
µPD78P4916
Function List (2/2)
Item Analog unit Function amplifier RECCTL driver (supports re-write operation) amplifier, comparator, amplifier DPFG separator (Three-value) Reel comparator channels) CSYNC comparator
Interrupt External
Programmable levels, vectored interrupt, macro service, context switching (including NMI) (including software interrupt) HALT mode/STOP mode Low-power consumption mode: HALT mode Release from STOP mode pin's active edge, Watch interrupt (INTW), INTP1/INTP2/KEY0-KEY4 pins' input.
Internal Standby function
Watch function Power supply voltage Package
0.5-sec interval, capable low-voltage operation (VDD 100-pin plastic
µPD78P4916
Configuration (Top View)
Normal Operation Mode 100-pin plastic
µPD78P4916GF-3BA
CSYNCIN REEL0IN/INTP3 REEL1IN DFGIN DPGIN CFGCPIN CFGAMPO CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECTTL- RECTTL+ CTLDLY AVSS2 ANI11 ANI10
P65/HWIN P66/PWM4 P67/PWM5 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 PWM0 PWM1 SCK2 SI2/BUSY RESET PTO02 PTO01 PTO00 P87/PTO11 P86/PTO10 P85/PWM3 P84/PWM2 P83/ROTC P82/HASW
ANI9 ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVDD2 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV INTP0 INTP1 INTP2
Caution Connect (Internally Connected) directly.
µPD78P4916
ANI0-ANI11 AVDD1, AVDD2 AVSS1 AVSS2 AVREF BUSY CFGAMPO CFGCPIN CFGIN CSYNCIN CTLDLY CTLIN DFGIN DPGIN HASW HWIN INTP0-INTP3 KEY0-KEY4 Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Serial Busy Buzzer Output Capstan Amplifier Output Capstan Capacitor Input Analog Unit Input Clock Output Analog Unit Input Control Delay Input Amplifier Input Capacitor Analog Unit Input Analog Unit Input Envelope Input Head Amplifier Switch Output Hardware Timer External Input Internally Connected Interrupt From Peripherals Return Nonmaskable Interrupt P00-P07 P40-P47 P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96 PTO00-PTO02, PTO10, PTO11 PWM0 PWM5 Pulse Width Modulation Output RECCTL+, RECCTL- RECCTL Output/PBCLT Input REEL0IN, REEL1IN Analog Unit Input RESET ROTC SCK1, SCK2 SI1, SO1, STRB VREFC XT1, Reset Chrominance Rotate Output Serial Clock Serial Input Serial Output Serial Strobe Power Supply Reference Amplifier Capacitor Ground Crystal (Main System Clock) Crystal (Subsystem Clock) Port0 Port4 Port5 Port6 Port7 Port8 Port9 Programmable Timer Output
CTLOUT1, CTLOUT2 Amplifier Output
µPD78P4916
PROM Programming Mode 100-pin plastic
µPD78P4916GF-3BA
OPEN
OPEN OPEN
OPEN
OPEN
OPEN OPEN RESET IC/VPP OPEN
10099 9695 9190 8685 3536 4041 4546
Cautions
Connect pull-down resistors individually. Connect ground.
OPEN Leave this unconnected. RESET Apply level. Address Data Chip Enable Output Enable Program RESET Reset Power Supply Programming Power Supply Ground
µPD78P4916
Internal Block Diagram
INTP0 INTP3 PWM0 PWM5 PTO00 PTO02 PTO10, PTO11 VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTL CTLDLY AVDD1, AVDD2 AVSS1, AVSS2 AVREF ANI0 ANI11 1536 bytes Kbytes Port0 Port4 Port5 Serial Interface Port6 Port7 Port8 Port9 Super Timer Unit System Control Interrupt Control
RESET Used PROM programming mode
Clock Output Buzzer Output 78K/IV 16-bit Core (RAM bytes)
Input
KEY0 KEY4
Analog Unit Converter
Real-Time Output Port P80, P82,
SCK1 SI2/BUSY SCK2 STRB Serial Interface
P80,
µPD78P4916
System Configuration Example Camcorder
PD78P4916
Drum motor Driver DFGIN DPGIN PORT PORT PWM0 PORT SCK1 INTP0 Capstan motor Driver PWM1 INTP0 Microcontroller camera control PD78356 PORT matrix
CFGIN
head
RECCTL+ RECCTL- PORT SCK2 BUSY PORT
Camera block DATA BUSY
Loading motor
Driver
PWM2
PD7225
display panel Composite sync signal Audio-video signal processor Video head switch Audio head switch Pseudo-vertical sync signal Signals from remote controller Remote control receive signal CSYNCIN PORT PTO00 PTO01 STRB DATA BUSY
PD6456
INTP2
PORT
Mechanical block
PC2800A
32.768
µPD78P4916
Deck-type
PD78P4916
Drum motor DFGIN DPGIN PORT SCK1 DOUT PD16311
Driver
PWM0
CFGIN PORT SCK2
matrix
Capstan motor
Driver
PWM1
PD6454 DATA
head
RECCTL+ RECCTL-
PORT CSYNCIN PTO00 Composite synchronous signal Video head switch Audio head switch Pseudo-vertical synchronous signal Audio-video signal processor unit
Loading motor
Driver
PWM2
PTO01
Reel
REEL0IN PWM5
Reel motors
Driver
PWM3
Tuner unit PORT
Driver
PWM4
PORT
Mechanical block
Reel
REEL1IN INTP2 Low-frequency oscillation mode
Remote control receive signal
Signals from remote controller
PC2800A
32.768
µPD78P4916
CONTENTS
DIFFERENCES BETWEEN µPD78P4916 µPD784915, µPD784916A FUNCTION
Normal Operation Mode PROM Programming Mode (VPP RESET Circuits Recommended Connection Unused Pins
INTERNAL MEMORY CAPACITY SELECT REGISTER (IMS) PROM PROGRAMMING
Operation Mode PROM Write Procedure PROM Read Procedure Screening One-time PROM Versions
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX SOCKET DRAWING RECOMMENDED FOOTPRINT APPENDIX RELATED DOCUMENTS
µPD78P4916
DIFFERENCES BETWEEN µPD78P4916 µPD784915, µPD784916A
Other than memory types, their capacities, memory-related points, functions three devices identical: PD78P4916 incorporates one-time PROM that rewritable users, while µPD784915 784916A contain mask ROMs. Table shows differences among these devices. sure keep mind these differences especially when debugging pre-producing application system with PROM version then mass-producing with mask-ROM version. details about functions on-chip hardware, refer µPD784915 Subseries User's Manual-Hardware (U10444E). Table 1-1. Differences among µPD784915 Subseries Devices
Parameters Internal
µPD78P4916
One-time PROM KbytesNote
µPD784915
Mask Kbytes 1280 bytes provided
µPD784916A
Mask Kbytes 1280 bytes provided
Internal Internal memory size select register (IMS) Pinouts Other
2048 bytesNote Provided
Pins related PROM writing reading provided µPD78P4916. There differences noise immunity, noise radiation, some electrical specifications, because differences circuit complexity mask layout.
Note
internal PROM capacities µPD78P4916 changed through internal memory size select register (IMS).
Caution There differences noise immunity noise radiation between PROM mask-ROM versions. When pre-producing application with PROM version then massproducing with mask-ROM version, sure conduct sufficient evaluations using consumer samples (not engineering samples) mask-ROM version.
µPD78P4916
FUNCTION Normal Operation Mode
Port Pins
Name Input/Output Alternate function Real-time output port Description 8-bit input/output port (Port0) Specifiable input output mode bitwise. With software-specifiable on-chip pull-up resistors (P00 P07). 8-bit input/output port (Port4) Specifiable input output mode bitwise. With software-specifiable on-chip pull-up resistors (P40 P47). 8-bit input/output port (Port5) Specifiable input output mode bitwise. With software-specifiable on-chip pull-up resistors (P50 P57). 8-bit input/output port (Port6) Specifiable input output mode bitwise. With software-specifiable on-chip pull-up resistors (P60 P67).
STRB/CLO SCK1/BUZ HWIN PWM4 PWM5
Input
ANI0 ANI7 Real-time output port
8-bit input port (Port7) Pseudo-V SYNC output HASW output ROTC output 7-bit input/output port (Port8) Specifiable input output mode bitwise. With software-specifiable on-chip pull-up resistors (P80, P87)
PWM2 PWM3 PTO10 PTO11 KEY0 KEY4 7-bit input/output port (Port9)
Specifiable input output mode bitwise. With software-specifiable on-chip pull-up resistors (P90 P96).
µPD78P4916
Non-Port Pins (1/2)
Name REEL0IN REEL1IN DFGIN DPGIN CFGIN CSYNCIN CFGCPIN CFGAMPO PTO00 PTO01 PTO02 PTO10 PTO11 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 HASW ROTC SCK1 SCK2 BUSY STRB ANI0 ANI7 ANI8 ANI11 CTLIN CTLOUT1 CTLOUT2 RECCTL+, RECCTL- CTLDLY VREFC Output Input Output Output Input Input Output Input Output Input Output Analog inputs Output Output Output Input/Output Input Alternate function INTP3 P61/BUZ BUSY P60/CLO amplifier input capacitor amplifier output Logic input/CTL amplifier output RECCTL output/PBCTL input External time-constant connection rewrite RECCTL) ground VREF amplifier Non-maskable interrupt request input Head amplifier switch output Chrominance rotate output Envelope input Serial data input (Serial interface channel Serial data output (Serial interface channel Serial clock input/output (Serial interface channel Serial data input (Serial interface channel Serial data output (Serial interface channel Serial clock input/output (Serial interface channel Serial busy input (Serial interface channel Serial strobe output (Serial interface channel Analog inputs converter outputs super timer unit Drum input (Three-value) Drum input Capstan input Composite SYNC input comparator input amplifier output Programmable timer outputs super timer unit Reel inputs Description
µPD78P4916
Non-Port Pins (2/2)
Name INTP0 INTP2 INTP3 KEY0 KEY4 HWIN RESET AVDD1, AVDD2 AVSS1, AVSS2 AVREF Input/Output Input Input Input Output Output Input Input Input Input Crystal resonator connection subsystem clock oscillation Crystal resonator connection clock oscillation watch Positive power supply analog unit analog unit Reference voltage input converter Positive power supply digital unit digital unit Internally connected. Connect directly VSS. Alternate function REEL0IN P60/STRB P61/SCK1 input signal Clock output Buzzer output Hardware timer external input Reset input Crystal resonator connection main system clock oscillation Description External interrupt request input
PROM Programming Mode (VPP RESET
name Input/output Function PROM programming mode High voltage applied program write/verify operation level input setting PROM programming mode Address input Input Data input/output Program inhibit input PROM programming mode PROM enable input programming pulse input Read strobe input PROM Positive power supply potential
RESET
Input
µPD78P4916
Circuits Recommended Connection Unused Pins
Table shows input/output circuit types device's pins recommended connection pins which unnecessary user's application. circuit diagrams circuits shown Figure 2-1. Table 2-1.
Pins P00-P07 P40-P47 P50-P57 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 P65/HWIN P66/PWM4 P67/PWM5 P70/ANI0-P77/ANI7 P82/HASW P83/ROTC P84/PWM2 P85/PWM3 P86/PTO10 P87/PTO11 P90/ENV P91/KEY0-P95/KEY4 SI2/BUSY SCK2 ANI8-ANI11 RECCTL+, RECCTL-
Circuits Recommended Connection Unused Pins (1/2)
circuit types Direction Recommended connection unused pins Input mode: Connect Output mode: Leave unconnected.
Input Connect VSS. Input mode: Connect Output mode: Leave unconnected.
Input Output Input
Connect High-impedance mode: Connect pull-down resistor. Otherwise: Leave unconnected. Input mode: Connect Output mode: Leave unconnected. Connect VSS. When ENCTL ENREC Connect
Remark ENCTL: amplifier control register (AMPC) ENREC: amplifier mode register (AMPM0)
µPD78P4916
Table 2-1.
Pins DFGIN DPGIN CFGIN, CFGCPIN CSYNCIN REEL0IN/INTP3, REEL1IN CTLOUT1 CTLOUT2 CFGAMPO CTLIN VREFC CTLDLY PWM0, PWM1 PTO00-PTO02 INTP0 INTP1, INTP2 AVDD1 AVDD2 AVREF AVSS1, AVSS2 RESET
Circuits Recommended Connection Unused Pins (2/2)
circuit types Direction Input Recommended connection unused pins ENDRUM Connect VSS. ENDRUM ENDRUM SELPGSEPA Connect VSS. ENCAP Connect ENCSYN Connect ENREEL Connect VSS. Leave unconnected. When ENCTL ENCOMP Connect ENCTL Leave unconnected. Leave unconnected. When ENCTL Leave unconnected. When ENCTL, ENCAP, ENCOMP Leave unconnected. Leave unconnected. Leave unconnected. Connect Connect Connect Connect Connect VSS. Connect VSS. Leave unconnected. Connect directly VSS.
Output Output
Output Input Input
Remark
ENDRUM: ENCAP: ENCSYN: ENREEL: ENCTL: ENCOMP:
amplifier control register (AMPC) amplifier control register (AMPC) amplifier control register (AMPC) amplifier control register (AMPC) amplifier control register (AMPC) amplifier control register (AMPC)
SELPGSEPA: amplifier mode register (AMPM0)
µPD78P4916
Figure 2-1. Circuit Diagrams (1/2)
Type
Type pullup enable data P-ch
Schmitt triggered input with hysteresis characteristics.
Type output disable
P-ch N-ch
P-ch
pullup enable
input enable
Schmitt triggered input with hysteresis characteristics. Type Type P-ch data N-ch VREF (Threshold voltage) P-ch N-ch Comparator
Type Type data P-ch output disable N-ch output disable Push-pull output that also output high-impedance state (both P-ch N-ch transistors turned off.) N-ch data pullup enable P-ch
P-ch
µPD78P4916
Figure 2-1. Circuit Diagrams (2/2)
Type
P-ch N-ch
Comparator
VREF (Threshold voltage)
input enable
µPD78P4916
INTERNAL MEMORY CAPACITY SELECT REGISTER (IMS)
Internal memory capacity select register (IMS) specifies effective area on-chip memory (PROM, RAM) µPD78P4916. Setting this register required when capacity mask version smaller than that PD78P4916. memory capacity PD78P4916 appropriately defined using this register, bugs application programs accessing address beyond memory capacity actual chip avoided. register write-only register. write this register, 8-bit manipulation instruction. register initialized RESET input (ROM: Kbytes, RAM: 2048 bytes).
Figure 3-1. Internal Memory Capacity Select Register (IMS) Format
Address FFFCH
State reset
ROM1 ROM0
RAM1 RAM0
RAM1 RAM0 Other ROM1 ROM0 Other
Specification internal capacity 1280 bytes 2048 bytes Setting prohibited
Specification internal capacity Kbytes Kbytes Setting prohibited
Caution µPD78P4916 µPD784915 784916A have However, write instruction executed µPD784915 784916A, does cause conflicts malfunctions.
µPD78P4916
PROM PROGRAMMING
µPD78P4916 on-chip 62-Kbyte PROM program memory. PROM programming mode entered setting VDD, IC/V RESET pins specified. settings unused pins this mode, refer drawing "(2) PROM Programming Mode" section "Pin Configuration (Top View)".
Operation Mode
PROM programming mode entered applying IC/V pin, +6.5 pins, low-level voltage RESET pin. Table shows operation mode specified pins. possible read contents PROM setting read operation mode. Table 4-1. Operation Mode PROM Programming
Pins Operation mode Page data latch Page write Byte write Program verify Program inhibit
RESET
IC/VPP +12.5
+6.5
Data input High impedance Data input Data output High impedance
Read Output disable Standby
Data output High impedance High impedance
Remark high level
µPD78P4916
Read mode setting device enters read mode. Output disable mode setting device enters output disable mode, where data output pins high impedance state. Therefore possible read data from specified device enabling only device read, more µPD78P4916s connected data bus. Standby mode setting device enters Standby mode. this mode, data output pins high impedance state regardless condition. Page data latch mode setting beginning page programming mode, device enters page data latch mode. this mode, 4-byte data latched page units (consisting bytes) internal address/data latch circuit. Page programming mode After one-page data (consisting bytes) their address latched page data latch mode, page programming operation executed applying 0.1-ms programming pulse (active low) under conditions. Following that operation, programming data verified setting When data programmed programming pulse, write verify operations repeated times 10). Byte programming mode Applying 0.1-ms programming pulse (active low) under condition, byte programming operation executed. Next, programming data verified setting When data programmed programming pulse, write verify operations repeated times 10). Program verify mode setting device enters program verify mode. Check whether data programmed correctly this mode after write operation. Program inhibit mode When pins, pins, D0-D7 pins more PD78P4916s connected parallel, program inhibit mode write data those devices. Programming executed page programming mode byte programming mode mentioned above. that time, data programmed device which high level voltage applied pin.
µPD78P4916
PROM Write Procedure
Figure 4-1. Flowchart Page Programming Mode
Start Address 12.5
Latch Address Address Latch Address Address Latch Address Address Address Address Latch
0.1-ms programming pulse Fail
Verify bytes Pass Address
Pass
Verify bytes Pass Write operation
Fail
Defective
Remarks Start address address program
µPD78P4916
Figure 4-2. Operation Timing Page Programming Mode
Page data latch
Page programming
Program verify
Address input
Address input
Hi-Z Data input
Hi-Z Data output
Hi-Z
VDD+1.5
µPD78P4916
Figure 4-3. Flowchart Byte Programming Mode
Start Address 12.5
Address Address 0.1-ms programming pulse Fail
Verify Pass Address
Pass
Verify bytes Pass Write operation
Fail
Defective
Remarks Start address address program
µPD78P4916
Figure 4-4. Operation Timing Byte Programming Mode
Programming Program verify
Address input
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
VDD+1.5
Cautions Apply voltage before applying voltage voltage after voltage off. voltage including overshoot applied must kept less than +13.5 device inserted removed while +12.5 applied pin, adversely affected reliability.
µPD78P4916
PROM Read Procedure
contents PROM read onto external data (D0-D7) described below: RESET supply pin. Connect other unused pins specified "(2) PROM Programming Mode" section "Pin Configuration (Top View)." Supply pins. Input address data read A0-A16 pins. Enter read mode Output data D0-D7 pins. above operation timing from shown Figure 4-5. Figure 4-5. PROM Read Timing
Address input
(Input)
(Input)
Hi-Z
Data output
Hi-Z
Screening One-time PROM Versions
one-time PROM version (µPD78P4916GF-3BA) cannot completely tested shipment because structure. screening, recommended verify PROM after storing necessary data under following conditions:
Storage Temperature Storage Time hours
µPD78P4916
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol AVDD1 AVDD2 AVSS1 AVSS2 Input voltage Analog input voltage (ANI0-ANI11) Output voltage Output current, Total output pins Output current, high Total output pins Operating ambient temperature Storage temperature VIAN AVDD2 AVDD2 Conditions AVDD1 AVDD2 AVDD1 AVDD2 Ratings -0.5 +7.0 -0.5 +7.0 -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 -0.5 DD+0.5 -0.5 AVDD2 +0.5 -0.5 DD+0.5 -0.5 DD+0.5 Unit
+150
Caution above parameters exceeds absolute maximum ratings, even momentarily, device reliability impaired. absolute maximum ratings values that physically damage product. sure product within ratings. Operating Conditions
Operating ambient temperature
Clock frequency
Operating condition functions function only
Supply voltage (VDD +4.5 +5.5 +4.0 +5.5 +2.7 +5.5
Subclock operation (CPU, watch, Port functions only)
µPD78P4916
Oscillator Characteristics (Main Clock) AVDD AVSS
Resonator Crystal resonator Recommended circuit Item Oscillation frequency MIN. MAX. Unit
Oscillator Characteristics (Subclock) AVDD
Resonator Crystal resonator Recommended circuit Item Oscillation frequency (fXT) MIN. MAX. Unit
Caution When using main system clock subsystem clock oscillators, wiring area enclosed with dotted lines should carried follows avoid adverse effect from wiring capacitance: Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. amplification degree subsystem clock oscillator reduce current consumption, particular attention wiring method.
µPD78P4916
Characteristics AVDD AVSS
Parameter Input voltage, Symbol VIL1 VIL2 VIL3 Input voltage, high VIH1 VIH2 VIH3 Output voltage, VOL1 VOL2 VOL3 Output voltage, high Input leakage current Output leakage current power supply current VOH1 VOH2 Conditions Other than pins indicated Note below Pins indicated Note below Other than pins indicated Note below Pins indicated Note below (Pins listed Note below) -1.0 -100 VDD-1.0 VDD-0.4 MIN. 0.7V 0.8VDD VDD-0.5 TYP. MAX. 0.3V 0.2VDD 0.45 0.25 Unit
IDD1
Operation mode
(Low frequency oscillation mode) Internal main clock operation 32.768 Subclock operation (CPU, Watch, Port)
IDD2
HALT mode
(Low frequency oscillation mode) Internal main clock operation 32.768 Subclock operation (CPU, Watch, Port)
27.5
Data retention voltage Data retention current Note
VDDDR IDDDR
STOP mode STOP mode VDDDR STOP mode VDDDR STOP mode VDDDR Subclock oscillation
Subclock oscillation
Subclock suspended
Pull-up resistor
Notes RESET, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/KEY4. P46, When subclock suspended STOP mode, disconnect feedback resistor connect potential.
µPD78P4916
Characteristics peripheral unit operation clocks
Parameter operation clock cycle time Symbol tCLK Conditions AVDD function only MHz, frequency oscillation mode bit7 Peripheral unit operation clock cycle time tCLK1 MHz, frequency oscillation mode bit7 TYP. Unit
Serial interface SIOn: AVDD AVSS
Parameter Serial clock cycle time Symbol tCYSK Input Output Conditions External clock fCLK1/8 fCLK1/16 fCLK1/32 fCLK1/64 fCLK1/128 fCLK1/256 Serial clock high/low level width tWSKH tWSKL set-up time SCKn hold time (from SCKn output delay time (from SCKn tSSSK tHSSK tDSSK Input Output External clock Internal clock MIN. tCYSK/2-50 MAX. Unit
Remarks fCLK1: Operation clock peripheral unit MHz)
Only SIO2 (TA= AVDD AVSS
Parameter SCK2(8) STRB Strobe high level width BUSY setup time BUSY detection timing) BUSY hold time (from BUSY detection timing) Busy inactive SCK2(1) Symbol tDSTRB tWSTRB tSBUSY tHBUSY tLBUSY Conditions MIN. tWSKH MAX. tCYSK CYSK+t WSKH Unit
tCYSK tCYSK+30
Remarks value parentheses following SCK2 indicates sequential number SCK2. BUSY detection timing tCYSK 1,.) after SCK2(8) BUSY inactive SCK2(1) value time data already written SIO2.
µPD78P4916
Other Operations AVDD AVSS
Parameter Timer unit input level width Symbol tWCTL Conditions DFGIN, CFGIN, DPGIN, REEL0IN, REEL1IN logic level input DFGIN, CFGIN, DPGIN, REEL0IN, REEL1IN logic level input DFGIN, CFGIN DPGIN input MIN. tCLK1 MAX. Unit
Timer unit input high level width
tWCTH
tCLK1
Timer unit input signal valid edge input cycle CSYNCIN level width
tPERIN
tWCR1L
Digital noise eliminator used Digital noise eliminator used (INTM2 Digital noise eliminator used (INTM2
8tCLK1 108t CLK1
180t CLK1
CSYNCIN high level width
tWCR1H
Digital noise eliminator used Digital noise eliminator used (INTM2 Digital noise eliminator used (INTM2
8tCLK1 108t CLK1
180t CLK1
Digital noise eliminator
Eliminated pulse width Passed pulse width
tWSEP
INTM2 INTM2 INTM2 INTM2 108t CLK1 180t CLK1 2tCLK1 2tCLK1 Other than STOP mode When cancelling STOP mode 2tCLK1 2tCLK1 2tCLK1
Note
104t CLK1 176t CLK1
level width high level width INTP0 INTP3 level width INTP0 INTP3 high level width INTP1, KEY0 KEY4 level width INTP1, KEY0 KEY4 high level width INTP2 level width
tWNIL tWNIH tWIPL0 tWIPH0 tWIPL1
AVDD AVDD
tWIPH1
Other than STOP mode When cancelling STOP mode
tWIPL2
Main clock operation normal mode Subclock operation normal mode
Sampled Sampled fCLK/128 Sampled Sampled fCLK/128
Note
When cancelling STOP mode INTP2 high level width tWIPH2 Main clock operation normal mode Subclock operation normal mode Sampled Sampled fCLK/128 Sampled Sampled fCLK/128
2tCLK1
Note
Note
When cancelling STOP mode RESET level width tWRSL
Note
high level level input times succession during sampling period, high level level detected.
Remark tCLK1: Operation clock cycle time peripheral unit (125 ns).
µPD78P4916
Clock Output Operation AVDD AVSS
Parameter cycle time level width high level width rising time falling time Symbol tCYCL tCLL tCLH tCLR tCLF tCYCL/2 tCYCL/2 Expression MIN. MAX. 2000 1050 1050 Unit
Data Retention Characteristics AVDD AVSS
Parameter Input voltage, Input voltage, high Symbol Conditions Pins listed Note below MIN. 0.9V DDDR TYP. MAX. 0.1VDDDR VDDDR Unit
Note
RESET, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/KEY4
Watch Function AVDD AVSS
Parameter Subclock oscillation retention voltage Hardware watch function operation voltage Symbol DDXT Conditions MIN. MAX. Unit
Subclock Oscillation Suspension Detection Flag
Parameter Oscillation suspension detection width Symbol tOSCF Conditions MIN. MAX. Unit
Converter Characteristics AVDD AVREF AVSS
Parameter Resolution Total error Quantization error Conversion time tCONV Sampling time tSAMP Analog input voltage Analog input impedance AVREF current VIAN 160tCLK1 CLK1 CLK1 CLK1 1000 AVREF AVREF Symbol Conditions MIN. ±1/2 TYP. MAX. Unit
µPD78P4916
VREF Amplifier AVDD AVSS
Parameter Reference voltage Charge current Symbol ICHG AMPM0.0 pins listed Note below. Conditions MIN. 2.35 TYP. 2.50 MAX. 2.65 Unit
Note
RECCTL+, RECCTL-, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN
Amplifier AVDD AVSS
Parameter CTL+, input resistance Feedback resistance Bias resistance Minimum voltage gain Maximum voltage gain Gain switching step Common mode signal rejection Comparator voltage waveform regulation, high Comparator reset voltage waveform regulation, high Comparator voltage waveform regulation, Comparator reset voltage waveform regulation, Comparator high voltage flag Comparator voltage flag Comparator high voltage flag Comparator voltage flag VPBCTLLS VREF -0.53 VREF -0.50 VREF -0.47 Symbol RICTL RFCTL RBCTL GCTLMIN CTLMAX GAIN VPBCTLHS Voltage gain: Conditions MIN. TYP. 1.77 VREF+0.47 VREF+0.50 VREF+0.53 MAX. Unit
VPBCTLHR
VREF+0.27 VREF+0.30 VREF+0.33
VPBCTLLR
VREF -0.33 VREF -0.30 VREF -0.27
VFSL VFLH VFLL
VREF+1.00 VREF+1.05 VREF+1.10 VREF -1.10 VREF -1.05 VREF -1.00 VREF+1.40 VREF+1.45 VREF+1.50 VREF -1.50 VREF -1.45 VREF -1.40
µPD78P4916
Amplifier Coupling) AVDD AVSS
Parameter Voltage gain Voltage gain CFGAMPO output current, high CFGAMPO output current, Comparator high voltage Comparator voltage Duty precision Symbol GCFG1 GCFG2 IOHCFG IOLCFG CFGH VCFGL DUTY Note below. Conditions kHz, open loop kHz, open loop MIN. VREF+0.09 VREF+0.12 VREF +0.15 VREF -0.15 VREF -0.12 REF-0.09 49.7 50.0 50.3 TYP. MAX. Unit
Note
following circuit input signal conditions assumed. Input signal: sine wave input mVp-p), Voltage gain:
CFGAMPO 0.01 CFGCPIN CFGIN
µPD78P4916
Amplifier Coupling) AVDD AVSS
Parameter Voltage gain Feedback resistance Input protect resistance Comparator high voltage Comparator voltage Symbol RFDFG RIDFG DFGH VDFGL Conditions open loop MIN. VREF+0.07 VREF+0.10 VREF+0.14 VREF -0.14 VREF -0.10 VREF -0.07 TYP. MAX. Unit
Caution resistance connected DFGIN must below resistance higher than limit, amplifier oscillate.
Comparator Coupling) AVDD AVSS
Parameter Input impedance Comparator high voltage Comparator voltage Symbol IDPG VDPGH DPGL Conditions MIN. TYP. MAX. Unit
VREF+0.02 VREF+0.05 VREF+0.08 VREF -0.08 VREF -0.05 VREF -0.02
µPD78P4916
Three-value divider AVDD AVSS
Parameter Input impedance Comparator high voltage Comparator voltage Symbol IPFG VPFGH VPFGL Conditions MIN. TYP. MAX. Unit
VREF +0.5 VREF+0.7 VREF+0.9 REF-1.4 VREF-1.2 VREF-1.0
CSYNC Comparator Coupling) AVDD AVSS
Parameter Input impedance Comparator high voltage Comparator voltage Symbol ZICSYN VCSYNH VCSYNL Conditions MIN. TYP. MAX. Unit
VREF+0.07 VREF+0.10 VREF+0.13 VREF -0.13 VREF -0.10 VREF -0.07
Reel Comparator Coupling) AVDD
Parameter Input impedance Comparator high voltage Comparator voltage Symbol ZIRLFG VRLFGH VRLFGL Conditions MIN. TYP. MAX. Unit
VREF+0.02 VREF+0.05 VREF+0.08 VREF -0.08 VREF -0.05 VREF -0.02
RECCTL Driver AVDD AVSS
Parameter RECCTL+, high level output voltage RECCTL+, level output voltage CTLDLY on-chip resistor CTLDLY charge current CTLDLY discharge current Symbol VOHREC VOLREC RCTL IOHCTL IOLCTL On-chip resistor disabled Conditions MIN. -0.8 TYP. MAX. Unit
µPD78P4916
Timing Waveform timing test point
Test points
Serial Transfer Timing (SIOn:
tWSKL SCKn tCYSK tSSSK tHSSK tWSKH
Input data
tDSSK Output data
µPD78P4916
Serial Transfer Timing (Only SIO2) busy processing
tWSKL SCK2 tCYSK BUSY active-high tDSTRB STRB Invalid busy tWSTRB tWSKH
Continue busy processing
tWSKL SCK2 tCYSK BUSY active-high tDSTRB STRB tWSTRB tWSKH tSBUSY 10+n tHBUSY
Terminate busy processing
tWSKL SCK2 tCYSK BUSY active-high tWSKH 10+n tHBUSY 11+n tLBUSY
Caution busy control strobe control whenever external clock selected serial clock.
µPD78P4916
Super timer unit input timing
tWCTH DFGIN, CFGIN, DPGIN, REEL0IN REEL1IN logic level input tWCTL
tWCR1H CSYNCIN logic level input
tWCR1L
Interrupt input timing
tWNIH
tWNIL
tWIPH0 INTP0, INTP3
tWIPL0
tWIPH1 INTP1, KEY0 KEY4
tWIPL1
tWIPH2 INTP2
tWIPL2
Reset input timing
tWRSL
RESET
µPD78P4916
Clock output timing
tCLH tCLR tCLF tCLL tCYCL
µPD78P4916
Programming Characteristics AVSS
Parameter Input voltage, high Input voltage, Input leakage current Output voltage, high Symbol ILIP VOH1 VOH2 Output voltage, Output leakage current supply voltage VDDP Symbol VOH1 VOH2 VDDP
Note
Note
Conditions
MIN. -0.3
TYP.
MAX. VDDP+0.3
Unit
-400 -100 VDDP, Program memory write mode Program memory read mode
VDDP-0.7 0.45 6.25 6.75
4.50
5.50
supply voltage
Program memory write mode Program memory read mode
12.2
12.5
12.8
VDDP
supply current
Program memory write mode Program memory read mode
supply current
Program memory write mode Program memory read mode
Notes Corresponding symbols µPD27C1001A. VDDP during programming.
µPD78P4916
Programming Characteristics AVSS PROM Write Operation Mode (Page Programming Mode)
Parameter Address setup time time Input data setup time Address hold time Symbol Note tCES tAHL tAHV Input data hold time Output data hold time setup time VDDP setup time Initial programming pulse width time valid data delay time pulse width during data latch set-up time hold time hold time tVPS tVDS
Note
Conditions
MIN. 0.095
TYP.
MAX.
Unit
0.105
tOES tPGMS tCEH tOEH
Notes Correspond symbols µPD27C1001A (except tVDS tVDS corresponds tVCS PD27C1001A.
µPD78P4916
PROM Write Mode (Byte Programming Mode)
Parameter Address setup time time Input data setup time Address hold time Input data hold time Output data hold time setup time VDDP setup time Initial programming pulse width time valid data delay time Symbol Note tCES tVPS tVDS
Note
Conditions
MIN. 0.095
TYP.
MAX.
Unit
0.105
tOES
Notes Correspond symbols µPD27C1001A (except tVDS tVDS corresponds tVCS PD27C1001A. PROM Read Mode
Parameter Address data output time data output time data output time Data hold time (from Note Data hold time (from address) Symbol Note tACC Conditions MIN. TYP. MAX. Unit
Notes Correspond symbols µPD27C1001A. time after either rose first.
µPD78P4916
PROM Write Mode Timing (Page Programming Mode)
Page data latch Hi-Z tVPS VDDP tVDS VDDP +1.5 VDDP VDDP Data input tAHL
Page programming
Program verify
tAHV
Hi-Z tPGMS Data output Hi-Z
tCES tOES tCEH
tOEH
µPD78P4916
PROM Write Mode Timing (Byte Programming Mode)
Programming
Program verify
Hi-Z VDDP tVPS VDD+1.5 VDDP VDDP tVDS tCES tOES Data input Hi-Z Data output Hi-Z
Cautions Apply voltage VDDP before applying voltage VPP, VDDP voltage after voltage off. voltage, including overshoot, applied must kept less than +13.5 device inserted removed while +12.5 applied pin, adversely affected reliability.
PROM Read Mode Timing
Valid address
tOENote tACCNote Hi-Z tDFNote Data output Hi-Z
Notes data need read within tACC, maximum delay time active level input from falling should time after either first rose VIH.
µPD78P4916
PACKAGE DRAWING
PLASTIC
detail lead
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition. ITEM
P100GF-65-3BA1-2 MILLIMETERS 23.6 20.0 14.0 17.6 0.30 0.10 0.15 0.65 (T.P.) 0.15+0.10 -0.05 0.10 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
5°±5°
µPD78P4916
RECOMMENDED SOLDERING CONDITIONS
This device should soldered mounted under following conditions. details about recommended conditions, refer document "Semiconductor Device Mounting Technology Manual" (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Table 7-1. Surface Mounting Type Soldering Conditions
µPD78P4916GF-3BA: 100-pin plastic
Soldering Method Infrared rays reflow Soldering Conditions Peak package's surface temperature: Reflow time: seconds less higher), Number reflow processes: less <Attention> Wait device temperature come down room temperature after first reflow before starting second reflow. perform flux cleaning soldered portion after first reflow. Peak package's surface temperature: Reflow time: seconds less higher), Number reflow processes: less <Attention> Wait device temperature come down room temperature after first reflow before starting second reflow. perform flux cleaning soldered portion after first reflow. Symbol IR35-00-2
VP15-00-2
Wave soldering
Solder temperature: below, Flow time: seconds less, Number flow WS60-00-1 process: Preheating temperature; max. (package surface temperature) temperature: below, Time: seconds less (per row)
Partial heating
Caution different soldering methods together (except partial heating).
µPD78P4916
APPENDIX
DEVELOPMENT TOOLS
following development tools prepared system development using µPD78P4916. Language Software
RA78K4 CC78K4
Note Note Note
Assembler package common 78K/IV Series compiler package common 78K/IV Series compiler library source file common 78K/IV Series
CC78K4-L
PROM Writing Tool
PG-1500 PA-78P4916GF PG-1500 Controller
Note
PROM programmer Programmer adapter connected PG-1500 Control program PG-1500
Debugging Tool
IE-784000-R IE-784000-R-BK IE-784000-R-EM IE-784915-R-EM1 IE-78000-R-SV3 IE-70000-98-IF-B In-circuit emulator common 78K/IV Series Break board common 78K/IV Series Emulation board common 78K/IV Series Emulation board evaluation µPD784915 Subseries Interface adapter when using host machine Interface adapter when using PC-9800 series (except notebook type) host machine Interface adapter cable when using notebook type PC-9800 series host machine Interface adapter when using PC/ATas host machine Emulation probe common µPD784915 subseries Conversion socket 100-pin plastic mount device target system System emulator 78K/IV series devices Integrated debugger IE-784000-R Device file common µPD784915 subseries
IE-70000-98N-IF
IE-70000-PC-IF-B EP-784915GF-R EV-9200GF-100 SM78K4 ID78K4
Note
Note Note
DF784915
Real-time
RX78K/IV MX78K4
Note
Real-time common 78K/IV series common 78K/IV series
Note
µPD78P4916
Notes PC-9800 series (for MS-DOSTM) based PC/AT compatibles (for DOS, Windows, MS-DOS, DOSTM) based HP9000 series 700(for (for HP-UXTM) based SPARCstationSunOSTM) based
NEWS (NEWS-OSTM) based PC-9800 series (for MS-DOS) based PC/AT compatibles (for DOS, Windows, MS-DOS, DOS) based PC-9800 series (for Windows MS-DOS) based PC/AT compatibles (for DOS, Windows, MS-DOS, DOS) based HP9000 series (for HP-UX) based SPARCstation (for SunOS) based PC-9800 series (for MS-DOS) based PC/AT compatibles (for DOS, Windows, MS-DOS, DOS) based HP9000 series (for HP-UX) based SPARCstation (for SunOS) based Remark RA78K4, CC78K4, SM78K4, ID78K4 should used combination with DF784915.
µPD78P4916
APPENDIX
SOCKET DRAWING RECOMMENDED FOOTPRINT
Figure B-1. EV-9200GF-100 Drawing
(For reference purpose only)
EV-9200GF-100
No.1 index
EV-9200GF-100-G0 ITEM MILLIMETERS 24.6 18.6 12.0 22.6 25.3 16.6 19.3 0.35 INCHES 0.969 0.827 0.591 0.732 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.323 0.315 0.098 0.079 0.014
0.091 0.059
µPD78P4916
Figure B-2. Recommended EV-9200GF-100 Footprint (For reference purpose only)
EV-9200GF-100-P1 ITEM Caution MILLIMETERS 26.3 21.6 INCHES 1.035 0.85
0.65±0.02 29=18.85±0.05 0.026 +0.001 1.142=0.742+0.002 -0.002 -0.002 0.65±0.02 19=12.35±0.05 0.026 +0.001 0.748=0.486 +0.003 -0.002 -0.002 15.6 20.3 0.05 0.05 0.35 0.02 0.614 0.799 0.472 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
µPD78P4916
APPENDIX
RELATED DOCUMENTS
Document related device
Title Document Japanese English U10444E U10905E
µPD784915 Subseries User's Manual Hardware µPD784915 Subseries Special Function Register Table
78K/IV Series User's Manual Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction 78K/IV Series Application Note Software Basics
U10444J U10976J U10905J U10594J U10595J U10095J
Development tool documents (User's Manual)
Title Document Japanese RA78K Series Assembler Package Language Operation RA78K Series Structured Assembler Preprocessor CC78K Series Compiler Language Operation CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PG-1500 Controller IE-784000-R IE-784915-R-EM1 EP-784915GF-R PC-9800 series MS-DOS base series base EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-777 EEU-651 EEU-704 EEU-5008 EEU-5004 U10931J U10440J English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEU-1335 EEU-1291 U10540E EEU-1534 IEU-1412
ID78K4 Integrated Debugger Reference
Embedded-software documents (User's Manual)
Title Document Japanese RX78K/IV Series Real-time Basics Installation Debugger U10604J U10603J U10364J English
Caution contents documents listed above subject change without prior notice users. sure latest edition when starting design.
µPD78P4916
Other documents
Title Document Japanese Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Devices Microcontroller-Related Product Guide Third Party Products IEI-635 C10535J IEI-620 IEM-5068 MEM-539 MEI-603 MEI-604 English IEI-1213 C10535E IEI-1209 MEI-1202
Caution contents documents listed above subject change without prior notice users. sure latest edition when starting design.
µPD78P4916
[MEMO]
µPD78P4916
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78P4916
trademark Corporation. MS-DOS Windows trademarks Microsoft Corporation. DOS, PC/AT, trademarks International Business Machines Corporation. HP9000 Series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation. related documents indicated this publication include preliminary versions. However, preliminary versions marked such.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative. application circuits their parameters reference only intended actual design-in's.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customer must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact Sales Representative advance. Anti-radioactive design implemented this product.
94.11

µPD78P4916 16-BIT SINGLE-CHIP MICROCONTROLLER µPD78P4916 µPD

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