µPD78P4908 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION
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INTEGRATED CIRCUIT
µPD78P4908
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P4908, 78K/IV series' product, one-time PROM version PD784907 PD784908 with internal mask ROM. Since user programs written PROM, this microcomputer best suited evaluation system development, manufacture small quantities multiple products, fast start-up applications. specific functions other detailed information, consult following user's manuals. These manuals required reading design work. µPD784908 Subseries User's Manual Hardware U11787E 78K/IV Series User's Manual Instruction U10905E
FEATURES
78K/IV series Internal PROM: Kbytes Internal RAM: 4,352 bytes Supply voltage: main clock: 12.58 MHz, internal system clock fCYK (Other than above: fCYK
ORDERING INFORMATION
Part number Package 100-pin plastic Internal One-time PROM
µPD78P4908GF-3BA
information this document subject change without notice. Document U11681EJ2V0DS00 (2nd edition) Date Published February 1999 CP(K) Printed Japan
mark
shows major revised points.
1996
PD78P4908
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
Under mass production Under development
supported
Multimaster supported
µPD784038Y
Standard models
µPD784225Y µPD784225
pins, added correction Multimaster supported
µPD784038
Enhanced internal memory capacity, compatible with µPD784026 Multimaster supported
µPD784026
Enhanced A/D, 16-bit timer, power management
µPD784216Y µPD784216
pins, enhanced internal memory capacity
µPD784218Y µPD784218
Enhanced internal memory capacity, added correction
µPD784054 µPD784046
ASSP models Equipped with 10-bit
PD784955
inverter control
PD784938 PD784908
Equipped with IEBus controller
Enhanced function µPD784908, enhanced internal memory capacity, added correction
Multimaster supported
PD784928Y PD784928 µPD784915
software servo control, equipped with analog circuit VCR, enhanced timer Enhanced function µPD784915
Data Sheet U11681EJ2V0DS00
PD78P4908
FUNCTIONS
(1/2)
Item Number basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space ports Total Input Input/output Additional function pinsNote direct drive outputs Transistor direct drive N-ch open drain Real-time output ports IEBus controller Timer/counter Function
bits registers banks, bits registers banks (memory mapping)
ns/636 ns/1.27 s/2.54 6.29 MHz) ns/320 ns/636 ns/1.27 12.58 MHz)
Kbytes 4,352 bytes Program data: Mbyte
bits bits Incorporated (simple version) Timer/counter bits) Timer register Capture register Compare register Timer register Capture register Capture/compare register Compare register Timer register Capture register Capture/compare register Compare register Timer register Compare register Pulse output capability Toggle output PWM/PPG output One-shot pulse output Real-time output port
Timer/counter bits)
Timer/counter bits)
Pulse output capability Toggle output PWM/PPG output
Timer bits) Clock timer
Interrupt requests generated 0.5-second intervals. clock timer oscillator incorporated.) Either main clock (6.29 MHz/12.58 MHz) real-time clock (32.768 kHz) selected input clock. Selected from CLK, fCLK/2, CLK/4, fCLK/8, fCLK/16 (can used 1-bit output port) 12-bit resolution channels UART/IOE (3-wire serial I/O) channels (incorporating baud rate generator) (3-wire serial I/O) channels
Clock output outputs Serial interface
Note Additional function pins included pins.
Data Sheet U11681EJ2V0DS00
PD78P4908
(2/2)
Item converter Watchdog timer Standby Interrupt Hardware source Software source Nonmaskable Maskable 8-bit resolution channels channel HALT/STOP/IDLE mode internal, external (sampling clock variable input: BRKCS instruction, operand error internal, external internal, external Function
4-level programmable priority operation statuses: vectored interrupt, macro service, context switching
Power supply voltage
main clock: 12.58 MHz, internal system clock fXX: fCYK
(Other than above: fCYK
Package 100-pin plastic
Data Sheet U11681EJ2V0DS00
PD78P4908
CONTENTS
DIFFERENCES BETWEEN µPD78P4908 MASK PRODUCTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS
PINS NORMAL OPERATING MODE PINS PROM PROGRAMMING MODE +12.5 RESET 4.2.1 4.2.2 Functions Functions
CIRCUITS PINS HANDLING UNUSED PINS
INTERNAL MEMORY SIZE SELECT REGISTER (IMS) PROM PROGRAMMING
OPERATION MODE PROM WRITE SEQUENCE PROM READ SEQUENCE
SCREENING ONE-TIME PROM PRODUCTS ELECTRICAL CHARACTERISTICS PACKAGE DRAWING
RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS. APPENDIX CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING APPENDIX RELATED DOCUMENTS
Data Sheet U11681EJ2V0DS00
PD78P4908
DIFFERENCES BETWEEN µPD78P4908 MASK PRODUCTS
µPD78P4908 produced replacing mask PD784907 PD784908 with PROM which data written. functions µPD78P4908 same those PD784907 µPD784908 except PROM specification such writing verification, except that PROM size changed Kbytes, except that internal size changed 3,584 4,352 bytes. Table shows differences between these products. Table 1-1. Differences Between µPD78P4908 Mask Products
Product name Item Internal program memory
µPD78P4908
PD784907
PD784908
128-Kbyte PROM changed
Kbytes
96-Kbyte mask
128-Kbyte mask
Internal
4,352-byte internal changed 3,584
bytes
3,584-byte internal
4,352-byte internal
connection Power supply voltage
functions related writing reading PROM have been added µPD78P4908.
main clock: 12.58 MHz, internal system clock fCYK (Other than above: fCYK
main clock: 12.58 MHz, internal system clock fCYK (Other than above: fCYK
Electrical characteristics
Partially differs between these products.
Data Sheet U11681EJ2V0DS00
PD78P4908
CONFIGURATION (TOP VIEW)
Normal operation mode
100-pin plastic
µPD78P4908GF-3BA
P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI AVSS AVREF1 AVDD P77/ANI7
P36/TO2 P37/TO3 P100 P101 P102 P103 P104 P105/SCK3 P106/SI3 P107/SO3 RESET REGOFFNote REGCNote P67/REFRQ/HLDAK P66/WAIT/HLDRQ P65/WR
P34/TO0 P33/SO0 P32/SCK0 P31/TxD/SO1
P35/TO1
P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 TESTNote PWM1 PWM0 P14/TxD2/SO2 P13/RxD2/SI2 P12/ASCK2/SCK2 ASTB/CLKOUT P40/AD0 P41/AD1 P42/AD2
P64/RD P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11
Notes Connect TEST directly. Connect REGOFF directly (select regulator operation) Connect REGC through capacitor.
P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3
Data Sheet U11681EJ2V0DS00
PD78P4908
A8-A19 AD0-AD7 ANI0-ANI7 ASTB AVDD AVREF1 AVSS CLKOUT HLDAK HLDRQ P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P90-P97 P100-P107 Address Address/data Analog input Address strobe Analog power supply Reference voltage Analog ground Clock input Clock output Hold acknowledge Hold request Non-maskable interrupt Port Port Port Port Port Port Port Port Port Port PWM0, PWM1 Pulse width modulation output REFRQ REGC REGOFF RESET RxD, RxD2 SCK0-SCK3 SI0-SI3 SO0-SO3 TEST TO0-TO3 TxD, TxD2 WAIT XT1, Read strobe Refresh request Regulator capacitance Regulator Reset IEBus receive data Receive data Serial clock Serial input Serial output Test Timer output IEBus transmit data Transmit data Power supply Ground Wait Write strobe Crystal (main system clock) Crystal (watch)
ASCK, ASCK2 Asynchronous serial clock
INTP0-INTP5 Interrupt from peripherals
Data Sheet U11681EJ2V0DS00
PD78P4908
PROM programming mode
100-pin plastic
µPD78P4908GF-3BA
OPEN OPEN OPEN OPEN
OPEN
RESET OPEN OPEN
OPEN
OPEN
Caution
Connect these pins separately pins through 10-k pull-down resistors. connected ground.
Open Nothing should connected these pins. RESET: low-level input. A0-A16 D0-D7 Address Chip enable Data Output enable Program RESET Reset Power supply Programming power supply Ground
Data Sheet U11681EJ2V0DS00
PD78P4908
BLOCK DIAGRAM
INTP0-INTP5 INTP3 UART/IOE2 Baud-rate generator UART/IOE1 Baud-rate generator RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SCK0 Clocked serial interface core
(RAM bytes)
Programmable interrupt controller
Timer/counter bits)
INTP0
Timer/counter bits)
INTP1 INTP2/CI
Timer/counter bits)
(128 Kbytes)
SCK3 Clocked serial interface ASTB /CLKOUT AD0-AD7 A8-A15 A16-A19 WAIT/HLDRQ REFRQ/HLDAK D0-D7Note A0-A16Note CENote OENote PGMNote P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P90-P97 P100-P107
Timer bits) P00-P03 Real-time output port P04-P07
Clock output
interface PWM0 PWM1 ANI0-ANI7 AVDD AVREF1 AVSS INTP5 IEBus controller RESET TEST REGC REGOFF VPPNote Watch timer converter Port Port Port Port Port Port Port System control (regulator) Port Watchdog timer Port Port
(3,840 bytes)
Note PROM programming mode.
Data Sheet U11681EJ2V0DS00
PD78P4908
FUNCTIONS
PINS NORMAL OPERATING MODE
Port pins (1/2)
P00-P07 Also used Function Port (P0): 8-bit port. Functions real-time output port bits Inputs outputs specified bit. built-in pull-up resistors simultaneously specified software pins input mode. drive transistor. Port (P1): 8-bit port. Inputs outputs specified bit. built-in pull-up resistors simultaneously specified software pins input mode. drive LED.
P15-P17 P34-P37 P40-P47
ASCK2/SCK2 RxD2/SI2 TxD2/SO2
Input
INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5
Port (P2): 8-bit input-only port. does function general-purpose port (nonmaskable interrupt). However, input level checked interrupt service routine. built-in pull-up resistors specified software pins units bits). P25/INTP4/ASCK/SCK1 functions SCK1 input/output CSIM1.
RxD/SI1 TxD/SO1 SCK0 TO0-TO3
Port (P3): 8-bit port. Inputs outputs specified bit. built-in pull-up resistors simultaneously specified software pins input mode. N-ch open-drain pin. Port (P4): 8-bit port. Inputs outputs specified bit. built-in pull-up resistors simultaneously specified software pins input mode. drive LED.
AD0-AD7
Data Sheet U11681EJ2V0DS00
PD78P4908
Port pins (2/2)
P50-P57 Also used A8-A15 Function Port (P5): 8-bit port. Inputs outputs specified bit. built-in pull-up resistors simultaneously specified software pins input mode. drive LED. Port (P6): 8-bit port. Inputs outputs specified bit. built-in pull-up resistors simultaneously specified software pins input mode.
P60-P63 P70-P77
A16-A19 WAIT/HLDRQ REFRQ/HLDAK
ANI0-ANI7
Port (P7): 8-bit port. Inputs outputs specified bit. Port (P9): 8-bit port. Inputs outputs specified bit. built-in pull-up resistors simultaneously specified software pins input mode. Port (P10): 8-bit port. Inputs outputs specified bit. built-in pull-up resistors simultaneously specified software pins input mode. P105 P107 N-ch open-drain pin.
P90-P97
P100-P104 P105 P106 P107
SCK3
Data Sheet U11681EJ2V0DS00
PD78P4908
Non-port pins (1/2)
TO0-TO3 RxD2 TxD2 ASCK ASCK2 SCK0 SCK1 SCK2 SCK3 INTP0 Input Output Input Input Output Output Input Input Also used P34-P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P30/RxD P13/RxD2 P106 P31/TxD P14/TxD2 P107 P25/INTP4/ASCK P12/ASCK2 P105 Timer output Input count clock timer/counter Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial Serial data input (3-wire serial Serial data input (3-wire serial Serial data input (3-wire serial Serial data output (3-wire serial Serial data output (3-wire serial Serial data output (3-wire serial Serial data output (3-wire serial Serial clock (3-wire serial Serial clock (3-wire serial Serial clock (3-wire serial Serial clock (3-wire serial External interrupt request Input count clock timer/counter Capture/trigger signal CR11 CR12 Input count clock timer/counter Capture/trigger signal CR22 Input count clock timer/counter Capture/trigger signal CR21 Input count clock timer/counter Capture/trigger signal CR02 Input conversion start trigger converter Time multiplexing address/data (for connecting external memory) High-order address (for connecting external memory) High-order address during address expansion (for connecting external memory) Strobe signal output reading contents external memory Strobe signal output writing external memory Wait signal insertion Refresh pulse output external pseudo static memory Input hold request Output hold response Latch timing output time multiplexing address (A0-A7) (for connecting external memory) Function
INTP1
INTP2
P23/CI
INTP3
INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 WAIT REFRQ HLDRQ HLDAK ASTB Output Output Output Output Input Output Input Output Output
P25/ASCK/SCK1 P40-P47 P50-P57 P60-P63 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT
Data Sheet U11681EJ2V0DS00
PD78P4908
Non-port pins (2/2)
CLKOUT PWM0 PWM1 REGC Output Output Output Input Output Also used ASTB Clock output output output Data input (IEBus) Data output (IEBus) Capacitor connection stabilizing regulator output/Power supply when regulator stopped. Connect 1-µF capacitor. Signal specifying regulator operation. Directly connect (regulator selected). Chip reset Crystal input system clock oscillation clock pulse also input pin.) Real-time clock connection Function
REGOFF
RESET ANI0-ANI7 AVREF1 AVDD AVSS TEST
Input Input Input Input P70-P77
Analog voltage inputs converter Application converter reference voltage Positive power supply converter Ground converter Positive power supply Ground
Input
Directly connect (The TEST test.)
PINS PROM PROGRAMMING MODE +12.5 RESET
4.2.1 Functions
name Function PROM programming mode selection High voltage input during program write verification PROM programming mode selection Address Input Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input during PROM programming mode Positive power supply
RESET A0-A16 D0-D7
Input
Data Sheet U11681EJ2V0DS00
PD78P4908
4.2.2 Functions
(Programming power supply): Input Input setting PD78P4908 PROM programming mode. When input voltage this +6.5 more when RESET input goes low, PD78P4908 enters PROM programming mode. When made +12.5 high, program data written into internal PROM cell selected A16. RESET (Reset): Input Input setting PD78P4908 PROM programming mode. When input this low, when input voltage goes more, µPD78P4908 enters PROM programming mode. (Address bus): Input Address that selects internal PROM address (0000H 1FFFFH) (Data bus): Data through which program written read from internal PROM (Chip enable): Input This inputs enable signal from internal PROM. When this signal active, program written read. (Output enable): Input This inputs read strobe signal internal PROM. When this signal made active low, onebyte program internal PROM cell selected read onto (Program): Input input operation mode control signal internal PROM. Upon activation, writing internal PROM enabled. Upon inactivation, reading from internal PROM enabled. Positive power supply Ground potential
Data Sheet U11681EJ2V0DS00
PD78P4908
CIRCUITS PINS HANDLING UNUSED PINS
Table describes types circuits pins handling unused pins. Figure shows configuration these various types circuits. Table 4-1. Types Circuits Pins Handling Unused Pins (1/2)
P00-P07 P10, P12/ASCK2/SCK2 P13/R XD2/SI2 P14/TXD2/SO2 P15-P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 Input state: connected Output state: left open connected connected Input connected circuit type Recommended connection method unused pins Input state: connected Output state: left open
P26/INTP5 P27/SI0 P30/R XD/SI1 P31/TXD/SO1 P32/SCK0 P33/SO0 P34/TO0-P37/TO3 P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7 P90-P97 P100-P104 P105/SCK3 P106/SI3 P107/SO3 ASTB/CLKOUT
Input
Input state: connected Output state: left open
10-A
Input state:
connected Output state left open
10-A 10-A Output left open
Data Sheet U11681EJ2V0DS00
PD78P4908
Table 4-1. Types Circuits Pins Handling Unused Pins (2/2)
RESET TEST PWM0, PWM1 AVREF1 AVSS AVDD connected Input Output Input Output circuit type Input connected directly left open connected left open connected left open connected Recommended connection method unused pins
Caution When mode dual-function unpredictable, connect through resistor (particularly when voltage reset input becomes higher than that level input power-on when switched software). Remark Since type numbers consistent series, those numbers always serial each product. (Some circuits included.)
Data Sheet U11681EJ2V0DS00
PD78P4908
Figure 4-1. Circuits Pins
Type Type Pull-up enable
Type Schmitt trigger input with hysteresis characteristics Type P-ch Data N-ch Output disable Input enable Type Data Output disable Pull-up enable Data Push-pull output which output high impedance (both positive negative channels off.) Type 10-A Pull-up enable IN/OUT Output disable Type Output disable Type Pull-up enable Data
Schmitt trigger input with hysteresis characteristics Type IN/OUT
IN/OUT
Data IN/OUT
Data Open drain Output disable
Comparator Type Analog output voltage Input enable VREF (Threshold voltage)
Data Sheet U11681EJ2V0DS00
PD78P4908
INTERNAL MEMORY SIZE SELECT REGISTER (IMS)
This register enables software avoid using part internal memory. establish same memory mapping used mask products that have different internal memory (ROM RAM) configurations. using 8-bit memory operation instructions. RESET input sets FFH. Figure 5-1. Internal Memory Size Select Register (IMS)
IMS7 IMS6 IMS5 IMS4 IMS3 IMS2 IMS1 IMS0 Address 0FFFCH Reset value
IMS0-7
Other than above
Memory size Same µPD784908 Same µPD784907
contained mask product PD784907 PD784908). action affected write command executed mask product.
Data Sheet U11681EJ2V0DS00
PD78P4908
PROM PROGRAMMING
PD78P4908 on-chip 128-KB PROM device program memory. When programming, RESET pins PROM programming mode. CONFIGURATION (TOP VIEW) PROM programming mode with regard handling other, unused pins. OPERATION MODE
PROM programming mode selected when +6.5 added pin, +12.5 added pin, low-level input added RESET pin. This mode operation mode setting pin, pin, shown Table below. addition, PROM contents read setting read mode. Table 6-1. PROM Programming Operation Mode
Operation mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High impedance High impedance Data input High impedance Data input Data output High impedance RESET D0-D7
Remark
Data Sheet U11681EJ2V0DS00
PD78P4908
Read mode read mode. Output disable mode high impedance data output output disable mode. Consequently, several PD78P4908 devices connected data bus, pins controlled select data output from devices. Standby mode standby mode. this mode, data output high impedance regardless setting. Page data latch mode beginning page write mode, page data latch mode. this mode, page bytes) data latched internal address/data latch circuit. Page write mode After latching address data page bytes) using page data latch mode, adding program pulse (active, low) with both causes page write executed. Later, setting both causes program verification executed. programming completed after program pulse, write verify operations repeated times (where 10). Byte write mode Adding program pulse (active, low) with setting causes byte write executed. Later, setting causes program verification executed. programming completed after program pulse, write verify operations repeated times (where 10). Program verify mode program verify mode. verify mode verification following each write operation. Program inhibit mode Program inhibit mode used write single device when several µPD78P4908 devices connected parallel pins. page write mode byte write mode described above each write operation. Write operations cannot done devices which been
Data Sheet U11681EJ2V0DS00
PD78P4908
PROM WRITE SEQUENCE Figure 6-1. Page Program Mode Flowchart
Start Address +6.5 +12.5 Latch Address Address Latch Address Address Latch Address Address Latch X=X+1 program pulse
Address Address
Verify bytes Pass Address
Fail
Pass
Verify bytes pass Write
Fail
Defective
Remark Start address Program address
Data Sheet U11681EJ2V0DS00
PD78P4908
Figure 6-2. Page Program Mode Timing
Page data latch
Page program
Program verify
A2-A16
Hi-Z D0-D7 Data input
Hi-Z Data output
Data Sheet U11681EJ2V0DS00
PD78P4908
Figure 6-3. Byte Program Mode Flowchart
Start Address +6.5 +12.5 program pulse Fail Address Address
Verify Pass Address Pass
Verify bytes pass Write
Fail
Defective
Remark Start address Program address
Data Sheet U11681EJ2V0DS00
PD78P4908
Figure 6-4. Byte Program Mode Timing
Program Program verify
A0-A16
D0-D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
Cautions before turn after allow exceed 13.5 including overshoot. Reliability problems result device inserted pulled while 12.5 applied VPP.
Data Sheet U11681EJ2V0DS00
PD78P4908
PROM READ SEQUENCE
Follow this sequence read PROM contents external data D7). RESET level pin. CONFIGURATION (TOP VIEW) PROM programming mode with regard handling other, unused pins. pins. Input data address read pins A16. read mode. Output data pins Figure shows timing steps above. Figure 6-5. PROM Read Timing
A0-A16
Address input
(input)
(input)
D0-D7
Hi-Z
Data output
Hi-Z
SCREENING ONE-TIME PROM PRODUCTS
cannot execute complete test one-time PROM products µPD78P4908GF-3BA) their structure before shipment. recommended that screen (verify) PROM products after writing necessary data into them storing them 125°C hours.
Data Sheet U11681EJ2V0DS00
PD78P4908
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Symbol AVDD AVSS Input voltage Analog input voltage Output voltage Output current Total P00-P07, P30P37, P54-P57, P60-P67, P100-P107 pins Total P10-P17, P40P47, P50-P53, P70-P77, P90-P97, PWM0, PWM1, pins Output high current Total P00-P07, P30P37, P54-P57, P60-P67, P100-P107 pins Total P10-P17, P40P47, P50-P53, P70-P77, P90-P97, PWM0, PWM1, pins converter reference input voltage Operating ambient temperature Storage temperature AVREF1 pins other than VPP, Conditions Rating -0.3 +7.0 -0.3 -0.3 +0.3 -0.3 -0.3 +13.5 AVSS AVREF1 -0.3 Unit
-0.3
Tstg
+150
Caution Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values. Remark Unless otherwise stated, characteristics dual-function same those port pin.
Data Sheet U11681EJ2V0DS00
PD78P4908
OPERATING CONDITIONS Operating ambient temperature Power supply voltage clock cycle time: Figure 8-1. Internal regulator operation selected (REGOFF pin: level) Figure 8-1. Power Supply Voltage Clock Cycle Time
10,000 4,000 Clock cycle time tCYK [ns]
1,000 Guaranteed operating range
Power supply voltage
CAPACITANCE
Parameter Input capacitance Output capacitance capacitance Symbol Conditions pins other than measured pins MIN. TYP. MAX. Unit
Data Sheet U11681EJ2V0DS00
PD78P4908
MAIN OSCILLATOR CHARACTERISTICS
Parameter Oscillator frequency Symbol Conditions Ceramic crystal resonator MIN. MAX. 12.58 Unit
Caution When using clock generator, wires according following rules avoid effects such stray capacitance: Minimize wiring length. Never cause wires cross other signal lines. Never cause wires near line carrying large varying current. grounding point capacitor oscillator circuit must always same potential VSS1. Never connect capacitor ground pattern carrying large current. Never extract signal from oscillator. Remark Connect 12.582912 6.291456 oscillator operate internal clock timer with main clock. CLOCK OSCILLATOR CHARACTERISTICS
Parameter Oscillator frequency Oscillation settling time Symbol Conditions Ceramic crystal resonator MIN. TYP. 32.768 MAX. Oscillation hold voltage Watch timer operating voltage VDDXT VDDW Unit
Data Sheet U11681EJ2V0DS00
PD78P4908
CHARACTERISTICS AVSS (1/2)
Parameter Input voltageNote Symbol VIL1 Conditions pins other than those described Notes pins described Note pins described Note pins other than those described Notes pins described Note pins described Note VOL2 pins described Note -100 VOH2 pins described Note MIN. -0.3 TYP. MAX. Unit
VIL2 VIL3
-0.3 -0.3
+0.8
Input high voltage
VIH1
VIH2 VIH3
Output voltage
VOL1
Output high voltage
VOH1
Notes RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, P107/SO3, XT1, P40/AD0-P47/AD7, P50/A8-P57/A15, P60/A16-P67/REFRQ/HLDAK, P00-P07 P00-P07 P10-P17, P40/AD0-P47/AD7, P50/A8-P57/A15 Other than pull-up resistors
Data Sheet U11681EJ2V0DS00
PD78P4908
CHARACTERISTICS AVDD AVSS (2/2)
Parameter Input leakage current Symbol Conditions pins other than Operation mode 12.58 6.29 12.58 fXX/8 (STBC B1H) Peripheral operation stops. 6.29 fXX/8 (STBC 31H) Peripheral operation stops. IDLE mode 12.58 6.29 MIN. TYP. MAX. Unit
Output leakage current supply current Note
HALT mode
10.4
Pull-up resistor
Note These values valid when internal regulator (REGOFF level). They include AVREF1 currents.
Data Sheet U11681EJ2V0DS00
PD78P4908
CHARACTERISTICS +85°C, AVSS Read/write operation
Parameter Address setup time ASTB) ASTB high-level width Address hold time ASTB) Address hold time Delay from address Address float time Delay from address data input Symbol SAST Conditions (0.5 MAX. Unit
MIN.
WSTH HSTLA DAID
(0.5 0.5T 0.5T
(2.5
Delay from ASTB data input DSTID Delay from data input Delay from ASTB Data hold time Delay from address active Delay from ASTB low-level width Delay from address Address hold time Delay from ASTB data output DRID DSTR HRID
(1.5 0.5T
0.5T
DRST DSTOD
0.5T (1.5 0.5T 0.5T
Delay from data output DWOD Delay from ASTB Data setup time Data hold time Delay from ASTB low-level width DSTW SODWR HWOD DWST 0.5T (1.5 0.5T 0.5T (1.5
Remark
tCYK (system clock cycle time) (MIN.) during address wait, otherwise, Number wait states
Data Sheet U11681EJ2V0DS00
PD78P4908
External wait timing
Parameter Symbol Conditions MIN. MAX. Unit
Delay from address WAIT DAWT input Delay from ASTB WAIT input DSTWT
1.5T
Hold time from ASTB WAIT HSTWT Delay from ASTB WAIT Delay from WAIT input Hold time from WAIT Delay from WAIT Delay from WAIT data input Delay from WAIT Delay from WAIT Delay from WAIT input Hold time from WAIT Delay from WAIT DSTWTH DRWTL
(0.5 (1.5
HRWT DRWTH DWTID
0.5T
DWTR DWTW DWWTL
0.5T 0.5T
HWWT DWWTH
Remark
tCYK (system clock cycle time) (MIN.) during address wait, otherwise, Number wait states
Data Sheet U11681EJ2V0DS00
PD78P4908
hold timing
Parameter Delay from HLDRQ float Symbol FHQC Conditions MIN. MAX. Unit
Delay from HLDRQ HLDAK DHQHHAH Delay from float HLDAK DCFHA
Delay from HLDRQ HLDAK DHQLHAL Delay from HLDRQ active DHAC
Remark
tCYK (system clock cycle time) (MIN.) during address wait, otherwise, Number wait states
Refresh timing
Parameter Random read/write cycle time REFRQ low-level pulse width Delay from ASTB REFRQ Delay from REFRQ Delay from REFRQ Delay from REFRQ ASTB REFRQ high-level pulse width Symbol WRFQL DSTRFQ DRRFQ DWRFQ DRFQST WRFQH Conditions 1.5T 0.5T 1.5T 1.5T 0.5T 1.5T MIN. MAX. Unit
Remark tCYK (system clock cycle time) (MIN.)
Data Sheet U11681EJ2V0DS00
PD78P4908
SERIAL OPERATION AVSS CSI, CSI3
Parameter Serial clock cycle time (SCK0, SCK3) Symbol CYSK0 Input Conditions Other than Output Other than fXX/8 fXX/8 Serial clock low-level width (SCK0, SCK3) WSKL0 Input Other than Output Other than fXX/8 fXX/8 Serial clock high-level width (SCK0, SCK3) WSKH0 Input Other than Output Other than fXX/8 fXX/8 Setup time SI0, SCK0, SCK3) Hold time SI0, SCK0, SCK3) Output delay time SO0, SCK0, SCK3) SSSK0 MIN. 16/fXX MAX. Unit
HSSK0
External clock Internal clock
1/fCLK External clock Internal clock 0.5tCYSK0 1/fCLK 1/fCLK
DSBSK1
CMOS push-pull output
DSBSK2
Open-drain output
External clock Internal clock
Output hold time SO0, SCK0, SCK3)
HSBSK
When data transferred
Remarks values this table those when 12.58 MHz, fCLK System clock frequency (selectable from fXX/2, fXX/8 standby control register (STBC)) Oscillation frequency 12.58 6.29 MHz)
Data Sheet U11681EJ2V0DS00
PD78P4908
IOE1, IOE2 AVSS
Parameter Serial clock cycle time (SCK1, SCK2) Symbol CYSK1 Input Conditions MIN. 1,280 Output Serial clock low-level width (SCK1, SCK2) WSKL1 Input Internal, divided Output Serial clock high-level width (SCK1, SCK2) WSKH1 Input Internal, divided 0.5T Output Setup time SCK1, SCK2) Hold time SCK1, SCK2) SSSK1 Internal, divided 0.5T MAX. Unit
HSSK1
Output delay time DSOSK SCK1, SCK2) Output hold time SCK1, SCK2) HSOSK When data transferred
0.5t CYSK1
Remarks values this table those when Serial clock cycle software. minimum value 8/fXX UART, UART2 AVDD AVSS
Parameter ASCK clock input cycle time Symbol CYASK Conditions MIN. ASCK clock low-level width WASKL ASCK clock high-level width WASKH MAX. Unit
Data Sheet U11681EJ2V0DS00
PD78P4908
CLOCK OUTPUT OPERATION +85°C, AVDD AVSS
Parameter CLKOUT cycle time CLKOUT low-level width Symbol CYCL 0.5T 0.5T CLKOUT high-level width 0.5T 0.5T CLKOUT rise time CLKOUT fall time Conditions MIN. MAX. 32,000 Unit
Remark
Dividing ratio software tCYK (system clock cycle time)
OTHER OPERATIONS AVDD AVSS
Parameter low-level width high-level width INTP0 low-level width INTP0 high-level width Low-level width INTP1INTP3 High-level width INTP1INTP3 Symbol WNIL WNIH WIT0L WIT0H WIT1L Conditions MIN. tCYSMP tCYSMP CYCPU MAX. Unit
WIT1H
CYCPU
Low-level width INTP4 WIT2L INTP5 High-level width INTP4 WIT2H INTP5 RESET low-level widthNote RESET high-level width WRSL WRSH
Note RESET low-level width ensure lapse oscillation settling time when power applied. Remark tCYSMP Sampling clock software tCYCPU: operation clock software
Data Sheet U11681EJ2V0DS00
PD78P4908
CONVERTER CHARACTERISTICS AVDD AVREF1
Parameter Resolution Total errorNote IEAD IEAD Quantization error Conversion time tCONV 120/f 240/f Sampling time tSAMP 18/f 36/f Analog input impedance AVREF1 impedance AVDD power supply voltage RREF1 AIDD1 AIDD2 STOP mode 19.1 1,000 Symbol Conditions MIN. ±1/2 TYP. MAX. Unit
Note Quantization error included. This parameter indicated ratio full-scale value. Caution execute conversion converter port multiplexed with input lines, output mode prevent data from being inverted. Remark fCLK: System clock frequency (selectable from fXX/2, fXX/4, XX/8 standby control register (STBC)) IEBus CONTROLLER CHARACTERISTICS -40°C +85°C, AVDD AVREF1 AVSS
Parameter IEBus standard frequencyNote Driver delay time (delay from output line)Note Receiver delay time (delay from line output)Note Transmission delay busNote Symbol Conditions Transfer speed: mode MIN. 6.20 TYP. 6.29 MAX. 6.39 Unit
tDTX
pFNote
tDRX
tDBUS
0.85
Notes value conforms IEBus standard. IEBus controller operable within range oscillator frequency oscillator characteristics. value measured when IEBus system clock: 6.29 MHz. load capacitance output line.
Data Sheet U11681EJ2V0DS00
PD78P4908
DATA RETENTION CHARACTERISTICS
Parameter Data retention voltage Data retention current Symbol VDDDR DDDR STOP mode STOP mode VDDDR AVREF Note VDDDR AVREF1 Note rise time fall time hold time STOP mode setting) STOP clear signal input time Oscillation settling time Conditions MIN. TYP. MAX. Unit
DREL WAIT Crystal resonator Ceramic resonator
DDDR VDDDR VDDDR
Input voltage Input high voltage
Specific
pins Note
Notes Valid when input voltages pins described Note satisfy above table. RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, P107/SO3 pins TIMING TEST POINTS
Test points
0.45
Data Sheet U11681EJ2V0DS00
PD78P4908
TIMING WAVEFORM Read operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTID tDRST
tDAID AD0-AD7 tDSTR tDAR tWRL tFRA tDRID
tHRA
tHRID tDRA
Write operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTOD tDWST
tHWA AD0-AD7 tDSTW tDAW tWWL tDWOD tSODWR tHWOD
Data Sheet U11681EJ2V0DS00
PD78P4908
HOLD TIMING
ASTB, A8-A19, AD0-AD7, tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC
EXTERNAL WAIT SIGNAL INPUT TIMING Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT tDWWTL WAIT tHWWT tDWWTH tDWTW
Data Sheet U11681EJ2V0DS00
PD78P4908
REFRESH TIMING WAVEFORM Random read/write cycle
ASTB
When refresh memory accessed read write same time
ASTB
tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
Refresh after read
ASTB tDRFQST tDRRFQ REFRQ tWRFQL
Refresh after write
ASTB tDRFQST tDWRFQ REFRQ tWRFQL
Data Sheet U11681EJ2V0DS00
PD78P4908
SERIAL OPERATION (CSI, CSI3)
tWSKL0 SCK0, SCK3 tCYSK0 SI0,
tWSKH0
tSSSK0 tHSSK0 Input data tDSBSK1 tHSBSK1
SO0,
Output data
SERIAL OPERATION (IOE1, IOE2)
tWSKL1 SCK1, SCK2 tCYSK1 SI1, tDSOSK SO1, tHSOSK tSSSK1 tHSSK1 tWSKH1
Input data
Output data
SERIAL OPERATION (UART, UART2)
tWASKH tWASKL
ASCK, ASCK2 tCYASK
CLOCK OUTPUT TIMING
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
Data Sheet U11681EJ2V0DS00
PD78P4908
INTERRUPT REQUEST INPUT TIMING
tWNIH tWNIL
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
INTP1-INTP3
tWIT2H
tWIT2L
INTP4, INTP5
RESET INPUT TIMING
tWRSH tWRSL
RESET
Data Sheet U11681EJ2V0DS00
PD78P4908
EXTERNAL CLOCK TIMING
tWXH tWXL
tCYX
DATA RETENTION CHARACTERISTICS
STOP mode setting
tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
(Clearing falling edge)
(Clearing rising edge)
Data Sheet U11681EJ2V0DS00
PD78P4908
PROGRAMMING CHARACTERISTICS ±5°C,
Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Output leakage current VDDP supply voltage
Symbol
SymbolNote
Conditions
MIN.
TYP.
MAX. VDDP
Unit
VDDP Note -400 VDDP Program memory write mode Program memory read mode
-0.3
+0.8
0.45
VDDP
6.25 12.2
12.5 VDDP
6.75 12.8
supply voltage
Program memory write mode Program memory read mode
VDDP supply current
Program memory write mode Program memory read mode
supply current
Program memory write mode Program memory read mode
Notes Symbols corresponding µPD27C1001A VDDP represents viewed programming mode.
Data Sheet U11681EJ2V0DS00
PD78P4908
PROGRAMMING CHARACTERISTICS 25°C ±5°C, PROM Write Mode (Page Program Mode)
Parameter Address setup time time Input data setup time Address hold time SymbolNote Input data hold time Output data hold time setup time VDDP setup time Initial program pulse width time Valid data delay time from pulse width data latch setup time hold time hold time tVPS VDSNote PGMS Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Notes These symbols (except tVDS) correspond those corresponding PD27C1001A. µPD27C1001A, read tVDS tVCS
Data Sheet U11681EJ2V0DS00
PD78P4908
PROM Write Mode (Byte Program Mode)
Parameter Address setup time time Input data setup time Address hold time Input data hold time Output data hold time setup time VDDP setup time Initial program pulse width time Valid data delay time from Symbol Note tVDSNote tOES Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Notes These symbols (except tVDS) correspond those corresponding PD27C1001A. µPD27C1001A, read tVDS tVCS PROM Read Mode
Parameter Data output time from address Delay from data output Delay from data output Data hold time Note Data hold time address Symbol Note Conditions MIN. TYP. MAX. Unit
Notes These symbols correspond those corresponding PD27C1001A. time measured from when either reaches VIH, whichever faster.
Data Sheet U11681EJ2V0DS00
PD78P4908
PROM Write Mode Timing (Page Program Mode)
Page data latch Page program Program verify
A2-A16 D0-D7 Hi-Z tVPS VDDP tVDS VDDP VDDP VDDP tCES tOES tCEH tOEH Data input Hi-Z tPGMS Data output Hi-Z tAHL tAHV
Data Sheet U11681EJ2V0DS00
PD78P4908
PROM Write Mode Timing (Byte Program Mode)
Program Program verify
A0-A16 D0-D7 Hi-Z Data input Hi-Z Data output Hi-Z
VDDP
tVPS VDDP VDDP VDDP tVDS tCES tOES
Cautions must applied before VPP, must after VPP. including overshoot must exceed 13.5 Plugging board with supplied with 12.5 adversely affect reliability. PROM Read Mode Timing
A0-A16
Valid address
tDFNote tACCNote D0-D7 Hi-Z tOENote Data output Hi-Z
Notes reading within tACC, delay input from falling edge must within ACC-tOE. time measured from when either reaches VIH, whichever faster.
Data Sheet U11681EJ2V0DS00
PD78P4908
PACKAGE DRAWING
100PIN PLASTIC (14x20)
detail lead
ITEM MILLIMETERS 23.6±0.4 20.0±0.2 14.0±0.2 17.6±0.4 0.30±0.10 0.15 0.65 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX. INCHES 0.929±0.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.693±0.016 0.031 0.024 0.012 +0.004 -0.005 0.006 0.026 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.004±0.004 5°±5° 0.119 MAX. P100GF-65-3BA1-3
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Remark shape material version same those corresponding mass-produced product.
Data Sheet U11681EJ2V0DS00
PD78P4908
RECOMMENDED SOLDERING CONDITIONS
conditions listed below shall when soldering µPD78P4908. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with sales offices case other soldering process used, case soldering done under different conditions. Table 10-1. Soldering Conditions Surface-Mount Devices
PD78P4908GF-3BA: 100-pin plastic
Soldering process Infrared reflow Soldering conditions Peak package's surface temperature: 235°C Reflow time: seconds less (210°C more) Maximum allowable number reflow processes: Exposure limit: days Note hours pre-baking required 125°C afterward) Peak package's surface temperature: 215°C Reflow time: seconds less (200°C more) Maximum allowable number reflow processes: Exposure limit: days Note hours pre-baking required 125°C afterward) Solder temperature: 260°C less Flow time: seconds less Number flow processes: Preheating temperature: 120°C MAX. (measured package surface) Exposure limit: days Note hours pre-baking required 125°C afterward) Partial heating method Terminal temperature: 300°C less Heat time: seconds less (for side device) Symbol IR35-207-2
VP15-207-2
Wave soldering
WS60-207-1
Note Maximum number days during which product stored temperature 25°C relative humidity less after dry-pack package opened. Caution apply more different soldering methods chip (except partial heating method terminal sections).
Data Sheet U11681EJ2V0DS00
PD78P4908
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using PD78P4908. also Notes using development tools. Language processing software
RA78K4 CC78K4 DF784908 CC78K4-L Assembler package 78K/IV series models compiler package 78K/IV series models Device file µPD784908 subseries models compiler library source file 78K/IV series models
PROM write tools
PG-1500 PA-78P4908GF PG-1500 controller PROM programmer Programmer adapter, connects PG-1500 Control program PG-1500
Debugging tools When using in-circuit emulator IE-78K4-NS
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A In-circuit emulator 78K/IV series models Power supply unit IE-78K4-NS Interface adapter when PC-9800 series computer (other than notebook) used host machine compatible) card interface cable when notebook used host machine (PCMCIA socket compatible) IE-70000-PC-IF-C Interface adapter when PC/ATcompatible used host machine (ISA compatible) Adapter when computer with host machine Emulation board evaluating µPD784908 subseries models Emulation probe 100-pin plastic (GF-3BA type) Socket mounting target system board made 100-pin plastic (GF-3BA type). Used mode. Integrated debugger IE-78K4-NS System simulator 78K/IV series models Device file µPD784908 subseries models
IE-7000-PCI-IF IE-784908-NS-EM1Note NP-100GFNote EV-9200GF-100
ID78K4-NS SM78K4 DF784908
Note Under development
Data Sheet U11681EJ2V0DS00
PD78P4908
When using in-circuit emulator IE-784000-R
IE-784000-R IE-70000-98-IF-C In-circuit emulator 78K/IV series models Interface adapter when PC-9800 series computer (other than notebook) used host machine compatible) Interface adapter when PC/AT compatible used host machine (ISA compatible) Adapter when computer with host machine Interface adapter cable when used host machine Emulation board evaluating µPD784908 subseries models Emulation board 78K/IV series models Conversion board emulation probes required IE-784908-NSEM1 IE-784000-R. board needed when conventional product IE-784908-R-EM1 used. Emulation probe 100-pin plastic (GF-3BA type) Socket mounting target system board made 100-pin plastic (GF-3BA type) Integrated debugger IE-784000-R System simulator 78K/IV series models Device file µPD784908 subseries models
IE-70000-PC-IF-C
IE-7000-PCI-IF IE-78000-R-SV3 IE-784908-NS-EM1 IE-784908-R-EM1 IE-784000-R-EM IE-78K4-R-EX2
EP-78064-GF-R EV-9200GF-100
ID78K4 SM78K4 DF784908
Real-time
RX78K/IV MX78K4 Real-time 78K/IV series models 78K/IV series models
Data Sheet U11681EJ2V0DS00
PD78P4908
Notes when using development tools ID78K4-NS, ID78K4, SM78K4 used combination with DF784908. CC78K4 RX78K/IV used combination with RA78K4 DF784908. NP-100GF product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult sales representative purchasing. host machines operating systems corresponding each software shown below.
Host machine [OS] PC-9800 series [WindowsTM] PC/AT compatibles [Windows] HP9000 series 700[HP-UXTM] SPARCstation[SunOSTM, Solaris NEWS(RISC) [NEWS-OSTM]
Software RA78K4 CC78K4 PG-1500 controller ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note Note Note Note
Note Software under MS-DOS
Data Sheet U11681EJ2V0DS00
PD78P4908
APPENDIX CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING
Connect PD78P4908GF-3BA (100-pin plastic mm)) circuit board combination with EV-9200GF-100. Figure B-1. Package Drawings EV-9200GF-100 (Reference)
EV-9200GF-100
No.1 index
EV-9200GF-100-G0 ITEM MILLIMETERS 24.6 18.6 12.0 22.6 25.3 16.6 19.3 0.35 INCHES 0.969 0.827 0.591 0.732 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.323 0.315 0.098 0.079 0.014
0.091 0.059
Data Sheet U11681EJ2V0DS00
PD78P4908
Figure B-2. Recommended Pattern Mount EV-9200GF-100 Substrate (Reference)
EV-9200GF-100-P1E ITEM Caution MILLIMETERS 26.3 21.6 INCHES 1.035 0.85
0.65±0.02 29=18.85±0.05 0.026 +0.001 1.142=0.742+0.002 -0.002 -0.002 0.65±0.02 19=12.35±0.05 0.026 +0.001 0.748=0.486 +0.003 -0.002 -0.002 15.6 20.3 0.05 0.05 0.35 0.02 0.614 0.799 0.472 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
Data Sheet U11681EJ2V0DS00
PD78P4908
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document name Document Japanese English U11680E This document U11787E U10905E U10095E
PD784907, 784908 Data Sheet PD78P4908 Data Sheet PD784908 Subseries User's Manual Hardware PD784908 Subseries Special Function Registers
78K/IV Series User's Manual Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction 78K/IV Series Application Note Software Basic
U11680J U11681J U11787J U11589J U10905J U10594J U10595J U10095J
Documents Related Development Tools (User's Manual)
Document name RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Base PG-1500 Controller Series Base IE-78K4-NS IE-784000-R IE-784908-R-EM1 IE-784908-NS-EM1 EP-78064 SM78K4 System Simulator Windows Base SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Document Japanese U11334J U11162J U11743J U11572J U11571J U11940J EEU-704 EEU-5008 U13356J U12903J U11876J U13743J EEU-934 U10093J U10092J English U11334E U11162E U11743E U11572E U11571E U11940E EEU-1291 U10540E U13356E U12903E preparation EEU-1469 U10093E U10092E
ID78K4-NS Integrated Debugger Base ID78K4 Integrated Debugger Windows Base
U12796J U10440J U11960J
U12796E U10440E U11960E
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base Reference
Caution above documents revised without notice. latest versions when design application systems.
Data Sheet U11681EJ2V0DS00
PD78P4908
Documents Related Software Incorporated into Product (User's Manual)
Document name 78K/IV Series Real-Time Fundamental Installation Debugger 78K/IV Series MX78K4 Fundamental Document Japanese U10603J U10604J U10364J U11779J English U10603E U10604E
Other Documents
Document name Package Manual (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Guide Quality Assurance Semiconductor Devices Guide Products Related Microcomputer: Other Companies C10535J C11531J C10983J C11892J U11416J Document Japanese English C13388E C10535E C11531E C10983E C11892E MEI-1202
Caution above documents revised without notice. latest versions when design application systems.
Data Sheet U11681EJ2V0DS00
PD78P4908
[MEMO]
Data Sheet U11681EJ2V0DS00
PD78P4908
[MEMO]
Data Sheet U11681EJ2V0DS00
PD78P4908
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U11681EJ2V0DS00
PD78P4908
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U11681EJ2V0DS00
PD78P4908
IEBus trademark Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. PC/AT trademarks Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks SONY Corporation. Some related documents preliminary versions. Note that, however, what documents preliminary indicated this document. export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative. application circuits their parameters reference only intended actual design-ins.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
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