µPD78P4038Y 16/8-BIT SINGLE-CHIP MICROCONTROLLER µPD78P4038Y

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µPD78P4038Y 16/8-BIT SINGLE-CHIP MICROCONTROLLER µPD78P4038Y

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INTEGRATED CIRCUIT
µPD78P4038Y
16/8-BIT SINGLE-CHIP MICROCONTROLLER
µPD78P4038Y, 78K/IV Series' product, one-time PROM EPROM version µPD784035Y, µPD784036Y, µPD784037Y, µPD784038Y with internal masked ROM. Since user programs written PROM, this microcontroller best suited evaluation system development, manufacture small quantities multiple products, fast start-up applications. specific functions other detailed information, consult following user's manual. This manual required reading design work. µPD784038, 784038Y Sub-Series User's Manual, Hardware U11316E 78K/IV Series User's Manual, Instruction U10905E
FEATURES
Compatible with µPD78P238, µPD78P4026, µPD78P4038 Internal PROM: Kbytes µPD78P4038YKK-T EPROM (best suited system evaluation) µPD78P4038YGC-3B9 PROM (best suited manufacture small quantities)
µPD78P4038YGC-8BT PROM (best suited manufacture small quantities) µPD78P4038YGK-BE9 PROM (best suited manufacture small quantities) Internal RAM: 4,352 bytes Supply voltage: QTOPmicrocomputer
Remark QTOP microcomputer microcomputer with built-in one-time PROM that totally supported NEC. support includes writing application programs, marking, screening, verification.
ORDERING INFORMATION
Part number Package 80-pin plastic 80-pin plastic 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin plastic TQFP (fine pitch) 80-pin ceramic WQFN Internal One-time PROM One-time PROM One-time PROM (QTOP microcomputer) One-time PROM One-time PROM (QTOP microcomputer) EPROM
µPD78P4038YGC-3B9 µPD78P4038YGC-8BT µPD78P4038YGK-BE9 µPD78P4038YKK-T
this reference, components that common one-time PROM EPROM referred PROM.
information this document subject change without notice. Document U10742EJ2V0DS00 (2nd edition) Date Published July 1998 CP(K) Printed Japan mark shows major revised points.
1995
µPD78P4038Y
QUALITY GRADE
Part number Package 80-pin plastic 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin ceramic WQFN Quality grade Standard (for general electronic equipment) Standard (for general electronic equipment) Standard (for general electronic equipment) Standard (for general electronic equipment) Standard (for general electronic equipment) applied (for function evaluation)
µPD78P4038YGC-3B9 µPD78P4038YGC-8BT µPD78P4038YGK-BE9 µPD78P4038YKK-T
80-pin plastic 80-pin plastic TQFP (fine pitch)
Please refer "Quality Grades Semiconductor Devices" (Document C11531E) published Corporation know specification quality grade devices recommended applications.
Caution EPROM versions µPD78P4038Y intended mass-produced products; they have reliability high enough such purposes. Their should restricted functional evaluation experiment trial manufacture. Remark code suffix.
µPD78P4038Y
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
Product under mass production Product under preparation
Standard Products Development
Connectable
PD784038Y µPD784038 PD784026
converters, 16-bit timers, power management functions have been enhanced. Internal memory been expanded. Pin-compatible with PD784026 Connectable multimaster
Connectable multimaster
µPD784225Y PD784225
pins correction function been added. Connectable multimaster
µPD784216Y PD784216
pins been enhanced. Internal memory been expanded.
µPD784218Y PD784218
Internal memory been expanded. correction function been added.
PD784054 PD784046
Built-in 10-bit converter
ASSP Development
PD784955
inverter control
PD784908
Built-in IEBuscontroller
PD784937
Functions PD784908 have been enhanced. Internal memory been expanded. correction function been added. Connectable multimaster
PD784928Y PD784915
Software servo control Built-in analog circuit Timers have been enhanced.
PD784928
Functions PD784915 have been enhanced.
µPD78P4038Y
FUNCTIONS
(1/2)
Item Number basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space ports Total Input Input/output Additional function pinsNote PROM bits registers banks, bits registers banks (memory mapping) ns/250 ns/500 ns/1,000 MHz) Functions
Kbytes (Can changed Kbytes software) 4,352 bytes (Can changed 2,048 3,584 bytes software) Program data: Mbyte
Pins with pull- resistor direct drive outputs Transistor direct drive
bits bits Timer/counter Timer register Capture register Compare register Timer/counter Timer register Capture register Capture/compare register Compare register Timer/counter Timer register Capture register Capture/compare register Compare register Timer Timer register Compare register Pulse output capability Toggle output PWM/PPG output One-shot pulse output Pulse output capability Real-time output bits
Real-time output ports Timer/counter
Pulse output capability Toggle output PWM/PPG output
outputs Serial interface
12-bit resolution channels UART/IOE (3-wire serial I/O): channels (incorporating baud rate generator) (3-wire serial I/O, 2-wire serial I/O, bus): channel 8-bit resolution channels 8-bit resolution channels
converter converter
Note Additional function pins included pins.
µPD78P4038Y
(2/2)
Item Clock output Watchdog timer Standby Interrupt Functions Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 (can used 1-bit output port) channel HALT/STOP/IDLE mode Hardware source internal, external (sampling clock variable input: Software source Nonmaskable Maskable instruction, BRKCS instruction, operand error internal, external internal, external 4-level programmable priority operation statuses: vectored interrupt, macro service, context switching Supply voltage Package 80-pin 80-pin 80-pin 80-pin plastic plastic plastic TQFP (fine pitch) ceramic WQFN
µPD78P4038Y
CONTENTS
DIFFERENCES BETWEEN µPD78P4038Y MASKED PRODUCTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM LIST FUNCTIONS
Pins Normal Operating Mode Pins PROM Programming Mode (VPP +12.5 RESET 4.2.1 4.2.2 functions functions
Circuits Pins Handling Unused Pins
INTERNAL MEMORY SWITCHING (IMS) REGISTER PROM PROGRAMMING
Operation Mode PROM Write Sequence PROM Read Sequence
ERASURE CHARACTERISTICS (µPD78P4038YKK-T ONLY) PROTECTIVE FILM COVERING ERASURE WINDOW (µPD78P4038YKK-T ONLY) QUALITY
SCREENING ONE-TIME PROM PRODUCTS ELECTRICAL CHARACTERISTICS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX CONVERSION SOCKET (EV-9200GC-80) CONVERSION ADAPTER (TGK-080SDW). APPENDIX RELATED DOCUMENTS
µPD78P4038Y
DIFFERENCES BETWEEN µPD78P4038Y MASKED PRODUCTS
µPD78P4038Y produced replacing masked µPD784035Y, µPD784036Y, µPD784037Y, µPD784038Y with PROM which data written. functions µPD78P4038Y same those µPD784035Y, µPD784036Y, µPD784037Y, µPD784038Y except PROM specification such writing verification, except that PROM size changed Kbytes, except that internal size changed 2,048 3,584 bytes. Table shows differences between these products. Table 1-1. Differences between µPD78P4038Y Masked Products
Product Name Item Internal program memory 128-Kbyte PROM changed Kbytes 48-Kbyte masked 64-Kbyte masked 96-Kbyte masked 128-Kbyte masked
µPD78P4038Y
µPD784035Y
µPD784036Y
µPD784037Y
µPD784038Y
Internal
4,352-byte 2,048-byte internal internal changed 2,048 3,584 bytes 80-pin plastic 80-pin plastic 80-pin plastic TQFP (fine pitch) 80-pin ceramic WQFN
3,584-byte internal
4,352-byte internal
Package
µPD78P4038Y
CONFIGURATION (TOP VIEW)
Normal operating mode 80-pin plastic
µPD78P4038YGC-3B9,
80-pin plastic
µPD78P4038YGC-8BT
80-pin plastic TQFP (fine pitch)
µPD78P4038YGK-BE9,
80-pin ceramic WQFN
µPD78P4038YKK-T
P25/INTP4/ASCK/SCK1
P31/ TxD/SO1
P23/INTP2/CI
P30/RxD/SI1
P22/INTP1
P24/INTP3
P26/INTP5
P21/INTP0
P77/ANI7
P76/ANI6
P32/SCK0/SCL P33/SO0/SDA P34/ P35/ P36/ P37/ RESET VDD1 VSS1 P67/REFRQ/HLDAK
P75/ANI5
P20/NMI
P27/SI0
AVREF3
AVREF2
AVREF1
ANO1
ANO0
AVDD
AVSS
P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD0 P14/TXD2/SO2 P13/RXD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 TESTNote VSS0 ASTB/CLKOUT P40/AD0 P41/AD1 P42/AD2
P66/ WAIT/HLDRQ
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Note
Connect TEST VSS0 directly.
P43/AD3
P65/
P64/RD
µPD78P4038Y
A8-A19 AD0-AD7 ANI0-ANI7 Address Address/data Analog input P60-P67 P70-P77 REFRQ RESET RxD, RxD2 SCK0-SCK2 SI0-SI2 SO0-SO2 TEST TO0-TO3 TxD, TxD2 VDD0, VDD1 VSS0, VSS1 WAIT Port Port Read strobe Refresh request Reset Receive data Serial clock Serial clock Serial data Serial input Serial output Test Timer output Transmit data Power supply Ground Wait Write strobe Crystal
PWM0, PWM1 Pulse width modulation output
ANO0, ANO1 Analog output ASCK, ASCK2 Asynchronous serial clock ASTB AVDD AVSS CLKOUT HLDAK HLDRQ P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 Address strobe Analog power supply Analog ground Clock input Clock output Hold acknowledge Hold request Non-maskable interrupt Port Port Port Port Port Port
AVREF1-AVREF3 Reference voltage
INTP0-INTP5 Interrupt from peripherals
µPD78P4038Y
PROM programming mode 80-pin plastic
µPD78P4038YGC-3B9,
80-pin plastic
µPD78P4038YGC-8BT
80-pin plastic TQFP (fine pitch)
µPD78P4038YGK-BE9,
80-pin ceramic WQFN
µPD78P4038YKK-T
Open Open Open
Open
RESET Open
Open
Open
Open
Caution
Connect these pins separately pins through 10-k pull-down resistors. connected ground.
Open Nothing should connected these pins. RESET: low-level input. A0-A16 D0-D7 Address Chip enable Data Output enable Program RESET Reset Power supply Programming power supply Ground
µPD78P4038Y
BLOCK DIAGRAM
INTP0-INTP5 INTP3 Programmable interrupt controller UART/IOE2 Baud-rate generator UART/IOE1 Timer/counter bits) Baud-rate generator Clocked serial interface Clock output Timer/counter bits) K/IV core (RAM bytes) PROM (128 Kbytes) RXD/SI1 TXD/SO1 ASCK/SCK1 RXD2/SI2 TXD2/SO2 ASCK2/SCK2 SCK0/SCL SO0/SDA ASTB/CLKOUT AD0-AD7 A8-A15 A16-A19 WAIT/HLDRQ REFRQ/HLDAK D0-D7Note A0-A16Note CENote OENote PGMNote (3,840 bytes) Port Port Port converter Port Port Port ANI0-ANI7 AVDD AVREF1 AVSS INTP5 Watchdog timer System control converter Port Port P60-P67 P70-P77
RESET TEST Note VDD0, VDD1 VSS0, VSS1
INTP0
Timer/counter bits)
INTP1 INTP2/CI
Timer bits)
interface
P00-P03 P04-P07 PWM0
Real-time output port
P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57
PWM1
ANO0 ANO1 AVREF2 AVREF3
Note
PROM programming mode.
µPD78P4038Y
LIST FUNCTIONS
Pins Normal Operating Mode
Port pins (1/2)
P00-P07 Alternate-Function Function Port (P0): 8-bit port. Functions real-time output port bits Inputs outputs specified bit. pull-up resistors specified software pins input mode together. drive transistor. Port (P1): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together. drive LED.
P15-P17 P34-P37 P40-P47
PWM0 PWM1 ASCK2/SCK2 RXD2/SI2 TXD2/SO2
Input
Port (P2): 8-bit input-only port. INTP0 does function general-purpose port (nonmaskable INTP1 interrupt). However, input level checked interrupt service routine. INTP2/CI pull-up resistors specified software pins INTP3 units bits). INTP4/ASCK/SCK1 P25/INTP4/ASCK/SCK1 functions SCK1 output INTP5 CSIM1.
RXD/SI1 TXD/SO1 SCK0/SCL SO0/SDA TO0-TO3
Port (P3): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together.
AD0-AD7
Port (P4): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together. drive LED.
µPD78P4038Y
Port pins (2/2)
P50-P57 Alternate-Function A8-A15 Function Port (P5): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together. drive LED. Port (P6): 8-bit port. Inputs outputs specified bit. pull-up resistors specified software pins input mode together.
P60-P63 P70-P77
A16-A19 WAIT/HLDRQ REFRQ/HLDAK
ANI0-ANI7
Port (P7): 8-bit port. Inputs outputs specified bit.
µPD78P4038Y
Non-port pins (1/2)
TO0-TO3 RXD2 TXD2 ASCK ASCK2 SCK0 SCK1 SCK2 INTP0 Input Output Input Input Output Output Input Input Alternate-Function P34-P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P33/SO0 P30/RXD P13/RXD2 P33/SDA P31/TXD P14/TXD2 P32/SCL P25/INTP4/ASCK P12/ASCK2 P32/SCK0 Timer output Input count clock timer/counter Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data (2-wire serial I/O, bus) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock (3-wire serial I/O0) Serial clock (3-wire serial I/O1) Serial clock (3-wire serial I/O2) Serial clock (2-wire serial I/O, bus) External interrupt request Input count clock timer/counter Capture/trigger signal CR11 CR12 Input count clock timer/counter Capture/trigger signal CR22 Input count clock timer/counter Capture/trigger signal CR21 Input count clock timer/counter Capture/trigger signal CR02 Input conversion start trigger converter Time multiplexing address/data (for connecting external memory) High-order address (for connecting external memory) High-order address during address expansion (for connecting external memory) Strobe signal output reading contents external memory Strobe signal output writing external memory Wait signal insertion Refresh pulse output external pseudo static memory Input hold request Output hold response Latch timing output time multiplexing address (A0-A7) (for connecting external memory) Clock output Function
INTP1
INTP2
P23/CI
INTP3
INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 WAIT REFRQ HLDRQ HLDAK ASTB Output Output Output Output Input Output Input Output Output
P25/ASCK/SCK1 P40-P47 P50-P57 P60-P63 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT
CLKOUT
Output
ASTB
µPD78P4038Y
Non-port pins (2/2)
RESET ANI0-ANI7 ANO0, ANO1 AVREF1 AVREF2, AVREF3 AVDD AVSS VDD0Note VDD1Note VSS0Note VSS1Note TEST Input Input Input Output P70-P77 Alternate-Function Chip reset Crystal input system clock oscillation clock pulse also input pin.) Analog voltage inputs converter Analog voltage inputs converter Application converter reference voltage Application converter reference voltage Positive power supply converter Ground converter Positive power supply port part Positive power supply except port part Ground port part Ground except port part Directly connect VSS0. (The TEST test.) Function
Notes potential VDD0 must equal that VDD1 pin. potential VSS0 must equal that VSS1 pin. Pins PROM Programming Mode (VPP +12.5 RESET
4.2.1 functions
Name PROM programming mode selection High voltage input during program write verification RESET A0-A16 D0-D7 Input Input PROM programming mode selection Address Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input during PROM programming mode Positive power supply Function
µPD78P4038Y
4.2.2 functions
(Programming power supply): Input Input setting µPD78P4038Y PROM programming mode. When input voltage this more when RESET input goes low, µPD78P4038Y enters PROM programming mode. When made +12.5 high, program data written into internal PROM cell selected A16. RESET (Reset): Input Input setting µPD78P4038Y PROM programming mode. When input this low, when input voltage goes more, µPD78P4038Y enters PROM programming mode. (Address bus): Input Address that selects internal PROM address (0000H 1FFFFH) (Data bus): Data through which program written read from internal PROM (Chip enable): Input This inputs enable signal from internal PROM. When this signal active, program written read. (Output enable): Input This inputs read strobe signal internal PROM. When this signal made active low, onebyte program internal PROM cell selected read onto (Program): Input input operation mode control signal internal PROM. Upon activation, writing internal PROM enabled. Upon inactivation, reading from internal PROM enabled. Positive power supply Ground potential
µPD78P4038Y
Circuits Pins Handling Unused Pins
Table describes types circuits pins handling unused pins. Figure shows configuration these various types circuits. Table 4-1. Types Circuits Pins Handling Unused Pins (1/2)
P00-P07 P10/PWM0 P11/PWM1 P12/ASCK2/SCK2 P13/RXD2/SI2 P14/TXD2/SO2 P15-P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 Input state: connected VDD0 Output state: left open connected VDD0 connected VDD0 Input connected VDD0 VSS0 Circuit Type Recommended Connection Method Unused Pins Input state: connected VDD0 Output state: left open
P26/INTP5 P27/SI0 P30/RXD/SI1 P31/TXD/SO1 P32/SCK0/SCL P33/SO0/SDA P34/TO0-P37/TO3 P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7
Input
Input state: connected VDD0 Output state: left open
10-B
20-A
Input state: connected VDD0 VSS0 Output state: left open left open
ANO0, ANO1 ASTB/CLKOUT
Output
µPD78P4038Y
Table 4-1. Types Circuits Pins Handling Unused Pins (2/2)
RESET TEST AVREF1-AVREF3 AVSS AVDD connected VDD0 Circuit Type Input connected VSS0 directly connected VSS0 Recommended Connection Method Unused Pins
Caution When mode alternate-function unpredictable, connect VDD0 through resistor kilohms (particularly when voltage reset input becomes higher than that level input power-on when switched software). Remark Since type numbers consistent Series, those numbers always serial each product. (Some circuits included.)
µPD78P4038Y
Figure 4-1. Circuits Pins
Type VDD0 VSS0 Type
Type
VDD0 Pull-up enable
Schmitt trigger input with hysteresis characteristics
Type
Schmitt trigger input with hysteresis characteristics
VDD0 Pull-up enable Data VDD0 IN/OUT Output disable VSS0
Type
Data
VDD0 Output disable VSS0
Push-pull output which output high impedance (both positive negative channels off.)
Input enable
Type VDD0 Pull-up enable Data VDD0 IN/OUT Output disable VSS0
Type
Analog output voltage
Type 10-B
Type 20-A VDD0 Data
VDD0 Pull-up enable VDD0 IN/OUT VSS0
IN/OUT
Output disable VSS0 Comparator AVSS AVREF (Threshold voltage) Input enable
Data Open drain Output disable
µPD78P4038Y
INTERNAL MEMORY SWITCHING (IMS) REGISTER
This register enables software avoid using part internal memory. register establish same memory mapping used products that have different internal memory (ROM RAM) configurations. register using 8-bit memory operation instructions. RESET input sets register FFH. Figure 5-1.
IMS7 IMS6 IMS5 IMS4
Internal Memory Switching (IMS) Register
IMS3 IMS2 IMS1 IMS0 Address 0FFFCH After Reset
IMS0-7
Memory Size Same µPD784038Y Same µPD784037Y Same µPD784036Y Same µPD784035Y
contained mask product (µPD784035Y, µPD784036Y, µPD784037Y, µPD784038Y). action affected write command executed mask product.
µPD78P4038Y
PROM PROGRAMMING
µPD78P4038Y on-chip 128-KB PROM device program memory. When programming, RESET pins PROM programming mode. Chapter with regard handling other, unused pins. Operation Mode
PROM programming mode selected when +12.5 added low-level input added RESET pin. This mode operation mode setting pin, pin, shown Table below. addition, PROM contents read setting read mode. Table 6-1. PROM Programming Operation Mode
Operation Mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High impedance High impedance Data input High impedance Data input Data output High impedance RESET D0-D7
Remark
µPD78P4038Y
Read mode read mode. Output disable mode high impedance data output output disable mode. Consequently, several µPD78P4038Y devices connected data bus, pins controlled select data output from devices. Standby mode standby mode. this mode, data output high impedance regardless setting. Page data latch mode beginning page write mode, page data latch mode. this mode, page bytes) data latched internal address/data latch circuit. Page write mode After latching address data page bytes) using page data latch mode, adding program pulse (active, low) with both causes page write executed. Later, setting both causes program verification executed. programming completed after program pulse, write verify operations repeated times (where 10). Byte write mode Adding program pulse (active, low) with both causes byte write executed. Later, setting causes program verification executed. programming completed after program pulse, write verify operations repeated times (where 10). Program verify mode program verify mode. verify mode verification following each write operation. Program inhibit mode Program inhibit mode used write single device when several µPD78P4038Y devices connected parallel VPP, pins. page write mode byte write mode described above each write operation. Write operations cannot done devices which been
µPD78P4038Y
PROM Write Sequence Figure 6-1. Page Program Mode Flowchart
Start Address +6.5 +12.5 Latch Address Address Latch Address Address Latch Address Address Latch X=X+1 program pulse
Address Address
Verify bytes Pass Address 4.5-5.5
Fail
Pass
Verify bytes pass Write
Fail
Defective
Remark Start address Program address
µPD78P4038Y
Figure 6-2.
Page data latch
Page Program Mode Timing
Page program Program verify
A2-A16
D0-D7 Data input VDD+1.5 Data output
µPD78P4038Y
Figure 6-3. Byte Program Mode Flowchart
Start Address +6.5 +12.5 program pulse Fail Address Address
Verify Pass Address 4.5-5.5 Pass
Verify bytes pass Write
Fail
Defective
Remark Start address Program address
µPD78P4038Y
Figure 6-4. Byte Program Mode Timing
Program Program verify
A0-A16
D0-D7
Data input
Data output
VDD+1.5
Cautions before VPP, turn after VPP. allow exceed +13.5 including overshoot. Reliability problems result device inserted pulled while +12.5 applied VPP.
µPD78P4038Y
PROM Read Sequence
Follow this sequence read PROM contents external data D7). RESET level pin. Chapter with regard handling other, unused pins. pins. Input data address read pins A16. read mode. Output data pins Figure shows timing steps above. Figure 6-5. PROM Read Timing
A0-A16
Address input
(input)
(input)
D0-D7
Hi-Z
Data output
Hi-Z
µPD78P4038Y
ERASURE CHARACTERISTICS (µPD78P4038YKK-T ONLY)
Data written µPD78P4038YKK-T program memory erased (FFH); therefore users write other data memory. erase written data, expose erasure window light with wavelength shorter than approx. Normally, ultraviolet light with wavelength employed. amount light required completely erase data follows: Intensity ultraviolet light erasing time: 57.6 min. Erasing time: About minutes (When using 12,000 µW/cm2 ultraviolet lamp. may, however, take more time lamp deterioration, dirt erasure window, like.) ultraviolet lamp should placed within from erasure window during erasure. addition, filter attached ultraviolet lamp, remove filter before erasure.
PROTECTIVE FILM COVERING ERASURE WINDOW (µPD78P4038YKK-T ONLY)
prevent EPROM from being erased inadvertently light other than that from lamp used erasing EPROM, prevent internal circuits other than EPROM from malfunctioning light, stick protective film erasure window except when EPROM erased.
QUALITY
µPD78P4038YKK-T intended mass-produced products; they have reliability high enough such purposes. Their should restricted functional evaluation experiment trial manufacture.
SCREENING ONE-TIME PROM PRODUCTS
cannot execute complete test one-time PROM products (µPD78P4038YGC-3B9, µPD78P4038YGC8BT, µPD78P4038YGK-BE9) their structure before shipment. recommended that screen (verify) PROM products after writing necessary data into them storing them 125°C hours.
µPD78P4038Y
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS 25°C)
Parameter Supply voltage Symbol AVDD AVSS Input voltage TEST/VPP P21/INTP0/A9 PROM programming mode Conditions Rating -0.5 +7.0 AVSS -0.5 +0.5 -0.5 -0.5 +13.5 Unit
Output voltage Output current
Total output pins
-0.5 -100 -0.5
Output high current
Total output pins
converter reference input voltage converter reference input voltage Operating ambient temperature Storage temperature
AVREF1
AVREF2 AVREF3 Tstg
-0.5 -0.5 +150
Caution Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values.
µPD78P4038Y
OPERATING CONDITIONS Operating ambient temperature (TA) Power supply voltage clock cycle time +85°C Figure 11-1. Rise time fall time (tr, pins which specified)
Figure 11-1. Power Supply Voltage Clock Cycle Time
10,000 4,000
Clock cycle time tCYK [ns]
1,000 Guaranteed operating range 62.5
Power supply voltage
CAPACITANCE 25°C,
Parameter Input capacitance Output capacitance capacitance Symbol Conditions pins other than measured pins MIN. TYP. MAX. Unit
µPD78P4038Y
OSCILLATOR CHARACTERISTICS +85°C, +4.5
Resonator Ceramic resonator crystal Recommended Circuit Parameter Oscillator frequency (fXX) MIN. MAX. Unit
VSS1
External clock
input frequency (fX)
input rise fall times (tXR, tXF) input high-level lowlevel widths (tWXH, tWXL)
HCMOS inverter
Caution When using system clock generator, wires portion surrounded broken lines according following rules avoid effects such stray capacitance: Minimize wiring. Never cause wires cross other signal lines. Never cause wires near line carrying large varying current. Cause grounding point capacitor oscillator circuit have same potential VSS1. Never connect capacitor ground pattern carrying large current. Never extract signal from oscillator.
µPD78P4038Y
OSCILLATOR CHARACTERISTICS +85°C, +2.7
Resonator Ceramic resonator crystal Recommended Circuit Parameter Oscillator frequency (fXX) MIN. MAX. Unit
VSS1
External clock
input frequency (fX)
input rise fall times (tXR, tXF) input high-level lowlevel widths (tWXH, tWXL)
HCMOS inverter
Caution When using system clock generator, wires portion surrounded broken lines according following rules avoid effects such stray capacitance: Minimize wiring. Never cause wires cross other signal lines. Never cause wires near line carrying large varying current. Cause grounding point capacitor oscillator circuit have same potential VSS1. Never connect capacitor ground pattern carrying large current. Never extract signal from oscillator.
µPD78P4038Y
CHARACTERISTICS +85°C, AVDD +2.7 AVSS (1/2)
Parameter Input voltage Symbol VIL1 Conditions pins other than those described Notes pins described Notes +5.0 pins described Notes pins other than those described Notes pins described Notes +5.0 pins described Notes pins other than those described Note pins described Note pins described Note VOL3 +5.0 pins described Notes +5.0 pins described Note EXTC VIL2 EXTC VIH2 MIN. -0.3 TYP. MAX. 0.3VDD Unit
VIL2
-0.3
0.2VDD
VIL3
-0.3
+0.8
Input high voltage
VIH1
0.7VDD
VIH2 VIH3
0.8VDD
Output voltage
VOL1
VOL2
Output high voltage
VOH1 VOH2
input current
input high current
Notes RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, TEST P40/AD0 P47/AD7, P50/A8 P57/A15 P60/A16 P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK P32/SCK0/SCL, P33/SO0/SDA
µPD78P4038Y
CHARACTERISTICS +85°C, AVDD +2.7 AVSS (2/2)
Parameter Input leakage current Symbol Conditions pins other than when EXTC Operation mode +5.0 +2.7 IDD2 HALT mode +5.0 +2.7 IDD3 IDLE mode (EXTC +5.0 +2.7 Pull-up resistor MIN. TYP. MAX. Unit
Output leakage current supply current
IDD1
µPD78P4038Y
CHARACTERISTICS +85°C, AVDD +2.7 AVSS Read/write operation (1/2)
Parameter Address setup time Symbol tSAST Conditions +5.0 MIN. (0.5 (0.5 ASTB high-level width tWSTH +5.0 (0.5 (0.5 Address hold time ASTB) tHSTLA +5.0 0.5T 0.5T Address hold time Delay from address tHRA tDAR +5.0 0.5T Address float time Delay from address data input tFRA tDAID +5.0 (2.5 (2.5 Delay from ASTB data input tDSTID +5.0 Delay from data input tDRID +5.0 (1.5 (1.5 Delay from ASTB Data hold time Delay from address active tDSTR tHRID tDRA After program read After data read Delay from ASTB low-level width tDRST tWRL +5.0 +5.0 0.5T 0.5T 0.5T +5.0 1.5T 1.5T 0.5T (1.5 (1.5 Address hold time Delay from address tHWA tDAW +5.0 0.5T Delay from ASTB data output tDSTOD +5.0 0.5T 0.5T Delay from data output Delay from ASTB tDWOD tDSTW 0.5T 0.5T MAX. Unit
Remarks tCYK (system clock cycle time) (during address wait), otherwise, Number wait states
µPD78P4038Y
Read/write operation (2/2)
Parameter Data setup time Symbol tSODW Conditions +5.0 MIN. (1.5 (1.5 Data hold time WR)Note tHWOD +5.0 0.5T 0.5T Delay from ASTB low-level width tDWST tWWL +5.0 0.5T (1.5 (1.5 MAX. Unit
Note hold time includes time during which VOH1 VOL1 held under load conditions Remarks tCYK (system clock cycle time) Number wait states
hold timing
Parameter Delay from HLDRQ float Symbol tFHQC Conditions MIN. MAX. Delay from float HLDAK Delay from HLDRQ HLDAK tDCFHA tDHQLHAL +5.0 Delay from HLDAK active tDHAC +5.0 Unit
Delay from HLDRQ HLDAK tDHQHHAH +5.0
Remarks tCYK (system clock cycle time) (during address wait), otherwise, Number wait states
µPD78P4038Y
External wait timing
Parameter Delay from address WAIT input Symbol tDAWT Conditions +5.0 MIN. MAX. Delay from ASTB WAIT input tDSTWT +5.0 1.5T 1.5T Hold time from ASTB WAIT tHSTWTH +5.0 (0.5 (0.5 Delay from ASTB WAIT tDSTWTH +5.0 (1.5 (1.5 Delay from WAIT input tDRWTL +5.0 Hold time from WAIT tHRWT +5.0 Delay from WAIT tDRWTH +5.0 Delay from WAIT data input tDWTID +5.0 0.5T 0.5T Delay from WAIT Delay from WAIT Delay from WAIT input tDWTW tDWTR tDWWTL +5.0 0.5T 0.5T Hold time from WAIT tHWWT +5.0 Delay from WAIT tDWWTH +5.0 Unit
Remarks tCYK (system clock cycle time) (during address wait), otherwise, Number wait states
Refresh timing
Parameter Random read/write cycle time REFRQ low-level pulse width Symbol tWRFQL +5.0 Conditions MIN. 1.5T 1.5T Delay from ASTB REFRQ Delay from REFRQ Delay from REFRQ Delay from REFRQ ASTB REFRQ high-level pulse width tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH +5.0 0.5T 1.5T 1.5T 0.5T 1.5T 1.5T MAX. Unit
Remark tCYK (system clock cycle time)
µPD78P4038Y
SERIAL OPERATION +85°C, +2.7 AVSS
Parameter Serial clock cycle time (SCK0) Symbol tCYSK0 Input Conditions External clock When SCK0 CMOS MIN. 10/fXX MAX. Unit
Output Serial clock low-level width (SCK0) tWSKL0 Input External clock When SCK0 CMOS
5/fXX
Output Serial clock high-level width (SCK0) tWSKH0 Input External clock When SCK0 CMOS
0.5T 5/fXX
Output setup time SCK0) hold time SCK0) output delay time SCK0) tSSSK0 tHSSK0 tDSBSK1 CMOS push-pull output (3-wire serial mode) Open-drain output (2-wire serial mode),
0.5T 5/fXX
tDSBSK2
Remarks values this table those when Serial clock cycle software. minimum value 16/fXX. Oscillator frequency
Parameter Symbol Standard Mode MIN. clock frequency Time hold clock Time hold high clock Data hold time Data setup time Rise time signal Fall time signal Load capacitance each line fSCL tLOW tHIGH tHD; tSU; 1,000 MAX. Standard Mode MIN. 0.1Cb MAX. Unit
0.1Cb
µPD78P4038Y
IOE1, IOE2
Parameter Serial clock cycle time (SCK1, SCK2) Symbol tCYSK1 Input Conditions +5.0 MIN. Output Serial clock low-level width (SCK1, SCK2) tWSKL1 Input Internal, divided +5.0 Output Serial clock high-level width (SCK1, SCK2) tWSKH1 Input Internal, divided +5.0 0.5T Output Setup time SCK1, SCK2) Hold time SCK1, SCK2) Output delay time SCK1, SCK2) Output hold time SCK1, SCK2) tSSSK1 Internal, divided 0.5T MAX. Unit
tHSSK1
tDSOSK
tHSOSK
When data transferred
0.5tCYSK1
Remarks values this table those when Serial clock cycle software. minimum value 16/fXX. UART, UART2
Parameter ASCK clock input cycle time Symbol tCYASK Conditions +5.0 MIN. ASCK clock low-level width tWASKL +5.0 52.5 ASCK clock high-level width tWASKH +5.0 52.5 MAX. Unit
µPD78P4038Y
CLOCK OUTPUT OPERATION
Parameter CLKOUT cycle time CLKOUT low-level width Symbol tCYCL tCLL +5.0 Conditions MIN. 0.5tCYCL 0.5tCYCL CLKOUT high-level width tCLH +5.0 0.5tCYCL 0.5tCYCL CLKOUT rise time tCLR +5.0 CLKOUT fall time tCLF +5.0 MAX. Unit
Remarks
Divided frequency ratio software
tCYK (system clock cycle time) OTHER OPERATIONS
Parameter low-level width high-level width INTP0 low-level width INTP0 high-level width Low-level width INTP1INTP3 High-level width INTP1INTP3 Low-level width INTP4 INTP5 High-level width INTP4 INTP5 RESET low-level width RESET high-level width Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L Conditions MIN. 4tCYSMP 4tCYSMP 4tCYCPU MAX. Unit
tWIT1H
4tCYCPU
tWIT2L
tWIT2H
tWRSL tWRSH
Remarks tCYSMP: Sampling clock software tCYCPU: operation clock software
µPD78P4038Y
CONVERTER CHARACTERISTICS +85°C, AVDD AVREF1 +2.7 AVSS
Parameter Resolution Total errorNote AVDD +5.0 AVDD +2.7 +85°C Linearity calibrationNote Quantization error Conversion time tCONV Sampling time tSAMP Analog input voltage Analog input impedance AVREF1 current AVDD supply current VIAN AIREF1 AIDD1 AIDD2 MHz, STOP mode, -0.3 1,000 AVREF1 Symbol Conditions MIN. TYP. MAX. Unit
±1/2
tCYK tCYK tCYK tCYK
Note Quantization error included. This parameter indicated ratio full-scale value. Remark tCYK: System clock cycle time
µPD78P4038Y
CONVERTER CHARACTERISTICS +85°C, AVDD +2.7 AVSS
Parameter Resolution Total error Load conditions: AVDD AVREF2 +2.7 AVREF3 AVDD +2.7 AVREF2 0.75VDD AVREF3 0.25VDD Load conditions: AVDD AVREF2 +2.7 AVREF3 AVDD +2.7 AVREF2 0.75VDD AVREF3 0.25VDD Settling time Output resistance Analog reference voltage AVREF2 AVREF3 Resistance AVREF2 AVREF3 Reference power supply input current RAIREF DACS0, Load conditions: DACS0, 0.75VDD 0.25VDD Symbol Conditions MIN. TYP. MAX. Unit
AIREF2 AIREF3
µPD78P4038Y
DATA RETENTION CHARACTERISTICS +85°C)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR +2.7 VDDDR +2.5 rise time fall time hold time STOP mode setting) STOP clear signal input time Oscillation settling time tRVD tFVD tHVD Conditions MIN. TYP. MAX. Unit
tDREL tWAIT Crystal Ceramic resonator
0.9VDDDR 0.1VDDDR VDDDR
Input voltage Input high voltage
Specific pinsNote
Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA pins TIMING TEST POINTS
0.8VDD Test points 0.45 0.8VDD
µPD78P4038Y
TIMING WAVEFORM Read operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTID tDRST
tDAID AD0-AD7 tDSTR tDAR tWRL tFRA tDRID
tHRA
tHRID tDRA
Write operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTOD tDWST
tHWA AD0-AD7 tDSTW tDAW tWWL tDWOD tSODW tHWOD
µPD78P4038Y
HOLD TIMING
ADTB, A8-A19, AD0-AD7, tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC
EXTERNAL WAIT SIGNAL INPUT TIMING Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT tDWWTL WAIT tHWWT tDWWTH tDWTW
µPD78P4038Y
REFRESH TIMING WAVEFORM Random read/write cycle
ASTB
When refresh memory accessed read write same time
ASTB
tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
Refresh after read
ASTB tDRFQST tDRRFQ REFRQ tWRFQL
Refresh after write
ASTB tDRFQST tDWRFQ REFRQ tWRFQL
µPD78P4038Y
SERIAL OPERATION
tWSKL0 tCYSK0 tDSBSK1 Output data tSSSK0 tHSSK0 Input data tWSKH0
tHD;DAT tSU;DAT tHIGH tLOW
IOE1, IOE2
tWSKL1 tCYSK1 tDSOSK tHSOSK tSSSK1 tHSSK1 tWSKH1
Input data
Output data
UART, UART2
tWASKH
tWASKL
ASCK, ASCK2 tCYASK
µPD78P4038Y
CLOCK OUTPUT TIMING
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
INTERRUPT INPUT TIMING
tWNIH tWNIL
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
INTP1-INTP3
tWIT2H
tWIT2L
INTP4, INTP5
RESET INPUT TIMING
tWRSH tWRSL
RESET
µPD78P4038Y
EXTERNAL CLOCK TIMING
tWXH tWXL
tCYX
DATA RETENTION CHARACTERISTICS
STOP mode setting
tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
(Clearing falling edge)
(Clearing rising edge)
µPD78P4038Y
PROGRAMMING CHARACTERISTICS 5°C,
Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Output leakage current VDDP supply voltage Symbol SymbolNote Conditions MIN. TYP. MAX. VDDP Unit
VDDPNote -400 VDDP, Program memory write mode Program memory read mode
-0.3
ILIP
0.45
VDDP
6.25 12.2
12.5 VDDP
6.75 12.8
supply voltage
Program memory write mode Program memory read mode
VDDP supply current
Program memory write mode Program memory read mode
supply current
Program memory write mode Program memory read mode
Notes Symbols corresponding µPD27C1001A VDDP represents viewed programming mode.
µPD78P4038Y
PROGRAMMING CHARACTERISTICS 5°C, PROM Write Mode (Page Program Mode)
Parameter Address setup time time Input data setup time Address hold time SymbolNote tCES tAHL tAHV Input data hold time Output data hold time setup time VDDP setup time Initial program pulse width time Valid data delay time from pulse width data latch setup time hold time hold time tVPS tVDSNote tOES tPGMS tCEH tOEH Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Notes These symbols (except tVDS) correspond those corresponding µPD27C1001A. µPD27C1001A, read tVDS tVCS.
µPD78P4038Y
PROM Write Mode (Byte Program Mode)
Parameter Address setup time time Input data setup time Address hold time Input data hold time Output data hold time setup time VDDP setup time Initial program pulse width time Valid data delay time from SymbolNote tCES tVPS tVDSNote tOES Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Notes These symbols (except tVDS) correspond those corresponding µPD27C1001A. µPD27C1001A, read tVDS tVCS. PROM Read Mode
Parameter Data output time from address Delay from data output Delay from data output Data hold time Note SymbolNote tACC Conditions MIN. TYP. MAX. Unit
Data hold time address
Notes These symbols correspond those corresponding µPD27C1001A. time measured from when either reaches VIH, whichever faster.
µPD78P4038Y
PROM Write Mode Timing (Page Program Mode)
Page data latch Page program Program verify
A2-A16 D0-D7 Hi-Z tVPS VDDP tVDS VDDP VDDP VDDP tCES tOES tCEH tOEH Data input Hi-Z tPGMS Data output Hi-Z tAHL tAHV
µPD78P4038Y
PROM Write Mode Timing (Byte Program Mode)
Program Program verify
A0-A16 D0-D7 Hi-Z Data input Hi-Z Data output Hi-Z
VDDP
tVPS VDDP VDDP VDDP tVDS tCES tOES
Cautions VDDP must applied before VPP, must after VPP. including overshoot must exceed +13.5 Plugging board with supplied with 12.5 adversely affect reliability. PROM Read Mode Timing
A0-A16 Valid address
tACC D0-D7
Note
Note
Data output
Note
Hi-Z
Hi-Z
Notes reading within tACC, delay input from falling edge must within tACC-tOE. time measured from when either reaches VIH, whichever faster.
µPD78P4038Y
PACKAGE DRAWINGS
PLASTIC (14x14)
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX.
INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-5
µPD78P4038Y
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
µPD78P4038Y
PLASTIC TQFP (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 14.00±0.20 12.00±0.20 12.00±0.20 14.00±0.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.145 +0.055 -0.045 0.10 1.05 0.10±0.05 5°±5° 1.27 MAX. INCHES 0.551±0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551±0.008 0.049 0.049 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.006±0.002 0.004 0.041 0.004±0.002 5°±5° 0.050 MAX. P80GK-50-BE9-5
µPD78P4038Y
CERAMIC WQFN
X80KW-65A-1 NOTE Each lead centerline located within 0.06 (0.003 inch) true position (T.P.) maximum material condition. ITEM MILLIMETERS 14.0 13.6 13.6 14.0 1.84 MAX. 0.45 0.10 0.06 0.65 (T.P.) 0.15 0.825 0.825 0.75 0.15 0.10 INCHES 0.551 0.008 0.535 0.535 0.551 0.008 0.072 0.142 MAX. 0.018+0.004 -0.005 0.003 0.024 (T.P.) 0.039+0.007 -0.006 0.012 0.032 0.032 0.079 0.354 0.083 0.030+0.006 -0.007 0.004
µPD78P4038Y
RECOMMENDED SOLDERING CONDITIONS
conditions listed below shall when soldering µPD78P4038Y. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with sales offices case other soldering process used, case soldering done under different conditions. Table 13-1. Soldering Conditions Surface-Mount Devices (1/2) µPD78P4038YGC-3B9: 80-pin plastic
Soldering Process Infrared reflow Soldering Conditions Peak package's surface temperature: 235°C Reflow time: seconds less (210°C more) Maximum allowable number reflow processes: Peak package's surface temperature: 215°C Reflow time: seconds less (200°C more) Maximum allowable number reflow processes: Solder temperature: 260°C less Flow time: seconds less Number flow processes: Preheating temperature 120°C max. (measured package surface) Terminal temperature: 300°C less Heat time: seconds less (for side device) Symbol IR35-00-3
VP15-00-3
Wave soldering
WS60-00-1
Partial heating method
Caution apply more different soldering methods chip (except partial heating method terminal sections). µPD78P4038YGC-8BT: 80-pin plastic
Soldering Process Infrared reflow
Soldering Conditions Peak package's surface temperature: 235°C Reflow time: seconds less (210°C more) Maximum allowable number reflow processes: Peak package's surface temperature: 215°C Reflow time: seconds less (200°C more) Maximum allowable number reflow processes: Solder temperature: 260°C less Flow time: seconds less Number flow processes: Preheating temperature 120°C max. (measured package surface) Terminal temperature: 300°C less Heat time: seconds less (for side device)
Symbol IR35-00-2
VP15-00-2
Wave soldering
WS60-00-1
Partial heating method
Caution apply more different soldering methods chip (except partial heating method terminal sections).
µPD78P4038Y
Table 13-1. Soldering Conditions Surface-Mount Devices (2/2) µPD78P4038YGK-BE9: 80-pin plastic TQFP (fine pitch)
Soldering Process Infrared reflow Soldering Conditions Peak package's surface temperature: 235°C Reflow time: seconds less (210°C more) Maximum allowable number reflow processes: Exposure limit: daysNote hours pre-baking required 125°C afterward) <Caution> Non-heat-resistant trays, such magazine taping trays, cannot baked before unpacking. Peak package's surface temperature: 215°C Reflow time: seconds less (200°C more) Maximum allowable number reflow processes: Exposure limit: daysNote hours pre-baking required 125°C afterward) <Caution> Non-heat-resistant trays, such magazine taping trays, cannot baked before unpacking. Terminal temperature: 300°C less Heat time: seconds less (for side device) Symbol IR35-107-2
VP15-107-2
Partial heating method
Note Maximum number days during which product stored temperature 25°C relative humidity less after dry-pack package opened. Caution apply more different soldering methods chip (except partial heating method terminal sections).
µPD78P4038Y
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78P4038Y. also (5). Language processing software
RA78K4 CC78K4 DF784038 CC78K4-L Assembler package 78K/IV Series models compiler package 78K/IV Series models Device file µPD784038Y Subseries models compiler library source file 78K/IV Series models
PROM write tools
PG-1500 PA-78P4026GC PA-78P4038GK PA-78P4026KK PG-1500 controller Control program PG-1500 PROM programmer Programmer adaptor, connects PG-1500
Debugging tools When using in-circuit emulator IE-78K4-NS
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C In-circuit emulator 78K/IV Series models Power supply unit IE-78K4-NS Interface adapter when PC-9800 series computer (other than notebook) used host machine card interface cable when PC-9800 series notebook used host machine Interface adapter when PC/ATor compatible used host machine IE-784038-NS-EM1Note NP-80GC NP-80GKNote EV-9200GC-80 Emulation board evaluating µPD784038Y Subseries models Emulation probe 80-pin plastic (GC-3B9 GC-8BT types) Emulation probe 80-pin plastic TQFP (GK-BE9 type) Socket mounting target system board made 80-pin plastic (GC-3B9 GC-8BT types) Adapter mounting target system board made 80-pin plastic TQFP (fine pitch) (GK-BE9 type) Tool used remove µPD78P4038YKK-T from EV-9200GC-80 Integrated debugger IE-78K4-NS System simulator 78K/IV Series models Device file µPD784038Y Subseries models
IE-70000-CD-IF
IE-70000-PC-IF-C
TGK-080SDW
EV-9900 ID78K4-NS SM78K4-NS DF784038
Note Under development
µPD78P4038Y
When using in-circuit emulator IE-784000-R
IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-C IE-70000-98N-IF In-circuit emulator 78K/IV Series models Interface adapter when PC-9800 series computer (other than notebook) used host machine Interface adapter cable when PC-9800 series notebook used host machine Interface adapter when PC/AT compatible used host machine Interface adapter cable when used host machine Emulation board evaluating µPD784038Y Subseries models Emulation board 78K/IV Series models Conversion board pins IE-784038-NS-EM1 IE-784000-R. board needed when conventional product IE-784038-R-EM1 used. Emulation probe 80-pin plastic (GC-3B9 GC-8BT types) Emulation probe 80-pin plastic TQFP (fine pitch) (GK-BE9 type) µPD784038Y Subseries Socket mounting target system board made 80-pin plastic (GC-3B9 GC-8BT types) Adapter mounting target system board made 80-pin plastic TQFP (fine pitch) (GK-BE9 type) Tool used remove µPD78P4038YKK-T from EV-9200GC-80 Integrated debugger IE-784000-R System simulator 78K/IV Series models Device file µPD784038Y Subseries models
IE-70000-PC-IF-B IE-70000-PC-IF-C IE-78000-R-SV3 IE-784038-NS-EM1Note IE-784038-R-EM1 IE-78400-R-EM IE-78K4-R-EX2Note
EP-78230GC-R EP-78054GK-R
EV-9200GC-80
TGK-080SDW
EV-9900 ID78K4 SM78K4 DF784038
Note Under development Real-time
RX78K/IV MX78K4 Real-time 78K/IV Series models 78K/IV Series models
µPD78P4038Y
Notes when using development tools ID78K-NS, ID78K4, SM78K4 used combination with DF784038. CC78K4 RX78K/IV used combination with RA78K4 DF784038. NP-80GC product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult sales representative purchasing. TGK-080SDW product from TOKYO ELETECH CORPORATION. Refer Daimaru Kogyo, Ltd. Tokyo Electronic Components Division (03-3820-7112) Osaka Electronic Components Division (06-244-6672) host machines operating systems corresponding each software shown below.
Host Machine [OS]
Software RA78K4 CC78K4 PG-1500 controller ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
PC-9800 Series [WindowsTM] HP9000 Series 700[HP-UXTM] PC/AT Compatibles [Windows] SPARCstation[SunOSTM] NEWS(RISC) [NEWS-OSTM]
Note Note Note
Note Note
Note Software under MS-DOS
µPD78P4038Y
APPENDIX CONVERSION SOCKET (EV-9200GC-80) CONVERSION ADAPTER (TGK-080SDW)
Conversion socket (EV-9200GC-80) package drawings recommended pattern mount socket Connect µPD78P4038YKK-T (80-pin ceramic WQFN mm)) EP-78230GC-R circuit board combination with EV-9200GC-80. Figure B-1. Package Drawings EV-9200GC-80 (Reference) (unit:
Based EV-9200GC-80 Package drawing
EV-9200GC-80
No.1 index
EV-9200GC-80-G0E ITEM MILLIMETERS 18.0 14.4 14.4 18.0 16.0 18.7 16.0 18.7 0.35 INCHES 0.709 0.567 0.567 0.709 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014
0.091
0.059
µPD78P4038Y
Figure B-2. Recommended Pattern Mount EV-9200GC-80 Substrate (Reference) (unit:
Based EV-9200GC-80 drawing
EV-9200GC-80-P1E ITEM Caution MILLIMETERS 19.7 15.0 0.65±0.02 19=12.35±0.05 INCHES 0.776 0.591 0.026+0.001 -0.002 0.748=0.486 +0.003 -0.002
0.65±0.02 19=12.35±0.05 0.026 +0.001 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 0.05 0.05 0.35 0.02 0.591 0.776 0.236 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
µPD78P4038Y
Conversion adapter (TGK-080SDW) package drawings Connect EP-78054GK-R circuit board combination with TGK-080SDW. Figure B-3. Package Drawings TGK-080SDW (Reference) (unit:
TGK-080SDW (TQPACK080SD TQSOCKET080SDW) Package dimension (unit:
ITEM MILLIMETERS 18.0 11.77 0.5x19=9.5 0.5x19=9.5 11.77 18.0 1.58 7.64 1.58 1.58 7.64 1.58 INCHES 0.709 0.463 0.020x0.748=0.374 0.020 0.020x0.748=0.374 0.463 0.709 0.020 0.062 0.047 0.301 0.047 0.062 0.062 0.047 0.301 0.047 0.062 ITEM MILLIMETERS 0.5x19=9.5±0.10 0.25 INCHES 0.020x0.748=0.374±0.004 0.010
screw
Protrusion places
3.55
1.85±0.2 0.25 14.0 1.4±0.2 1.4±0.2 h=1.8 0~5°
0.209 0.209 0.051 0.140 0.012
0.073±0.008 0.138 0.079 0.118 0.010 0.551 0.055±0.008 0.055±0.008 h=0.071 0.051 0.000~0.197° 0.232 0.031 0.094 0.106 0.154 TGK-080SDW-G1E
3.55
12.31 10.17 8.24 14.8 1.4±0.2
0.140
0.079 0.485 0.400 0.268 0.324 0.583 0.055±0.008
note: Product TOKYO ELETECH CORPORATION.
µPD78P4038Y
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Name Document English Japanese U11504J U10741J U10742J U11316J U11090J U10905J U10594J U10595J U10095J
µPD784031Y Data Sheet µPD784035Y, 784036Y, 784037Y, 784038Y Data Sheet µPD78P4038Y Data Sheet µPD784038, 784038Y Sub-Series User's Manual, Hardware µPD784038Y Sub-Series Special Function Registers
78K/IV Series User's Manual, Instruction 78K/IV Series Instruction Summary Sheet 78K/IV Series Instruction 78K/IV Series Application Note, Software Basic
U11504E U10741E This manual U11316E U10905E
Documents Related Development Tools (User's Manual)
Document Name Document English RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 Series Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Base PG-1500 Controller Series DOSTM) Base IE-78K4-NS U11334E U11162E U11743E U11572E U11571E U12322E U11940E EEU-1291 U10540E released soon IE-784000-R IE-784038-NS-EM1 IE-784038-R-EM1 EP-78230 EP-78054GK-R SM78K4 System Simulator Windows Base SM78K Series System Simulator Reference External Parts User Open Interface Specifications Reference Reference Reference EEU-1534 Planned U11383E EEU-1515 EEU-1468 U10093E U10092E U12903J Planned U11383J EEU-985 EEU-932 U10093J U10092J Japanese U11334J U11162J U11743J U11572J U11571J U12322J U11940J EEU-704 EEU-5008 U13356J
ID78K4-NS Integrated Debugger ID78K4 Integrated Debugger Windows Base ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base
U12796E U10440E U11960E
U12796J U10440J U11960J
Caution above documents revised without notice. latest versions when design application systems.
µPD78P4038Y
Documents Related Software Incorporated into Product (User's Manual)
Document Name Document English 78K/IV Series Real-Time Basic Installation Debugger 78K/IV Series MX78K4 Basic U10603E U10604E Japanese U10603J U10604J U10364J U11779J
Other Documents
Document Name Document English PACKAGE MANUAL Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System C10943X C10535E C11531E C10983E C10535J C11531J C10983J C11892J C12769J U11416J Japanese
Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) C11892E Semiconductor Device Quality Control/Reliability Handbook Guide Products Related Microcomputer: Other Companies
Caution above documents revised without notice. latest versions when design application systems.
µPD78P4038Y
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78P4038Y
Caution This product contains interface circuit. When using interface, notify when ordering custom code. guarantee following only when customer informs interface: Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
IEBus QTOP trademarks Corporation. MS-DOS Windows registered trademarks trademarks Microsoft Corporation United States and/or other countries. PC/AT trademarks Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks SONY Corporation.
µPD78P4038Y
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J98.
µPD78P4038Y
Some related documents preliminary versions. Note that, however, what documents preliminary indicated this document.
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative.
License needed customer must judge need license µPD78P4038YKK-T µPD78P4038YGC-3B9, µPD78P4038YGC-8BT µPD78P4038YGK-BE9,
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.

µPD78P4038Y 16/8-BIT SINGLE-CHIP MICROCONTROLLER µPD78P4038Y

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