µPD78CP18(A) 8-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

µPD78CP18(A) 8-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION

Datasheet Thumbnail

Top Searches for this datasheet

INTEGRATED CIRCUIT
µPD78CP18(A)
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
µPD78CP18(A) version µPD78C18(A) which internal mask replaced one-time PROM. one-time PROM version programmed once only users, ideally suited small-scall many differnt products, rapid development time-to-market product. detailed functions descrived following user's manual. Read this manual before starting design work. 87AD series µPD78C18 user's manual: IEU-1314
FEATURES
High reliability compared µPD78CP18 Compatible with µPD78C11A(A), 78C12A(A), 78C14(A), 78C18(A) Internal PROM: 32768 Internal PROM capacity changed software conform µPD78C11A(A), 78C12A(A), 78C14(A), 78C18(A). PROM programming characteristics: µPD27C256A compatible Power supply voltage range: Supports QTOPmicrocomputer Remark QTOP microcomputer generic name NEC's single-chip microcomputers which provides total service including writing, marking, screening, inspection.
ORDERING INFORMATION
Part Number Package 64-pin plastic 64-pin plastic QUIP Internal One-time PROM One-time PROM
µPD78CP18GF(A)-3BE µPD78CP18GQ(A)-36
QUALITY GRADE
Part Number Quality Grade Special Special
µPD78CP18GF(A)-3BE µPD78CP18GQ(A)-36
Please refer "Quality grade Semiconductor Devices" (Document number IEI-1209) published Corporation know specification quality grade devices recommended applications.
information this document subject change without notice. mark Document IC-3233A IC-8702A) Date Published March 1995 Printed Japan
shows major revised points.
1994 1993
µPD78CP18(A)
CONFIGURATION (TOP VIEW)
A0/PA0 A1/PA1 A2/PA2 A3/PA3 A4/PA4 A5/PA5 A6/PA6 A7/PA7 CE/PB6 OE/PB7 PC0/T PC1/R PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 A9/NMI INT1 MODE1 RESET MODE0
STOP/V PD7/O7 PD6/O6 PD5/O5 PD4/O4 PD3/O3 PD2/O2 PD1/O1 PD0/O0 PF6/A14 PF5/A13 PF4/A12 PF3/A11 PF2/A10 PF0/A8 AREF
µPD78CP18GQ(A)-36
µPD78CP18(A)
PF6/A14
PF5/A13
PF4/A12
PF3/A11
PF2/A10
PD2/O2
PD1/O1
PD0/O0
PF0/A8
AREF
O3/PD3 O4/PD4 O5/PD5 O6/PD6 O7/PD7 STOP A0/PA0 A1/PA1 A2/PA2 A3/PA3 A4/PA4 A5/PA5
MODE0 RESET MODE1 INT1
µPD78CP18GF(A)-3BE
A6/PA6
A7/PA7
PC0/T
PC3/INT2
PC4/TO
PC6/CO0
PC7/CO1
PC2/SCK
PC5/CI
PC1/R
A9/NM1
CE/PB6
OE/PB7
PORT
MAIN PROM (32-KBYTE)
Note
PORT
PORT
PC5/CI PC6/CO0 PC7/CO1 TIMER/EVENT COUNTER LATCH LATCH
INTERNAL DATA INST.
PORT
VAREF AVDD AVSS
CONVERTER
(8/16) INST. DECODER
PORT
LATCH INC/DEC INT1 INT. CONTROL BUFFER PC3/INT2/TI TIMER PC4/TO 8/16 PF7/AB15 PF6/A14/AB14 PF2/A10/AB10 PF1/AB9 PF0/A8/AB8 PC0/TXD PC1/RXD PC2/SCK SERIAL PD7/O7/AD7 PD0/O0/AD0 A9/NMI DATA MEMORY (1-KBYTE) OE/PB7 CE/PB6 PA7/A7 PA0/A0 READ/WRITE CONTROL SYSTEM CONTROL STANDBY CONTROL MODE1 MODE0 RESET VPP/STOP
BLOCK DIAGRAM
µPD78CP18(A)
Note used only when register External memory needed case
µPD78CP18(A)
DIFFERENCES BETWEEN µPD78CP18(A) µPD78CP18
Product Name Item Quality grade Electrical specifications Package Special Input leakage current AN0: (MAX.) 64-pin plastic 64-pin plastic QUIP Standard Input leakage current AN0; (MAX.) 64-pin plastic shrink (750 mil) 64-pin plastic QUIP 64-pin plastic 64-pin ceramic shrink with window (750 mil) 64-pin ceramic WQFN
µPD78CP18(A)
µPD78CP18
µPD78CP18(A)
CONTENTS LIST PORT FUNCTIONS
PORT FUNCTIONS NON-PORT FUNCTIONS NORMAL OPERATION) NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY READ) HANDLING UNUSED PINS
MEMORY CONFIGURATION MEMORY EXTENSION
MODE PINS MEMORY MAPPING REGISTER (MM)
PROM PROGRAMMING
PROM PROGRAMMING OPERATING MODES PROM WRITING PROCEDURE PROM READING PROCEDURE
SCREENING ONE-TIME PROM VERSIONS ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVES (REFERENCE VALUE) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS
DIFFERENCES BETWEEN µPD78CP18(A) µPD78C18(A) APPENDIX. DEVELOPMENT TOOLS
µPD78CP18(A)
LIST PORT FUNCTIONS
PORT FUNCTIONS
Name (Port (Port (Port (Port (Port 8-bit input-output port, which specify input/output byte units. Input/Output
Function 8-bit input-output port, which specify input/output bit-wise.
8-bit input-output port, which specify input/output bit-wise.
Remark
These port pins have alternate function pins shown "NON-PORT FUNCTIONS NORMAL OPERATION)" "NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY READ)".
µPD78CP18(A)
NON-PORT FUNCTIONS NORMAL OPERATION)
Alternate Function Serial data output
Name (Transmit Data) (Receive Data) (Serial Clock)
Output
Function
Input
Serial data input
Input/output
Serial clock input/output pin. Output when internal clock used, input when external clock used. Edge trigger (falling edge) maskable interrupt input
INT2 Input (Interrupt Request) (Timer Input) Zero-cross (Timer Output) (Counter Input) (Counter Output (Address/Data AB15 (Address (Write Strobe) Input
Timer external clock input
Input Output
input zero-cross detection During timer count time, square wave with internal clock cycle half cycle output. Timer/event counter external pulse input
Input
Output
Square wave output programmable timer/event counter.
Input/output
Multiplexed address/data when external memory used
Output
Address when external memory used
Output
Strobe signal which output write operation external memory. becomes high cycle other than data write machine cycle external memory. When RESET signal either hardware STOP mode, this signal becomes high-impedance. Strobe signal which output read operation external memory. becomes high cycle other than data read machine cycle external memory. When RESET signal either hardware STOP mode, this signal becomes output high-impedance. Strobe signal latch externally lower address information which output pins access external memory. When RESET signal either hardware STOP mode, this signal becomes highimpedance. MODE0 (low level), MODE1 (high level)Note
(Read Strobe)
Output
Output (Address Latch Enable) MODE0 MODE1 (Mode) (Non-Maskable Interrupt) Input Input/output
Input
Non-maskable interrupt input edge trigger (falling edge)
Note Pull-up. Pull-up resister tCYC (tCYC unit).
µPD78CP18(A)
Name INT1 (Interrupt Request) (Analog Input) VAREF (Reference Voltage) AVDD (Analog VDD) AVSS (Analog VSS) (Crystal) Input
Alternate Function
Function maskable interrupt input edge trigger (rising edge). Also, used zero-cross detection input. pins analog input converter. used edge detection (falling edge) input. common serving both reference voltage input converter control converter operation. Power supply converter. converter. Crystal connection pins system clock oscillation. should input when clock supplied from outside. Inverted clock should input
Input Input
RESET (Reset) STOP (Stop)
Input
Low-level active system reset input.
Input
Hardware STOP mode control signal input pin. When level input this pin, oscillation stops. Positive power supply pin. pin.
µPD78CP18(A)
NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY READ)
Alternate Function Input Input MODE0 (high level), MODE1 (low level). Address lower input pins Chip enable signal input Output enable signal input Data input/output pins Address higher input pins Function
Name MODE0 MODE1 RESET Input Input Input
Input/output Input
Input STOP
(low level). High-voltage application (high level) input when EPROM read.
HANDLING UNUSED PINS
Recommended Connection
Connect resistor.
STOP INT1, AVDD VAREF AVSS
Leave open.
Connect VDD. Connect VDD. Connect VDD. Connect VSS. Connect AVSS AVDD.
µPD78CP18(A)
MEMORY CONFIGURATION
µPD78CP18(A) memory operate following modes according mode specification.
µPD78C11A mode (see Figure 2-1) µPD78C12A mode (see Figure 2-2) µPD78C14 mode (see Figure 2-3) µPD78C18 mode (see Figure 2-4)
addition, internal PROM internal address ranges specified efficient mapping external memory (excluding PROM) (see "MEMORY MAPPING REGISTER (MM)"). vector area call table area common modes. Setting hardware/software STOP mode HALT mode enables internal data retained consumption current.
µPD78CP18(A)
Figure 2-1. Memory (µPD78C11A Mode)
0000H
0000H RESET
Internal PROM 4096W
0004H
0008H INTT0/INTT1 0FFFH 1000H
0010H INT1/INT2
External Memory 61184W Vector Area
0018H INTE0/INTE1
0020H INTEIN/INTAD FEFFH FF00H Internal 256W FFFFH 0028H INTSR/INTST
0060H SOFTI
0080H 0081H Call Table Area 0082H 0083H
ADRS HIGH ADRS ADRS HIGH ADRS
00BEH 00BFH 00C0H
ADRS HIGH ADRS
USER'S AREA
0FFFH
µPD78CP18(A)
Figure 2-2. Memory (µPD78C12A Mode)
0000H
0000H RESET
Internal PROM 8192W
0004H
0008H INTT0/INTT1 1FFFH 2000H
0010H INT1/INT2
External Memory 57088W Vector Area
0018H INTE0/INTE1
0020H INTEIN/INTAD FEFFH FF00H Internal 256W FFFFH 0028H INTSR/INTST
0060H SOFTI
0080H 0081H Call Table Area 0082H 0083H
ADRS HIGH ADRS ADRS HIGH ADRS
00BEH 00BFH 00C0H
ADRS HIGH ADRS
USER'S AREA
1FFFH
µPD78CP18(A)
Figure 2-3. Memory (µPD78C14 Mode)
0000H
0000H RESET
Internal PROM 16384W
0004H
0008H INTT0/INTT1 3FFFH 4000H
0010H INT1/INT2
External Memory 48896W Vector Area
0018H INTE0/INTE1
0020H INTEIN/INTAD FEFFH FF00H Internal 256W FFFFH 0028H INTSR/INTST
0060H SOFTI
0080H 0081H Call Table Area 0082H 0083H
ADRS HIGH ADRS ADRS HIGH ADRS
00BEH 00BFH 00C0H
ADRS HIGH ADRS
USER'S AREA
3FFFH
µPD78CP18(A)
Figure 2-4. Memory (µPD78C18 Mode)
0000H
0000H RESET
Internal PROM 32768W
0004H
0008H INTT0/INTT1 7FFFH 8000H
0010H INT1/INT2
External Memory 31744W Vector Area
0018H INTE0/INTE1
0020H INTEIN/INTAD FBFFH FC00H Internal 1024W FFFFH 0028H INTSR/INTST
0060H SOFTI
0080H 0081H Call Table Area 0082H 0083H
ADRS HIGH ADRS ADRS HIGH ADRS
00BEH 00BFH 00C0H
ADRS HIGH ADRS
USER'S AREA
7FFFH
µPD78CP18(A)
MEMORY EXTENSION
PD78CP18(A) allows external memory extension means MEMORY MAPPING register (MM) MODE0 MODE1 pins. Also, internal PROM internal access areas specified means bits MM7, MEMORY MAPPING register. MODE PINS µPD78CP18(A) switched between programming mode normal operation mode according specification MODE0 MODE1 pins. Table shows modes MODE pins. Table 3-1. Modes MODE Pins
MODE1 MODE2 Operating Mode Setting prohibited Programming modeNote Normal operation mode Setting prohibited
Note "PROM PROGRAMMING". When MODE0 MODE1 driven high, tCYC pull-up resistor should used (tCYC: units).
µPD78CP18(A)
MEMORY MAPPING REGISTER (MM)
MEMORY MAPPING register 8-bit register which performs following controls: Port/extension mode specification Enabling/disabling internal accesses Specification internal PROM access areas configuration MEMORY MAPPING register shown Figure 3-1. Bits These bits control port/extension mode specification, input/output specification, address output specification. shown Figure 3-1, there choice four capacities connectable external memory: bytes Kbytes Kbytes K/48 K/56 K/60 Kbytes (set bits MM5) Ports used address outputs used general-purpose ports. When RESET signal input hardware STOP mode, these bits reset input port mode (high-impedance). (RAE) This enables (RAE disables (RAE internal access. This should during standby operation when externally connected RAM, internal RAM, used. normal operation this retains value when RESET signal input. However, undefined after power-on reset, must therefore initialized instruction. Bits These bits specify access area internal PROM. When STOP RESET signal input, these bits reset, selecting 32-Kbyte mode (µPD78C18 mode). These bits only valid µPD78CG14, 78CP14, 78CP18, 78CP14(A), 78CP18(A); data written these bits µPD78C11A(A), 78C12A(A), 78C14(A), 78C18(A), will ignored. Therefore, program developed µPD78CP18(A) directly ported mask ROM.
µPD78CP18(A)
Figure 3-1. MEMORY MAPPING Register Format
Port Single chip mode Exten- bytes sion mode Kbytes
Kbytes
K/48 56K/60KNote bytes
Input port Port mode Output port Port mode Extension mode Port mode Extension mode Port mode Extension mode Port mode Extension mode
Note
Depends bit-setting
Internal Access Disable Enable
Internal PROM/RAM Access Areas Internal PROM Access Area 0000H 7FFFH Kbytes: µPD78C18 mode) 0000H 3FFFH Kbytes: µPD78C14 mode) 0000H 1FFFH Kbytes: µPD78C12A mode) 0000H 0FFFH Kbytes: µPD78C11A mode) Internal Access Area FC00H FFFFH Kbyte) FF00H FFFFH (256 bytes) FF00H FFFFH (256 bytes) FF00H FFFFH (256 bytes)
Other than above
Setting Prohibited
µPD78CP18(A)
Figure 3-2. External Extension Modes MEMORY MAPPING Register
Port Mode 256-Byte Extension Mode 4-KByte Extension Mode
Internal PROM (4/8/16/32 KBytes)
Internal PROM (4/8/16/32 KBytes)
Internal PROM (4/8/16/32 KBytes)
Used
Used External Memory(4 KBytes) External Memory(256 Bytes) Used Used Internal Internal Internal 16-KByte Extension Mode 32-/48-/56-/60-KByte Extension Mode Internal PROM (4/8/16/32 KBytes) Internal PROM (4/8/16/32 KBytes) External Memory KBytes)
Used
Caution
internal PROM internal access areas determined MM5.
Used Internal Internal
External Memory (32/48/56/ KBytes)
µPD78CP18(A)
PROM PROGRAMMING
µPD78CP18(A) incorporates 32768 8-bit PROM program memory. pins shown Table used write/verify operations this PROM. µPD78CP18(A) program timing compatible with µPD27C256A. Please read following conjunction with documentation µPD27C256A. Table 4-1. Pins Used PROM Programming
Name RESET MODE0 MODE1
Note
Function Low-level input write/verify read) High-level input write/verify read) Low-level input write/verify read) High-voltage input write/verify), high-level input read) Chip enable input Output enable input
Note
Note Note
Address input Data input write), data output verify, read) Supply voltage input
Note
Note
Note These pins correspond µPD27C256A. Caution µPD78CP18(A) one-time PROM version equipped with erasure window, therefore ultraviolet erasure cannot performed
µPD78CP18(A)
PROM PROGRAMMING OPERATING MODES
PROM programming operating mode shown Table 4-2. Pins used programming should handled shown Table 4-3. Table 4-2. PROM Programming Modes
Operating Mode Program Program verify Program inhibit Read Output disable Standby Note CENote OENote VPPNote +12.5 VDDNote RESET MODE0 MODE1
These pins correspond µPD27C256A.
Caution When +12.5 applied applied VDD, setting both prohibited.
Table 4-3. Recommended Connection Unused Pins PROM Programming Mode)
INT1 VAREF AVDD AVSS Pins other than above Connect individual resistor. Leave open. Recommended Connection Connect VSS.
µPD78CP18(A)
PROM WRITING PROCEDURE
PROM writing procedure shown below, allowing high-speed writing. Connect unused pins pull-down resistor, supply +12.5 VPP. Provide initial address. Provide write data. Provide 1-ms program pulse (active low) pin. Verify mode. written, (7); written, repeat (5). write operation failed times, (6). Halt write operation defective device. Provide write data program pulse times repeated times from (5)) (additional write). Increment address. Repeat until final address. Figure 4-1. PROM Write/Verify Timing
Repeated Times
Write
Verify
Additional Write
A14/PF6-A10/PF2 A9/NMI A8/PF0 Address (Higher Bits)
A7/PA7-A0/PA0
Address (Lower Bits)
O7/PD7-O0/PD0
Data Input
Data Output
Data Input
CE/PB6 OE/PB7
µPD78CP18(A)
PROM READING PROCEDURE
PROM contents read onto external data using following procedure. Connect unused pins pull-down resistor. Supply pins. Input address data read pins Read mode Output data pins Timing steps above shown Figure 4-2. Figure 4-2. PROM Read Timing
A14/PF6-A10/PF2 A9/NMI A8/PF0 Address Input
CE/PB6
OE/PB7
O7/PD7-O0/PD0
Data Output
µPD78CP18(A)
SCREENING ONE-TIME PROM VERSIONS
Because their construction, one-time PROM versions cannot fully tested before shipment. After necessary data been written, recommended that screening implemented which PROM verification performed after high-temperature storage under following conditions.
Storage Temperature
Storage Time hours
provides writing, marking, screening, inspection services single-chip microcomputers labeld QTOP microcomputers. details, consult NEC.
µPD78CP18(A)
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL AVDD
TEST CONDITIONS
RATINGS -0.5 +7.0 AVSS -0.5 +0.5 -0.5 +13.5
UNIT
Power supply voltage AVSS Other than NMI/A9 Input voltage NMI/A9 Output voltage output pins Output current Total output pins output pins Output current high Total output pins converter reference input voltage Ambient operating temperature Storage temperature VAREF Tstg -0.5 AVDD +150 -2.0 -0.5 +13.5 -0.5
-0.5
Caution
absolute maximum rating even above parameters exceeded even momentarily, quality product degraded. absolute maximum ratings, therefore, specify values exceeding which product physically damaged. sure product with these rated values never exceeded.
µPD78CP18(A)
AVDD +5.0 AVSS -0.8 VDD, VAREF AVDD)
OSCILLATOR CHARACTERISTICS
RESONATOR
RECOMMENDED CIRCUIT
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
converter used Oscillator frequency (fXX)
Ceramic crystal resonator
converter used
converter used
input frequency (fX) converter used
External clock rise time, fall time (tr,
HCMOS Inverter
input high-, lowlevel width (tH,
Cautions
Place oscillator close possible pins. Ensure that other signal lines pass through shaded area.
µPD78CP18(A)
CAPACITANCE
PARAMETER Input capacitance Output capacitance Input-output capacitance
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Unmeasured pins returned
CHARACTERISTICS AVDD +5.0 AVSS
PARAMETER
SYMBOL VIL1
TEST CONDITIONS except RESET, STOP, NMI, SCK, INT1, RESET, STOP, NMI, SCK, INT1, except RESET, STOP, NMI, SCK, INT1, AN7, RESET, STOP, NMI, SCK, INT1, AN7, -1.0
MIN.
TYP.
MAX.
UNIT
Input voltage VIL2 0.2VDD
VIH1 Input voltage high VIH2 Output voltage
0.45
±200
Output voltage high
-100
Input current
INT1Note1, TI(PC3)Note2 except INT1, (PC3), AN0; AN0;
Input leakage current
Output leakage current AVDD power supply current
AIDD1 AIDD2 IDD1 IDD2 VDDDR
Operating mode STOP mode Operating mode HALT mode Hardware/software STOP mode Hardware/softwareNote3 VDDDR VDDDR
power supply current Data retention voltage Data retention current
IDDDR STOP mode
Notes self-bias should generated register. control mode register, self-bias should generated register. self-bias generated.
µPD78CP18(A)
CHARACTERISTICS AVDD +5.0 AVSS READ/WRITE OPERATION:
PARAMETER input cycle time Address setup time Address hold time (from delay time from address Address float time from Data input time from address Data input time from Data input time from delay time from Data hold time (from delay time from
SYMBOL tCYC tAFR tLDR
TEST CONDITIONS
MIN.
MAX.
UNIT
MHz,
MHz, tRDH MHz, data read MHz, low-level width code fetch MHz, high-level width delay time from address Data output time from Data output time from delay time from Data setup time Data hold time (from delay time from low-level width MHz, tLDW tWDH MHz, MHz,
ZERO-CROSS CHARACTERISTICS
PARAMETER Zero-cross detection input Zero-cross accuracy Zero-cross detection input frequency SYMBOL coupling 60-Hz sine wave 0.05 TEST CONDITIONS MIN. MAX. ±135 UNIT VACP-P
µPD78CP18(A)
SERIAL OPERATION
PARAMETER SYMBOL TEST CONDITIONS Note1 input cycle time tCYK output Note1 input low-level width tKKL output Note1 input high-level width tKKH output setup time hold time (from delay time from tRXK tKRX tKTX Note1 Note1 Note1 Note2 Note2 Note2 MIN. MAX. UNIT
Notes clock rate asynchronous mode, synchronous mode, interface mode. clock rate asynchronous mode. Remark numeric values table those when MHz,
OTHER OPERATION
PARAMETER high-, low-level width SYMBOL tTIH, tTIL Event counter mode tCI1H, tCI1L Frequency test mode high-, low-level width tCI2H, tCI2L Pulse width test mode ECNT latch clear input INTEIN input high-, low-level width INT1 high-, low-level width INT2 high-, low-level width AN7, low-level width RESET high-, low-level width tNIH, tNIL tI1H, tI1L tI2H, tI2L tANH, tANL tRSH, tRSL tCYC tCYC TEST CONDITIONS MIN. MAX. UNIT tCYC
tCYC tCYC tCYC
µPD78CP18(A)
CONVERTER CHARACTERISTICS +5.0 AVSS VDD, VAREF AVDD)
PARAMETER Resolution
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT Bits
VAREF AVDD, tCYC Absolute accuracyNote VAREF AVDD, tCYC VAREF AVDD, tCYC tCYC Conversion time tCONV tCYC tCYC Sampling time tSAMP tCYC -0.3 Operating mode STOP mode Operating mode STOP mode
±0.8 ±0.6 ±0.4
tCYC tCYC tCYC tCYC
Analog input voltage
VIAN VAREF IAREF1
VAREF
Analog input impedance Reference voltage
AVDD
VAREF current IAREF2 AVDD power supply current AIDD1 AIDD2
Note Quantization error (±1/2 LSB) included.
Timing Test Point
0.45
Test Points
µPD78CP18(A)
tCYC-Dependent Characteristics Expression
PARAMETER tLDR data read) code fetch) tLDW tWDH tCYK tKKL 2.5T (SCK input)Note1 (SCK input)Note2 (SCK output) (SCK input)Note1 (SCK input)Note2 MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. MIN. EXPRESSION MIN./MAX. MIN. MIN. MIN. MAX. MAX. MAX. MIN. MIN. UNIT
(SCK output) tKKH 2.5T (SCK input)Note1 (SCK input)Note2 MIN.
(SCK output)
Notes clock rate asynchronous mode, synchronous mode, interface mode. clock rate asynchronous mode. Remarks tCYC 1/fXX Other items which listed this table dependent oscillator frequency (fXX).
µPD78CP18(A)
Timing Waveforms Read Operation
tCYC
Address (Lower) tAFR tLDR
Address (Higher)
Read Data
tRDH
Write Operation
tLDW Address (Lower)
Address (Higher)
Write Data tWDH
µPD78CP18(A)
Serial Operation
tCYK tKKL tKTX tKKH
tRXK tKRX
Timer Input Timing
tTIH
tTIL
Timer/Event Counter Input Timing
Event Counter Mode tCI1H tCI1L
Pulse Width Test Mode tCI2H tCI2L
µPD78CP18(A)
Interrupt Input Timing
tNIH tNIL
tI1L
tI1H
INT1
tI2H
tI2L
INT2
Reset Input Timing
tRSH tRSL
RESET
0.8VDD 0.2VDD
External Clock Timing
0.8VDD tCYC
µPD78CP18(A)
DATA MEMORY STOP MODE POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
PARAMETER Data retention power supply voltage Data retention power supply current rise/fall time STOP setup time VDD) STOP hold time (from VDD) SYMBOL VDDDR VDDDR IDDDR VDDDR Note Note TEST CONDITIONS MIN. TYP. MAX. UNIT
tRVD, tFVD tSSTVD
tHVDST
Note tCYC 1/fXX
Data Retention Timing
tFVD tSSTVD STOP VDDDR tRVD tHVDST VIH2 VIL2
µPD78CP18(A)
PROGRAMMING CHARACTERISTICS MODE1 VIL, MODE0 VIH,
PARAMETER Input voltage high Input voltage Input leakage current Output voltage high Output voltage Output leakage current VDDP supply voltage SYMBOL ILIP SYMBOLNote
TEST CONDITIONS
MIN. -0.3
TYP.
MAX. VDDP
UNIT
VDDP; except INT1, (PC3) -1.0 VDDP, EPROM programming mode 5.75 12.2 12.5 VDDP
0.45 6.25 12.8
VDDP
EPROM read mode
supply voltage
EPROM programming mode EPROM read mode EPROM programming mode
VDDP supply current
EPROM read mode VIL, EPROM programming mode VIL, EPROM read mode
supply current
Note Corresponding µPD27C256A symbol
µPD78CP18(A)
PROGRAMMING CHARACTERISTICS MODE1 VIL, MODE0 VIH,
PARAMETER Address setup time delay time from data Input data setup time Address hold time (from Input data hold time (from Output data hold time (from setup time VDDP setup time Initial program pulse width Additional program pulse width EPROM programming/read mode setup time CE)Note2 Data output time from address Data output time from Data output time from Data hold time (from Data hold time (from address) SYMBOL tSAC tDDOO tSIDC tHCA tHCID tHOOD tSVPC tSVDC tWL1 tWL2 tSMC tDAOD tDCOD tDOOD tHCOD tHAOD SYMBOLNote1 tOES tVPS tVDS tOPW tACC TEST CONDITIONS MIN. 0.95 2.85 1.05 78.75 TYP. MAX. UNIT
Notes Corresponding µPD27C256A symbol Indicates state which MODE1 MODE0 VIH.
µPD78CP18(A)
PROM Programming Mode Timing
tSAC
Effective Address tHOOD tHCA
Data Input tSIDC tHCID
Data Output
Data Input tSIDC MODE1 MODE0 tHCID
MODE1 MODE0 VDDP tSVPC tSMC
VDDP
VDDP VDDP tSVDC
tWL1 tDDOO tDOOD tWL2
Cautions
Ensure that VDDP applied before VPP, after VPP. Ensure that does exceed including overshoot.
PROM Read Mode Timing
Effective Address
tDCOD
tDAOD Hi-Z Data Output tDOOD tHCOD tHAOD Hi-Z
Cautions
wish read within tDAOD range, input delay time from fall should maximum tDAOD tDOOD. tHCOD time from point which (whichever first) reaches VIH.
µPD78CP18(A)
CHARACTERISTIC CURVES (REFERENCE VALUE)
IDD1, IDD2
MHz)
IDD1 (TYP.)
Power Supply Current IDD1, IDD2 [mA]
IDD2 (TYP.)
Power Supply Voltage
IDD1, IDD2
Power Supply Current IDD1, IDD2 [mA]
IDD1 (TYP.)
IDD2 (TYP.)
Oscillator Frequency [MHz]
µPD78CP18(A)
TYP.
Output Current [mA]
Output Voltage
-1.5
TYP.
Output Current High [mA]
-1.0
-0.5
Power Supply Voltage Output Voltage High
µPD78CP18(A)
IDDDR VDDDR
Data Retention Power Supply Current IDDDR
TYP.
Data Retention Power Supply Voltage VDDDR
µPD78CP18(A)
PACKAGE DRAWINGS
PLASTIC QUIP
P64GQ-100-36 NOTE Each lead centerline located within 0.25 (0.010 inch) true position (T.P.) maximum material condition. ITEM MILLIMETERS 41.5 16.5
0.50 +0.10 +0.3 -0.2
INCHES 1.634+0.012 -0.008 0.650 0.020 +0.004 -0.005 0.010 0.100 (T.P.) 0.050 (T.P.) 0.043+0.011 -0.006 0.010 +0.004 -0.003 0.157+0.013 -0.012 0.142 -0.005 0.950
+0.042 +0.042 +0.004
0.25 2.54 (T.P.) 1.27 (T.P.) +0.25 -0.15
+0.10 0.25 -0.05 +0.3
+0.1
24.13 +1.05 19.05 +1.05
0.750
µPD78CP18(A)
PLASTIC
detail lead
P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline located within 0.20 (0.008 inch) true position (T.P.) maximum material condition. ITEM MILLIMETERS 23.6 20.0 14.0 17.6 0.40 0.10 0.20 (T.P.) 0.15+0.10 -0.05 0.12 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.071-0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.005 0.106 0.004 0.004 0.119 MAX.
+0.008
5°±5°
µPD78CP18(A)
RECOMMENDED SOLDERING CONDITIONS
µPD78CP18(A) should soldered mounted under following recommended conditions. details recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual (IEI-1207)". soldering methods conditions other than those recommended below, contact representative. Table 9-1. Surface Mount Type Soldering Conditions
µPD78CP18GF(A)-3BE: 64-Pin Plastic
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: Duration: sec. max. higher), Count: Twice less <Attention> Perform second reflow time device temperature lowered room temperature from heating first reflow. wash soldered portion with flux following first reflow. VP15-00-2 Recommended Condition Symbol IR35-00-2
Package peak temperature: Duration: sec. max. higher), Count: Twice less <Attention> Perform second reflow time device temperature lowered room temperature from heating first reflow. wash soldered portion with flux following first reflow.
Wave soldering
Solder bath temperature: max., Duration: sec. max., Count: Once Preheating temperature: max. (package surface temperature) temperature: max., Duration: sec. max. (per device side pins)
WS60-00-1
Partial heating
Caution
more than soldering method should avoided (except case part heating).
Table 9-2. Through-Hole Type Soldering Conditions
µPD78CP18GQ(A)-36: 64-Pin Plastic QUIP
Soldering Method Wave soldering (pin part only) Partial heating Soldering Conditions Solder bath temperature: max., Duration: sec. max. temperature: max., Duration: sec. max. (per pin)
Caution
Wave soldering used only, care must taken prevent solder from coming into direct contact with body.
µPD78CP18(A)
DIFFERENCES BETWEEN µPD78CP18(A) µPD78C18(A)
Part Number Item Internal
µPD78CP18(A)
bits (PROM) bits PB7/OE PB6/CE STOP/VPP NMI/A9 PA7/A7 PA0/A0 PF6/A14 PF2/A10 PF0/A8 PD7/O7 PD0/O0
µPD78C18(A)
bits (mask ROM) bits STOP Operates µPD78C17(A) (ROM-less mode) External memory extension mode Input/output
Internal connection
Mode MODE pins (when MODE0 MODE1
PROM programming mode
MODE0 input/output function Internal memory access area setting register Port Port
Input onlyNote
Pull-up resistors incorporated
Pull-up resistor incorporation selectable bit-wise mask option
Note emulation control signal output even MODE0 pulled high.
µPD78CP18(A)
APPENDIX DEVELOPMENT TOOLS
following development tools available develop system which uses µPD78CP18(A). Language Processor
87AD series relocatable assembler (RA87) This program which converts program written mnemonic object code which microcomputer execution possible. Moreover, contains function automatically create symbol/table, optimize branch instructions.
Host Machine PC-9800 series
MS-DOSVer. 2.11 Ver. 5.00ANote
Supply Medium 3.5-inch
Ordering Code (Product Name)
µS5A13RA87
5-inch
µS5A10RA87
3.5-inch PC/ATPC DOS(Ver. 3.1) 5-inch
µS7B13RA87
µS7B10RA87
PROM Write Tools
PG-1500 With provided board optional programmer adapter connected, this PROM programmer manipulate from stand-alone host machine perform programming single-chip microcomputer which incorporates PROM. also capable programming typical PROM ranging from bits. PA-78CP14GF/ PA-78CP14GF PA-78CP14GQ PG-1500 controller PROM programmer adapter µPD78CP18(A). Used connecting PG-1500.
Hardware
µPD78CP18GF(A)-3BE µPD78CP18GQ(A)-36 Connects PG-1500 host machine using serial parallel interface, control PG1500 host machine.
Host Machine Software PC-9800 series
MS-DOS Ver. 2.11 Ver. 5.00ANote (Ver. 3.1)
Supply Medium 3.5-inch
Ordering Code (Product Name)
µS5A13PG1500
5-inch
µS5A10PG1500
PC/AT
5-inch
µS7B10PG1500
Note Versions 5.00 5.00A have task swap function, this function cannot used with this software. Remark operations assembler PG-1500 controller guaranteed only above host machines operating systems.
µPD78CP18(A)
Debugging Tools in-circuit emulator (IE-78C11-M) available program debugging tool PD78CP18(A). following table shows system configuration.
Hardware
IE-78C11-M
IE-78C11-M in-circuit emulator which works with 87AD series. connected host machine perform efficient debugging.
IE-78C11-M control program controller)
Connects IE-78C11-M host machine using RS-233C, control IE-78C11-M host machine.
Software
Host Machine PC-9800 series
MS-DOS Ver. 2.11 Ver. 3.30D (Ver. 3.1)
Supply Medium 3.5-inch
Ordering Code (Product Name)
µS5A13IE78C11
5-inch
µS5A10IE78C11
PC/AT
5-inch
µS7B10IE78C11
Remark
operations controller guaranteed only above host machines operating systems.
µPD78CP18(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static
electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards wiht semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78CP18(A)
[MEMO]
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customer must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact Sales Representative advance. Anti-radioactive design implemented this product.
94.11
QTOP trademark Corporation. MS-DOS trademark Microsoft Corporation. PC/AT trademarks Corporation.

µPD78CP18(A) 8-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION

Top Searches for this datasheet

Other recent searches