µPD784224, 784225, 784224Y, 784225Y 16/8-BIT SINGLE-CHIP MICROCON
|
|
|
Top Searches for this datasheet
INTEGRATED CIRCUIT
µPD784224, 784225, 784224Y, 784225Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
µPD784224 784225 products µPD784225 Subseries 78K/IV Series. Besides highspeed high performance CPU, these controllers have ROM, RAM, ports, 8-bit resolution converters, timers, serial interfaces, real-time output port, interrupt functions, various other peripheral hardware. µPD784224Y 784225Y based µPD784225 Subseries with addition multimastersupporting interface. Flash memory versions, µPD78F4225 78F4225Y, which replace internal mask version with flash memory, various development tools also available. functions explained detail following user's manuals. sure read this manual when designing your system.
µPD784225, 784225Y Subseries User's Manual Hardware U12697E
78K/IV Series User's Manual Instruction U10905E
FEATURES
correction Inherits peripheral functions PD780058Y Subseries Minimum instruction execution time (main system clock 12.5 MHz) (subsystem clock 32.768 kHz) port: pins Timer/counter: 16-bit timer/counter unit 8-bit timer/counter units Serial interface: channels UART/IOE (3-wire serial I/O): channels (3-wire serial I/O, multi-master supporting busNote): channel Note µPD784225Y Subseries only Standby function HALT/STOP/IDLE mode power-saving mode: HALT/IDLE mode (with subsystem clock) Clock division function Watch timer: channel Watchdog timer: channel Clock output function fXX, XX/2, fXX/22, fXX/23 fXX/24, fXX/25, XX/26, fXX/27 selectable Buzzer output function fXX/210, fXX/211, fXX/212, fXX/213 selectable converter: 8-bit resolution channels converter: 8-bit resolution channels Supply voltage:
APPLICATION FIELD
audio, portable audio, telephones, etc. Unless contextually excluded, references this document µPD784225 mean µPD784224, 784225, 784224Y, 784225Y.
information this document subject change without notice. Before using this document, please confirm that this latest version. Document U12376EJ1V0DS00 (1st edition) Date Published 2000 CP(K) Printed Japan
mark
shows major revised points.
1997, 2000
µPD784224, 784225, 784224Y, 784225Y
ORDERING INFORMATION
Part Number Package 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin plastic plastic plastic plastic plastic plastic plastic plastic TQFP (fine pitch) TQFP (fine pitch) TQFP (fine pitch) TQFP (fine pitch) Internal (Bytes) Internal (Bytes) 3,584 3,584 4,352 4,352 3,584 3,584 4,352 4,352
Note Under development Remark indicates code suffix.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
78K/IV SERIES LINEUP
mass production Under development Supports Supports multi-master
PD784038Y PD784038
PD784225Y PD784225
80-pin, correction added Supports multi-master
Standard models
PD784026
Enhanced converter, 16-bit timer, power management
Enhanced internal memory capacity Pin-compatible with PD784026 Supports multi-master
µPD784216AY PD784216A
100-pin, enhanced internal memory capacity
µPD784218AY PD784218A
Enhanced internal memory capacity, correction added
µPD784054 µPD784046
ASSP models
PD784956A
inverter control
On-chip 10-bit converter
PD784938A
Enhanced functions PD784908, enhanced internal memory capacity, correction added. Supports multi-master
PD784908
On-chip IEBuscontroller
PD784928Y µPD784915
Software servo control On-chip analog circuit VCRs Enhanced timer
PD784928
Enhanced functions PD784915
PD784967
On-chip controller/driver
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
FUNCTIONS
Part Number Item Number basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space port Total CMOS Input CMOS Pins with ancillary Pins with pull-up resistor bits registers banks, bits registers banks (memory mapping) ns/320 ns/640 ns/1,280 ns/2,560 (main system clock: 12.5 MHz) (subsystem clock: 32.768 kHz) Kbytes 3,584 bytes bits bits Timer/event counter (16-bit) Timer counter Capture/compare register Pulse output PWM/PPG output Square wave output One-shot pulse output Pulse output output Square wave output Pulse output output Square wave output Kbytes 4,352 bytes
µPD784224, µPD784224Y
µPD784225, µPD784225Y
with program data spaces combined
functionsNote LEDs direct drive output Real-time output port Timer
Timer/event counter Timer counter (8-bit) Compare register Timer/event counter Timer counter (8-bit) Compare register Timer (8-bit) Timer (8-bit) Serial interface converter converter Clock output Buzzer output Watch timer Watchdog timer Standby Interrupt Hardware Software Non-maskable Maskable Timer counter Compare register Timer counter Compare register
UART/IOE (3-wire serial I/O): channels (on-chip baud rate generator) (3-wire serial I/O, busNote supporting multi master): channel 8-bit resolution channels 8-bit resolution channels Selectable from fXX, /22, /23, /24, fXX/26 fXX/27, Selectable from /210, /211, fXX/212, fXX/213 channel channel HALT/STOP/IDLE mode power-saving mode (with subsystem clock): HALT/IDLE mode (internal: external: instruction, BRKCS instruction, operand error Internal: external: Internal: external: programmable priority levels service modes: vectored interrupt/macro service/context switching
Supply voltage Package
80-pin plastic QFP(14 80-pin plastic TQFP (fine pitch)
Notes pins with ancillary functions included pins. µPD784225Y Subseries only
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
CONTENTS
DIFFERENCES AMONG MODELS µPD784225, 784225Y SUBSERIES MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES µPD780058Y SUBSERIES CONFIGURATION (Top View) BLOCK DIAGRAM FUNCTION
Port Pins Pins Other Than Port Pins Circuit Type Respective Pins Recommended Connections Unused Pins
ARCHITECTURE
Memory Space Registers 6.2.1 6.2.2 6.2.3 General-purpose registers Control registers Special function registers (SFRs)
PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generator Real-Time Output Port Timer Converter Converter Serial Interface 7.7.1 7.7.2 Asynchronous serial interface/3-wire serial (UART/IOE) Clocked serial interface (CSI)
Clock Output Function Buzzer Output Function
7.10 Edge Detection Function 7.11 Watch Timer 7.12 Watchdog Timer
INTERRUPT FUNCTION
Interrupt Sources Vectored Interrupt Context Switching Macro Service Application Example Macro Service
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
LOCAL INTERFACE
Memory Expansion Programmable Wait External Access Status Function
STANDBY FUNCTION RESET FUNCTION CORRECTION INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
DIFFERENCES AMONG MODELS µPD784225, 784225Y SUBSERIES
only difference among µPD784224 784225 lies internal memory capacity. µPD784224Y 784225Y based µPD784224 784225 respectively, with addition control function. µPD78F4225 78F4225Y provided with 128-Kbyte flash memory instead mask above models. These differences summarized Table 1-1. Table 1-1. Differences among Models µPD784225, 784225Y Subseries
Part Number Item Internal
µPD784224, µPD784224Y
Kbytes (mask ROM) 3,584 bytes
µPD784225, µPD784225Y
Kbytes (mask ROM) 4,352 bytes
µPD78F4225, µPD78F4225Y
Kbytes (Flash memory)
Internal
Internal memory None size switching register (IMS)Note Supply voltage Electrical specifications Recommended soldering conditions TEST Provided None Refer data sheet each device.
Provided
None Provided
Note internal flash memory capacity internal capacity changed using internal memory size switching register (IMS). Caution There differences noise immunity noise radiation between flash memory mask versions. When pre-producing application with flash memory version then mass-producing with mask version, sure conduct sufficient evaluations commercial samples (not engineering samples) mask version.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES µPD780058Y SUBSERIES
Series Name Item Minimum instruction execution time With main system clock selected With subsystem clock
µPD784225, 784225Y Subseries
16-bit 12.5 MHz) 32.768 kHz)
µPD784216Y Subseries
µPD780058Y Subseries
8-bit MHz) 32.768 kHz)
Memory space port Total CMOS input CMOS N-ch open-drain Pins with ancillary functionNote Pins with pull-up resistor direct drive output Medium-voltage Timer/counter
Mbytes pins pins pins pins pins pins pins pins pins
Kbytes pins pins pins pins pins (flash memory model: pins) pins
pins 16-bit timer/event counter unit 8-bit timer/event counter units
pins
pins 16-bit timer/event counter unit 8-bit timer/event counter units
pins 16-bit timer/event counter unit 8-bit timer/event counter units UART (time-division transfer function)/IOE (3-wire serial I/O) channels (3-wire serial I/O, 2-wire serial I/O, bus) channel (3-wire serial with automatic transmission/reception function) channel None None None levels HALT/STOP mode
Serial interface
UART/IOE (3-wire serial I/O) channels (3-wire serial I/O, multi-master supporting busNote channel
Interrupt
Macro service Context switching
Provided Provided Provided
Programmable priority levels Standby function HALT/STOP/IDLE mode Power-saving mode: HALT/IDLE Mode Provided 80-pin plastic 80-pin plastic TQFP (fine pitch) None 100-pin plastic (fine pitch) 100-pin plastic
correction Package
Provided 80-pin plastic 80-pin plastic TQFP (fine pitch)
Notes Pins with ancillary function included pins. µPD784225Y 784216Y Subseries only
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
CONFIGURATION (Top View)
80-pin plastic
80-pin plastic TQFP (fine pitch)
P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2/NMI P01/INTP1 P00/INTP0
TESTNote
A14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVDD
VDD1
VDD0
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD2 P71/SO2/TxD2 P72/SCK2/ASCK2 P20/SI1/RxD1 P21/SO1/TxD1 P22/SCK1/ASCK1 P23/PCL P24/BUZ P25/SI0/SDA0Note P26/SO0 P27/SCK0/SCL0Note P40/AD0 P41/AD1
VSS0
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RPT2 P121/RTP1 P120/RTP0 P37/EXA P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS1
Notes SCL0 SDA0 pins available µPD784225Y Subseries only. Connect TEST VSS0 directly pull-down resistor. pull-down connection, resistor with resistance ranging from recommended. Caution Connect AVSS VSS0. Remark When using applications where noise from inside microcomputer reduced, recommended take countermeasures against noise such supplying power VDD0 VDD1 independently, connecting VSS0 VSS1 different ground lines.
Data Sheet U12376EJ1V0DS00
P56/A14 P57/A15 P60/A16 P61/A17 P62/A18 P63/A19 P64/RD
µPD784224, 784225, 784224Y, 784225Y
ANI0 ANI7 ANO0, ANO1 ASCK1, ASCK2 ASTB AVDD AVREF1 AVSS INTP0 INTP5 P120 P127 Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock External Access Status Output Interrupt from Peripherals Non-maskable Interrupt Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12 P130, P131 RESET RTP0 RTP7 RxD1, RxD2 SCK0 SCK2 SCL0Note SDA0 Note TEST TxD1, TxD2 VDD0, VDD1 VSS0, VSS1 WAIT XT1, Port13 Programmable Clock Read Strobe Reset Real-time Output Port Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Test Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
TI00, TI01, TI1, Timer Input
Note SCL0 SDA0 pins available µPD784225Y Subseries only.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
BLOCK DIAGRAM
INTP2/NMI INTP0, INTP1, INTP3 INTP5 TI00 TI01 PROGRAMMABLE INTERRUPT CONTROLLER TIMER/EVENT COUNTER BITS) TIMER/EVENT COUNTER1 BITS) TIMER/EVENT COUNTER2 BITS) TIMER/COUNTER5 BITS) 78K/IV CORE TIMER/COUNTER6 BITS) PORT0 WATCH TIMER PORT1 PORT2 WATCHDOG TIMER RTP0 RTP7 NMI/INTP2 ANO0 ANO1 AVREF1 AVSS ANI0 ANI7 AVDD AVSS P03/INTP3 REAL-TIME OUTPUT PORT PORT3 PORT4 PORT5 PORT6 CONVERTER PORT7 PORT12 CONVERTER PORT13 P120 P127 P130, P131 RESET CLOCK OUTPUT CONTROL SYSTEM CONTROL BUZZER OUTPUT VDD0, VDD1 VSS0, VSS1 TEST UART/IOE1 BAUD-RATE GENERATOR UART/IOE2 BAUD-RATE GENERATOR CLOCKED SERIAL INTERFACE RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SI0/SDA0Note SCK0/SCL0Note WAIT ASTB
Note This function supports interface available µPD784225Y Subseries only. Remark internal capacities differ depending model.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
FUNCTION Port Pins (1/2)
Name Input Alternate Function INTP0 INTP1 INTP2/NM1 INTP3 INTP4 INTP5 ANI0 ANI7 Port (P1): 8-bit input port Port (P2): 8-bit port input output mode bit-wise. Pins input mode connected internal pull-up resistors software bit-wise. Function Port (P0): 6-bit port input output mode bit-wise. Pins input mode connected internal pull-up resistors software bit-wise.
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 SI0/SDA0Note SCK0/SCL0Note
TI00 TI01
Port (P3): 8-bit port input output mode bit-wise. Pins input mode connected internal pull-up resistors software bit-wise.
Port (P4): 8-bit port input output mode bit-wise. pins input mode connected internal pull-up resistors software. drive LEDs. Port (P5): 8-bit port input output mode bit-wise. pins input mode connected internal pull-up resistors software. drive LEDs.
Note This function available µPD784255Y Subseries only.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Port Pins (2/2)
Name Alternate Function WAIT ASTB RxD2/SI2 Port (P7): 3-bit port input output mode bit-wise. Pins input mode connected internal pull-up resistor software bit-wise. Function Port (P6): 8-bit port input output mode bit-wise. pins input mode connected internal pull-up resistors software.
TxD2/SO2
ASCK2/SCK2
P120 P127
RTP0 RTP7
Port (P12): 8-bit port input output mode bit-wise. Pins input mode connected internal pull-up resistor software bit-wise. Port (P13): 2-bit port input output mode bit-wise.
P130, P131
ANO0, ANO1
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Pins Other Than Port Pins (1/2)
Name TI00 TI01 RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 SDA0Note SCK0 SCK1 SCK2 SCL0Note INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 RTP0 RTP7 Output Output Output Input Output Input Intput Output Input Output Input Alternate Function P20/SI1 P70/SI2 P21/SO1 P71/SO2 P22/SCK1 P72/SCK2 P25/SDA0Note P20/RxD1 P70/RxD2 P21/TxD1 P71/TxD2 P25/SI0 P27/SCL0Note P22/ASCK1 P72/ASCK2 P27/SCK0 P02/INTP2 P02/NMI P120 P127 Clock output (for trimming main system clock subsystem clock) Buzzer output Real-time output port that outputs data synchronization with trigger Low-order address/data when external memory connected Middle-order address when external memory connected High-order address when external memory connected Serial data input (UART1) Serial data input (UART2) Serial data output (UART1) Serial data output (UART2) Baud rate clock input (UART1) Baud rate clock input (UART2) Serial data input (3-wire serial clock I/O0) Serial data input (3-wire serial clock I/O1) Serial data input (3-wire serial clock I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial data input/output (I2C bus) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Serial clock input/output (I2C bus) Non-maskable interrupt request input External interrupt request input Function External count clock input 16-bit timer register Capture trigger signal input capture/compare register External count clock input 8-bit timer register External count clock input 8-bit timer register 16-bit timer output (shared 14-bit output) 8-bit timer output (shared 8-bit output)
Output
Note This function available µPD784255Y Subseries only.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Pins Other Than Port Pins (2/2)
Name WAIT ASTB Input Output Output Alternate Function Function Strobe signal output read operation external memory Strobe signal output write operation external memory insert wait state(s) when external memory accessed Strobe output externally latch address information output ports access external memory External access status output System reset input connect main system clock oscillation crystal
RESET ANI0 ANI7 ANO0, ANO1 AVREF1 AVDD AVSS VDD0 VSS0 VDD1 VSS1 TEST
Output Input Input Input Input Output
connect subsystem clock oscillation crystal
P130, P131
Analog voltage input converter Analog voltage output converter apply reference voltage converter Positive power supply converter. Connected VDD0. converter converter. Connected VSS0. Positive power supply port block potential port block Positive power supply (except port block) potential (except port block) Connect this VSS0 directly pull-down resistor. pull-down connection, resistor with resistance ranging from recommended.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Circuit Type Respective Pins Recommended Connections Unused Pins
Table shows symbols indicating circuit types respective pins recommended connection unused pins. circuit diagram each type circuit, refer Figure 5-1. Table 5-1. Circuit Type Respective Pins Recommended Connections Unused Pins (1/2)
Name P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P05/INTP5 P10/ANI0 P17/ANI7 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SDA0Note/SI0 P26/SO0 P27/SCL0Note/SCK0 P30/TO0 P32/TO2 P33/TI1, P34/TI2 P35/TI00, P36/TI01 P37/EXA P40/AD0 P47/AD7 P50/A8 P57/A15 P60/A16 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 10-I 10-J 10-I 10-I 10-J 10-I 10-J Input Connected VSS0 VDD0 Input Individually connected VSS0 resistor Output: Open Circuit Type Recommended Connections Unused Pins Input Individually connected VSS0 resistor Output: Open
Note This function available µPD784255Y Subseries only. Remark Because circuit type numbers standardized among Series products, they sequential some models (i.e., some circuits provided).
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Table 5-1. Circuit Type Respective Pins Recommended Connections Unused Pins (2/2)
Name P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1 RESET AVREF1 AVDD AVSS TEST/VPPNote Connected VSS0 Directly connected VSS0 Circuit Type 12-D Input Connected VSS0 Open Connected VDD0 Recommended Connections Unused Pins Input Individually connected VSS0 resistor Output: Open
Note available µPD78F4225, 78F4255Y only. Remark Because circuit type numbers standardized among Series products, they sequential some models (i.e., some circuits provided).
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Figure 5-1. Types Circuits (1/2)
Type
Type
VDD0
pullup enable VDD0 data P-ch
P-ch
IN/OUT Schmitt trigger input with hysteresis characteristics output disable VSS0 input enable Type pullup enable VDD0 data P-ch IN/OUT output disable VSS0 input enable Type VDD0 Type 10-I VDD0 N-ch input enable VDD0 Type N-ch
P-ch P-ch N-ch Comparator
VREF (threshold voltage)
pullup enable VDD0 data P-ch
P-ch
pullup enable VDD0 data IN/OUT P-ch
P-ch
IN/OUT open drain output disable VSS0 N-ch
output disable VSS0
N-ch
Type
VDD0
Type 10-J
VDD0
pullup enable VDD0 data P-ch
P-ch
pullup enable VDD0 data IN/OUT P-ch
P-ch
IN/OUT open drain output disable VSS0 N-ch
open drain output disable VSS0
N-ch
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Figure 5-1. Types Circuits (2/2)
Type 12-D
VDD0 data P-ch IN/OUT output disable input enable N-ch VSS0 P-ch Analog output voltage
N-ch
VSS0
Type feedback cut-off P-ch
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
ARCHITECTURE Memory Space
memory space Mbyte accessed. Mapping internal data area (special function registers internal RAM) specified LOCATION instruction. LOCATION instruction must always executed after RESET cancellation, must used more than once. When LOCATION instruction executed Internal memory internal data area internal area mapped follows:
Part Number Internal Data Area 0F100H 0FFFFH Internal Area 00000H 0F0FFH 10000H 17FFFH 00000H 0EDFFH 10000H 1FFFFH
µPD784224, µPD784224Y µPD784225, µPD784225Y
0EE00H 0FFFFH
Caution
following areas that overlap internal data area internal cannot used when LOCATION instruction executed.
Part Number Unusable Area 0F100H 0FFFFH (3,840 bytes)
µPD784224, µPD784224Y µPD784225, µPD784225Y
0EE00H 0FFFFH (4,608 bytes)
External memory external memory accessed external memory expansion mode. When LOCATION instruction executed Internal memory internal data area internal area mapped follows:
Part Number Internal Data Area FF100H FFFFFH Internal Area 00000H 17FFFH
µPD784224, µPD784224Y µPD784225, µPD784225Y
FEE00H FFFFFH
00000H 1FFFFH
External memory external memory accessed external memory expansion mode.
Data Sheet U12376EJ1V0DS00
Figure 6-1. Memory µPD784224, 784224Y
execution LOCATION instruction
function registers (SFR) (256 bytes)
execution LOCATION instruction
Special FDFH Note FD0H
External memory (928 Kbytes)
FFE8
Note
General-purpose registers (128 bytes) Internal (3,584 bytes)
Internal
FFE3 FFE0
(SFR)
Macro service control word area bytes) Data area (512 bytes)
(32,768 bytes) Special function registers FDFH Note FD0H (256 bytes)
Internal (3,584 bytes) Program/data area (3,072 bytes)
External memory (980,736 bytes)
Note
Note
Data Sheet U12376EJ1V0DS00
Note
Program/data area CALLF entry area Kbytes)
Note
Internal (61,696 bytes)
CALLT table area bytes) Vector table area bytes)
Internal Kbytes)
Note
Notes Accessed external memory expansion mode.
This 3,840-byte area used internal only when LOCATION instruction executed.
µPD784224, 784225, 784224Y, 784225Y
execution LOCATION instruction: 94,464 bytes, execution LOCATION instruction: 98,304 bytes
Base area entry area reset interrupt. However, internal area used reset entry area.
Figure 6-2. Memory µPD784225, 784225Y
execution LOCATION instruction
function registers (SFR) (256 bytes)
Note
Special FDFH Note FD0H
execution LOCATION instruction
External memory (896 Kbytes) General-purpose registers (128 bytes) Internal (4,352 bytes)
FFE8
Internal (65,536 bytes)
FFE0 FFE3
function registers (SFR) (256 bytes)
Macro service control word area bytes) Data area (512 bytes)
Special FDFH Note FD0H
Internal (4,352 bytes) Program/data area (3,840 bytes)
External memory (912,896 bytes)
Note
Note
Data Sheet U12376EJ1V0DS00
Note
Program/data area
Note
Internal (60,928 bytes)
CALLF entry area Kbytes)
CALLT table area bytes) Vector table area bytes)
Internal (128 Kbytes)
Note
Notes Accessed external memory expansion mode.
This 4,608-byte area used internal only when LOCATION instruction executed.
execution LOCATION instruction: 126,464 bytes, execution LOCATION instruction: 131,072 bytes
µPD784224, 784225, 784224Y, 784225Y
Base area entry area reset interrupt. However, internal area used reset entry area.
µPD784224, 784225, 784224Y, 784225Y
Registers
6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers available. 8-bit registers also used pairs 16-bit register. 16-bit registers, four used combination with 8-bit register address expansion 24-bit address specification registers. Eight banks these registers available which selected using software context switching function. general-purpose registers except registers address expansion mapped internal RAM. Figure 6-3. General-Purpose Register Format
(R1) (RP0) (R3) (RP1) (RG4) (RP4)
(R0) (R2)
(RP5) (RG5) (R13) (R12) (RP6) (RG6) (R15) (R14) banks (RG7) (RP7) indicate absolute name.
Parentheses
Caution
Registers RP2, used registers, respectively, setting However, this function only recycling program 78K/III Series.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
6.2.2 Control registers Program counter (PC) program counter 20-bit register whose contents automatically updated when program executed. Figure 6-4. Program Counter (PC) Format
Program status word (PSW) This register holds statuses CPU. contents automatically updated when program executed. Figure 6-5. Program Status Word (PSW) Format
PSWH PSWL
Note
RBS2
RBS1
RBS0
Note This flag provided maintain compatibility with 78K/III Series. sure clear this flag except when software 78K/III Series used. Stack pointer (SP) This 24-bit pointer that holds first address stack. sure write higher bits this pointer. Figure 6-6. Stack Pointer (SP) Format
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
6.2.3 Special function registers (SFRs) special function registers, such mode registers control registers internal peripheral hardware, registers which special functions allocated. These registers mapped 256-byte space addresses 0FF00H 0FFFFHNote. Note execution LOCATION instruction. FFF00H FFFFFH execution LOCATION instruction. Caution access address this area which allocated. such address accessed mistake, µPD784225 deadlock status. This deadlock status cleared only inputting RESET signal. Table lists special function registers (SFRs). meanings symbols this table follows: Symbol Symbol indicating SFR. compiler (CC78K4). Indicates whether read-only, write-only, read/write. Read/write Read-only Write-only This symbol reserved NEC's assembler
(RA78K4). used variable #pragma directive with
units manipulation units which value manipulated. SFRs that manipulated 16-bit units described operand sfrp instruction. specify address this SFR, describe even address. SFRs that manipulated 1-bit units described operand manipulation instruction. reset Indicates status register when RESET signal been input.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Table 6-1. Special Function Register (SFR) List (1/4)
AddressNote Special Function Register (SFR) Name Symbol Units Manipulation 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF0CH 0FF0DH 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF18H 0FF1AH 0FF1CH 0FF20H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF2CH 0FF2DH 0FF30H 0FF32H 0FF33H 0FF37H 0FF3CH 0FF40H Capture/compare register (16-bit timer/counter) Capture/compare register (16-bit timer/counter) Capture/compare control register 16-bit timer mode control register 16-bit timer output control register Prescaler mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Clock output control register CRC0 TMC0 TOC0 PRM0 PM12 PM13 PU12 CR01 CR00 Port Port Port Port Port Port Port Port Port Port 16-bit timer counter Bits Bits 0000H 00HNote Reset
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. Because each port initialized input mode reset, "00H" actually read. output latch initialized "0".
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Table 6-1. Special Function Register (SFR) List (2/4)
AddressNote Special Function Register (SFR) Name Symbol Units Manipulation 0FF42H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF60H 0FF61H 0FF64H 0FF65H 0FF68H 0FF69H 0FF6CH 0FF6DH 0FF70H 0FF71H 0FF72H 0FF73H 0FF74H Port function control register Pull-up resistor option register 8-bit timer counter 8-bit timer counter Compare register (8-bit timer/counter Compare register (8-bit timer/counter 8-bit timer mode control register 8-bit timer mode control register Prescaler mode register Prescaler mode register 8-bit timer counter 8-bit timer counter Compare register (8-bit timer/counter Compare register (8-bit timer/counter 8-bit timer mode control register 8-bit timer mode control register Prescaler mode register Prescaler mode register Asynchronous serial interface mode register Asynchronous serial interface mode register Asynchronous serial interface status register Asynchronous serial interface status register Transmit shift register Receive buffer register 0FF75H Transmit shift register Receive buffer register 0FF76H 0FF77H 0FF7AH 0FF80H 0FF81H 0FF83H 0FF84H 0FF85H 0FF86H 0FF87H Baud rate generator control register Baud rate generator control register Oscillation mode select register converter mode register converter input select register conversion result register conversion value setting register conversion value setting register converter mode register converter mode register CR10 CR1W CR20 TMC1 TMC1W TMC2 PRM1 PRM1W PRM2 TM5W CR50 CR5W CR60 TMC5 TMC5W TMC6 PRM5 PRM5W PRM6 ASIM1 ASIM2 ASIS1 ASIS2 TXS1 RXB1 TXS2 RXB2 BRGC1 BRGC2 ADIS ADCR DACS0 DACS1 DAM0 DAM1 Undefined TM1W Bits Bits 0000H Reset
Note When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Table 6-1. Special Function Register (SFR) List (3/4)
AddressNote Special Function Register (SFR) Name Symbol Units Manipulation 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8DH 0FF90H 0FF91H 0FF92H 0FF94H 0FF95H 0FF96H 0FF98H 0FF99H 0FF9AH 0FF9BH 0FF9CH 0FFA0H 0FFA2H 0FFA8H 0FFA9H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFAFH 0FFB0H 0FFB2H 0FFB4H 0FFB6H 0FFB8H 0FFC0H 0FFC2H 0FFC4H 0FFC7H 0FFC8H 00FFCEH 0FFCFH 0FFD0H 0FFDFH External access status enable register Serial operation mode register Serial operation mode register Serial operation mode register Serial shift register Serial shift register Serial shift register Real-time output buffer register Real-time output buffer register Real-time output port mode register Real-time output port control register Watch timer mode control register External interrupt rising edge enable register External interrupt falling edge enable register In-service priority register Interrupt select control register Interrupt mode control register Interrupt mask flag register Interrupt mask flag register Interrupt mask flag register Interrupt mask flag register control registerNote Prescaler mode register serial clock Slave address register status registerNote EXAE CSIM0 CSIM1 CSIM2 SIO0 SIO1 SIO2 RTBL RTBH RTPM RTPC WEGP0 EGN0 ISPR SNMI MK0L MK0H MK1L MK1H IICCL0 SPRM0 SVA0 IICS0 IIC0 STBC PWC1 PWC2 OSTS AAAAH FFFFH correction control register correction address pointer correction address pointer CORC CORAH CORAL Bits Bits 0000H Reset
Serial shift register Standby control register Watchdog timer mode register Memory expansion mode register Programmable wait control register Programmable wait control register Clock status register Oscillation stabilization time specification register External area
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. µPD784225Y Subseries only
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Table 6-1. Special Function Register (SFR) List (4/4)
AddressNote Special Function Register (SFR) Name Symbol Units Manipulation 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH 0FFF0H 0FFF1H 0FFF2H 0FFF3H 0FFF4H 0FFF5H 0FFF6H 0FFF9H Interrupt control register (INTWDTM) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTIIC0/INTCSI0) Interrupt control register (INTSER1) Interrupt control register (INTSR1/INTCSI1) Interrupt control register (INTST1) Interrupt control register (INTSER2) Interrupt control register (INTSR2/INTCSI2) Interrupt control register (INTST2) Interrupt control register (INTTM3) Interrupt control register (INTTM00) Interrupt control register (INTTM01) Interrupt control register (INTTM1) Interrupt control register (INTTM2) Interrupt control register (INTAD) Interrupt control register (INTTM5) Interrupt control register (INTTM6) Interrupt control register (INTWT) WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 CSIIC0 SERIC1 SRIC1 STIC1 SERIC2 SRIC2 STIC2 TMIC3 TMIC00 TMIC01 TMIC1 TMIC2 ADIC TMIC5 TMIC6 WTIC Bits Bits Reset
Note When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
PERIPHERAL HARDWARE FUNCTIONS Ports
ports shown Figure provided make various control operations possible. Table shows function each port. Ports connected internal pull-up resistors software when inputting. Figure 7-1. Port Configuration
Port
Port
Port
Port
P120
Port
Port Port Port
Port
P127 P130 P131
Port
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Table 7-1. Port Functions
Port Name Name Function Specification Pull-up Resistor Connection Software specified bit-wise specified bit-wise specified bit-wise specified 1-port units
Port Port Port Port Port
input output mode bit-wise Input port input output mode bit-wise input output mode bit-wise input output mode bit-wise directly drive LEDs input output mode bit-wise directly drive LEDs input output mode bit-wise input output mode bit-wise input output mode bit-wise input output mode bit-wise
Port
specified 1-port units
Port Port Port Port
P120 P127 P130, P131
specified 1-port units specified bit-wise specified bit-wise
Clock Generator
on-chip clock generator necessary operation provided. This clock generator frequency divider. high-speed operation necessary, internal operating frequency lowered frequency divider reduce current consumption. Figure 7-2. Block Diagram Clock Generator
Subsystem clock oscillator
Watch timer, clock output function Prescaler
Main system clock oscillator
IDLE controller
Frequency divider
Selector
Prescaler
Clock peripheral hardware
STOP (MCK) standby control register (STBC) when subsystem clock selected clock
Selector STOP, IDLE controller HALT controller clock (fCPU)
Internal system clock (fCLK)
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Figure 7-3. Example Using Main System Clock Oscillator Crystal/ceramic oscillation External clock
VSS1
Crystal resorator ceramic resonator
External clock PD74HCU04
Figure 7-4. Example Using Subsystem Clock Oscillator Crystal oscillation External clock
32.768 VSS1
External clock
µPD74HCU04
Caution
When using main system clock subsystem clock oscillator, wire dotted portions Figures follows avoid adverse influence from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity lines through which high alternating current flows. Always keep potential ground point capacitor oscillator same VSS1. ground ground pattern through which high current flows. extract signals from oscillator. Note that subsystem clock oscillator amplification factor reduce current consumption.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Real-Time Output Port
real-time output function transfer data advance real-time output buffer register output latch soon timer interrupt external interrupt occurred order output data external device. pins that output data external device constitute port called real-time output port. Because real-time output port output signals without jitter, ideal controlling stepping motor. Figure 7-5. Block Diagram Real-Time Output Port
Internal Real-time output port control register (RTPC) RTPOE BYTE EXTR
INTP2TRG INTTM1 INTTM2 Output trigger controller
Higher bits real-time output buffer register (RTBH)
Lower bits real-time output buffer register (RTBL) Real-time output port mode register (RTPM)
Port output latch
Real-time output port output latch
P120
RTP0
RTPOE
P12n/RTPn output
P120/ RTP7 RTP0
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Timer
unit 16-bit timers/event counters, units timers/event counters, 8-bit timers provided. Because total interrupt requests supported, these timers/counters timer used units timers/counters. Table 7-2. Operations Timers
Name Item Count width bits bits Operation mode Interval timer External event counter Function Timer output output output Square wave output One-shot pulse output Pulse width measurement Number interrupt requests inputs 16-Bit 8-Bit 8-Bit Timer/Event Timer/Event Timer/Event Counter Counter Counter 8-Bit Timer 8-Bit Timer
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Figure 7-6. Block Diagram Timers (1/2) 16-bit timer/event counter
fXX/4 fXX/16 INTTM3
Clear
Selector
16-bit timer counter (TM0)
Selector
TI01
Edge detector
INTTM00
INTTM01 TI00 Edge detector 16-bit capture/compare register (CR01)
Output controller
16-bit capture/compare register (CR00)
8-bit timer/event counter
fXX/22 fXX/23 Clear
Selector
fXX/2
fXX/25 fXX/27 fXX/29 Edge detector
8-bit timer counter (TM1)
Output controller
8-bit compare register (CR10) INTTM2
Selector
INTTM1
8-bit timer/event counter
fXX/22 fXX/23 fXX/24 fXX/2 fXX/2
Clear
Selector
8-bit timer counter (TM2)
Output controller
fXX/29 Edge detector 8-bit compare register (CR20) INTTM2
Remark OVF: Overflow flag
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Figure 7-6. Block Diagram Timers (2/2) 8-bit timer
fXX/22 fXX/23 fXX/24 fXX/25 fXX/27 fXX/29 Clear
Selector
8-bit timer counter (TM5)
8-bit compare register (CR50) INTTM6
Selector
INTTM5
8-bit timer
fXX/22 Selector fXX/2
Clear
fXX/24 fXX/25 fXX/2
8-bit timer counter (TM6)
fXX/29
8-bit compare register (CR60)
INTTM6
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Converter
converter converts analog input variable into digital signal. This microcontroller provided with converter with resolution bits channels (ANI0 ANI7). This converter successive approximation type result conversion stored 8-bit conversion result register (ADCR). converter started following ways: Hardware start Conversion started trigger input (P03). Software start Conversion started setting converter mode register. analog input channel selected from ANI0 ANI7 conversion. When conversion started means hardware start, conversion stopped after been completed. When conversion started means software start, conversion repeatedly executed, each time conversion been completed, interrupt request (INTAD) generated. Figure 7-7. Block Diagram Converter
Series resistor string ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVSS Successive approximation register (SAR) Selector Voltage comparator Sample hold circuit selector AVDD
INTP3/P03
Edge detector
Controller
INTAD
Edge detector
conversion result register (ADCR) INTP3 Internal
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Converter
converter converts input digital signal into analog voltage. This microcontroller provided with voltage output type converter with resolution bits channels. conversion method R-2R resistor ladder type. conversion started setting DACE0 converter mode register (DAM0) DACE1 converter mode register (DAM1). converter operates following modes: Normal mode converter outputs analog voltage immediately after completed conversion. Real-time output mode converter outputs analog voltage synchronization with output trigger after completed conversion. Figure 7-8. Block Diagram Converter
DACS0 ANO0 AVREF1
Selector DACS1 ANO1
Selector AVSS
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Serial Interface
Three independent serial interface channels provided. Asynchronous serial interface (UART)/3-wire serial (IOE) Clocked serial interface (CSI) 3-wire serial (IOE) interface (I2C) (µPD784225Y Subseries only) Therefore, communication with external system local communication within system simultaneously executed (see Figure 7-9). Figure 7-9. Example Serial Interface UART
PD784225Y (master) PD4711A
[UART] RxD1 RS-232C driver/receiver TxD1
VDD0
VDD0
µPD780078Y (slave)
SDA0 SCL0
Port
PD780308Y (slave)
PD4711A
[UART] RxD2 RS-232C driver/receiver TxD2
Port
UART 3-wire serial
PD784225Y (master)
PD4711A
[UART] RxD2 RS-232C driver/receiver TxD2
PD753106 (slave)
[3-wise serial I/O] Note Port
SCK1 INTPm Port
Port
Note Handshake line
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
7.7.1 Asynchronous serial interface/3-wire serial (UART/IOE) channels serial interfaces that select asynchronous serial interface mode 3-wire serial mode provided. Asynchronous serial interface mode this mode, data byte following start transferred received. Because on-chip baud rate generator provided, wide range baud rates set. Moreover, clock input ASCK divided define baud rate. When baud rate generator used, baud rate conforming MIDI standard (31.25 kbps) also obtained. Figure 7-10. Block Diagram Asynchronous Serial Interface Mode
Internal Receive buffer register (RXB1, RXB2) RxD1, RxD2 TxD1, TxD2 Receive control parity check INTSR1, INTSR2 Transmit control parity addition INTST1, INTST2 Receive shift register (RX1, RX2) Transmit shift register (TXS1, TXS2)
Baud rate generator
5-bit counter Transmit/receive clock generation ASCK1, ASCK2
Selector
fXX/25
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
3-wire serial mode this mode, master device starts transfer making serial clock active transfers 1-byte data synchronization with this clock. This mode used communicate with device having conventional clocked serial interface. Basically, communication established using three lines: serial clocks (SCK1 SCK2), serial data inputs (SI1 SI2), serial data outputs (SO1 SO2). connect more devices, handshake line necessary. Figure 7-11. Block Diagram 3-wire Serial Mode
Internal Direction controller SI1, Serial shift register (SIO1, SIO2)
SO1, SCK1, SCK2 Serial clock counter Serial clock controller Interrupt generator INTCSI1, INTCSI2 fXX/8 fXX/16
Selector
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
7.7.2 Clocked serial interface (CSI) this mode, master device starts transfer making serial clock active communicates 1-byte data synchronization with this clock. 3-wire serial mode This mode communicate with devices having conventional clocked serial interface. Basically, communication established this mode with three lines: serial clock (SCK0) serial data (SI0 SO0) lines. Generally, handshake line necessary check reception status. Figure 7-12. Block Diagram 3-Wise Serial Mode
Internal Direction controller Serial shift register (SIO0)
SCK0 Serial clock counter Serial clock controller Interrupt generator INTCSI0
Selector
fXX/8 fXX/16
(Inter mode (supporting multi-master) (µPD784225Y Subseries only) This mode communicate with devices conforming format. This mode transfer 8-bit data with more devices using lines: serial clock (SCL0) serial data (SDA0). During transfer, "start condition", "data", "stop condition" output onto serial data bus. During reception, these data automatically detected hardware.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Figure 7-13. Block Diagram Mode
Internal Direction controller SDA0 Serial shift register (SIO0) Output latch Slave address register (SVA0) Wakeup controller
Start condition/ acknowledge detector Stop condition detector SCL0 Serial clock counter Serial clock controller
Acknowledge generator
Interrupt generator
INTIIC0
Selector
TO2/18 TO2/68 fXX/24 fXX/178
Clock Output Function
Clocks following frequencies output. 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 (main system clock: 12.5 MHz) 32.768 (subsystem clock: 32.768 kHz) Figure 7-14. Block Diagram Clock Output Function
fXX/2 fXX/22 fXX/24 fXX/25 fXX/26 fXX/27
Selector
fXX/23
Synchronizer
Output controller
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Buzzer Output Function
Clocks following frequencies output buzzer output. kHz/3.1 kHz/6.1 kHz/12.2 (main system clock: 12.5 MHz) Figure 7-15. Block Diagram Buzzer Output Function
fXX/210 fXX/211 fXX/212 fXX/213
Selector
Output controller
7.10 Edge Detection Function
interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 INTP5) used only input interrupt requests also input trigger signals internal hardware units. Because these pins operate edge input signal, they have function detect edge. Moreover, noise reduction circuit also provided prevent erroneous detection noise.
Name INTP0 INTP5 Detectable Edge Either both rising falling edges Noise Reduction analog delay
7.11 Watch Timer
watch timer following functions: Watch timer Interval timer watch timer interval timer functions used same time. Watch timer watch timer sets WTIF flag interrupt control register (WTIC) time intervals seconds using 32.768-kHz subsystem clock. Interval timer interval timer generates interrupt request (INTTM3) predetermined time intervals.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Figure 7-16. Block Diagram Watch Timer
Selector
Selector
fXX/27
Selector
5-bit counter
Prescaler
INTWT
Selector
INTTM3 16-bit timer/counter
7.12 Watchdog Timer
watchdog timer provided detect hang CPU. This watchdog timer generates non-maskable maskable interrupt unless cleared software within specified interval time. Once enabled operate, watchdog timer cannot stopped software. Whether interrupt watchdog timer interrupt input from takes precedence specified. Figure 7-17. Block Diagram Watchdog Timer
fCLK
Timer
fCLK/221 fCLK/220
Selector
RUNNote HALT IDLE STOP
fCLK/219 fCLK/217
INTWDT
Note Write (RUN) watchdog timer (WDM). Remark fCLK: Internal system clock (fXX fXX/8)
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
INTERRUPT FUNCTION
servicing response interrupt request, three types shown Table selected program. Table 8-1. Servicing Interrupt Request
Servicing Mode Vectored interrupt Entity Servicing Software Servicing Branches executes servicing routine (servicing arbitrary). Automatically switches register bank, branches executes servicing routine (servicing arbitrary). Firmware Executes data transfer between memory (servicing fixed) Contents Saves restores from stack. Saves restores from fixed area register bank
Context switching
Macro service
Retained
Interrupt Sources
Table shows interrupt sources available. shown, interrupts generated types sources, execution instruction, BRKCS instruction, operand error. priority interrupt servicing four levels, that nesting controlled during interrupt servicing that which more interrupts that simultaneously occur should serviced first. When macro service function used, however, nesting always proceeds. default priority priority (fixed) service that performed more interrupt requests, having same request, simultaneously generate (see Table 8-2).
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Table 8-2. Interrupt Sources
Type Software Default Priority Source Name instruction BRKCS instruction Operand error Trigger Instruction execution Instruction execution result exclusive between operands byte byte when STBC, #byte instruction WDM, #byte instruction, LOCATION instruction executed input edge detection Overflow watchdog timer Overflow watchdog timer input edge detection External Internal Internal External Internal/ External Macro Service
Non-maskable Maskable
(highest)
INTWDT INTWDINTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTIIC0Note INTCSI0 INTSER1 INTSR1 INTCSI1 INTST1 INTSER2 INTSR2 INTCSI2 INTST2 INTTM3 INTTM00
transfer CSI0 3-wire transfer CSI0 Occurrence UART reception error ASI1 UART reception ASI1 3-wire transfer CSI1 UART transfer ASI1 Occurrence UART reception error ASI2 UART reception ASI2 3-wire transfer CSI2 UART transfer ASI2 Reference time interval signal from watch timer Signal indicating coincidence between 16-bit timer counter capture/compare register (CR00) Signal indicating coincidence between 16-bit timer counter capture/compare register (CR01) Occurrence coincidence signal 8-bit timer/counter Occurrence coincidence signal 8-bit timer/counter conversion converter Occurrence coincidence signal 8-bit timer/counter Occurrence coincidence signal 8-bit timer/counter Overflow watch timer
Internal
INTTM01
(lowest)
INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTWT
Note µPD784255Y Subseries only Remarks Asynchronous Serial Interface Clocked Serial Interface There interrupt sources watchdog timer: non-maskable interrupts (INTWDT) maskable interrupts (INTWDTM). Either (but both) should selected actual use.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Vectored Interrupt
Execution branches servicing routing using memory contents vector table address corresponding interrupt source address branch destination. that performs interrupt servicing, following operations performed: branching: Saves status (contents PSW) stack returning Restores status (contents PSW) from stack return main routine from interrupt service routine, RETI instruction used. branch destination address range FFFFH. Table 8-3. Vector Table Address
Interrupt Source instruction Operand error INTWDT (non-maskable) INTWD(maskable) INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTIIC0 INTCSI0 INTSER1 INTSR1 INTCSI1 0018H 001AH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0016H Interrupt Source INTST1 INTSER2 INSR2 INTCSI2 INTST2 INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTWT 0022H 0024H 0026H 0028H 002AH 002CH 002EH 00030H 0032H 0038H Vector Table Address 001CH 001EH 0020H
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Context Switching
When interrupt request generated when BRKCS instruction executed, predetermined register bank selected hardware. Context switching function that branches execution vector address stored advance register bank, stack current contents program counter (PC) program status word (PSW) register bank. branch address range FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Generated
0000B Transfer Register bank
PC19 PC16
Register bank Switching register bank (RBS0 RBS2
PC15
Save (bits through temporary register)
Exchange
Save
Temporary register Save
Macro Service
This function transfer data between memory special function register (SFR) without intervention CPU. macro service controller accesses memory same transfer cycle directly transfers data without loading Because this function does save restore status CPU, load data, data transferred high speeds. Figure 8-2. Macro Service
Read Memory Write Macro service controller
Write Read
Internal
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Application Example Macro Service
Transmission serial interface
Transfer data storage buffer (memory) Data Data
Data Data
Internal
TxD1, TxD2
Transmit shift register TXS1, TXS2 (SFR)
Transfer control
INTST1, INTST2
Each time macro service request INTST1 INTST2 generated, next transmit data transferred from memory TXS1 TXS2. When data (last byte) been transferred TXS1 TXS2 (when transmit data storage buffer become empty), vectored interrupt request INTST1 INTST2 generated. Reception serial interface
Receive data storage buffer (memory) Data Data
Data Data
Internal
Receive buffer register RXB1, RXB2 (SFR)
RxD1, RxD2
Receive shift register
Reception control
INTSR1, INTSR2
Each time macro service request INTSR1 INTSR2 generated, receive data transferred from RXB1 RXB2 memory. When data (last byte) been transferred memory (when receive data storage buffer become full), vectored interrupt request INTSR1 INTSR2 generated.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
LOCAL INTERFACE
local interface connect external memory (memory mapped I/O) support memory space Mbyte (refer Figure 9-1). Figure 9-1. Example Local Interface (Multiplexed bus)
PD784225
VDD1 SRAM Data I/O1 I/O8 Address Address latch
ASTB
Memory Expansion
External program data memory connected stages: Kbytes Mbytes. connect external memory, ports used. external memory connected using time-division address/data bus. number ports used when external memory connected reduced this mode.
Programmable Wait
Wait state(s) inserted memory space (00000H FFFFFH) while signals active. addition, there address wait function that extends active period ASTB signal gain address decode time.
External Access Status Function
active external access status signal output from P37/EXA pin. This signal notifies other devices connected external external access status, disable data output external from other devices, enables reception. external access status signal output during external access.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
STANDBY FUNCTION
This function reduce power consumption chip, used following modes: HALT mode Stops supply operating clock CPU. This mode used combination with normal operation mode intermittent operation reduce average power consumption. IDLE mode Stops entire system with oscillator continuing operation. power consumption this mode close that STOP mode. However, time required restore normal program operation from this mode almost same that from HALT mode. STOP mode Stops main system clock thereby stop internal operations chip. Consequently, power consumption minimized with only leakage current flowing. Power-saving mode main system clock stopped with subsystem clock used system clock. operate subsystem clock reduce current consumption. Power-saving HALT mode This standby function power-saving mode stops operation clock CPU, reduce power consumption entire system. Power-saving IDLE mode This standby function power-saving mode stops entire system except oscillator, reduce power consumption entire system. These modes programmable. macro service started from HALT mode power-saving HALT mode. After executing macro service processing, returns HALT mode.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Figure 10-1. Transition Standby Status
Macro service
sing
Powersaving HALT mode (standby) Interrupt request masked interrupt
Power-saving HALT mode set. Interrupt requestNote
Power-saving IDLE mode set. PowerPowersaving mode saving IDLE (operation NMI, INTP02 INTP6 input, Note mode subsystem INTWT (standby) clock) Interrupt request masked interrupt
er-sa Norm ving erati resto red.
oscilla tion stabiliza tion time
STOP (standby)
Interrupt request masked interrupt
IDLE (standby)
Interrupt request masked interrupt
Interrupt request masked interrupt
HALT (standby)
Waits oscillation stabilization
Notes Only unmasked interrupt requests Only unmasked INTP0 INTP6, INTWT, return interrupt (P80 P87) Remark valid only external input. watchdog timer cannot used release standby (HALT mode/STOP mode/IDLE mode).
Normal operation (operation main system clock)
Macro service request processing macro service
Macro service
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
RESET FUNCTION
When low-level signal input RESET pin, system reset, each hardware unit initialized (reset). During reset period, oscillation main system clock unconditionally stopped. Consequently, current consumption entire system reduced. When RESET signal goes high, reset status cleared, oscillation stabilization time (41.9 12.5 MHz) elapses, contents reset vector table program counter (PC), execution branches address program execution started from that branch address. Therefore, program reset started from address. Figure 11-1. Oscillation Main System Clock during Reset Period
Main system clock oscillator Oscillation unconditionally stopped during rest period fCLK
RESET input Oscillation stabilization time
RESET input analog delay noise eliminator prevent malfunctioning noise. Figure 11-2. Accepting Reset Signal
Time until clock starts oscillation Analog delay Oscillation stabilization time
Analog delay
Analog delay
RESET input
Internal reset signal
Internal clock
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
CORRECTION
correction function replace part program internal with program internal RAM. using correction function, instruction bugs found internal avoided flow program changed. correction used four places internal (program). Figure 12-1. Block Diagram Correction
Program counter (PC)
Coincidence Comparator
Correction branch processing request signal (CALLT instruction)
Correction address pointer
Correction address registers (CORAH, CORAL)
CORENn CORCHm correction control register (CORC) Internal
Remark
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
INSTRUCTION
8-bit instructions (The instructions parentheses combinations realized describing MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 13-1. Instruction List 8-Bit Addressing
Second Operand #byte First Operand (MOV)
Note
saddr saddr'
!addr16 !!addr24
[saddrp] [%saddrg]
PSWL PSWH
[WHL+] [WHL-]
NoneNote
(MOV) (XCH)
(MOV)Note (XCH)Note
(XCH)
(MOV) (XCH)
ADDNote
(MOV) (XCH) (ADD)Note Note MULU DIVUW
(ADD)Note (ADD)Note (ADD)Note (ADD)Note ADDNote
Note
(MOV) (XCH)
ADDNote
ADDNote
(ADD)Note ADDNote
saddr
Note
(MOV) Note
ADDNote
DBNZ PUSH CHKL CHKLA
(ADD)Note ADDNote
ADDNote (ADD)Note ADDNote
!addr16 !!addr24 [saddrp] [%saddrg] mem3
(MOV) ADDNote ADDNote
ROR4 ROL4
PSWL PSWH STBC, [TDE+] [TDE-]
DBNZ (MOV) (ADD)
Note
MOVBKNote
MOVMNote
Notes operands ADDC, SUB, SUBC, AND, XOR, same that ADD. Either second operand used, second operand operand address. operands ROL, RORC, ROLC, SHR, same that ROR. operands XCHM, CMPME, CMPMNE, CMPMNC, CMPMC same that MOVM. operands XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC same that MOVBK. code length some instructions having saddr2 saddr this combination short.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
16-bit instructions (The instructions parentheses combinations realized describing MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 13-2. Instruction List 16-Bit Addressing
Second Operand #word First Operand (MOVW) ADDW
Note
saddrp saddrp'
sfrp
!addr16 !!addr24
[saddrp] [%saddrg]
[WHL+]
byte
NoneNote
(MOVW) (XCHW)
(MOVW) (MOVW) (XCHW) (XCHW)
Note
MOVW (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
Note
(ADD)Note (ADDW)Note (ADDW)Note (ADDW)Note MOVW ADDW
Note
(MOVW) (XCHW) (ADDW)
Note
MOVW XCHW ADDW
Note
MOVW XCHW ADDW
Note
MOVW XCHW ADDW
Note
MOVW
SHRW SHLW
MULW Note INCW DECW INCW DECW
saddrp
MOVW (MOVW)Note MOVW ADDW
Note
MOVW XCHW ADDWNote
(ADDW)
Note
ADDW
Note
sfrp
MOVW
MOVW
MOVW
PUSH MOVTBLW
ADDWNote (ADDW)Note ADDWNote !addr16 !!addr24 [saddrp] [%saddrg] MOVW MOVW (MOVW) MOVW
PUSH
ADDWG SUBWG
post
PUSH PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes operands SUBW CMPW same that ADDW. Either second operand used, second operand operand address. code length some instructions having saddrp2 saddrp this combination short. operands MULUW DIVUX same that MULW.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
24-bit instructions (The instructions parentheses combinations realized describing MOVG, ADDG, SUBG, INCG, DECG, PUSH, Table 13-3. Instruction List 24-Bit Addressing
Second Operand #imm24 First Operand (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH saddrg !!addr24 mem1 [%saddrg] MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] None Note
Note Either second operand used, second operand operand address.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR, BFSET Table 13-4. Manipulation Instructions
Second Operand saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit First Operand !addr16.bit !!addr24.bit MOV1 AND1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BTCLR BFSET /saddr.bit /sfr. /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 NOT1 SET1 CLR1 None Note
Note Either second operand used, second operand operand address.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Call return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, BTCLR, BFSET, DBNZ Table 13-5. Call Return/Branch Instructions
Operand Instruction Address Basic instruction BCNote CALL CALL RETCS RETCSB Compound instruction BTCLR BFSET DBNZ CALL CALL CALL CALL CALL CALLF CALLF BRKCS RETI RETB $addr20 $!addr20 !addr16 !!addr20 [rp] [rg] !addr11 [addr5] None
Note operands BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, same Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, SWRS
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol VDD0 AVDD AVSS AVREF1 Input voltage Analog input voltage Output voltage Output current, Total pins Output current, high Total pins Operating ambient temperature Storage temperature Analog input converter reference voltage input Conditions Ratings -0.3 +6.5 -0.3 VDD0 -0.3 VSS0 -0.3 VDD0 -0.3 VDD0 AVSS AVREF1 -0.3 +150 Unit
Tstg
Caution
Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Operating Conditions Operating ambient temperature (TA): -40°C +85°C Power supply voltage clock cycle time: Figure 14-1 Operating voltage when subsystem clock operating: Figure 14-1. Power Supply Voltage Clock Cycle Time (CPU Clock Frequency: fCPU)
10,000
8,000
Clock cycle time tCYK [ns]
Guaranteed operation range
Supply voltage
Capacitance 25°C, VDD1
Parameter Input capacitance Output capacitance capacitance Symbol Unmeasured pins returned Conditions MIN. TYP. MAX. Unit
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Main System Clock Oscillator Characteristics -40°C +85°C, VDD1)
Resonator Recommended Circuit Ceramic resonator crystal resonator Parameter Oscillation frequency (fX) Conditions MIN. TYP. MAX. 12.5 6.25 3.125 Unit
External clock
input frequency (fX)
12.5 6.25 3.125
input high-/lowlevel width (tWXH, tWXL)
PD74HCU04
input rising/falling time (tXR, tXF)
Cautions When using main system clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock. Remark resonator selection oscillator constant, customers required either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Subsystem Clock Oscillator Characteristics -40°C +85°C, VDD0 DD1)
Resonator Recommended Circuit Crystal resonator
Parameter Oscillation frequency (fXT) Oscillation stabilization timeNote
Conditions
MIN.
TYP. 32.768
MAX.
Unit
External clock
input frequency (fXT) input high-/low-level width (tXTH, tXTL)
14.3
15.6
PD74HCU04
Note Time required stabilize oscillation after applying supply voltage (VDD). Cautions When using subsystem clock oscillator, wire follows area enclosed broken lines above figures avoid adverse effect from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock. Remark resonator selection oscillator constant, customers required either evaluate oscillation themselves apply resonator manufacturer evaluation.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Characteristics -40°C +85°C, VDD0 VDD1 AVSS (1/2)
Parameter Input voltage, Symbol VIL1 Note Conditions VIL2 P05, P20, P22, P33, P34, P70, P72, RESET VIL4 P17, P130, P131 VIL5 XT1, VIL6 P25, Input voltage, high VIH1 Note VIH2 P05, P20, P22, P33, P34, P70, P72, RESET VIH4 P17, P130, P131 VIH5 XT1, VIH6 P25, Output voltage, VOL1 pins other than P47, P57, mANote P47, mANote VOL2 Output voltage, high VOH1 µANote mANote Except XT1, XT1, VDD0 Except XT1, XT1, VOUT MIN. 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD TYP. MAX. 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.2VDD 0.1VDD 0.3VDD 0.2VDD Unit
-100 Input leakage current, ILIL1
µANote
ILIL2 Input leakage current, high ILIH1
ILIH2 Output leakage current, Output leakage current, high ILOL1
ILOH1
VOUT
Notes P21, P23, P24, P26, P32, P37, P47, P57, P67, P71, P87, P120 P127
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Characteristics -40°C +85°C, VDD0 VDD1 AVSS (2/2)
Parameter Supply voltage Symbol IDD1 Operation mode Conditions 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD2 HALT mode 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD3 IDLE mode 12.5 MHz, ±10% MHz, ±10% MHz, ±10% IDD4 Operation modeNote kHz, ±10% kHz, ±10% kHz, ±10% IDD5 HALT modeNote kHz, ±10% kHz, ±10% kHz, ±10% IDD6 IDLE modeNote kHz, ±10% kHz, ±10% kHz, ±10% Data retention voltage Data retention current VDDDR IDDDR HALT, IDLE modes STOP mode ±10% ±10% Pull-up resistor MIN. TYP. MAX. Unit
Note When main system clock stopped. Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Characteristics -40°C +85°C, VDD0 VDD1 AVSS Read/write operation (1/3)
Parameter Cycle time Symbol tCYK Conditions Address setup time ASTB) tSAST ±10% ±10% ±10% Address hold time (from ASTB) tHSTLA ±10% ±10% ±10% ASTB high-level width tWSTH ±10% ±10% ±10% Address hold time (from tHRA ±10% ±10% ±10% Delay time from address tDAR ±10% ±10% ±10% Address float time (from tFAR ±10% ±10% ±10% Data input time from address tDAID ±10% ±10% ±10% Data input time from ASTB tDSTID ±10% ±10% ±10% Data input time from tDRID ±10% ±10% ±10% MIN. (0.5 (0.5 (0.5 0.5T 0.5T 0.5T (0.5 (0.5 (0.5 0.5T 0.5T 0.5T (2.5 (2.5 (2.5 (1.5 (1.5 (1.5 TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Characteristics -40°C +85°C, VDD0 VDD1 AVSS Read/write operation (2/3)
Parameter Delay time from ASTB Symbol tDSTR Conditions ±10% ±10% ±10% Data hold time (from tHRID ±10% ±10% ±10% Address active time from tDRA ±10% ±10% ±10% Delay time from ASTB tDRST ±10% ±10% ±10% low-level width tWRL ±10% ±10% ±10% Delay time from address tDAW ±10% ±10% ±10% Address hold time (from tHRD ±10% ±10% ±10% Delay time from ASTB data output tDSTOD ±10% ±10% ±10% Delay time from data output tDWOD ±10% ±10% ±10% Delay time from ASTB tDSTW ±10% ±10% ±10% Data setup time tSODWR ±10% ±10% ±10% 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 MIN. 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Characteristics -40°C +85°C, VDD0 VDD1 AVSS Read/write operation (3/3)
Parameter Data hold time (from Symbol tHWOD Conditions ±10% ±10% ±10% Delay time from ASTB tDWST ±10% ±10% ±10% low-level width tWWL ±10% ±10% ±10% MIN. 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (1.5 (1.5 (1.5 TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Characteristics -40°C +85°C, VDD0 VDD1 AVDD VSS0 VSS1 AVSS External wait timing (1/2)
Parameter Input time from address WAIT Symbol tDAWT Conditions ±10% ±10% ±10% Input time from ASTB WAIT tDSTWT ±10% ±10% ±10% Hold time from ASTB WAIT tHSTWT ±10% ±10% ±10% Delay time from ASTB WAIT tDSTWTH ±10% ±10% ±10% Input time from WAIT tDRWTL ±10% ±10% ±10% Hold time from WAIT tHRWT ±10% ±10% ±10% Delay time from WAIT tDRWTH ±10% ±10% ±10% Input time from WAIT data tDWTID ±10% ±10% ±10% Delay time from WAIT tDWTR ±10% ±10% ±10% Delay time from WAIT tDWTW ±10% ±10% ±10% Delay time from WAIT tDWWTL ±10% ±10% ±10% 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T (0.5 (0.5 (0.5 (1.5 (1.5 (1.5 MIN. TYP. MAX. 1.5T 1.5T 1.5T Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
External wait timing (2/2)
Parameter Hold time from WAIT Symbol tHWWT Conditions ±10% ±10% ±10% Delay time from WAIT tDWWTH ±10% ±10% ±10% MIN. TYP. MAX. Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Serial Operation -40°C +85°C, VDD0 VDD1 VSS0 VSS1 AVSS 3-wire serial mode (SCK: Internal clock output)
Parameter cycle time Symbol tKCY1 Conditions MIN. 3,200 high-/low-level width setup time SCK) tKH1, tKL1 tSIK1 1,500 hold time (from SCK) output delay time (from SCK) tKSI1 tKSO1 TYP. MAX. Unit
3-wire serial mode (SCK: External clock input)
Parameter cycle time Symbol tKCY2 Conditions MIN. 3,200 high-/low-level width setup time SCK) tKH2 tKL2 tSIK2 1,600 hold time (from SCK) output delay time (from SCK) tKSI2 tKSO2 TYP. MAX. Unit
UART mode
Parameter ASCK cycle time Symbol tKCY3 Conditions MIN. 1,667 ASCK high-/low-level width tKH3 tKL3 TYP. MAX. Unit
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
mode (µPD784225Y only)
Parameter Symbol MIN. SCL0 clock frequency free time (between stop start conditions) Hold timeNote1 Low-level width SCL0 clock High-level width SCL0 clock Setup time start/restart conditions Data hold When using time CBUS-compatible master When using Data setup time Rising time SDA0 SCL0 signals Falling time SDA0 SCL0 signals Setup time stop condition Pulse width spike restricted input filter Load capacitance each line fCLK tBUF Standard Mode MAX. High-Speed Mode MIN. MAX. Unit
tLOW
tHIGH
0Note
1,000
0Note 100Note 0.1CbNote 0.1CbNote
0.9Note
Notes start condition, first clock pulse generated after hold time. fill undefined area SCL0 falling edge, necessary device provide internal SDA0 signal VIHmin.) with least hold time. device does extend SCL0 signal low-level hold time LOW), only maximum data hold time needs satisfied. high-speed mode used standard mode system. this case, conditions described below must satisfied. device does extend SCL0 signal low-level hold time device extends SCL0 signal low-level hold time sure transmit data SDA0 line before SCL0 line released (tRmax. 1,000 1,250 standard mode specification) Total capacitance line (unit:
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Other Operations -40°C +85°C, VDD0 VDD1 AVDD VSS0 VSS1
Parameter high-/low-level width INTP input high-/lowlevel width RESET high-/low-level width Symbol tWNIL tWNIH tWITL tWITH tWRSL tWRSH INTP0 INTP6 Conditions MIN. TYP. MAX. Unit
Clock Output Operation -40°C +85°C, VDD0 VDD1 VSS0 VSS1 AVSS
Parameter cycle time high-/low-level width rising/falling time Symbol tCYCL tCLL tCLH tCLR tCLF Conditions 0.5T MIN. TYP. MAX. 31,250 15,615 Unit
Remark tCYK 1/fXX (fXX: Main system clock frequency) Divided frequency ratio software When using main system clock: When using subsystem clock:
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Converter Characteristics -40°C +85°C, VDD0 VDD1 AVSS
Parameter Resolution Overall errorNote 6.25 12.5 MHz, AVDD VDD0 3.125 6.25 MHz, AVDD VDD0 3.125 MHz, AVDD VDD0 MHz, AVDD VDD0 Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVDD AVSS tCONV tSAMP VIAN AVDD RAVREF0 conversion performed 24/fXX AVSS AVDD Symbol Conditions MIN. TYP. MAX. Unit
±1.2 %FSR ±1.2 %FSR ±1.6 %FSR ±1.6 %FSR
Note Excludes quantization error (±0.2%FSR). Remark FSR: Full-scale range Converter Characteristics -40°C +85°C, VDD0 VDD1 AVSS
Parameter Resolution Overall errorNote AVREF1 AVREF1 Settling time Load conditions: AVREF1 AVREF1 AVREF1 Output resistance Reference voltage AVREF1 current AVREF1 AIREF1 only channel DACS0, VDD0 Symbol Conditions MIN. TYP. MAX. Unit
±0.6 %FSR ±1.2 %FSR
Note Excludes quantization error (±0.2%FSR). Remark FSR: Full-scale range
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Data Retention Characteristics -40°C +85°C, VDD0 VDD1 AVSS
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR ±10% VDDDR ±10% rise time fall time hold time (from STOP mode setting) STOP release signal input time Oscillation stabilization wait time Low-level input voltage High-level input voltage tRVD tFVD tHVD Conditions MIN. TYP. MAX. Unit
tDREL
tWAIT
Crystal resonator Ceramic resonator RESET, P00/INTP0 P06/INTP6
0.9VDDDR 0.1VDDDR VDDDR
Timing Measurement Points
0.8VDD
Points measurement
0.8VDD
0.45
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Timing Waveform Read operation
(CLK) tCYK
(Output)
Lower address
Lower address
(Output) tDAID
Higher address tHRA tDRA Hi-Z Data (Input) tHRID tFAR Hi-Z
Higher address
tDSTID (Input/output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTR tDAR tDRID tWRL tDRWTL tDAWT tDRWTH tHRWT tDWTR tDWTID tDRST
(Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Write operation
(CLK) tCYK
(Output)
Lower address
Lower address
(Output) tDAID
Higher address tHWA tDAW Hi-Z Data (Output) tHWOD tFAR tSODWR Hi-Z
Higher address
tDSTOD (Output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tWSTH tDSTW tDAW tDWOD tWWL tDWWTL tDAWT tDWWTH tHWWT tDWTW tDWTID tDWST
(Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Serial Operation 3-wire serial mode
tKCY1, tKH1, tKL1, tKSO1, tKSI1, tSIK1, SI/SO
UART mode
tKCY3 tKH3 ASCK tKL3
mode (µPD784255Y Subseries only)
tLOW SCL0
tHIGH
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Clock Output Timing
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
Interrupt Input Timing
tWNIH tWNIL
tWITH
tWITL
INTP0 INTP6
Reset Input Timing
tWRSH tWRSL
RESET
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Clock Timing
tWXH tWXL
1/fX
tXTH
tXTL
1/fXT
Data Retention Characteristics
STOP mode setting
tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
(Cleared falling edge)
(Cleared rising edge)
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
PACKAGE DRAWINGS
80-PIN PLASTIC (14x14)
detail lead
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline located within 0.13 true position (T.P.) maximum material condition.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
detail lead
NOTE Each lead centerline located within 0.08 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22±0.05 0.08 (T.P.) 1.0±0.2 0.145±0.05 0.08 0.1±0.05 1.1±0.1 0.25 0.6±0.15 P80GK-50-9EU-1
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
RECOMMENDED SOLDERING CONDITIONS
µPD784225 should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Caution Soldering conditions undetermined because these products under development. Table 16-1. Soldering Conditions Surface Mount Type 80-pin plastic
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-00-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Solder bath temperature: 260°C max., Time: seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) Exposure limit: daysNote (after that, prebake 125°C hours)
VP15-00-2
Wave soldering
Partial heating
temperature: 300°C max., Time: seconds max. (per row)
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
80-pin plastic TQFP (fine pitch)
80-pin plastic TQFP (fine pitch)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-103-2
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: seconds max. 200°C higher), Count: times less, Exposure limit: daysNote (after that, prebake 125°C hours) Solder bath temperature: 260°C max., Time: seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature) temperature: 300°C max., Time: seconds max. (per row)
VP15-103-2
Wave soldering
Partial heating
Caution
different soldering methods together (except partial heating).
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD784225. Also (5). Language Processing Software
RA78K4 CC78K4 DF784225 CC78K4-L Assembler package common 78K/IV Series compiler package common 78K/IV Series Device file common µPD784225, 784225Y Subseries compiler library source file common 78K/IV Series
Flash Memory Writing Tools
Flashpro (Part No.: FL-PR2), Flashpro (Part No.: FL-PR3, PG-FP3) FA-80GC FA-80GK Dedicated flash programmer microcontroller incorporating flash memory
Adapter writing 80-pin plastic (GC-8BT type) flash memory. Adapter writing 80-pin plastic LQFP (GK-BE9 type) flash memory.
Debugging Tools When IE-78K4-NS in-circuit emulator used
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C In-circuit emulator common 78K/IV Series Power supply unit IE-78K4-NS Interface adapter used when PC-9800 series (except notebook type) used host machine supported) card cable when notebook used host machine (PCMCIA socket supported) Interface adapter when using PC/ATor compatible host machine (ISA supported) Interface adapter when using that incorporates host machine Emulation board emulate µPD784225, 784225Y Subseries Emulation probe 100-pin plastic (GF-3BA type) Emulation probe 100-pin plastic LQFP (GC-8EU type) Socket mounted target system board made 100-pin plastic (GF-3BA type) Conversion adapter connect NP-100GC target system board which 100pin plastic LQFP (GC-8EU type) mounted Integrated debugger IE-78K4-NS System simulator common 78K/IV Series Device file common µPD784225, 784225Y Subseries
IE-70000-CD-IF-A IE-70000-PC-IF-C
IE-70000-PCI-IF IE-784225-NS-EM1 NP-100GF NP-100GC EV-9200GF-100 TGC-100SDW
ID78K4-NS SM78K4 DF784225
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
When IE-784000-R in-circuit emulator used
IE-784000-R IE-70000-98-IF-C In-circuit emulator common 78K/IV Series Interface adapter used when PC-9800 series (except notebook type) used host machine supported) Interface adapter when using PC/AT compatible host machine (ISA supported) Interface adapter when using that incorporates host machine Interface adapter cable used when used host machine Emulation board emulate µPD784225, 784225Y Subseries
IE-70000-PC-IF-C
IE-70000-PCI-IF IE-78000-R-SV3 IE-784225-NS-EM1 IE-784218-R-EM1 IE-784000-R-EM IE-78K4-R-EX3
Emulation board common 78K/IV Series Emulation probe conversion board necessary when using IE-784225-NS-EM1 IE784000-R. necessary when IE-784216-R-EM1 used. Emulation probe 100-pin plastic (GF-3BA type) Emulation probe 100-pin plastic LQFP (GC-8EU type) Socket mounted target system board made 100-pin plastic (GF-3BA type) Conversion adapter connect NP-100GC target system board which 100pin plastic LQFP (GC-8EU type) mounted Integrated debugger IE-784000-R System simulator common 78K/IV Series Device file common µPD784225, 784225Y Subseries
EP-78064GF-R EP-78064GC-R EV-9200GF-100 TGC-100SDW
ID78K4 SM78K4 DF784225
Real-time
RX78K/IV MX78K4 Real-time 78K/IV Series 78K/IV Series
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Cautions Using Development Tools ID78K4-NS, ID78K4, SM78K4 used combination with DF784225. CC78K4 RX78K/IV used combination with RA78K4 DF784218. FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, NP-100GC products made Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). TGC-100SDW product made TOKYO ELETECH CORPORATION. further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672) third-party development tools, 78K/IV Series Selection Guide (U13355E). host machine suitable each software follows:
Host Machine [OS] Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note
PC-9800 series [Windows] PC/AT compatibles [Japanese/English Windows]
Note Note
HP9000 series 700[HP-UXTM] SPARCstation[SunOSTM, SolarisTM] NEWS(RISC) [NEWS-OSTM]
Note DOS-based software
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
APPENDIX RELATED DOCUMENTS
Documents related device
Document Name Japanese Document English This document Planned Planned U10905E U10095E
µPD784224, 784225, 784224Y, 784225Y Data Sheet µPD78F4225, 78F4225Y Data Sheet µPD784225, 784225Y Subseries User's Manual Hardware µPD784225Y Subseries Special Function Register Table
78K/IV Series User's Manual Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction 78K/IV Series Application Note Software Basics
U12376J U12377J Planned Planned U10905J U10594J U10595J U10095J
Documents related development tools (User's Manuals)
Document Name Japanese RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 Compiler Operation Language IE-78K4-NS IE-784000-R IE-784218-R-EM1 IE-784225-NS-EM1 EP-78064 SM78K4 System Simulator Windows Base SM78K Series System Simulator Reference External component user open interface specification Reference Reference Reference U11334J U11162J U11743J U11572J U11571J U13356J U12903J U12155J U13742J EEU-934 U10093J U10092J Document English U11334E U11162E U11743E U11572E U11571E U13356E U12903E U12155E U13742E EEU-1469 U10093E U10092E
ID78K4-NS Integrated Debugger Base ID78K4 Integrated Debugger Windows Base ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base
U12796J U10440J U11960J
U12796E U10440E U11960E
Caution
contents above related documents subject change without notice. sure latest edition document designing.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Documents related embedded software (User's Manual)
Document Name Japanese 78K/IV Series Real-Time Basics Installation Debugger 78K/IV Series MX78K4 Basics U10603J U10604J U10364J U11779J Document English U10603E U10604E
Other documents
Document Name Japanese SEMICONDUCTOR SELECTION GUIDE Products Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide Products Related Micro-Computer: Other Companies X13769X C10535J C11531J C10983J C11892J C10535E C11531E C10983E C11892E Document English
C12769J U11416J
MEI-1202
Caution
contents above related documents subject change without notice. sure latest edition document designing.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Caution This product contains interface circuit. When using interface, notify when ordering custom code. guarantee following only when customer informs interface: Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. IEBus trademark Corporation. Windows registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark International Business Machines Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U12376EJ1V0DS00
µPD784224, 784225, 784224Y, 784225Y
related documents indicated this publication include preliminary versions. However, preliminary versions marked such.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
information this document subject change without notice. Before using this document, please confirm that this latest version. devices/types available every country. Please check with local representative availability additional information. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. Descriptions circuits, software, other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software, information design customer's equipment shall done under full responsibility customer. Corporation assumes responsibility losses incurred customer third parties arising from these circuits, software, information. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance.
Other recent searches
XP04501 - XP04501 XP04501 Datasheet
XP4501 - XP4501 XP4501 Datasheet
ISD-9200 - ISD-9200 ISD-9200 Datasheet
EVM1D - EVM1D EVM1D Datasheet
EVM1E - EVM1E EVM1E Datasheet
EVM1U - EVM1U EVM1U Datasheet
CER0247B - CER0247B CER0247B Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
