µPD78363A,78365A,78366A,78368A 16/8-BIT SINGLE-CHIP MICROCONTROLL

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µPD78363A,78365A,78366A,78368A 16/8-BIT SINGLE-CHIP MICROCONTROLL

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INTEGRATED CIRCUIT
µPD78363A,78365A,78366A,78368A
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD78366A provided with high-speed, high-performance powerful operation functions. Unlike
existing µPD78328, µPD78366A also provided with high-resolution signal output function which substantially contributes improving performance inverter control. PROM model, µPD78P368A, also available. Detailed functions, etc. described following user's manual. sure read manual design systems.
µPD78366A User's Manual Hardware: U10205E µPD78356 User's Manual
U12117E
FEATURES
Internal 16-bit architecture, external 8-bit data High-speed processing pipeline control method high- speed operating clock
Minimum instruction execution time: (internal clock: MHz, external clock: MHz)
Real-time pulse unit inverter control 10-bit resolution converter: channels 8-/9-/10-/12-bit resolution variable signal output function: channels Powerful serial interface: channels Internal memory: ROM: none (µPD78365A) bytes (µPD78363A) bytes (µPD78366A) bytes (µPD78368A) RAM: bytes (µPD78363A) bytes (µPD78365A, 78366A, 78368A)
APPLICATION EXAMPLES
Inverter conditioner Factory automation fields, such industrial robots machine tools.
ORDERING INFORMATION
Part Number Package 80-pin plastic 80-pin plastic 80-pin plastic 80-pin plastic Internal Mask None Mask Mask
µPD78365AGF-3B9
Remark
indicates code suffix.
Unless otherwise specified, functions performances µPD78366 described throughout this document.
information this document subject change without notice. Document U11109EJ2V0DS00 (2nd edition) Date Published September 1997 Printed Japan
mark
shows major revised points.
1995 1995
µPD78363A, 78365A, 78366A, 78368A
78K/III Series Product Development
µPD78372 subseries
(for control application automotive appliance)
µPD78366A subseries
Reinforced timer, added
Pulse output function inverter control, expanded ROM,
µPD78361A µPD78362A µPD78P364A
µPD78363A µPD78365A µPD78366A µPD78368A µPD78P368A
(for inverter)
µPD78356 subseries
(for camera, HDD)
µPD78352A subseries
(for HDD)
A/D, relative instruction added, expanded ROM,
High-performance CPU, sum-of-products instruction added
Reinforced timer A/D, expanded
PD78334 subseries
(for control application fields)
µPD78322 subseries
High-speed, multi-function, reinforced interrupt, 10-bit
Pulse output function inverter control
µPD78328 subseries
(for inverter)
(for control application fields)
PD78312A subseries
(for control application fields)
µPD78363A, 78365A, 78366A, 78368A
CONFIGURATION (TOP VIEW)
80-pin plastic
78365AGF-3B9,
P85/TO05
P84/TO04
P83/TO03
P82/TO02
P81/TO01
P80/TO00
P57/A15
P56/A14
P55/A13
P54/A12
ASTB
P00/RTP0 P01/RTP1 P02/RTP2 P03/RTP3 P04/PWM0 P05/TCUD/PWM1 P06/TIUD/TO40 P07/TCLRUD WDTO MODE1 RESET P30/TXD0 P31/RXD0 P32/SO/SB0 P33/SI/SB1 P34/SCK P35/TX P36/RX P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0
P20/NMI
P24/INTP3/TI
P21/INTP0
P22/INTP1
P23/INTP2
Caution Connect directly VSS. Remark indicates code suffix
P25/INTP4
MODE0
P53/A11
P91/WR
P90/RD
µPD78363A, 78365A, 78366A, 78368A
P00-P07 P10-P17 P20-P25 P30-P36 P40-P47 P50-P57 P70-P77 P80-P85 P90-P93 RTP0-RTP3 INTP0-INTP4 TIUD TCUD TCLRUD ANI0-ANI7 TXD0, TXD1 RXD0, RXD1 SB0, PWM0, PWM1 WDTO MODE0, MODE1 AD0-AD7 A8-A15 ASTB RESET Port0 Port1 Port2 Port3 Port4 Port5 Port7 Port8 Port9 Real-time Port Nonmaskable Interrupt Interrupt From Peripherals Timer Input Timer Input Down Counter Timer Control Down Counter Timer Clear Down Counter Analog Input Transmit Data Receive Data Serial Input Serial Output Serial Serial Clock Pulse Width Modulation Output Watchdog Timer Ouput Mode Address/Data Address Address Strobe Read Strobe Write Strobe Reset Crystal Analog Analog Analog Reference Voltage Power Supply Ground Internally Connected
TO00-TO05, TO04 Timer Output
µPD78363A, 78365A, 78366A, 78368A
FUNCTIONAL OUTLINE
Item Product name
µPD78363A
µPD78365A
µPD78366A
µPD78368A
Minimum instruction execution time Internal memory Memory space General-purpose registers Number basic instructions Instruction
(internal clock: MHz, external clock: MHz)
bytes bytes
None bytes
bytes
bytes
bytes (externally expandable) bits banks Input 16-bit transfer/operation Multiplication/division bits bits, bits bits) manipulation String Sum-of-products operation bits bits bits) Relative operation
lines
which shared with analog input)
Real-time pulse unit
16-bit timer 10-bit dead time timer 16-bit compare register kinds output mode selected Mode set-reset output: channels Mode buffer output: channels 16-bit timer 16-bit compare register 16-bit timer 16-bit capture register 16-bit capture/compare register 16-bit timer 16-bit capture register 16-bit capture/compare register 16-bit timer 16-bit compare register 16-bit resolution output: channel Pulse outputs associated with real-time pulse unit: lines 8-/9-/10-/12-bit resolution variable output: channels 10-bit resolution, channels Dedicated baud rate generator UART (w/pin selection function): Clocked serial interface/SBI:
Real-time output port unit converter Serial interface
channel channel
Interrupt function
External: internal: which multiplexed with external) priority levels specified through software types interrupt processing modes selectable (vectored interrupt, macro service, context switching) 80-pin plastic Watchdog timer Standby function (HALT STOP modes)
Package Others
µPD78363A, 78365A, 78366A, 78368A
DIFFERENCES BETWEEN µPD78363A, 78365A, 78366A, 78368A
Item Product name Internal Input lines Port (P40-P47) input output mode units bits. external memory expansion mode, this port functions multiplexed address/data (AD0-AD7). input output mode 1-bit units. external memory expansion mode, this port functions address (A8-A15). input output mode 1-bit units. external memory expansion mode, outputs strobe signal, outputs strobe signal. Sets port input output mode units bits. external memory expansion mode, sets memory expansion width ports Sets port input output mode 1-bit units. ordinary operation mode: MODE0, ROM-less mode: MODE0, Always functions multiplexed address/ data (AD0-AD7). bytes bytes which multiplexed with analog input)
µPD78363A
bytes
µPD78366A
bytes
µPD78368A
bytes None
µPD78365A
Always functions address (A8-A15)
Port (P50-P57)
Port (P90-P93)
always functions strobe signal output pin, always functions strobe signal output pin. function port lines. Always fixed external memory expansion mode.
Memory expansion mode register (MM)
Port mode register (PM5) Setting MODE0, MODE1
None
Always follows: MODE0,
BLOCK DIAGRAM
INTP PROGRAMMABLE INTERRUPT CONTROLLER MAIN GENERAL REGISTERS DATA MEMORY
ROM/RAM
RESET ASTB
SYSTEM CONTROL CONTROL PREFETCH CONTROL
MODE1 MODE0 A8-A15 AD0-AD7
TIUD TCUD TCLRUD
TIMER/COUNTER UNIT (REAL-TIME PULSE UNIT)
MICRO SEQUENCE CONTROL MICRO
PERIPHERAL 1792
µPD78363A, 78365A, 78366A, 78368A
SO/SB0 SI/B1 SERIAL INTERFACE (SBI) (UART)
CONVERTER
WATCHDOG TIMER
PORT
INTP2
WDTO
REAL-TIME OUTPUT PORT
Remark internal capacities differ depending product.
µPD78363A, 78365A, 78366A, 78368A
CONTENTS FUNCTIONS
PORT PINS PINS OTHER THAN PORT PINS CIRCUITS PROCESSING UNUSED PINS
ARCHITECTURE
MEMORY SPACE DATA MEMORY ADDRESSING PROCESSOR REGISTERS 2.3.1 2.3.2 2.3.3 Control Registers General-Purpose Registers Special Function Registers (SFR)
FUNCTIONAL BLOCKS.
EXECUTION UNIT (EXU) CONTROL UNIT (BCU) ROM/RAM PORT FUNCTIONS CLOCK GENERATOR CIRCUIT REAL-TIME PULSE UNIT (RPU) REAL-TIME OUTPUT PORT (RTP) CONVERTER SERIAL INTERFACE
3.10 UNIT 3.11 WATCHDOG TIMER (WDT)
INTERRUPT FUNCTIONS
OUTLINE MACRO SERVICE CONTEXT SWITCHING 4.3.1 4.3.2 4.3.3 Context Switching Function Interrupt Request Context Switching Function BRKCS Instruction Restoration from Context Switching
EXTERNAL DEVICE EXPANSION FUNCTION STANDBY FUNCTIONS RESET FUNCTION INSTRUCTION EXAMPLE SYSTEM CONFIGURATION
ELECTRICAL SPECIFICATIONS
µPD78363A, 78365A, 78366A, 78368A
PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS APPENDIX DIFFERENCES BETWEEN µPD78366A µPD78328 APPENDIX TOOLS
DEVELOPMENT TOOLS EMBEDDED SOFTWARE
µPD78363A, 78365A, 78366A, 78368A
FUNCTIONS
PORT PINS
Function Port 8-bit port. input output mode 1-bit units. Shared RTP0-RTP3 PWM0 TCUD/PWM1 TIUD/TO40 TCLRUD Port 8-bit port. input output mode 1-bit units. Port 6-bit input port. INTP0 INTP1 Input INTP2 INTP3/TI INTP4 Port 7-bit port. input output mode 1-bit units. TXD0 RXD0 SO/SB0 SI/SB1 TXD1 RXD1 Port 8-bit Port. input output mode 8-bit units. Port 8-bit port. input output mode 1-bit units. Port 8-bit input port Port 6-bit port. input output mode 1-bit units. AD0-AD7
name P00-P03 P10-P17 P40-P47
P50-P57
A8-A15
P70-P77
Input
ANI0-ANI7
P80-P85
TO00-TO05
Port 4-bit port. input output mode 1-bit units.
µPD78363A, 78365A, 78366A, 78368A
PINS OTHER THAN PORT PINS (1/2)
Output Function Real-time output port that outputs pulses synchronization with trigger signal from real-time pulse unit. Non-maskable interrupt request input. External interrupt request input. Input Shared P00-P03 P24/TI External count clock input timer Input Count operation selection control signal input up/down counter (timer External count clock input up/down counter (timer Clear signal input up/down counter (timer Output Input Output Pulse output from real-time pulse unit. Analog input converter. Serial data output asynchronous serial interface. P05/PWM1 P06/TO40 P80-P85 P06/TIUD P70-P77 Input Input Ouput PWM0 Output PWM1 WDTO AD0-AD7 A8-A15 ASTB Output Read strobe signal output external memory. Write strobe signal output external memory. Output signal output. Signal output indicating overflow watchdog timer (generates nonmaskable interrupt). Multiplexed address/data when memory externally expanded. Address when memory externally expanded. Outputs timing signal which address information output from AD0-AD7 A8-A15 pins access external memory latched. Serial data input asynchronous serial interface. Serial clock input/output clocked serial interface. Serial data input clocked serial interface 3-line mode. Serial data output clocked serial interface 3-line mode. Serial data input/output clocked serial interface mode. P33/SB1 P32/SB0 P32/SO P33/SI P05/TCUD P40-P47 P50-P57 P24/INTP3
name RTP0-RTP3 INTP0 INTP1 INTP2 INTP3 INTP4 TCUD TIUD TCLRUD TO00-TO05 TO40 ANI0-ANI7 TXD0 TXD1 RXD0 RXD1
µPD78363A, 78365A, 78366A, 78368A
PINS OTHER THAN PORT PINS (2/2)
Input MODE1 RESET AVREF AVDD AVSS Input Input Input Function Control signal input operation mode. With µPD78363A, 78366A, 78368A MODE0 MODE1 usually connected VSS. With µPD78365A, MODE0 MODE1 always connected System reset input Crystal oscillator connecting pins system clock. clock externally supplied, input Leave open. converter reference voltage input. converter analog power supply. converter GND. Positive power supply Internally connected. Connect this VSS. Shared
name MODE0
µPD78363A, 78365A, 78366A, 78368A
CIRCUITS PROCESSING UNUSED PINS
Table shows circuit types respective pins, recommended connections unused pins. Figure shows circuits respective pins.
Table 1-1. Circuit Type Recommended Connections Unused Pins
P00/RTP0-P03/RTP3 P04/PWM0 P05/TCUD/PWM1 P06/TIUD/TO40 P07/TCLRUD P10-P17 P20/NMI P21/INTP0 P22/INTP1 Connect P23/INTP2 P24/INTP3/TI P25/INTP4 P30/TXD0 P31/RXD0 P32/SO/SB0 P33/SI/SB1 P34/SCK P35/TXD1 P36/RXD1 P40/AD0-P47/AD7 P50/A8-P57/A15 P70/ANI0-P77/ANI7 P80/TO00-P85/TO05 P90/RD P91/WR P92, ASTB WDTO MODE0, MODE1 RESET AVREF, AVSS AVDD Connect Connect Connect Connect Input Independently connect through resistor Output Leave unconnected Connect Input Independently connect through resistor Output Leave unconnected Input Independently connect through resistor Output Leave unconnected circuit type Recommended connections
µPD78363A, 78365A, 78366A, 78368A
Figure 1-1. Circuits
Type
P-ch N-ch Data Output disable Input enable
Type
Pull-up enable P-ch
P-ch
IN/OUT N-ch
Type
Type
Pull-up enable Data P-ch
P-ch
Schmitt trigger input with hysteresis characteristics
Output disable
IN/OUT N-ch
Type
Type
Comparator P-ch Pull-up enable P-ch N-ch Vref (Threshold voltage)
Input enable
Schmitt trigger input with hysteresis characteristics
Type
Data Output disable P-ch N-ch IN/OUT
Type
N-ch
Intput enable
µPD78363A, 78365A, 78366A, 78368A
ARCHITECTURE
MEMORY SPACE
µPD78366A access memory space bytes. Figures through show memory map.
Figure 2-1. Memory (µPD78368A)
MODE0, FFFFH MODE0, ROM-less mode
FF00H FEFFH
Special function register (SFR) (256
FEFFH FE80H FE25H FE06H
General-purpose register (128 Macro service control
Main (256 FF00H Data memory FDFFH Peripheral (1792 F700H F6FFH Memory space Program memory Data memory External memory Note (14080
F700H
Data area (768
BFFFH Program area 1000H 0FFFH 0800H 07FFH 0080H 007FH CALLT instruction table area Program memory Data memory Internal (49152 0040H 003FH Vector table area 0000H 0000H 0000H 0FFFH CALLF instruction entry area (2048 Program area External memory (63232
C000H BFFFH
Note Accessed external memory expansion mode. Caution word access (including stack operations) main area (FE00H-FEFFH), address that specifies operand must even value.
µPD78363A, 78365A, 78366A, 78368A
Figure 2-2. Memory (µPD78365A, 78366A)
MODE0, PD78366A) FFFFH Special function register (SFR) (256 MODE0, PD78365A PD78366A ORM-less mode
FF00H FEFFH
FEFFH FE80H FE25H FE06H
General-purpose register (128 Macro service control
Main (256 FF00H Data memory FDFFH Peripheral (1792 F700H F6FFH Memory space Program memory Data memory External memory Note (30464
F700H
Data area (2048
7FFFH Program area 1000H 0FFFH 0800H 07FFH 0080H 007FH CALLT instruction table area Program memory Data memory Internal (32768 0040H 003FH Vector table area 0000H 0000H 0000H 0FFFH CALLF instruction entry area (2048 Program area External memory (63232
8000H 7FFFH
Note Accessed external memory expansion mode. Caution word access (including stack operations) main area (FE00H-FEFFH), address that specifies operand must even value.
µPD78363A, 78365A, 78366A, 78368A
Figure 2-3. Memory (µPD78363A)
MODE0, FFFFH MODE0, ROM-less mode
FF00H FEFFH
Special function register (SFR) (256
FEFFH FE80H FE25H FE06H
General-purpose register (128 Macro service control
Main (256 FF00H Data memory FDFFH Peripheral (512 FC00H FBFFH Memory space Program memory Data memory External memory Note (39936
FC00H
Data area (768
5FFFH Program area 1000H 0FFFH 0800H 07FFH 0080H 007FH CALLT instruction table area Program memory Data memory Internal (24576 0040H 003FH Vector table area 0000H 0000H 0000H 0FFFH CALLF instruction entry area (2048 Program area External memory (64512
6000H 5FFFH
Note Accessed external memory expansion mode. Caution word access (including stack operations) main area (FE00H-FEFFH), address that specifies operand must even value.
µPD78363A, 78365A, 78366A, 78368A
DATA MEMORY ADDRESSING
µPD78366A provided with many addressing modes that improve operability memory used with high-level languages. Especially, area addresses F700H-FFFFH µPD78363A, FC00H-FFFFH) which data memory mapped addressed mode peculiar functions provided this area, including special function registers (SFR) general-purpose registers.
Figure 2-4. Data Memory Addressing (µPD78368A)
FFFFH Special function register (SFR)
FF20H FF1FH FF00H FEFFH
addressing
General-purpose register FE80H FE7FH FE20H FE1FH Main FE00H FDFFH Peripheral F700H F6FFH External memory 6C00H BFFFH Internal Note
Register addressing
Short direct addressing
Direct addressing Register indirect addressing Based addressing Based indexed addressing Based indexed addressing (with displacement)
0000H
Note external memory ROMless mode. Caution word access (including stack oprations) main area (FE00H-FEFFH), address that specifies operand must even value.
µPD78363A, 78365A, 78366A, 78368A
Figure 2-5. Data Memory Addressing (µPD78365A, 78366A)
FFFFH Special function register (SFR)
FF20H FF1FH FF00H FEFFH
addressing
General-purpose register FE80H FE7FH FE20H FE1FH Main FE00H FDFFH Peripheral F700H F6FFH External memory 8000H 7FFFH Internal Note
Register addressing
Short direct addressing
Direct addressing Register indirect addressing Based addressing Based indexed addressing Based indexed addressing (with displacement)
0000H
Note external memory ROMless mode µPD78365A µPD78366A. Caution word access (including stack oprations) main area (FE00H-FEFFH), address that specifies operand must even value.
µPD78363A, 78365A, 78366A, 78368A
Figure 2-6. Data Memory Addressing (µPD78363A)
FFFFH Special function register (SFR)
FF20H FF1FH FF00H FEFFH
addressing
General-purpose register FE80H FE7FH FE20H FE1FH Main FE00H FDFFH Peripheral FC00H FBFFH External memory 6000H 5FFFH Internal Note
Register addressing
Short direct addressing
Direct addressing Register indirect addressing Based addressing Based indexed addressing Based indexed addressing (with displacement)
0000H
Note external memory ROMless mode. Caution word access (including stack oprations) main area (FE00H-FEFFH), address that specifies operand must even value. PROCESSOR REGISTERS Control registers General-purpose registers Special function registers (SFRs)
µPD78366A provided with following three types processor registers:
µPD78363A, 78365A, 78366A, 78368A
2.3.1 Control Registers This 16-bit register that holds address instruction executed next. Program status word (PSW) This 16-bit register indicates status result instruction execution. Stack pointer (SP) This 16-bit register indicates first address stack area (LIFO) memory. control word (CCW) This 8-bit register used control CPU.
Program counter (PC)
Figure 2-7. Configuration Control Registers
Figure 2-8. Configuration
RBS2 RBS1 RBS0
User flag Sign flag (MSB execution result) Zero flag Register select flag Auxiliary carry flag Interrupt request enable flag Parity/overflow flag Carry flag
RBS0-RBS2: Register bank select flag
Figure 2-9. Configuration
Table position flag
µPD78363A, 78365A, 78366A, 78368A
2.3.2 General-Purpose Registers
µPD78366A provided with eight banks general-purpose registers with bank consisting words bits. Figure 2-10 shows configuration general-purpose register banks. generalpurpose registers mapped area addresses FE80H-FEFFH. Each these registers used 8-bit register. addition, registers used 16-bit register pair (refer Figure 2-11 These general-purpose registers facilitate complicated multitask processing.
Figure 2-10. Configuration General-Purpose Register Banks
Bank
Bank Bank
Figure 2-11. Processing Bits General-Purpose Registers
8-bit processing FEFFH RBNK0 RBNK1 RBNK2 RBNK3 RBNK4 RBNK5 RBNK6 FE80H RBNK7 16-bit processing
(FH) (DH) (BH) (9H) (7H) (5H) (3H) (1H)
(EH) (CH) (AH) (8H) (6H) (4H) (2H) (0H)
µPD78363A, 78365A, 78366A, 78368A
2.3.3 Special Function Registers (SFR)
Special function registers (SFRs) registers assigned special functions such mode registers control registers internal peripheral hardware, mapped 256-byte address space FF00H through FFFFH. Table lists SFRs. meanings symbols this table follows: Symbol Indicates mnemonic symbol SFR. This mnemonic coded operand field instruction. Indicates whether read written. Read/write Read only Write only
units manipulation Indicates units which manipulated. SFRs that manipulated 16-bit units coded sfrp operand. Specify even address these SFRs. SFRs that manipulated 1-bit units coded operand manipulation instructions. reset Indicates status register RESET input. Cautions access addresses range FF00H through FFFFH which special function register allocated. these addresses accessed, malfunctioning occur. write data read-only registers. Otherwise, internal circuit operate normally. When using read data byte data, process undefined bit(s) first. TOUT write-only registers. read these registers. Bits SBIC write-only bits. When these bits read, they always "0".
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List Special Function Registers (1/5)
units manipulation FF00H FF01H FF02H FF03H FF04H FF05H FF07H FF08H FF09H FF10H Compare register FF11H FF12H Compare register FF13H FF14H Compare register FF15H FF16H Compare register FF17H FF18H Buffer register CM00 FF19H FF1AH Buffer register CM01 FF1BH FF1CH Buffer register CM02 FF1DH FF1EH Timer register FF1FH FF20H FF21H FF23H FF25H FF28H FF29H FF2CH Reload register FF2DH FF2EH FF2FH FF30H Compare register FF31H FF32H Timer register FF33H 0000H CM10 Timer unit mode register Timer unit mode register TUM0 TUM1 Undefined DTIME Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register PM5Note 1111B 1111B 1111B Undefined 0000H BFCM02 BFCM01 BFCM00 CM03 CM02 CM01 Undefined CM00 Port Port Port Port Port Port Port Port Port P4Note P5Note bits bits
Address
Special function register (SFR)
Symbol
reset
Note provided µPD78365A.
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List Special Function Registers (2/5)
units manipulation FF34H Capture/compare register FF35H Undefined FF36H Capture register FF37H FF38H Timer register FF39H FF3AH Buffer register CM03 FF3BH FF3CH FF3DH FF40H FF43H FF44H FF45H FF48H FF4EH FF4FH FF50H Capture/compare register FF51H FF52H Capture register FF53H FF54H Capture register FF55H FF56H Timer register FF57H FF58H Compare register FF59H FF5AH Compare register FF5BH FF5CH Timer register FF5DH FF5EH FF5FH FF60H FF61H FF62H FF68H Timer control register Timer register Real-time output port register Real-time output port mode register Port read control register converter mode register TMC4 TOUT RTPM PRDC 0101B Undefined 0000H CM41 Undefined CM40 0000H CT31 CT30 Undefined CC30 External interrupt mode register External interrupt mode register Port mode control register Port mode control register Pull-up resistor option register Pull-up resistor option register Port mode control register Sampling control register Sampling control register INTM0 INTM1 PMC0 PMC3 PUOL PUOH PMC8 SMPC0 SMPC1 0000B 0000B BFCM03 Underfined 0000H CT20 CC20 bits bits
Address
Special function register (SFR)
Symbol
reset
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List Special Function Registers (3/5)
units manipulation FF70H FF71H FF72H FF73H FF74H FF75H FF76H FF77H FF78H FF79H FF7AH FF7BH FF7CH FF7DH FF7EH FF7FH FF80H FF82H FF84H FF85H FF86H FF88H FF8AH FF8CH FF8EH FFA0H FFA1H FFA2H FFA2H register FFA3H PWM0 Slave buffer register Slave buffer register Slave buffer register Slave buffer register Slave buffer register Slave buffer register Master buffer register Master buffer register Master buffer register Master buffer register Master buffer register Master buffer register Timer control register Timer control register Timer control register Timer control register Clocked serial interface mode register Serial interface control register Baud rate generator control register Baud rate generator compare register Serial shift register Asynchronous serial interface mode register Asynchronous serial interface status register Serial receive buffer: UART Serial transfer shift register: UART control register control register register SBUF0 SBUF1 SBUF2 SBUF3 SBUF4 SBUF5 MBUF0 MBUF1 MBUF2 MBUF3 MBUF4 MBUF5 TMC0 TMC1 TMC2 TMC3 CSIM SBIC BRGC ASIM ASIS PWMC0 PWMC1 PWM0L R/WNote bits bits Undefined Undefined Undefined Undefined
Address
Special function register (SFR)
Symbol
reset
Note Bits
read/write
Bits read-only Bits write-only
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List Special Function Registers (4/5)
units manipulation FFA4H FFA4H register FFA5H FFA8H FFAAH FFACH FFACH Interrupt mask register FFADH FFADH FFB0H conversion result register FFB1H FFB1H FFB2H conversion result register FFB3H FFB3H FFB4H conversion result register FFB5H FFB5H FFB6H conversion result register FFB7H FFB7H FFB8H conversion result register FFB9H FFB9H FFBAH conversion result register FFBBH FFBBH FFBCH conversion result register FFBDH FFBDH FFBEH conversion result register FFBFH FFBFH FFC0H FFC1H FFC2H conversion result register Standby control register control word Watchdog timer mode register ADCR7H STBCNote WDMNote 0000 ADCR7 conversion result register ADCR6H ADCR6 conversion result register ADCR5H ADCR5 conversion result register ADCR4H ADCR4 conversion result register ADCR3H Undefined ADCR3 conversion result register ADCR2H ADCR2 conversion result register ADCR1H ADCR1 conversion result register ADCR0H ADCR0 Interrupt mask register MK0H In-service priority register Interrupt mode control register Interrupt mask register ISPR MK0L FFFFH PWM1 register PWM1L bits bits Undefined
Address
Special function register (SFR)
Symbol
reset
Note written when special instruction executed.
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List Special Function Registers (5/5)
units manipulation FFC4H FFC6H Programmable wait control register FFC7H FFD0H FFDFH FFE0H FFE1H FFE2H FFE3H FFE4H FFE5H FFE6H FFE7H FFE8H FFE9H FFEAH FFEBH FFECH FFEDH FFEEH FFEFH Interrupt control register (INTOV3) Interrupt control register (INTP0/INTCC30) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3/INTCC20) Interrupt control register (INTP4) Interrupt control register (INTTM0) Interrupt control register (INTCM03) Interrupt control register (INTCM10) Interrupt control register (INTCM40) Interrupt control register (INTCM41) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTAD) OVIC3 PIC0 PIC1 PIC2 PIC3 PIC4 TMIC0 CMIC03 CMIC10 CMIC40 CMIC41 SERIC SRIC STIC CSIIC ADIC External area Undefined Memory expansion mode register bits bits Note C0AAH
Address
Special function register (SFR)
Symbol
reset
Note value register reset time differs depending product.
µPD78363A µPD78368A
µPD78365A, 78366A
µPD78363A, 78365A, 78366A, 78368A
FUNCTIONAL BLOCKS
EXECUTION UNIT (EXU)
controls address computation, arithmetic logical operations, data transfer through microprogram. internal main RAM. This accessed instructions faster than peripheral RAM. CONTROL UNIT (BCU)
starts necessary cycles according physical address obtained execution unit (EXU).If does request start cycle, address generated prefetch instruction. prefetched code stored instruction queue. ROM/RAM
internal capacities differ depending product. µPD78363A 24-KB 512-B peripheral RAM. µPD78366A 32-KB 1792-B peripheral RAM. µPD78368A 48-KB 1792-B peripheral RAM. µPD78365A does have only 1792-B peripheral RAM. Access disabled using MODE0 MODE1 pins, which case external memory accessed.
µPD78363A, 78365A, 78366A, 78368A
PORT FUNCTIONS
µPD78366A provided with ports shown Figure various control operations. functions each port listed Table 3-1. These ports function only digital ports also input/output lines internal hardware.
Figure 3-1. Port Configuration
Port
Port
Port
P70-P77
Port
Port Port Port Port
Port
P40-P47
µPD78363A, 78365A, 78366A, 78368A
Table 3-1. Functions Each Port
Port Port function 8-bit port. input output mode 1-bit units. Multiplexed function control mode, serves real-time output port (RTP), input operation control signal real-time pulse unit (RPU) output signal. Inputs external interrupt count pulse real-time pulse unit (RPU) (fixed control mode). control mode, inputs/outputs signals serial interfaces (UART, CSI). Address data (AD0-AD7) when memory externally expanded. Address (A8-A15) when memory externally expanded.
Port
Port
8-bit port. input output mode 1-bit units. 6-bit input port.
Port
Port
7-bit port. input output 1-bit units. 8-bit port. input output mode 8-bit units. 8-bit port. input output mode 1-bit units. 8-bit input port.
Port
Port Port
Input analog signals converter (fixed control mode). control mode, outputs timer real-time pulse unit (RPU).
Port
6-bit port. input output mode 1-bit units. 4-bit port. input output mode 1-bit units.
Port
Outputs control signal when memory externally expanded.
µPD78363A, 78365A, 78366A, 78368A
CLOCK GENERATOR CIRCUIT
clock generator circuit generates controls internal system clock (CLK) that supplied CPU.
Figure 3-2. Block Diagram Clock Generator Circuit
Frequency divider control circuit Frequency divider Internal system clock (CLK)
System cloock oscillator circuit
STOP mode
Remarks
crystal oscillation frequency external clock frequency fCLK internal system clock frequency
connecting 8-MHz crystal resonator across pins, internal system clock (fCLK) generated. system clock oscillation circuit oscillates using crystal resonator connected across pins. stops oscillation standby mode. external clock also input. input clock signal leave open. Caution STOP mode when external clock used.
µPD78363A, 78365A, 78366A, 78368A
Figure 3-3. External Circuit System Clock Oscillator Circuit
crystal oscillator
PD78366A
external clock
PD78366A
Open
Cautions Wire portion enclosed dotted line Figure follows avoid adverse influences wiring capacity when using system clock oscillation circuit. Keep wiring length short possible. cross wiring with other signal line. Make sure that wiring close lines through which high alternating current flows. Always keep ground point capacitor oscillation circuit same potential VSS. ground circuit ground pattern through which high current flows. extract signals from oscillator circuit. input external clock, connect load such wiring capacitance pin.
µPD78363A, 78365A, 78366A, 78368A
REAL-TIME PULSE UNIT (RPU)
real-time pulse unit (RPU) measure pulse intervals frequencies, output programmable pulses (six channels control signals). consists five 16-bit timers (timers through which provided with 10-bit dead time timer, which ideal inverter control. addition, function turn output software external interrupt also provided. Each timer following features:
Timer Controls period TO00 through TO05 pins. addition, operates
general-purpose interval timer. Timer following five operation modes: General-purpose interval timer mode mode (symmetrical triangular wave) mode (asymmetrical triangular wave) mode (saw-tooth wave) mode
Timer Operates general-purpose interval timer. Timers programmable input sampling circuit that rejects noise input signal,
capture function.
Timer Operates general-purpose timer up-down counter. When operating generalpurpose timer, controls cycle TO40 output pin. Timer following operation modes: General-purpose timer mode Up/down counter mode (UDC mode)
µPD78363A, 78365A, 78366A, 78368A
consists hardware shown Table 3-2. Figures through 3-12 show block diagrams respective timers.
Table 3-2. Configuration Real-Time Pulse Unit (RPU)
Timer register Register 16-bit compare register (CM00) Timer 16-bit timer (TM0) 16-bit compare register (CM01) 16-bit compare register (CM02) 16-bit compare register (CM03) Timer 16-bit timer (TM1) Timer 16-bit timer (TM2) 16-bit compare register (CM10) 16-bit capture/compare register (CC20) 16-bit capture register (CT20) 16-bit capture/compare register (CC30) Timer 16-bit timer (TM3) 16-bit capture register (CT30) 16-bit capture register (CT31) Timer 16-bit timer (TM4) 16-bit compare register (CM40) 16-bit compare register (CM41) Compare register coincidence interrupt INTCM03 INTCM10 INTCC20 INTCC30 INTCM40 INTCM41 INTP3 INTP0 INTP1 INTP4 TCLRUD INTCM40 INTCC30 INTCC20 INTCM10 Capture trigger Timer output Timer clear
INTCM03
µPD78363A, 78365A, 78366A, 78368A
Figure 3-4. Block Diagram Timer (PWM mode symmetrical triangular wave, asymmetrical triangular wave)
BFCM03 CM03 INTTM0 DOWN INTCM03
fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16
fCLK
DTIME
ALVTO Output function external interrupt software Underflow TO00 phase) TO01 phase)
BFCM00 CM00
DTM0
BFCM01 CM01 DTM1 Underflow
TO02 phase) TO03 phase)
BFCM02 CM02 DTM2 Underflow
TO04 phase) TO05 phase)
CM00-CM03 DTIME DTM0-DTM2
Timer register Compare registers Reload register Dead time timers
ALVTO: TUM0 register TMC0 register
BFCM00-BFCM03 Buffer registers
Remark internal system clock
µPD78363A, 78365A, 78366A, 78368A
Figure 3-5. Block Diagram Timer (PWM mode saw-tooth wave)
BFCM03 CM03 fCLK CM00 DTM0 Underflow BFCM01 CM01 DTM1 Underflow BFCM02 CM02 DTM2 Underflow TO04 phase) TO05 phase) TO02 phase) TO03 phase) TO00 phase) TO01 phase) Output function external interrupt software DTIME ALVTO Clear INTCM03
fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16
BFCM00
CM00-CM03 DTIME DTM0-DTM2 ALVTO
Timer register Compare registers Reload register Dead time timers TUM0 register
BFCM00-BFCM03 Buffer registers
Remark internal system clock
µPD78363A, 78365A, 78366A, 78368A
Figure 3-6. Block Diagram Timer (PWM mode
BFCM03 CM03 fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16 fCLK BFCM00 CM00 DTM0 6-bit buffer register Underflow SBUF1 MBUF0 SBUF0 MBUF3 SBUF3 MBUF2 BFCM01 CM01 DTM1 Underflow SBUF2 MBUF5 SBUF5 MBUF4 SBUF4 6-bit buffer register MBUF1 DTIME Clear INTCM03
BFCM02 CM02 DTM2
Underflow TOUT 6-bit write-only register Output function external interrupt software
TO00 TO02 TO04 phase) phase) phase) TO01 TO03 TO05 phase) phase) phase)
CM00-CM03 DTIME DTM0-DTM2
Timer register Compare registers Reload register Dead time timers
MBUF0-MBUF5 Master buffer registers SBUF0-SBUF5 Slave buffer registers TOUT Timer register
BFCM00-BFCM03 Buffer registers
Remark internal system clock
µPD78363A, 78365A, 78366A, 78368A
Figure 3-7. Block Diagram Timer (general-purpose interval timer mode)
Master buffer register (MBUF0) Compare register CM03 INTCM03
Slave buffer register (SBUF0)
Timer register
Clear
Timer register (TOUT)
Output function external interrupt software TO00 TO02 TO04 TO01 TO03 TO05
Figure 3-8. Block Diagram Timer
Clear
fCLK/4 fCLK/8 fCLK/16
Timer register Compare register CM10 INTCM10
Remark fCLK: internal system clock
µPD78363A, 78365A, 78366A, 78368A
Figure 3-9. Block Diagram Timer
Clear fCLK/22 fCLK/23 fCLK/24 fCLK/25 fCLK/26 fCLK/28 fCLK/29 fCLK/210 4-point sampling noise rejection circuit fCLK fCLK/22 fCLK/23 fCLK/24 fCLK/26 fCLK/27 fCLK/28 CLR2
Timer register
Capture/compare register CC20
INTP3
INTP3/INTCC20
Capture register CT20
Remark fCLK: internal system clock
Figure 3-10. Block Diagram Timer
Clear fCLK/22 fCLK/23 fCLK/24 fCLK/25 fCLK/26 fCLK/28 CLR3
Timer register
INTOV3
4-point sampling noise rejection circuit fCLK fCLK/22 fCLK/23 fCLK/24 INTP1 4-point sampling noise rejection circuit fCLK fCLK/22 fCLK/23 fCLK/24 INTP4 4-point sampling noise rejection circuit fCLK fCLK/22 fCLK/23 fCLK/24 Capture register CT31 INTP4 Capture register CT30 INTP1 Capture/compare register CC30
INTP0
INTP0/INTCC30
Remark fCLK: internal system clock
µPD78363A, 78365A, 78366A, 78368A
Figure 3-11. Block Diagram Timer (General-Purpose Timer Mode)
Clear fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16 fCLK/32
Timer register INTCM40 Compare register CM40 ALV40 Compare register CM41 TO40
INTCM41
Remark fCLK: internal system clock
Figure 3-12. Block Diagram Timer (UDC Mode)
Clear TCLRUD
fCLK/4 fCLK/8 fCLK/16
Timer register Pre-set
TIUD TCUD
Up/down detector
Compare register CM40
INTCM40
Compare register CM41
INTCM41
Remark fCLK: internal system clock
µPD78363A, 78365A, 78366A, 78368A
REAL-TIME OUTPUT PORT (RTP)
real-time output port 4-bit port that output contents real-time output port register (RTP) synchronization with trigger signal from real-time pulse unit (RPU). output synchronization pulses multiple channels. Also, modulation applied P00-P03.
Figure 3-13. Block Diagram Real-Time Output Port
Internal
INTCM03 (from RPU) INTCM10 (from RPU) INTP0/INTCC30 (from RPU) Software trigger
Output trigger control circuit
RTPM
PWM0 PWM1
signal control circuit
Output latch (P03-P00)
P03P02 P01P00
µPD78363A, 78365A, 78366A, 78368A
CONVERTER
µPD78366A contains high-speed, high-resolution 10-bit analog-to-digital (A/D) converter (conversion time 12.6 internal clock frequency MHz). Successive approximation type adopted. This converter provided with eight analog input lines (ANI0-ANI7) perform various operations application requires, select, scan, mixed modes. When conversion ends, internal interrupt (INTAD) occurs. This interrupt start macro service that executes automatic data transfer through hardware.
Figure 3-14. Block Diagram Converter
ANI0 ANI1
Input curcuit
Sample hold Resistor string
ANI2 ANI3 ANI4 ANI5
Comparator (10) ADCR0 ADCR1
ANI6 ANI7
INTCM03 INTP2 (Start trigger)
Controller
ADCR2 ADCR3 ADCR4 ADCR5
ADCR6 ADCR7 Internal
µPD78363A, 78365A, 78366A, 78368A
SERIAL INTERFACE
µPD78366A provided with following independent serial interfaces:
Asynchronous serial interface (UART) (with selection function) Clocked serial interface
3-line serial mode Serial interface mode (SBI mode) Since µPD78366A contains baud rate generator (BRG), serial transfer rate regardless operating clock frequency. baud rate generator block generate shift clock transmit/ receive serial interface, used commonly with channels serial interfaces. serial transfer rate selected range 38.4 Kbps mode register.
Figure 3-15. Block Diagram Asynchronous Serial Interface
Internal
ASIM Receive buffer ASIS
Selector
RXD0 RXD1 TXD0 TXD1
Receive shift register
Transfer shift register
Selector
Receive control parity check
INTSER INTSR
Transfer control parity append
INTST
Selector
Transfer/ receive baud rate generator output fCLK/8
µPD78363A, 78365A, 78366A, 78368A
Figure 3-16. Block Diagram Clocked Serial Interface
Internal CSIM CTXE CRXE MOD2 MOD1 MOD0 CLS1 CLS0 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT CMDT
Selector
MOD1 MOD2 SI/SB1
Shift register (SIO)
latch
SO/SB0
Busy/ acknowledge detector circuit
MOD1 MOD2
Selector
MOD1 release/ command/ acknowledge detector circuit
Interrupt signal generation control circuit
Selector
Serial clock counter
INTCSI
Serial clock control circuit CLS0 CLS1
Baud rate generator (BRG) CLK/8 CLK/32
Figure 3-17. Block Diagram Baud Rate Generator
Internal
BRGC
Coincidence
Clear TMBRG Prescaler CLK/2
Serial interface
µPD78363A, 78365A, 78366A, 78368A
3.10 UNIT
µPD78366A provided with lines that output 8-/9-/10-/12-bit resolution variable signals. output used digital-to-analog conversion output connecting external lowpass filter, ideal controlling actuators such motors. output between 62.5 obtaind, depending combination count clock (62.5 counter length internal clock frequency MHz).
Figure 3-18. Block Diagram Unit
CLK/2 CLK/4 CLK/8 CLK/16 Coincidence
Overflow Counter (12) PWMn ALVn
Comparator (12)
0-11
Compare register CMPn (12)
buffer register (12)
Remark
µPD78363A, 78365A, 78366A, 78368A
3.11 WATCHDOG TIMER (WDT)
watchdog timer free running timer equipped with non-maskable interrupt function prevent program hang-up deadlock. When error program detected, overflow interrupt (INTWDT) watchdog timer occurs watchdog timer output (WDTO) goes low. connecting this output RESET pin, malfunctioning application system program error prevented.
Figure 3-19. Block Diagram Watchdog Timer
CLK/29 CLK/211 CLK/213 Clear STOP INTWDT Watchdog timer bits) Overflow Clear Timer bits) Overflow WDTO
Oscillation stabilization time control circuit
µPD78363A, 78365A, 78366A, 78368A
INTERRUPT FUNCTIONS
OUTLINE
µPD78366A provided with powerful interrupt functions that process interrupt requests from internal hardware peripherals external sources. addition, following three interrupt processing modes available. addition, four levels interrupt priority specified. Vectored interrupt processing Macro service Context switching
Table 4-1. Interrupt Sources
Interrupt source Type
Note
Name Trigger input Watchdog timer Overflow timer INTWDT INTOV3
Source unit
Vector table address 0002H
Macro service
Context switching
Nonmaskable
External External/RPU
None 0004H 0006H 0008H 000AH External INTP2 INTP2 input External/RPU External 000CH 000EH 0010H 0012H 0014H Provided INTCM10 INTCM40 INTCM41 INTSER INTSR INTST INTCSI INTAD BRKCS TRAP RESET CM10 coincidence signal CM40 coincidence signal CM41 coincidence signal Receive error UART UART reception UART transfer transfer/reception conversion instruction BRKCS instruction Illegal code trap Reset input UART 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 003EH None 003CH
None
INTP0/INTCC30 INTP0 input/CC30 coincidence signal INTP1 INTP1 input
INTP3/INTCC20 INTP3 input/CC20 coincidence signal INTP4 INTTM0 INTCM03 INTP4 input Underflow timer CM03 coincidence signal
Maskable
Provided
None Provided
Software Exception Reset
None 0000H
Note Default priority Priority that takes precedence when more maskable interrupts occur same time. highest priority, lowest.
µPD78363A, 78365A, 78366A, 78368A
MACRO SERVICE
µPD78366A total five macro services. Each macro service described below. Counter mode: EVTCNT Operation Increments decrements 8-bit macro service counter (MSC). vector interrupt request generated when reaches
+1/-1
Application example: event counter, measure number times value captured Block transfer mode: BLKTRS Operation Transfers data block between buffer specified pointer (SFRP). transfer source destination buffer area. length transfer data specified byte word. number times data transferred (block size) specified MSC. auto decremented each time macro service been executed. When reaches vector interrupt request generated.
SFRP
Buffer
Buffer
Internal
Application example: transfer/receive data through serial interface
µPD78363A, 78365A, 78366A, 78368A
Block transfer mode (with memory pointer): BLKTRS-P Operation This block transfer mode above with memory pointer (MEMP). appended buffer area MEMP freely memory space. Remark Each time macro service executed, MEMP auto incremented byte data transfer word data transfer).
SFRP MEMP
Buffer
+1/+2
Buffer
Internal
Application example: Same Data differential mode: DTADIF Operation Calculates difference between contents (current value) specified SFRP contents saved last data buffer (LDB). Stores result calculation predetermined buffer area. Stores contents current value LDB. number times data transferred (block size) specified MSC. Each time macro service executed, auto decremented one. When reaches vector interrupt request generated. Remark differential calculation carried only with 16-bit SFRs.
SFRP Buffer
Buffer
Differential calculation
Internal
Application example measure cycle pulse width capture register real-time pulse unit (RPU)
µPD78363A, 78365A, 78366A, 78368A
Data differential mode (with memory pointer): DTADIF-P Operation This data differential mode above with memory pointer (MEMP). appending MEMP, buffer area which differential data stored freely memory space. Remarks differential calculation carried only with 16-bit SFRs. buffer specified result operation MEMP MSCNote. MEMP updated after data been transferred. Note MEMP (MSC
SFRP Buffer MEMP Buffer Differential calculation
Internal
Application example: Same
µPD78363A, 78365A, 78366A, 78368A
CONTEXT SWITCHING
This function select specific register bank through hardware, branch execution vector address predetermined register bank. same time, saves present contents register bank when interrupt occurs, when BRKCS instruction executed. 4.3.1 Context Switching Function Interrupt Request
When context switching enable flag corresponding each maskable interrupt request (interrupt enable) status, context switching function started. context switching operation interrupt request performed follows: When interrupt request generated, register bank which context switched specified contents low-order bits address (even address) corresponding vector table. predetermined vector address transferred register bank which context switched, contents immediately before switching takes place saved register bank. Execution branches address indicated contents newly set.
Figure 4-1. Operation Context Switching
Register Bank Exchange Save
Register Bank (0-7)
µPD78363A, 78365A, 78366A, 78368A
4.3.2 Context Switching Function BRKCS Instruction
context switching function started BRKCS instruction. operation context switching interrupt request follows: 8-bit register specified operand BRKCS instruction, register bank which context switched specified contents this register (only low-order bits bits valid). vector address predetermined register bank which context switched transferred same time, contents immediately before switching takes place saved register bank. Execution branches contents newly set. 4.3.3 Restoration from Context Switching
restore from switched context, following instructions used. Which instruction executed determined source that started context switching.
Table 4-2. Instructions Restore from Context Switching
Restore instruction RETCS RETCSB Context switching starting source Occurrence interrupt Execution BRKCS instruction
µPD78363A, 78365A, 78366A, 78368A
EXTERNAL DEVICE EXPANSION FUNCTION
µPD78366A connect external devices (data memory, program memory, peripheral devices) addition internal areas. connect external device, address/data read/ write strobe signals controlled using ports
Table 5-1. Function with External Device Connected
function with external device connected Function P40-P47 P50-P57 ASTB Multiplexed address/data Address Read strobe Write strobe Address strobe Name AD0-AD7 A8-A15 ASTB
µPD78363A, 78365A, 78366A, 78368A
STANDBY FUNCTIONS
µPD78366A provided with standby functions reduce power consumption system. standby functions effected following modes: HALT mode this mode, operating clock stopped. using this mode combination with ordinary operation mode, µPD78366A operates intermittently reduce total power consumption system. STOP mode this mode, oscillator stopped, therefore entire system stopped. Therefore, power consumption minimized with only leakage current flowing. Each mode through software. Figure shows transition status standby modes (STOP HALT modes).
Figure 6-1. Transition Standby Status
Ordinary
STOP
HALT
µPD78363A, 78365A, 78366A, 78368A
RESET FUNCTION
When level input RESET pin, system reset, each hardware enters initial status (reset status). When RESET goes high, reset status released, program execution started. Initialize contents each register through program necessary. Especially, change number cycles programmable wait control register necessary. RESET equipped with noise rejecter circuit analog delay prevent malfunctioning noise. Cautions While RESET active (low level), pins into high-impedance state (except WDTO, AVREF, AVDD, AVSS, VDD, VSS, pins). When external connected, connect pull-up resistor P90/RD P91/WR pins, because P90/RD P91/WR pins into high-impedance state, resulting destruction contents external RAM. addition, signal contention occurs address/data bus, resulting damage input/output circuit.
Figure 7-1. Accepting Reset Signal
RESET input
Analog delay
Analog delay
Analog delay
Rejected noise
Reset accepted
Reset released
effect reset when power applied, make sure that sufficient time elapses stabilize oscillation after power applied until reset signal accepted, shown Figure 7-2.
Figure 7-2. Reset Power Application
RESET Oscillation stabilization time
Analog delay Reset released
µPD78363A, 78365A, 78366A, 78368A
INSTRUCTION
Write operand operand field each instruction according description instruction (for details, refer Assembler Specifications). Some instructions have more operands. Select them. Uppercase characters, keywords must written Write appropriate numeric value label immediate data. write label, sure write
Table 8-1. Operand Representation Description
Representation sfrp
Description R10, R11, R12, R13, R14, RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP0, RP1, RP2, RP3, RP4, RP5, RP6, Special function register symbol (Refer Table 2-1.) Special function register symbol (register that manipulated 16-bit units. Refer Table 2-1.) RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, (More than symbol written. However, written only PUSH instructions, written only PUSHU POPU instructions.) [DE], [HL], [DE+], [HL+], [DE-], [HL-], [VP], [UP] DE], byte], byte], byte], byte], byte] word[A], word[B], word[DE], word[HL] register indirect mode based indexed mode based mode indexed mode
post
saddr saddrp addr16 addr16
FE20H-FF1FH immediate data label FE20H-FF1EH immediate data (however, bit0 label (manipulated 16-bit units) 0000H-FDFFH immediate data label; relative addressing 0000H-FDFFH immediate data label; immediate addressing (However, FFFFH written instruction. Only FE00H-FEFFH written MOVTBLW instruction.) 800H-FFFH immediate data label 40H-7EH immediate data (however, bit0 0)Note label 16-bit immediate data label 8-bit immediate data label 3-bit immediate data label 3-bit immediate data (0-7)
addr11 addr5 word byte
Note access bit0 (odd address) word units. Remarks same terms register name that written different code generated. rp1, post written absolute name (R0-R15, RP0-RP7) function name UP). Immediate addressing address entire space. Relative addressing address only range -128 +127 from first address next instruction.
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation #byte saddr, #byte sfrNote saddr saddr, saddr, saddr sfr, mem, #byte byte (saddr) byte byte (saddr) (saddr) (saddr) (saddr) (mem) (mem) ((saddrp)) ((saddrp)) (addr16) (addr16) PSWL byte PSWH byte PSWL PSWH (mem) (saddr) ((saddrp)) (saddr) (saddr)
8-bit data transfer
[saddrp] [saddrp], !addr16 !addri16, PSWL, #byte PSWH, #byte PSWL, PSWH, PSWL PSWH saddr [saddrp] saddr, saddr
Note When STBC written sfr, this instruction treated dedicated instruction whose number bytes different from that this instruction. Remark symbols flag, refer table below. Symbol (Blank) change Cleared Set/cleared according result flag functions parity flag flag operates overflow flag Value previously saved restored Remarks
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation rp1, #word saddrp, #word sfrp, #word saddrp saddrp, word (saddrp) word sfrp word (saddrp) (saddrp) (saddrp) (saddrp) sfrp sfrp (addr16) (addr16) (mem) (mem) (saddrp) sfrp (saddrp) (saddrp) (mem) byte (saddr), (saddr) byte sfr, byte (saddr) (saddr), (saddr) (saddr) (mem) (mem), (mem) byte (saddr), (saddr) byte sfr, byte (saddr) (saddr), (saddr) (saddr) (mem) (mem), (mem)
16-bit data transfer
MOVW
saddrp, saddrp sfrp sfrp, rp1, !addr16 !addr16, mem, saddrp sfrp
XCHW
saddrp, saddrp #byte saddr, #byte sfr, #byte
saddr
8-bit operation
saddr, saddr mem, #byte saddr, #byte sfr, #byte ADDC saddr saddr, saddr mem,
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation #byte saddr, #byte sfr, #byte saddr saddr, saddr mem, #byte saddr, #byte sfr, #byte byte (saddr), (saddr) byte sfr, byte (saddr) (saddr), (saddr) (saddr) (mem) (mem), (mem) byte (saddr), (saddr) byte sfr, byte (saddr) (saddr), (saddr) (saddr) (mem) (mem), (mem) byte (saddr) (saddr) byte byte (saddr) (saddr) (saddr) (saddr) (mem) (mem) (mem)
8-bit operation
SUBC saddr saddr, saddr mem, #byte saddr, #byte sfr, #byte saddr saddr, saddr mem,
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation #byte saddr, #byte sfr, #byte saddr saddr, saddr mem, #byte saddr, #byte sfr, #byte byte (saddr) (saddr) byte byte (saddr) (saddr) (saddr) (saddr) (mem) (mem) (mem) byte (saddr) (saddr) byte byte (saddr) (saddr) (saddr) (saddr) (mem) (mem) (mem) byte (saddr) byte byte (saddr) (saddr) (saddr) (mem) (mem)
8-bit operation
saddr saddr, saddr mem, #byte saddr, #byte sfr, #byte saddr saddr, saddr mem,
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation #word saddrp, #word sfrp, #word ADDW saddrp sfrp saddrp, saddrp #word word (saddrp), (saddrp) word sfrp, sfrp word (saddrp) sfrp (saddrp), (saddrp) (saddrp) word (saddrp), (saddrp) word sfrp, sfrp word (saddrp) sfrp (saddrp), (saddrp) (saddrp) word (saddrp) word sfrp word (saddrp) sfrp (saddrp) (saddrp) (quotient), (remainder) (high-order bits), (low-order bits) AXDE (quotient), (remainder) AXDE (high-order bits), (low-order bits) AXDE AXDE AXDE AXDE overflow (P/V then AXDE 7FFFFFFFH underflow (P/V then AXDE 80000000H (DE) (HL)
16-bit operation
saddrp, #word sfrp, #word SUBW saddrp sfrp saddrp, saddrp #word saddrp, #word sfrp, #word CMPW saddrp sfrp saddrp, saddrp
Multiplication /division
MULU DIVUW MULUW DIVUX MULW
Sum-of- Signed products multiplioperation cation
MACW
Sum-of-products operation with saturation
MACSW
Relative operation
SACW
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation MOVTBLW !addr16, saddr saddr INCW saddrp DECW RORC ROLC saddrp rp1, (addr16 (addr16), addr16 addr16 (saddr) (saddr) (saddr) (saddr) (saddrp) (saddrp) (saddrp) (saddrp) (CY, r1m-1 times (CY, r1m+1 r1m) times r10, r1m-1 r1m) times r17, r1m+1 times r10, r1m-1 r1m) times r17, r1m+1 times rp10, rp115 rp1m-1 rp1m) times rp115 rp10 rp1m+1 rp1m times A3-0 (rp1)3-0, (rp1)7-4 A3-0, (rp1)3-0 (rp1)7-4 A3-0 (rp1)7-4, (rp1)3-0 A3-0, (rp1)7-4 (rp1)3-0
Table shift
Increment/decrement Shift rotate
SHRW
SHLW
rp1,
ROR4
[rp1]
ROL4
[rp1]
adjustment
ADJBA ADJBS Decimal Adjust Accumelator
Data conversion
CVTBW
When When
Remarks
shift rotate instruction indicates number times shift rotate instruction executed. address table shift instruction ranges from FE00H FEFFH.
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation saddr.bit sfr.bit A.bit X.bit PSWH.bit PSWL.bit MOV1 saddr.bit, sfr.bit, A.bit, X.bit, PSWH.bit, PSWL.bit, saddr.bit /saddr.bit sfr.bit /sfr.bit (saddr.bit) sfr.bit A.bit X.bit PSWH.bit L.bit (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) (saddr.bit) sfr.bit sfr.bit A.bit A.bit X.bit X.bit PSWH.bit PSWH.bit PSWL.bit PSWL.bit (saddr.bit) (saddr.bit) sfr.bit sfr.bit A.bit A.bit X.bit X.bit PSWH.bit PSWH.bit PSWL.bit PSWL.bit
manipulation
A.bit /A.bit AND1 X.bit /X.bit PSWH.bit /PSWH.bit PSWL.bit /PSWL.bit saddr.bit /saddr.bit sfr.bit /sfr.bit A.bit /A.bit X.bit /X.bit PSWH.bit /PSWH.bit PSWL.bit /PSWL.bit
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation saddr.bit sfr.bit A.bit XOR1 X.bit PSWH.bit PSWL.bit saddr.bit sfr.bit A.bit SET1 X.bit PSWH.bit (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) (saddr.bit) sfr.bit sfr.bit A.bit A.bit X.bit X.bit PSWH.bit PSWH.bit PSWL.bit PSWL.bit
manipulation
PSWL.bit saddr.bit sfr.bit A.bit CLR1 X.bit PSWH.bit PSWL.bit saddr.bit sfr.bit A.bit NOT1 X.bit PSWH.bit PSWL.bit SET1 CLR1 NOT1
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation CALL !addr16 3)H, 3)L, addr16, 2)L, PC15 00001, PC10 addr11, 1)H, 1)L, (TPF, 00000000, addr5 (TPF, 00000000, addr5 2)H, 2)L, 2)H, 2)L, (rp1 (rp1), PSWH, 1)H, 1)L, (003EH), (003FH), (SP), (SP), PSWL PSWH (SP), PSWL PSWH sfrH sfrL {(SP postH, post times PSWH, PSWL, {(UP postH, post times sfrL (SP) sfrH {postL (SP), postH times PSWL (SP), PSWH {postL (UP),postH times word
CALLF
!addr11
CALLT
[addr5]
Call/return CALL [rp1]
RETB
RETI
sfrp PUSH post PUSHU Stack manipulation post
sfrp
post
POPU
post #word
MOVW
INCW DECW
Remark stack manipulation instruction number registers written post.
µPD78363A, 78365A, 78366A, 78368A
Unconditional Special Instructions branch
Flag Mnemonic Operand Byte Operation CHKL CHKLA !addr16 [rp1] $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 X.bit, $addr16 PSWH.bit, $addr16 PSWL.bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 X.bit, $addr16 PSWH.bit, $addr16 PSWL.bit, $addr16 (pin level) (signal level before output buffer) (pin level) (signal level before output buffer) addr16 rp1H, rp1L (rp1 (rp1) jdisp8 jdisp8
jdisp8
jdisp8
jdisp8
jdisp8
jdisp8 jdisp8 jdisp8 jdisp8 (P/V jdisp8 jdisp8 jdisp8 (P/V jdisp8 jdisp8 jdisp8 (saddr.bit) jdisp8 sfr.bit jdisp8 A.bit jdisp8 X.bit jdisp8 PSWH.bit jdisp8 PSWL.bit jdisp8 (saddr.bit) jdisp8 sfr.bit jdisp8 A.bit jdisp8 X.bit jdisp8 PSWH.bit jdisp8 PSWL.bit
Conditional branch
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation saddr.bit, $addr16 jdisp8 (saddr.bit) then reset (saddr.bit) jdisp8 sfr.bit then reset sfr.bit jdisp8 A.bit then reset A.bit jdisp8 X.bit then reset X.bit jdisp8 PSWH.bit then reset PSWH.bit jdisp8 PSWL.bit then reset PSWL.bit jdisp8 (saddr.bit) then (saddr.bit) jdisp8 sfr.bit then sfr.bit jdisp8 A.bit then A.bit jdisp8 X.bit then X.bit jdisp8 PSWH.bit then H.bit jdisp8 PSWL.bit then PSWL.bit then jdisp8 (saddr) (saddr) then jdisp8 (saddr) PSWH, PSWL, RBS2 addr16 PSWH PSWL addr16 PSWH PSWL
sfr.bit, $addr16
A.bit, $addr16 BTCLR X.bit, $addr16
PSWH.bit, $addr16
PSWL.bit, $addr16 Conditional branch
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16 BFSET X.bit, $addr16
PSWH.bit, $addr16
PSWL.bit, $addr16
$addr16 DBNZ saddr, $addr16 Context switching
BRKCS
RETCS
!addr16
RETCSB
!addr16
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation [DE+], MOVM [DE-], (DE+) (DE-) (DE+) (HL+), (DE-) (HL-), (DE+) (DE-) (DE+) (HL+), (DE-) (HL-), (DE+) (DE-) (DE+) (HL+), (DE-) (HL-), (DE+) (DE-) (DE+) (HL+), (DE-) (HL-), (DE+) (DE-) (DE+) (HL+), (DE-) (HL-),
[DE+], [HL+] MOVBK [DE-], [HL-]
[DE+], XCHM [DE-],
[DE+], [HL+] XCHBK [DE-], [HL-]
[DE+], CMPME String [DE-],
[DE+], [HL+] CMPBKE [DE-], [HL-]
[DE+], CMPMNE [DE-],
[DE+], [HL+] CMPBKNE [DE-], [HL-]
[DE+], CMPMC [DE-],
[DE+], [HL+] CMPBKC [DE-], [HL-]
µPD78363A, 78365A, 78366A, 78368A
Instructions
Flag Mnemonic Operand Byte Operation [DE+], CMPMNC (DE+) (DE-) (DE+) (HL+), (DE-) (HL-), STBC byteNote byteNote RBS2 RBS2 Operation (Enable Interruptt) (Disable Interrupt)
String
[DE-],
[DE+], [HL+] CMPBKNC [DE-], [HL-] STBC, #byte WDM, #byte control SWRS RBn,
Note code STBC register register manipulation instructions wrong, code trap interrupt occurs. Operation trap: PSWH, PSWL, 4)H, 4)L, (003CH), (003DH),
µPD78363A, 78365A, 78366A, 78368A
EXAMPLE SYSTEM CONFIGURATION
Controlling outdoor apparatus inverter conditioner
PD78366A
Real-time pulse unit CM03 Dead time setting register 16-bit timer
CM00
TO00 TO01 Inverter
CM01
Pulse generation circuit
TO02 TO03
CM02 (Analog signal)
power supply monitor External temperature Thermal exchange temperature Outlet temperature Inlet temperature
TO04 TO05
ANI0 ANI1 ANI2 ANI3 ANI4
bytes 10-bit converter bytes Generalpurpose port
4-way valve 2-way valve Outdoor motor
monitor Compressor motor temperature monitor
INTP1
Programmable interrupt controller
Real-time output port
Stepping motor (electronic expansion valve)
Indoor apparatus controller
Serial interface
µPD78363A, 78365A, 78366A, 78368A
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Parameter Power supply voltage Symbol Input voltage Pins other than P70/ANI0-P77/ANI7 Test conditions Rating -0.5 +7.0 -0.5 -0.5 +0.5 -0.5 Unit
Output voltage Low-level output current
Note Output pins other than those note Total output pins
-0.5
-3.0 +150
High-level output current
output pins Total output pins
Analog input voltage converter reference input voltage Operating ambient temperature Storage temperature
P70/ANI0-P77/ANI7 pins
Note P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40, P07/TCLRUD, P10-P17, P80/TO00-P85/TO05 pins. Caution Product quality suffer absolute rating exceeded parameter, even momentarily. other words, absolute maxumum rating value which possibility psysical damage product cannnot ruled out. Care must therefore taken ensure that these ratings exceeded during product.
Recommended Operating Conditions
Oscillation frequency +5.0
Capacitance
Parameter Input capacitance Output capacitance capacitance Symbol except measured pins Test conditions MIN. TYP. MAX. Unit
µPD78363A, 78365A, 78366A, 78368A
Oscillator Characteristics
Resonator Ceramic resonator crystal resonator Recommended circuit Parameter Oscillation frequency MIN. MAX. Unit
External clock Leave unconnected HCMOS inverter
input frequency
rise/fall time
input high-/low-level width
Caution When using system clock oscillation circuits, reduce effect wiring capacitouce, etc, wire area indicated dotted-line follows: Make wiring short possible. allow wiring intersect other signal lines. Keep away from other lines which varying high currents flow. Make sure that ground point oscillation circuit capacitor always same electric potential VSS. allow wiring grounded ground pattern which very high currents flowing. extract signals from oscillation circuit.
µPD78363A, 78365A, 78366A, 78368A
Characteristics
Parameter Low-level input voltage Symbol High-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current supply current Data retention voltage Data retention current DDDR DDDR Note Note Note Note Note Note Note -400 Operating mode HALT mode STOP mode STOP mode DDDR DDDR Pull-up resistance Test conditions MIN. 0.8V 0.45 TYP. MAX. 0.2V Unit
Notes Pins other than those specified Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3/TI, P25/INTP4, P32/ SO/SB0, P33/SI/SB1 P34/SCK pins. Pins other than those specified Notes P80/TO00-P85/TO05 pins (When operation, three pins simultaneously.) P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40 P07/TCLRUD pins (When operation, four pins simultaneously.) well P10-P17 pins (When operation, four pins simultaneously.). Caution When P80-P85, P00-P07, P10-P17 pins used under conditions specified Notes they have same characteristics Note
µPD78363A, 78365A, 78366A, 78368A
Characteristics MHz)
Read/Write Operation (when general-purpose memory connected)
Parameter System clock cycle time Address setup time (vs. ASTB Address hold time (vs. ASTB address float time Address data input time data input time ASTB delay time Data hold time (vs. address active time low-level width ASTB high-level width data output time ASTB delay time ASTB delay time Data setup time (vs. Data hold time (vs. low-level width Symbol SAST HSTA DAID DRID DSTR HRID tWRL WSTH DWOD DSTW DWST SODW HWOD Test conditions MIN. 62.5 MAX. 166.7 Unit
CYK-dependent Timing Definition
Parameter SAST HSTA WSTH DSTR DAID DRID DSTW DWST DWOD SODW Arithmetic expression (0.5 0.5T (0.5 0.5T (1.5 (2.5 (1.5 0.5T 0.5T 1.5T (1.5 0.5T MIN./MAX. MIN. MIN. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MAX. MIN. Unit
Remarks refers internal system clock frequency.) becomes when address wait inserted. Otherwise, becomes refers number wait cycles that inserted specifying register. Only timings indicated this table depend CYK.
µPD78363A, 78365A, 78366A, 78368A
Serial Operation
Parameter Serial clock cycle time Symbol CYSK output input Serial clock low-level width Serial clock high-level width setup time (vs. hold time (vs. delay time SRXSK HSKRX DSKTX WSKH WSKL output input output input Test conditions Internal dividing External clock Internal dividing External clock Internal dividing External clock MIN. MAX. Unit
Up/Down Counter Operation
Parameter TIUD high-/low-level width TCUD high-/low-level width TCLRUD high-/low-level width WCLUH, tWCLUL TCUD setup time (vs. TIUD TCUD hold time (vs. TIUD TIUD setup time (vs. TCUD) TIUD hold time (vs. TCUD) TIUD TCUD cycle time STCU HTCU S4TIU H4TIU CYC4 Mode Mode Mode Mode Other than mode Mode Symbol tWTIUH, WTIUL Test conditions Other than mode Mode WTCUH, WTCUL Other than mode Mode MIN. MAX. Unit
Remark tCYK 1/fCLK (fCLK refers internal system clock frequency.)
µPD78363A, 78365A, 78366A, 78368A
Other Operations
Parameter Symbol Test conditions MIN. INTP1 high-/low-level width WI1H, WI1L INTP2 high-/low-level width INTP3(TI) high-/lowlevel width WI3H, WI3L WI2H, WI2L 128T 256T INTP4 high-/low-level width WI4H, WI4L 16.0 32.0 64.0 MAX. Unit
high-/low-level width WNIH, WNIL RESET high-/low-level width WRSH, WRSL INTP0 high-/low-level width WI0H, WI0L
Remarks refers internal system clock frequency.) refers input sampling frequency. INTP0-INTP4 selected programmable.
µPD78363A, 78365A, 78366A, 78368A
Converter Characteristics
Parameter Resolution Total error Note Quantization error Conversion time CONV 62.5 166.6 Sampling time SAMP 62.5 166.6 Zero-scale error Note Full-scale error Note Nonlinearity error Note Analog input voltage Note When sampling When sampling Reference voltage REF1 current supply current converter data retention current DDDR Operating mode STOP mode DDDR DDDR -0.3 Note ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±2.5 ±4.5 ±2.5 ±4.5 ±2.5 ±4.5 AVREF Symbol Test conditions MIN. ±0.4 ±0.7 ±1/2 TYP. MAX. Unit %FSR %FSR
Analog input impedance
Notes quantization error excluded. When -0.3 conversion result becomes 000H. When conversion performed with 10-bit resolution. When +0.3 conversion result becomes 3FFH. analog input impedance time sampling same equivalent circuit shown below. (The values diagram TYP. values; they guaranteed values)
Analog input (Input capacitance included)
µPD78363A, 78365A, 78366A, 78368A
Cautions When using P70/ANI0-P77/ANI7 pins both digital analog inputs, previously described characteristics guaranteed. Therefore, ensure that eight P70/ANI0-P77/ANI7 pins used either analog input digital input. When using P70/ANI0-P77/ANI7 pins digital input, make sure that AVDD Timing Test Point
Test point
µPD78363A, 78365A, 78366A, 78368A
Read Operation
tCYK (CLK)
A8-A15 (Output) tSAST AD0-AD7 (Input/output) Hi-Z tDAID
High-order address
High-order address
Low-order address (Output) tWSTH
Hi-Z
Data (Input)
Hi-Z
Low-order address (Output)
Hi-Z
tHRID
ASTB (Output) tHSTA tFRA (Output) tDSTR tDRID tWRL tDRA
Write Operation
(CLK)
A8-A15 (Output) tSAST AD0-AD7 (Output) Low-order address (Output) tWSTH ASTB (Output) tHSTA (Output) tDSTW
High-order address
High-order address
Undefined
Data (Output) tHWOD
Low-order address (Output)
tDWST
tDWOD tWWL
tSODW
µPD78363A, 78365A, 78366A, 78368A
Serial Operation
tCYSK tWSKL tDSKTX tWSKH
tSRXSK tHSKRX
Up/Down Counter (Timer Input Timing
tWTIUH
TIUD
tSTCU tHTCU tWTCUL TCUD tWTCUH
tWTIUL
tWCLUH
TCLRUD
tWCLUL
TIUD tS4TIU tH4TIU tS4TIU tH4TIU
TCUD
µPD78363A, 78365A, 78366A, 78368A
Interrupt Input Timing
tWNIH tWNIL
tWInH
tWInL
INTPn
Remark Reset Input Timing
tWRSH tWRSL
RESET
µPD78363A, 78365A, 78366A, 78368A
PACKAGE DRAWING
PLASTIC
detail lead
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
P80GF-80-3B9-2 ITEM MILLIMETERS 23.6 20.0 14.0 17.6 0.35 0.10 0.15 (T.P.) 0.15+0.10 -0.05 0.15 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.106 0.004 0.004 0.119 MAX.
+0.008
5°±5°
µPD78363A, 78365A, 78366A, 78368A
RECOMMENDED SOLDERING CONDITIONS
These products should soldered mounted under conditions recommended below. details recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, please contact your sales representative.
Table 12-1. Surface Mount Type Soldering Conditions
80-Pin Plastic PD78365AGF-3B9
80-Pin Plastic
80-Pin Plastic 80-Pin Plastic
Recommended condition symbol IR35-00-3
Soldering method Infrared reflow
Soldering conditions Package peak temperature: Duration: sec. max. (210 above) Number times: max. Package peak temperature: Duration: sec. max. (200 above) Number times: max. Solder bath temperature: less, Time: sec. max., Number times: Pre-heating temperature: max. (Package surface temperature) temperature: less Duration: sec. max. (per side device)
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
Caution more than soldering method should avoided (except case partial heating).
µPD78363A, 78365A, 78366A, 78368A
APPENDIX DIFFERENCES BETWEEN µPD78366A µPD78328
Product name Item Minimum instruction execution time Internal memory Memory space General-purpose registers Number basic instructions Instruction bytes bytes bytes (can externally expanded) bits banks
µPD78366A
internal clock external clock bytes bytes
µPD78328
internal clock MHz, external clock
16-bit transfer/operation Multiplication/division bits bits, bits bits) manipulation String
Sum-of-products operation bits bits bits) Relative operation lines Input Real-time pulse unit which multiplexed with analog input) 16-bit timer 16-bit compare register 16-bit capture register 16-bit capture/compare register output modes selectable Mode set-reset output channels Mode buffer output channels
which multiplexed with analog input) 16-bit timer 16-bit compare register 16-bit capture/compare register output modes selectable Mode set-reset output channels toggle output channel Mode buffer output channels
16-bit resolution output: channel Real-time output port unit converter Serial interface (buffer output 4-bit units) 8-/9-/10-/12-bit resolution variable output: channels 10-bit resolution, channels Dedicated baud rate generator UART (with selection function) channel Clocked serial interface/SBI channel External: internal: multiplexed with external) programmable priority levels Dedicated baud rate generator UART channel Clocked serial interface/SBI channel External: internal: programmable priority levels (buffer output 4-/8-bit units) 8-bit resolution output: channel
Interrupt function
Three processing selectable (vectored interrupt/macro service/context switching) Test source control circuit Package Others None Provided (external internal: MHz) 80-pin plastic Watchdog timer Standby functions (HALT mode, STOP mode) Internal: None 64-pin plastic shrink 64-pin plastic
µPD78363A, 78365A, 78366A, 78368A
APPENDIX TOOLS
DEVELOPMENT TOOLS following development tools available support system development using µPD78366A Language Processor
78K/III series relocatable assembler (RA78K3) relocatable assembler, that used commonly 78K/III series products. Since this assembler provided with macro functions, enhances developmnt efficency. structured assembler, that explicitly describe program control structure, also supplied, that program productivity maintainability improved.
Host machine
Supply media 3.5"
Order code (product name)
µS5A13RA78K3 µS5A10RA78K3 µS7B13RA78K3 µS7B10RA78K3 µS3P16RA78K3 µS3K15RA78K3 µS3R15RA78K3
PC-9800 series
MS-DOS5"
PC/ATand compatible model HP9000 series 700SPARC stationNEWS78K/III series compiler (CC78K3)
DOS
3.5"
HP-UXSunOSNEWS-OS
Cartridge tape (QIC-24)
This compiler that commonly used 78K/III series. This program converts program written language object codes microcomputer execute. When using this compiler, 78K/III series relocatable assembler (RA78K3) necessary. Host machine Order code (product name)
Supply media 3.5"
µS5A13CC78K3 µS5A10CC78K3 µS7B13CC78K3 µS7B10CC78K3 µS3P16CC78K3 µS3K15CC78K3 µS3R15CC78K3
PC-9800 series
MS-DOS
PC/AT compatible model HP9000 series SPARC station NEWS
3.5"
HP-UX SunOS NEWS-OS
Cartridge tape (QIC-24)
Remark operations relocatable assembler compiler guaranteed only specified host machine described above.
µPD78363A, 78365A, 78366A, 78368A
PROM Writing Tools
PG-1500 This PROM programmer that program PROM-contained single-chip microcontrollers standalone mode under control host machine when accessory board optional programmer adapter connected. also program representative PROMs from 256K-bit 4M-bit models. PROM programmer adapters that writes program µPD78P368A general-purpose PROM programmer such PG-1500. PA-78P368GF µPD78P368AGF PA-78P368KL µPD78P368AKL Connects PG-1500 host machine with serial intrface parallel interface control PG-1500 from host machine.
Hardware
PA-78P368GF PA-78P368KL
PG-1500 controller
Host machine Software
Supply media 3.5"
Order code (part number)
µS5A13PG1500 µS5A10PG1500 µS7B13PG1500 µS7B10PG1500
PC-9800 series
MS-DOS
PC/AT compatible machines
3.5" 3.5"
Remark operation PG-1500 controller guaranteed only above host machine Debugging Tools (When Controller Used)
IE-78350-R Hardware In-circuit emulator that used develop debug application systems. Connected host machine debugging. emulation board that emulates peripheral functions target device such ports.
IE-78365-R-EM1
EP-78365GF-R
Emulation probe that connects IE-78350-R target system. conversion socket, EV-9200G-80 EV-9200G-80, used connect target system supplied accessory. Program that controls IE-78350-R host machine. automatically execute commands, enhancing debugging efficiency. Host machine Order code (part number)
IE-78350-R control program controller)
Supply media 3.5"
Software
µS5A13IE78365A µS5A10IE78365A µS7B13IE78365A µS7B10IE78365A
PC-9800 series
MS-DOS
PC/AT compatible machines
3.5" 3.5"
Remark operation controller guaranteed only above host machine
µPD78363A, 78365A, 78366A, 78368A
Development Tool Configuration (When Using Controller)
Host machine PC-9800 series series
RS-232-C
IE-78350-R in-circuit emulator IE-78365-R-EM1 emulation board (optional)
Emulation probe
Software
RS-232C PROM programmer
EP-78365GF-R
Relocatable assembler
compiler
PG-1500 controller
Conversion socket connecting emulation probe target systemNote PG-1500
controller EV-9200G-80 Built-in PROM models
PD78P368AGF PD78P368AKL
Programmer adapter
Target system
PA-78P368GF
PA-78P368KL
Note socket provided with emulation probe. Remarks Host machine PG-1500 directly connected RS-232-C. 3.5-inch represents supply media software this figure.
µPD78363A, 78365A, 78366A, 78368A
Debugging Tools (When Integrated Debugger Used)
IE-784000-R IE-78350-R-EM-A IE-78365-R-EM1 Hardware EP-78365GF-R EV-9200G-80 IE-70000-98-IF-B IE-70000-98N-IF In-circuit emulation that used develop debug application system. Connected host machine debugging. Emulation board that emulates peripheral functions target device such ports. emulation board that emulates peripheral functions target device such ports. Emulation probe connecting IE-784000-R target system. conversion socket, EV9200G-80, used connect target system supplied accessory. Interface adapter connect PC-9800 series (except notebook type personal computer) host machine.
Interface adapter cable connect PC-9800 series notebook type personal computer host machine. IE-70000-PC-IF-B Interface adapter cable connect host machine. IE-78000-R-SV3 Interface board connect host machine. Integrated debugger Program controlling in-circuit emulator 78K/III series. Used combination with device file (DF78365). debug program coded language, structured assembly (ID78K3) language, assembly language source program level. also split screen host machine into windows each which information displayed, enhancing debugging efficiency. Host machine PC-9800 series MS-DOS WindowsSupply media 3.5" Order code (part number)
Device File (DF78365)
µSAA13ID78K3 µSAA10ID78K3 PC/AT compatible 3.5" µSAB13ID78K3 Windows µSAB10ID78K3 machines (Japanese Windows) PC/AT compatible 3.5" µSBB13ID78K3 machines (English Windows) µSBB10ID78K3 File containing information peculiar device. combination with assembler (RA78 K3), compiler (CC78K3), integrated debugger (ID78K3). Host machine Order code (part number) Supply media PC-9800 series MS-DOS 3.5" µS5A13DF78365 µS5A10DF78365 PC/AT compatible 3.5" µS7B13DF78365 machines µS7B10DF78365
Remark operation integrated debugger device file guaranteed only above host machine
Software
µPD78363A, 78365A, 78366A, 78368A
Development Tool Configuration (When Using Integrated Debugger)
Host machine PC-9800 series PC/AT IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B
IE-784000-R in-circuit emulator IE-78350-R-EM-A emulation board (optional) IE-78365-R-EM1 emulation board (optional) RS-232C EP-78365GF-R Relocatable assembler compiler PG-1500 controller
Emulation probe
Software
Conversion socket connecting emulation probe target systemNote PROM programmer PG-1500 EV-9200G-80
Integrated Device file debugger Built-in PROM models
PD78P368AGF PD78P368AKL
Programmer adapter
Target system
PA-78P368GF
PA-78P368KL
Note socket provided with emulation probe. Remarks Desk top-type represents host machine this figure. 3.5-inch represents supply media software this figure.
µPD78363A, 78365A, 78366A, 78368A
EMBEDDED SOFTWARE following embedded software available enhancing efficiency program development maintenance. REAL-TIME
Real-time (RX78K/III)Note RX78K/III intended implement multi-tasking environment control field where real-time capability must. allocate idle time other processing improve overall performance system. RX78K/III provides system calls conforming µITRON specification. RX78K/III package supplies tool (configurator) create nucleus RX78K/III multiple information tables. Host machine PC-9800 series PC/AT compatible machines MS-DOS Supply media 3.5" 3.5" Pending Pending Pending Pending Order code (part number)
Note Under development Caution Before purchasing this product, requested conclude contract licensing filling specified form. Remark When using RX78K/III real-time RA78K3 assembler package (optional) necessary.
µPD78363A, 78365A, 78366A, 78368A
Fuzzy Inference Development Support System
Fuzzy knowledge data Program that supports input/editing evaluation (simulation) fuzzy knowledge (fuzzy rules membership functions). creation tool Host machine Order code (part number) (FE9000, FE9200) PC-9800 series MS-DOS Supply media 3.5" 3.5"
µS5A13FE9000 µS5A10FE9000 PC/AT compatible µS7B13FE9200 machines Windows µS7B10FE9200 Program that converts fuzzy knowledge data obtained using fuzzy knowledge data Translator creation tool into assembler source program RA78K/III. (FT78K3)Note Host machine Order code (part number) Supply media PC-9800 series MS-DOS 3.5" µS5A13FT78K3 µS5A10FT78K3 PC/AT compatible 3.5" µS7B13FT78K3 machines µS7B10FT78K3 Fuzzy inference module Program that executes fuzzy inference when linked with fuzzy knowledge data converted translator. (FI78K/III)Note Host machine Order code (part number) Supply media µS5A13FI78K3 PC-9800 series MS-DOS 3.5" µS5A10FI78K3 PC/AT compatible 3.5" µS7B13FI78K3 machines µS7B10FI78K3 Fuzzy inference debugger Support software that evaluates adjusts fuzzy knowledge data hardware level using in-circuit emulator. (FD78K/III) Host machine Order code (part number) Supply media PC-9800 series MS-DOS 3.5" µS5A13FD78K3 µS5A10FD78K3 PC/AT compatible 3.5" µS7B13FD78K3 µS7B10FD78K3 machines
Note Under development
µPD78363A, 78365A, 78366A, 78368A
[MEMO]
µPD78363A, 78365A, 78366A, 78368A
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78363A, 78365A, 78366A, 78368A
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78363A, 78365A, 78366A, 78368A
MS-DOS windows either registered trademarks trademarks Microsoft Corporation United states and/or other countries. PC/AT trademarks Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation. TRON abbreviation Realtime Operating system Nucleus. ITRON abbreviation Industrial TRON.
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative.
Lisence needed
µPD78365A
customer must judge need license µPD78363A, 78366A, 78368A part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD78363A,78365A,78366A,78368A 16/8-BIT SINGLE-CHIP MICROCONTROLL

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