µPD78323,78324 16/8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPT
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INTEGRATED CIRCUIT
µPD78323,78324
16/8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78324 16/8-bit single-chip microcontroller that incorporates high-performance 16-bit CPU. µPD78324 78K/III series. internal capacity significantly increased compared with conventional µPD78322. realtime pulse unit realtime pulse control required motor control, converter, ROM, have been integrated into chip. µPD78324 incorporates 32K-byte mask 1024-byte RAM. µPD78323 ROM-less version µPD78324. Also, provided µPD78P324 on-chip PROM product. Detailed information about product features specifications found following document.
µPD78322 User's Manual IEU-1248
FEATURES
Internal 16-bit architecture external 8-bit data High-speed processing pipeline control instruction prefetch Minimum instruction execution time: (with external clock operation) Instruction suitable control operations (µPD78312 upward compatible) Multiply/divide instructions bits bits, bits bits) manipulation instruction String instruction, etc. On-chip high-function interrupt controller 3-level priority specifiable 3-type interrupt processing mode selectable (Vectored interrupt function, context switching function, macro service function) Variety peripheral hardware Realtime pulse unit 8-channel, 10-bit converter Watchdog timer Powerful serial interface (with on-chip dedicated baud rate generator) UART (NEC Standard Serial Interface) 3-wire serial channel channel
APPLICATIONS
Motor control devices Unless there particular diferences, µPD78324 described representative model this document.
information this document subject change without notice. Document U10456EJ4V0DS00 (4th edition) (Previous IC-2870) Date Published November 1995 Printed Japan mark shows major revised points.
1991
µPD78323, 78324
ORDERING INFORMATION
Part Number Package 74-pin 68-pin 74-pin 68-pin plastic plastic plastic plastic mil) mil) On-chip None None Mask Mask
µPD78323GJ-5BJ µPD78323LP
Remark Indicates code number.
µPD78323, 78324
CONFIGURATION
74-pin plastic µPD78323GJ-5BJ
P07/RTP7 P06/RTP6 P05/RTP5 P04/RTP4 P03/RTP3 P02/RTP2 P01/RTP1
P93/TMD
P42/AD2
P41/AD1
P40/AD0
P92/TAS
P91/WR
P90/RD
ASTB
P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 P70/AN0 P71/AN1 P00/RTP0 WDTO RESET P85/TO11 P84/TO10 P83/TO03 P82/TO02 P81/TO01 P80/TO00 P34/SCK P33/SI/SB1 P32/SO/SB0 P31/R P30/T
P27/INTP6/TI
P21/INTP0
P22/INTP1
P23/INTP2
P24/INTP3
P25/INTP4
P26/INTP5
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
Caution should connected noise control (can also left open).
P20/NMI
µPD78323, 78324
68-pin plastic µPD78323LP mil)
P27/INTP6/TI
P26/INTP5
P25/INTP4
P24/INTP3
P23/INTP2
P22/INTP1
P21/INTP0
P77/AN7
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P20/NMI
P30/T P31/R P32/SO/SB0 P33/SI/SB1 P34/SCK P80/TO00 P81/TO01 P82/TO02 P83/TO03 P84/TO10 P85/TO11 RESET WDTO RTP0/P00
P71/AN1 P70/AN0 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3
P92/TAS
P93/TMD
P91/WR
P90/RD
ASTB
P40/AD0
P41/AD1
RTP1/P01
RTP2/P02
RTP3/P03
RTP4/P04
RTP5/P05
RTP6/P06
RTP7/P07
P42/AD2
µPD78323, 78324
INTP0 INTP6 RTP0 RTP7 SB0/SO SB1/SI TO00 TO03 TO10 TO11 Port0 Port2 Port3 Port4 Port5 Port7 Port8 Port9 Nonmaskable Interrupt Interrupt From Peripherals Realtime Port Timer Input Transmit Data Receive Data Serial Bus/Serial Output Serial Bus/Serial Input Serial Clock Timer Output RESET WDTO ASTB AVREF AVSS AVDD Reset Crystal Watchdog Timer Output External Access Turbo Mode Turbo Access Strobe Write Strobe Read Strobe Address Strobe Address/Data Address Analog Input Analog Reference Voltage Analog Analog Power Supply Ground Non-connection
µPD78323, 78324
GENERAL DESCRIPTION FUNCTIONS
Basic instructions Minimum instruction execution time (with external clock operation) bytes (µPD78324) None (µPD78323) bytes bytes bits banks (memory mapping) Input port (dual-function analog input: Input/output port (µPD78324) (µPD78323) 18/16-bit free running timer 16-bit timer/event counter 16-bit compare register 18-bit capture register 18-bit capture/compare register Realtime output port
Internal memory
Memory space General registers line
Real-time pulse unit
Serial communication interface converter
Serial interface with dedicated baud rate generator UART channel (NEC Serial Interface) channel 10-bit resolution analog inputs) External internal (dual-function external processing modes (vectored interrupt function, context switching function, macro service function) Internal STOP mode/HALT mode 16-bit transfer/operation instruction, multiplication/division instruction 16), manipulation instruction, string instruction, etc. On-chip watchdog timer 68-pin plastic mil) 74-pin plastic
Interrupt
Test factor Standby Instruction Others Package
µPD78323, 78324
DIFFERENCES BETWEEN µPD78324 78323
Product Name
Item Internal Input line Input /output
µPD78324
bytes (dual-function analog input: Specifiable 8-bit unit. Functions multiplexed address/data buses (AD0 AD7) external memory expansion mode. Specifiable bit-wise. Functions address A15) external memory expansion mode. Specifiable bit-wise. external memory expansion mode, function strobe signal output strobe signal output, respectively. external memory high-speed fetch mode, function output output respectively. Port mode 8-bit unit Port mode bit-wise.
µPD78323
None
Port (P40 P47)
Functions always multiplexed address/data buses.
Port (P50 P57)
Functions always address bus.
Port (P90 P93)
Always function strobe strobe signal output, respectively.
Memory expansion mode register (MM) Port mode register (PM5)
µPD78324 emulation mode, turbo acces acces manager (µPD71P301)Note pins controlled port port emulation pins.
Note Maintenance product
Main (P20) PROGRAMMABLE INTERRUPT CONTROLLER GENERAL REGISTERS bytes DATA MEMORY bytes RESET bytes
Note
BLOCK DIAGRAM
ROM/RAM
INTP0-INTP5 (P21-P26)
ASTB SYSTEM CONTROL CONTROL PREFETCH CONTROL (P90) (P91) (P92) (P93) A8-A15 (P50-P57) AD0-AD7 (P40-P47)
(P80) TO00 (P81) TO01 (P82) TO02 (P83) TO03 (P84) TO10 (P85) TO11 (P27) TI/INTP6
Peripheral bytes TIMER/COUNTER UNIT (REALTIME PULSE UNIT) MICRO SEQUENCE CONTROL MICRO ROM.
(P34) (P32) SO/SB0 (P33) SI/SB1 (P30) (P31) SERIAL INTERFACE (SBI) (UART) CONVERTER BIT) PORT
P90-P93
P80-P85
P70-P77
P50-P57
P40-P47
P30-P34
P20-P27
P00-P07 (REALTIME PORT)
AN0-AN7 (P70-P77)
AVDD
AVSS
AVREF
WDTO
µPD78323, 78324
Note µPD78323 does incorporate ROM.
µPD78323, 78324
CONTENTS LIST FUNCTIONS
PORT PINS PINS OTHER THAN PORTS INPUT/OUTPUT CIRCUITS RECOMMENDED CONNECTION UNUSED PINS
ARCHITECTURE
MEMORY SPACE PROCESSOR REGISTERS 2.2.1 2.2.2 2.2.3 2.3.1 2.3.2 2.3.3 Control Registers General Registers Special Function Registers (SFR) General Register Addressing Short Direct Addressing Special Function Register (SFR) Addressing
DATA MEMORY ADDRESSING
BLOCK FUNCTIONS
CONTROL UNIT (BCU) EXECUTION UNIT (EXU) ROM/RAM INTERRUPT CONTROLLER PORT FUNCTIONS CLOCK GENERATOR REALTIME PULSE UNIT (RPU) 3.7.1 3.7.2 Configuration Realtime Output Function
CONVERTER SERIAL INTERFACE
3.10 WATCHDOG TIMER
INTERRUPT FUNCTIONS
OVERVIEW MACRO SERVICE CONTEXT SWITCHING FUNCTION 4.3.1 4.3.2 Context Switching Function Interrupt Request Context Switching Function BRKCS Instruction
STANDBY FUNCTIONS EXTERNAL DEVICE EXPANSION FUNCTION OPERATION AFTER RESET INSTRUCTION ELECTRICAL SPECIFICATIONS
µPD78323, 78324
PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX LIST 78K/III SERIES PRODUCTS APPENDIX TOOLS
DEVELOPMENT TOOLS EVALUATION TOOLS
EMBEDDED SOFTWARE
µPD78323, 78324
LIST FUNCTIONS
PORT PINS
DualFunction
Name
Port 8-bit input/output port Input/output specified bit-wise Also serves realtime output port.
Function
Input/ output
RTP0 RTP7 INTP0 INTP1
Input/ output Port 8-bit input/output port Input/output specified 8-bit unit. Port 8-bit input/output port Input/output specified bit-wise Port Dedicated port 8-bit input Input/ output Port 5-bit input/output port Input/output specified bit-wise Input Port Dedicated port 8-bit input
INTP2 INTP3 INTP4 INTP5 INTP6/TI SO/SB0 SI/SB1
Input/ output
Input
TO00 TO01
Input/ output
Port 6-bit input/output port Input/output specified bit-wise
TO02 TO03 TO10 TO11
Input/ output
Port 4-bit input/output port Input/output specified bit-wise
µPD78323, 78324
PINS OTHER THAN PORTS (1/2)
DualFunction
Name
Function Realtime output port which generates pulses synchronization with trigger signal transmitted from realtime pulse unit (RPU). Nonmaskable interrupot request input capable specifying effective rising falling edge mode register.
RTP0 RTP7 Output
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6
Input
Input
External interrupt request input capable specifying effective edgy mode register.
P27/TI
Input Output Input Output Input Input /output Input /output Input /output Output
External count clock input timer (TM1) Serial data output asynchronous serial interface (UART) Serial data input asynchronous serial interface (UART) Serial data output clock synchronous serial interface 3-wire mode Serial data input clock synchronous serial interface 3-wire mode Serial data output clock synchronous serial interface mode
P27/INTP6 P32/SB0 P33/SB1 P32/SO P33/SI
Serial clock input/output clock synchronous serial interface
TO00 TO01 TO02
Multiplexed address/data external memory expansion Address external memory expansion
Output TO03 TO10 TO11 Output WDTO Output
Pulse output from realtime pulse unit
Strobe signal output generated external memory read operation Strobe signal output generated external memory write operation Control signal output generated access turbo access manager µPD71P301Note Signal output indicating that watchdog timer generated nonmascable interrupt. Timing signal output generated externally latching address information output from pins order access external memory.
ASTB
Output
Note Maintenance product
µPD78323, 78324
PINS OTHER THAN PORTS (2/2)
DualFunction
Name
Function µPD78324, normally connected VDD. Connecting sets ROM-less mode accesses external memory. µPD78323, this should fixed (low level). level cannot changed during operation. converter analog input. converter reference voltage input. converter analog power supply converter System reset input Crystal connect sysem clock oscillation. When external clock supplied, clock input inverted clock input also left open.) Positive power supply internally connected. Connected (GND) (can also left open).
Input
AVREF AVDD AVSS RESET
Input Input Input Input
µPD78323, 78324
INPUT/OUTPUT CIRCUITS RECOMMENDED CONNECTION UNUSED PINS input/output circuits, partly simplified, shown Table Figure 1-1. Table 1-1. Circuit Types Pins Their Recommended Connection Methods when Unused
Input/Output Circuit Type
Recommended Connection Method Input mode Individually connected resistor Output mode: Leave open
P00/RTP0 P07/RTP7 P20/NMI P21/INTP0 P26/INTP5 P27/INTP6/TI P30/TXD P31/RXD P32/SO/SB0 P33/SI/SB1 P34/SCK P40/AD0 P47/AD7 P50/A8 P57/A15 P70/AN0 P77/AN7 P80/TO00 P83/TO03 P84/TO10, P85/TO11 P90/RD P91/WR P92/TAS P93/TMD WDTO ASTB RESET AVREF, AVSS AVDD
Connected
Input mode Individually connected resistor Output mode: Leave open
Input mode Individually connected resistor Output mode: Leave open Connected
Leav open Connected Connected Connected (can also left open)
µPD78323, 78324
Figure 1-1. Input/Output Circuits
Type
Type
data
P-ch
IN/OUT
P-ch N-ch
input enable output disable N-ch
Type
Type
data P-ch
output disable N-ch
IN/OUT
Schmitt-trigger input having hysteresis characteristics. Type
Comparator P-ch N-ch
Type
P-ch N-ch
VREF (Threshold Voltage) input enable
Type data
P-ch
output disable
N-ch
Push-pull output which become high-impedance output (with both P-ch N-ch off)
µPD78323, 78324
ARCHITECTURE
MEMORY SPACE µPD78324 maximum bytes memory addressed (see Figure 2-1). Program fetches performed within area from 0000H FDFFH. However, when external memory expansion implemented area from FE00H FFFFH (main special function register area), program fetches also performed this area. this case, program fetch performed external memory, main special function registers. Vector table area Interrupt request from peripheral hardware, reset input, external interrupt request interrupt branch address
break instruction stored 0000H 003FH 64-byte area. Generation interrupt request sets even address content each table lower bits program counter (PC) address content higher bits. Interrupt Source RESET TMF0 EXF0 EXF1 EXF2 EXF3 EXF4/CCFX0 EXF5/CCFX1 EXF6/TI CMF00 CMF01 CMF02 CMF03 CMF10 CMF11 CSIIF Operation code Vector Table Address 0000H 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0024H 0026H 0028H 002AH 003CH 003EH
(RESET input) (NMI input) (Watchdog timer) (Realtime pulse unit) (INTP0 input) (INTP1 input) (INTP2 input) (INTP3 input) (INTP4 input/realtime pulse unit) (INTP5 input/realtime pulse unit) (INTP6/TI input) (Realtime pulse unit) (Realtime pulse unit) (Realtime pulse unit) (Realtime pulse unit) (Realtime pulse unit) (Realtime pulse unit) (Serial receive complete) (Serial send complete) (Clock synchronous serial interface) (A/D converter) trap (Break instruction)
(TPF) control word (CCW) 8002H 803FH external memory area used interrupt vector table place 0002H 003FH.
µPD78323, 78324
CALLT table area tables call addresses 1-byte call instruction (CALLT) stored 0040H 007FH 64-byte area. (TPF) control word (CCW) 8040H 807FH external memory area used CALLT instruction table place 0040H 007FH. CALLF entry area 0800H 0FFFH area directly subroutine-called 2-byte call instruction (CALLF). On-chip area 1024-byte built FB00H FEFFH. This area composed following RAMs. Peripheral FB00H FDFFH (768 bytes) Main FE00H FEFFH (256 bytes) main accessed high speed. main area, macro service control word general register group composed register banks mapped onto bytes from FE06H FE2BH bytes from FE80H FEFFH, respectively. Special function register (SFR) area Registers having specially assigned functions, such on-chip peripheral hardware mode registers control registers, mapped FF00H FFFFH area. Addresses without mapped registers cannot accessed. External memory area µPD78324 external memories (ROM, RAM) 32K-byte (8000H FFFFH) area. µPD78323 connect external memories (ROM, RAM) 64K-byte (0000H FFFFH) area. Each external memory accessed using P40/AD0 P47/AD7 (multiplexed address/data bus), P50/A8 P57/A15 (address bus) ASTB signals. external access area mapped FFD0H FFDFH 16-byte area special function register (SFR). this way, external memory accessed addressing. Dedicated pins (TAS pins) provided connect turbo access manager (µPD71P301)Note. µPD71P301 used, program processing speed equal that on-chip obtained. Note Maintenance product
Figure 2-1. Memory
µPD78323 µPD78324 ROM-Less Mode PD78324) FFFFH FF00H FEFFH Special Function Register (SFR) (256 FEFFH FE80H Main (256 FE00H Data Memory FDFFH Peripheral (768 FB00H FAFFH Memory Space (64K Program Memory Data Memory FB00H FE2BH FE06H General Register (128 Macro Service Control Data Area (1024 7FFFH External MemoryNote (31488 Program Area 1000H 0FFFH 0800H 07FFH 0080H 007FH CALLF Instruction Table Area 0040H 003FH Vector Table Area 0000H 0000H 0000H 0FFFH CALLF Instruction Entry Area (2048 Program Area External Memory (64256 8000H 7FFFH Program Memory Data Memory Internal (32768
µPD78323, 78324
Note Accessed external memory expansion mode. Caution word access (including stack operations) main area (FE00H-FEFFH), address that specifies operand must even value.
µPD78323, 78324
PROCESSOR REGISTERS processor registers consist mainly three groups. They general registers consisting banks sixteen 8bit registers, control registers consisting 8-bit register three 16-bit registers, special function registers such peripheral hardware mode registers. Figure 2-2. Register Configuration
Control Registers
General Registers
Special Function Registers
Remark CCWs control registers mapped special function register (SFR) area.
µPD78323, 78324
2.2.1 Control Register control registers carry dedicated functions such control program sequence, status stack memory, modification operand addressing. They consist three 16-bit registers 8-bit register. Program counter (PC) This 16-bit register which holds address information next program executed. normally incremented according number bytes instruction fetched. instruction with data branch executed, immediate data register content set. RESET input sets branches data 0000H 0001H reset vector tables Program status word (PSW) This 16-bit register consisting various flags which reset result instruction execution. Read/ write access carried units higher bits (PSWH) lower bits (PSWL). Each flag operated using operation instruction. interrupt request made instruction executed, data automatically saved stack recovered RETI RETB instruction. bits reset RESET input. Figure 2-3. Format Interrupt priority level transition flag (LT)
PSWH PSWL
RBS2 RBS1 RBS0
This flag used control interrupt priority. normal operation interrupt control circuit, this must operated program. Carry flag (CY) carry generated result execution operation instruction borrow generated into this flag other cases, this flag reset This flag tested conditional branch instruction. When control instruction executed, this flag functions accumulator. Zero flag When operation result zero, this flag other cases, this flag reset This flag tested conditional branch instruction. Sign flag When operation result "1", this flag When "0", this flag reset This flag tested conditional branch instruction. Parity/overflow flag (P/V) Only when overflow underflow occurs two's complement during execution arithmetic operation instruction, this flag other cases, reset (overflow flag operation). number operation result even during execution logic operation instruction, this flag number odd, this flag reset (parity flag operation). This flag tested conditional branch instruction.
µPD78323, 78324
Auxiliary carry flag (AC) carry generated result operation borrow generated into this flag
other cases, this flag reset This flag tested conditional branch instruction. Register select flag (RSS) This flag used specify general registers shown Table 2-1, value determines relationship between functional register absolute register. Thus, another register used switching flag. Interrupt request enable flag (IE) This flag used indicate interrupt request enable/disable. This flag execution instruction reset byexecution instruction acceptance interrupt. Register bank select flag (RBS0 RBS2) This 3-bit flag select eight register banks (RBANK0 RBANK7). User flag (UF) This flag reset user program used program control.
Stack pointer (SP) This 16-bit register which holds first address stack area (LIFO format) memory. operated dedicated instruction. decremented before write (save) operation into stack memory incremented after read (return) operation from stack memory. Since becomes indeterminate RESET input, must before subroutine call.
µPD78323, 78324
control word (CCW) This 8-bit register consisting control related flags. mapped special function register area controlled software. bits reset RESET input. Figure 2-4. Format
Table position flag (TPF) This flag used specify interrupt vector table area memory area used CALLT instruction table area. been reset after application RESET input, 0000H 007FH address used each table area. 8002H 807FH address external memory area place 0002H 007FH address used each table area setting using software. vector tables instruction, operation code trap interrupt reset input fixed 003EH, 003CH 0000H, respectively, they affected TPF. 2.2.2 General Registers These 128-byte registers mapped special area (FE80H FEFFH) internal space. They consist eight register banks. general register bank consists sixteen 8-bit registers. Figure 2-5. General Register Memory Location
8-Bit Processing FEFFH RBNK0 RBNK1 RBNK2 RBNK3 RBNK4 RBNK5 RBNK6 FE80H RBNK7
16-Bit Processing
(FH) (DH) (BH) (9H) (7H) (5H) (3H) (1H)
(EH) (CH) (AH) (8H) (6H) (4H) (2H) (0H)
µPD78323, 78324
sixteen 8-bit registers function eight 16-bit register pairs (RP0 RP7) well. shown Table 2-1, sixteen 8-bit registers characterized functional names. register functions lower half 16-bit accumulator, register functions upper half 8-bit 16-bit accumulator, registers function counter, function address register pairs. particular register function base register register user stack pointer. unique function register charges shown Table according value register select flag (RSS) PSW. Thus, program described functional name, another register used means flag. µPD78324 carry processed data addressing operations, implied addressing functional names with importance attached unique function each register register addressing absolute names with view fast processing with small number data transfers creating highly descriptive programs. Table 2-1. General Register Configuration
Absolute Name Functional Name Absolute Name Functional Name
µPD78323, 78324
2.2.3 Special Function Registers (SFR) These registers provided with special functions. They include various peripheral hardware mode registers control registers (CCW). special function registers assigned FF00H FFFFH 256-byte space. Short direct memory addressing applied FF00H FF1FH 32-byte area processing with short word length. manipulation, arithmetic transfer instructions executed areas. FFD0H FFDFH 16-byte area externally accessible addressing. Thus, external memory accessed external device manipulation carried instruction having short word length. Table lists special function registers (SFR). items table have following meanings. Symbol. Indicates address built-in special function register. described instruction operand column. R/W.Indicates corresponding special function register read write. Read/write enable Read only enable (register test enable) Manipulable unit Write only enable
Indicates applicable operation unit corresponding special function register. 16-bit manipulable described operand sfrp. When specified address, even address described. 1-bit manipulable described operation instruction. reset Indicates state each register when RESET input. Cautions Addresses which special function registers have been assigned cannot accessed FF00H FFFFH area. write read only register. data written, internal circuit malfunction.
µPD78323, 78324
Table 2-2. List Special Function Registers (1/4)
Manipulable Unit Address FF00H FF02H FF03H FF04H FF05H FF07H FF08H FF09H FF0AH FF0BH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF20H FF23H FF25H FF28H FF29H FF2AH FF2BH FF2CH Timer register FF2DH FF30H FF31H FF32H FF33H FF34H FF35H Capture register (higher bits)
Note
Special Function Register (SFR) Name Port Port Port Port Port Port Port Port Free running counter (lower bits) Note Capture register (lower bits)
Note
Symbol
bits bits
Reset
Undefined
TM0LW
0000H
CTX0LW CT01LW CT02LW CT03LW CCX0LW CC01LW TM0UW CTX0UW CT01UW CT02UW
Capture register (lower bits)
Note
Undefined
Capture register (lower bits)
Note
Capture register (lower bits) Note Capture/compoare register (lower bits)
Note
Capture/compoare register (lower bits)
Note
1111B 1111B 1111B
Port mode register Port mode register Port mode register Port mode register Port mode register Free runnting counter (higher bits)
Note
0000H
Capture register (higher bits)
Note
Undefined
Capture register (higher bits)
Note
Note Upper lower half 18-bit register.
µPD78323, 78324
Table 2-2. List Special Function Registers (2/4)
Manipulable Unit Address FF36H FF37H FF38H FF39H FF3AH FF3BH FF40H FF41H FF43H FF48H FF4CH Baud rate generator FF4DH FF60H FF61H FF62H FF68H FF6AH Realtime output port register Realtime output port reset register Port read control register converter mode register conversion result register ADCR (for 16-bit access) conversion result register FF6BH FF70H FF71H FF72H FF73H FF74H FF75H FF76H FF77H FF7CH FF7DH FF7EH Compare register FF7FH Clock synchronous serial FF80H FF82H FF86H interface mode register Serial interface control register Serial shift register CSIM SBIC CM11 Compare register CM10 Compare register CM03 Compare register CM02 Compare register CM01 Undefined ADCRH (for upper 8-bit access) Compare register CM00 RTPR PRDC Special Function Register (SFR) Name Capture register (higher bits)
Note
Symbol
bits bits
Reset
CT03UW
Capture/compoare register (higher bits)
Note
CCX0UW PMC0 RTPS PMC3 PMC8 CC01UW
Undefined
Capture/compoare register (higher bits)
Note
0000B 0000B
Port mode control register Realtime output port reset register Port mode control register Port mode control register
Undefined
Undefined
Note Upper lower half 18-bit register.
µPD78323, 78324
Table 2-2. List Special Function Registers (3/4)
Manipulable Unit Address Special Function Register (SFR) Name Asynchronous serial interface FF88H ASIM mode register Asynchronous serial interface FF8AH status register FF8CH FF8EH FFB0H FFB1H FFB2H FFB8H FFB9H FFBFH FFC0H FFC1H FFC2H FFC4H FFC6H FFC9H FFD0H External acces area FFDFH FFE0H FFE1H FFE2H FFE3H FFE4H FFE5H FFE6H FFE7H FFE8H FFE9H FFEAH FFEBH FFECH FFEDH FFEEH FFEFH Interrupt request flag rgister Interrupt request flag rgister Interrupt request flag rgister Interrupt mask flag rgister Interrupt mask flag rgister Interrupt mask flag rgister Priority specify bufer register Priority specify bufer register Priority specify bufer register
Interrupt processing mode specify register Interrupt processing mode specify register Interrupt processing mode specify register
Symbol
bits bits
Reset
ASIS :UART :UART BRGM TOC0 TOC1 RPUM STBC R/WNote R/WNote
Serial receive buffer Serial send shift register Timer control register Baud rate generator mode register Prescalar mode register Timer output control register Timer output control register mode register Standby control register control word Watchdog timer mode register Memory expansion mode register
Undefined Undefined 0000 000B
Programmable weight control register Fetch cycle control register
IF0L IF0H IF1L MK0L
MK0H MK1L PB0L PB0H PB1L ISM0L ISM0 ISM0H ISM1L ISM1
111B
Note Write enable case special instructions.
µPD78323, 78324
Table 2-2. List Special Function Registers (4/4)
Manipulable Unit Address FFF0H FFF1H FFF2H FFF3H FFF4H FFF5H FFF8H FFF9H Special Function Register (SFR) Name Context switching enable register Context switching enable register Context switching enable register External interupt mode register External interupt mode register In-service priority register Priority specify register Symbol CSE0L CSE0 CSE0H CSE1L CSE1 INTM0 INTM1 ISPR PRSL bits bits Reset
DATA MEMORY ADDRESSING
µPD78324, internal space (FB00H FEFFH) special function register area (FF00H FFFFH) mapped FB00H FFFFH area. FE20H FF1FH space data memory, short direct addressing enables direct addressing 1-byte data instruction word. Figure 2-6. Data Memory Addressing Space
FFFFH FF1FH FF00H FEFFH FE80H FE20H Main FE00H FDFFH Peripheral FB00H Direct Addressing Register Indirect Addressing Based Addressing Paste Indexed Addressing Paste Indexed Addressing (Provided with Displacement) Special Function Register (SFR) General Register Addressing
Register Addressing
Short Direct Addressing
External Memory
7FFFH
Internal ROMNote
0000H
Note When with µPD78323, this external memory. Caution word access (including stack operations) main area (FE00H-FEFFH), address that specifies operand must even value.
µPD78323, 78324
2.3.1 General Register Addressing general registers consist eight register banks, each consisting sixteen 8-bit registers eight 16-bit registers. General register addressing carried using register specify field bits supplied from instruction word, register bank select flag (RBS0 RBS2) register select flag (RSS) PSW. 2.3.2 Short Direct Addressing
Short direct addressing which enables direct address specification 1-byte data instruction work applied FE20H FF1FH space. short direct memory accessed 8-bit 16-bit data. When accessing memory 16bit data, specification even data 1-byte address specify data will cause 2-byte data specified continuous addresses even addresses accessed. specify number address specify data.) 2.3.3 Special Function Register (SFR) Addressing
This addressing applied operations special function register (SFR) mapped area FF00H FFFFH. Addressing performed 1-byte data instruction word corresponding lower bits special function register address. 16-bit access 16-bit operational SFR, 2-byte data specified continuous even addresses accessed case with short direct addressing.
µPD78323, 78324
BLOCK FUNCTIONS
CONTROL UNIT (BCU) BCU, necessary cycle started according physical address obtained execution unit (EXU). cycle startup request made from EXU, prefetch address generated instruction prefetch carried out. prefetched instruction code fetched into instruction queue. EXECUTION UNIT (EXU)
EXU, address calculation, arithmetic logical operation data transfer controlled microprograms. 256byte built EXU. 256-byte accessible relevant instruction faster than peripheral (768 bytes). ROM/RAM This block consists 32K-byte 768-byte RAM. However, µPD78323 does incorporate ROM. access disabled pin. INTERRUPT CONTROLLER Various interrupt requests (NMI, INTP0 INTP6) generated either externally from peripheral hardware processed context switch, vectored interrupt macro service function. 3-level interrupt priority also specified.
µPD78323, 78324
PORT FUNCTIONS
Table lists digital input/output ports. Each port carry many control operations including other data input/output operations. Table 3-1. Port Functions Features
Port Name Function Feature Specifiable bit-wise input/output. Also specifiable realtime output port. Remarks Serves RTP0 RTP7 pins. Serves NMI, INTP0 INTP5, INTP6/TI pins. Serves TXD, RXD, SO/SB0, SI/SB1, pins.
Port
8-bit input/outpput
Port
8-bit input
Input port pin. Functions external interrupt input.
Port
5-bit input/output
Specifiable bit-wise port pins control pins.
Port
8-bit input/output
Specifiable 8-bit units input output. Functions multiplexed address/data (AD0 AD7) external memory expansion mode. Specifiable bit-wise input output. Functions address A15) external memory expansion mode. Pins which used address used port. Input port pin. Also functions analog input converter.
--------
Port
8-bit input/output
--------
Port
8-bit input
Serves pins. Functions TO00 TO03, TO10 TO11 pins.
Port
6-bit input/output
Specifiable bit-wise port control pin.
Port
4-bit input/output
Specifiable bit-wise input/output. function output output, respectively, external memory expansion mode. function output output, respectively, high-speed fetch mode.
--------
µPD78323, 78324
CLOCK GENERATOR clock generator generates controls internal system clocks (CLK) supplied CPU. configured shown Figure 3-1. Figure 3-1. Block Diagram Clock Generator
Divider System Clock Generator fCLK Internal System Clock (CLK)
STOP Mode
Remarks
Crystal oscillator frequency External clock frequency fCLK Internal system clock frequency
system clock oscillator oscillates crystal resonator connected pins. stops oscillating when standby mode (STOP). External clocks input system clock oscillator. such cases, input clock signal input reverse phase clock signal pin. also left open. Caution When using external clocks, STBC bit. divider generates internal system clocks (fCLK) dividing system clock oscillator output (fxx crystal oscillation external clocks) into parts.
µPD78323, 78324
Figure 3-2. Externally-Mounted System Clock Generator Crystal oscillator
PD78324
External clock When inverted phase external clock input input
PD78324
External Clock
(ii) When left open
PD78324
External Clock
Open
Cautions When system clock oscillator used, following points should noted concerning wiring within broken lines shown Figure 3-2, order prevent effects wiring capacitance, etc. Keep wiring short possible. cross other signal lines, keep clear lines which high fluctuating current flows. Ensure that oscillator capacitor connection points always same potential VSS. ground ground pattern which high current flows. take signal from oscillator. When external clock input left open, ensure that loads such wiring capacitance connected pin.
µPD78323, 78324
REALTIME PULSE UNIT (RPU) This unit measure pulse intervals frequencies, generate programmable pulse outputs. consists mainly timers. flexibly cope with many applications, configuration registers connected timers changed using programs. meet various applications, toggle output max.) set/ reset output max.) selected timer output. 3.7.1 Configuration realtime pulse unit configured mainly timer (TM0) which functions 16-bit 18-bit free running timer timer (TM1) which functions 16-bit timer/event counter shown Figure 3-3.
Figure 3-3. Realtime Pulse Unit Configuration
fCLK/4 fCLK/8 INTCM00 COMPARE REG. CM00 COMPARE REG. CM01 COMPARE REG. CM02 COMPARE REG. CM03 INTP0 INTP1 INTP2 INTP3 INTCCX0 INTP5 CAPTURE REG. CT01 CAPTURE REG. CT02 CAPTURE REG. CT03 INTCC01 Match MODE0 MODE1 TO03 TO02 Match COMPARE REG. CM10 COMPARE REG. CM11 INTCM10 INTCM11 Match TO11 TO10 TO01 TO00 INTOV (CLEAR CONTROL) INTP6/TI fCLK/16 16-BIT TIMER/EVENT COUNTER INTP0 (OPPOSITE EDGE)
16/18-BIT FREE RUNNING TIMER
INTCM01 INTCM02 INTCM03
CAPTURE/COMPARE REG. CC01
µPD78323, 78324
INTP0 INTP4
CAPTURE REG. CTX0 CAPTURE/COMPARE REG. CCX0 Match
INTP0 INTCCX0
µPD78323, 78324
3.7.2 Realtime Output Function realtime output port set/reset port outputs bit-wise synchronization with trigger signal transmitted from (Realtime Pulse Unit). enables generate multi-channel synchronous pulses easily. Figure 3-4. Realtime Output Port
WRPORT
PMC0n
Output Latch
WRRTPR
INTCM03 RTPn
RTPRn
WRPTP
PMC0n
Internal
WRRTPS
RTPSn INTCCX0
PM0n
PM0n
µPD78323, 78324
CONVERTER µPD78324 incorporates high-speed, high-resolution 10-bit analog/digital (A/D) converter. This converter equipped with eight analog inputs (AN0 AN7) conversion result register (ADCR) which holds conversion results. Upon termination conversion, interrupt which start macro service generated. Figure 3-5. Converter Block Diagram
Sample Hold Circuit AVREF
Input Circuit
Converter
AVSS
Comparator
Internal
(10)
ADCR (10) Internal
SERIAL INTERFACE µPD78324 equipped with following independent channels serial interface function. Asynchronous serial interface Clock synchronous serial interface 3-wire serial mode Serial interface mode (SBI mode) Since µPD78324 incorporates baud rate generator, serial transfer rate irrespective operating frequency. baud rate generator functions 2-channel serial interface. serial transfer rate selected from 19.2 Kbps setting mode register.
Selector
Figure 3-6. Asynchronous Serial Interface Block Diagram
Internal ASIM Receive Buffer BRGM ASIS Shift Register Shift Register Match Receive Control Parity Check Clear INTSER INTSR Send Control Parity Addition fCLK/8 INTST Send/Receive Baud Rate Generator Output
µPD78323, 78324
fCLK/4
Baud Rate Generator
Figure 3-7. Block Diagram Clock Synchronous Serial Interface
Internal CSIM MOD2 CTXE CRXE MOD1 CLS1 CLS0 MOD0
SBIC
RELT CMDT RELD CMDD ACKT ACKE ACKD BSYE CLEAR
SI/SB1
Shift Register
Latch
SO/SB0 Busy/ Acknowledge Detector
N-ch Open Drain Output Enable
Release/ Command/Acknowledge Detector Interrupt Signal Generation Controller
Serial Clock Counter
INTCSI Baud Rate Generator Output fCLK/8 fCLK/32
µPD78323, 78324
Serial Clock Controller
CLS1 CLS0
µPD78323, 78324
3.10 WATCHDOG TIMER watchdog timer used prevent program overrun deadlock. Normal operation program system confirmed checking that watchdog timer interrupt been generated. Thus, instruction clear watchdog timer (timer start) into each program module. watchdog timer clear instruction cleared within time period into watchdog timer watchdog timer overflows, watchdog timer interrupt generated, level generated WDTO pin, thereby notifying error program. watchdog timer also used maintain oscillation stabilizing time oscillator after stop mode been released. Figure shows watchdog timer configuration. Figure 3-8. Watchdog Timer Configuration
fCLK/28 fCLK/210 fCLK/212 Timer Bits) Clear STOP INTWDT WDTO Watchdog Timer Bits) Overflow
Oscillation Stabilizing Time Controller
µPD78323, 78324
INTERRUPT FUNCTIONS
OVERVIEW µPD78324, various interrupt requests generated externally from on-chip peripheral hardware handled following three processing modes.
Interrupt Request
Handled Vectored Interrupt Processing Handled Context Switching Handled Macro Service
Interrupt requests classified into following three groups. Nonmaskable interrupt requests Maskable interrupt requests Interrupt requests software Figure shows maskable interrupt request processing modes. Table gives listing interrupt factors which processed. Figure 4-1. Interrupt Request Processing Modes
(Interrupt Masked) Vectored Interrupt Macro Service Reserved (Interrupt Unmasked) (Vectored Interrupt Processing Mode) Vectored Interrupt Processing Reserved Vectored Interrupt Processing Executed Context Switching Executed (Macro Service Processing Mode) Macro Service Processing Executed
µPD78323, 78324
Table 4-1. List Interrupt Factors
Interrupt Request Type Software Nonmaskable Maskable Reset INTCM00 INTCM01 INTCM02 INTCM03 INTCM10 INTCM11 INTSR INTST INTCSI INTAD INTSERNote RESET CM00 match signal CM01 match signal CM02 match signal CM03 match signal CM10 match signal CM11 match signal Serial receive terminate interrupt Serial send terminate interrupt Serial send/receive interrupt
conversion terminate interrupt
Default Priority Request Signal INTWDT INTOV INTP0 INTP1 INTP2 INTP3 INTP4/INTCCX0 INTP5/INTCC01 INTP6/TI
Interrupt Factor Function instruction Operation code trap input Watchdog timer Timer overflow INTP0 input INTP1 input INTP2 input INTP3 input
INTP4 input/CCX0 match signal
INTP5 input/CC01 match signal
Generator Unit (External interrupt) (WDT) (RPU) (External) (External) (External) (RPU/exteranl) (RPU/exteranl) (RPU/exteranl) (Exteranl) (RPU)
Macro Service
Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H
INTP6 input/TI input
Available (RPU) (RPU) (RPU) (RPU) (RPU) (UART) (UART) (CSI) (A/D) (UART) 0018H 001AH 001CH 001EH 0020H 0024H 0026H 0028H 002AH ---Note 0000H
Serial receive error signal Reset input
Note This test factor. vectored interrupt generated.
µPD78323, 78324
MACRO SERVICE macro service function executed interrupt request carry data operation data transfer hardware terms between special function register area memory space. Upon startup macro service, stops program execution temporarily. 1-byte/2-byte data operation transfer automatically carried between special function register (SFR) memory. Upon termination macro service, interrupt request flag reset restarts program execution. When carries macro service operations many into macro service counter (MSC), vectored interrupt request generated. Figure 4-2. Macro Service Processing Sequence Example
Macro Service Processing Interrupt Request Generated
Macro service execution
Data Transfer, Realtime Output Port Control Macro Service Counter (MSC) Decrement
MSC-1
Interrupt request flag
Vectored Interrupt Request Occurred
Next Instruction Executed
µPD78323, 78324
CONTEXT SWITCHING FUNCTION This function first select specified register bank hardware terms generating interrupt request executing BRKCS instruction, branch selected register bank vector address prestored register bank, also stack current contents into register bank. 4.3.1 Context Switching Function Interrupt Request
context switching function start enabled setting preset each interrupt request unmasked interrupt request which context switching function been enabled generated state, register bank which specified lower bits lower address (even address) corresponding interrupt vector table address selected. vector address prestored selected register bank transferred contents saved into register bank, operation branched interrupt processing routine. Return means executing RETCS instruction. Figure 4-3. Context Switching Interrupt Request
RBANK Exchange Save
Register Banks
µPD78323, 78324
4.3.2 Context Switching Function BRKCS Instruction context switching function started executing BRKCS instruction. context switched register bank specified lower 3-bit immediate data operation code BRKCS instruction. When BRKCS instruction executed, register bank specified 3-bit immediate data selected, vector address prestored register bank branched contents saved into register bank. Return means executing RETCSB instruction. Figure 4-4. Context Switching Execution BRKCS Instruction
CODE (BRKCS) CODE
Register Bank Specification RBANK0
RBANK7
RBANK Exchange Save
Register Banks
µPD78323, 78324
STANDBY FUNCTIONS
µPD78324 standby function decrease power consumption system. following modes available execution standby function. HALT mode. Mode halting operation clock. total power consumption system decreased intermittent operation combination with normal operating mode. STOP mode. Mode stopping whole system stopping oscillator. Considerably power consumption with leak current only set. Each mode software. Figure shows standby mode (STOP/HALT mode) transition. Figure 5-1. Standby Status Transition
Normal Status
HALT
STOP
µPD78323, 78324
EXTERNAL DEVICE EXPANSION FUNCTION
µPD78324 expand external devices (data memory, program memory peripheral device) areas (8000H FAFFH) except internal areas. Table show used external device access function setting procedure. Table 6-1. Function Setting (µPD78324)
Memory Expansion Mode Register Port mode Expansion mode Except Fetch Cycle Control Register Function Remarks
General port Setting prohibited General port steps External device connection mode
µPD71P301 connection mode
pins according externally expanded memory size. memory expanded steps from bytes about bytes. pins which used address used general-purpose input/output port. Table 6-2. Port Address Setting Port (µPD78324)
Port Port Port Port Port Port Port Port Port Port Port Port Port Port External Address Space bytes less bytes less bytes less About bytes less
Table 6-3. Function Setting (µPD78323)
Memory Expansion Mode Register ASTB Fetch Cycle Control Register Function Remarks
µPD78324 emulation mode
External device connection mode
General port
Except
µPD71P301 connection mode
µPD78323, 78324
OPERATION AFTER RESET
RESET input level, system reset applied each hardware becomes initialized status (reset status). RESET input becomes high level, program execution started. Initialize contents various registers program required. Change number cycles programmable wait register fetch cycle control register particular. RESET input equipped with analog delay noise suppressor prevent malfunctioning noise. Cautions While RESET active(low level), pins remain high impedance (except WDTO, AVREF, AVDD, AVSS, VDD, VSS, X2). been expanded externally, mount pull-up resistor P90/RD P91/WR pins. possible that P90/RD P91/WR pins become high impedance resulting external contents corruption input unit damage. addition, signals collide address/data bus, resulting destruction input/output circuit. Figure 7-1. Reset Signal Acknowledge
RESET Input
Reset Acknowledged
Reset Release
reset operation upon power-up, secure oscillation stabilizing time about msec from power-up reset acknowledge shown Figure 7-2. Figure 7-2. Reset Upon Power-Up
RESET
Reset Release
Oscillation Stabilizing Time
Analog Delay
Analog Delay Removed Noise
Analog Delay
Analog Delay
µPD78323, 78324
INSTRUCTION
This chapter covers instruction operations. operation codes number instruction execution clock cycles, µPD78322 User's Manual (IEU-1248). Operand representation format description method each instruction operand column, enter operand using description method instruction operand representation format (refer assembler specification details). more factors included description method column, select factor. capital alphabetic letters symbols keywords should described they are. case immediate data, describe appropriate numeric values labels. When describing labels, make sure describe symbols. Table 8-1. Operand Representation Description Method
Representation Format sfrp Description Method R10, R11, R12, R13, R14, RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP0, RP1, RP2, RP3, RP4, RP5, RP6, Special function register code (see Table 2-2) Special function register code (16-bit operation enable register; Table 2-2) RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, (Two more instructions described. Only PUSH instructions described only PUSHU POPU instructions described PSW.) [DE], [HL], [DE+], [HL+], [DE-], [HL-], [VP], [UP] [DE+A], [HL+A], [DE+B], [HL+B], [VP+DE], [VP+HL] [DE+byte], [HL+byte], [VP+byte], [UP+byte], [SP+byte] word[A], word[B], word[DE], word[HL] Register indirect mode Based indexed mode Based mode Index mode
post
saddr saddrp $addr16 !addr16 addr11 addr5 word byte
FE20H FF1FH Immediate data label FE20H FF1EH Immediate data (bit0 label (for 16-bit operation) 0000H FDFFH Immediate data label; relative addressing 0000H FDFFH Immediate data label; immediate addressing FFFFH describable instruction) 800H FFFH Immediate data label Immediate data (bit0 0)Note label 16-bit immediate data label 8-bit immediate data label 3-bit immediate data label 3-bit immediate data
Note make work access bit0 (odd address). Remarks Although have same describable register names, they generate different codes. post described with absolute names R15, RP7) well functional names (refer Table details relationships between absolute functional names). Immediate addressing enabled spaces. Relative addressing only enabled from first address subsequent instruction range -128 +127.
µPD78323, 78324
Instruction Group
Mnemonic
Operand
Bytes
Flags Operation byte (saddr) byte byte (saddr) (saddr) (saddr) (saddr)
#byte saddr, #byte sfrNote, saddr saddr, saddr, saddr sfr, 8-bit data transfer mem, [saddrp] [saddrp], !addr16 !addr16, PSWL, #byte PSWH, #byte PSWL, PSWH, PSWL PSWH saddr [saddrp] saddr, saddr #byte
(mem) (mem) ((saddrp)) ((saddrp)) (addr16) (addr16) PSWL byte PSWH byte PSWL PSWH PSWL PSWH
(mem) (saddr) ((saddrp)) (saddr) (saddr)
Note
STBC described sft, different dedicated instruction having different number bytes
used. Remark symbols Flags column, refer table below.
Symbol (Blank) Description change Clear Set/clear according result. flag operates parity flag flag operates overflow flag. previously stored value restored.
µPD78323, 78324
Instruction Group
Bytes
Flags Operation word (saddrp) word sfrp word (saddrp) (saddrp) (saddrp) (saddrp) sfrp sfrp (addr16) (addr16)
Mnemonic
Operand
rp1, #word saddrp, #word sfrp, #word saddrp saddrp, 16-bit data transfer MOVW saddrp, saddrp sfrp sfrp, rp1, !addr16 !addr16, mem, saddrp sfrp XCHW saddrp, saddrp rp,rp1 #byte saddr, #byte sfr, #byte saddr saddr, saddr 8-bit opration mem, #byte saddr, #byte sfr, #byte ADDC saddr saddr, saddr mem,
(mem) (mem) (saddrp) sfrp (saddrp) (saddrp)
(mem) byte (saddr), (saddr) byte sfr, byte (saddr) (saddr), (saddr) (saddr)
(mem) (mem), (mem) byte (saddr), (saddr) byte sfr, byte (saddr) (saddr), (saddr) (saddr)
(mem) (mem), (mem)
µPD78323, 78324
Instruction Group
Bytes
Flags Operation byte (saddr), (saddr) byte sfr, byte (saddr) (saddr), (saddr) (saddr)
Mnemonic
Operand
#byte saddr, #byte sfr, #byte saddr saddr, saddr mem, #byte saddr, #byte sfr, #byte 8-bit opration SUBC saddr saddr, saddr mem, #byte saddr, #byte sfr, #byte saddr saddr, saddr mem,
(mem) (mem), (mem) byte (saddr), (saddr) byte sfr, byte (saddr) (saddr), (saddr) (saddr)
(mem) (mem), (mem) byte (saddr) (saddr) byte byte (saddr) (saddr) (saddr) (saddr)
(mem) (mem) (mem)
µPD78323, 78324
Instruction Group
Bytes
Flags Operation byte (saddr) (saddr) byte byte (saddr) (saddr) (saddr) (saddr)
Mnemonic
Operand
#byte saddr, #byte sfr, #byte saddr saddr, saddr mem, #byte saddr, #byte sfr, #byte 8-bit opration saddr saddr, saddr mem, #byte saddr, #byte sfr, #byte saddr saddr, saddr mem,
(mem) (mem) (mem) byte (saddr) (saddr) byte byte (saddr) (saddr) (saddr) (saddr)
(mem) (mem) (mem) byte (saddr) byte byte (saddr) (saddr) (saddr)
(mem) (mem)
µPD78323, 78324
Instruction Group
Bytes
Flags Operation word (saddrp), (saddrp) word sfrp, sfrp word (saddrp) sfrp (saddrp), (saddrp) (saddrp) word (saddrp), (saddrp) word sfrp, sfrp word (saddrp) sfrp (saddrp), (saddrp) (saddrp) word (saddrp) word sfrp word (saddrp) sfrp (saddrp) (saddrp) AX(quotient), r1(remainder) AX(higher bits), rp1(lower bits)
Mnemonic
Operand
#word saddrp, #word sfrp, #word ADDW saddrp sfrp saddrp, saddrp #word saddrp, #word 16-bit opration sfrp, #word SUBW saddrp sfrp saddrp, saddrp #word saddrp, #word sfrp, #word CMPW saddrp sfrp saddrp, saddrp Multiplication/division MULU DIVUM MULUW
AXDE(quotient), rp1(remainder) AXDE AX(higher bits), rp1(lower bits)
DIVUX
Signed multiplication
MULW
µPD78323, 78324
Instruction Group
Mnemonic
Operand
Bytes
Flags Operation (saddr) (saddr) (saddr) (saddr) (saddrp) (saddrp) (saddrp) (saddrp) (CY, r10, r1m-1 r1m) times (CY, r17, r1m+1 r1m) times
r10, r1m-1 r1m) times r17, r1m+1 r1m) times r10, r1m-1 r1m) times r17, r1m+1 r1m) times rp10, rp115 rp1m-1 rp1m) times rp115, rp10 rp1m+1 rp1m) times
Increase/decrease saddr saddr INCW saddrp DECW RORC ROLC Shift-rotate SHRW SHLW saddrp rp1, rp1,
A3-0 (rp1)3-0, ROR4 [rp1] (rp1)7-4 A3-0, (rp1)3-0 (rp1)7-4 A3-0 (rp1)7-4, ROL4 [rp1] (rp1)3-0 A3-0, (rp1)7-4 (rp1)3-0
calibration
ADJBA ADJBS Decimal Adjust Accumulator
Data conversion
CVTBW
When When
µPD78323, 78324
Instruction Group
Bytes
Flags Operation (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) (saddr.bit) sfr.bit sfr.bit A.bit A.bit X.bit X.bit PSWH.bit PSWH.bit PSWL.bit PSWL.bit (saddr.bit) (saddr.bit) sfr.bit sfr.bit A.bit A.bit X.bit X.bit PSWH.bit PSWH.bit PSWL.bit PSWL.bit
Mnemonic
Operand
saddr. sfr. PSWH. PSWL. MOV1 saddr. bit, sfr. bit, bit, bit, PSWH. bit, PSWL. bit, saddr. /saddr. sfr. /sfr. manipulation AND1 PSWH. /PSWH. PSWL. /PSWL. saddr. /saddr. sfr. /sfr. PSWH. /PSWH. PSWL. /PSWL.
µPD78323, 78324
Instruction Group
Bytes
Flags Operation (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) sfr.bit A.bit X.bit PSWH.bit PSWL.bit (saddr.bit) (saddr.bit) sfr.bit sfr.bit A.bit A.bit X.bit X.bit PSWH.bit PSWH.bit PSWL.bit PSWL.bit
Mnemonic
Operand
saddr. sfr. XOR1 PSWH. PSWL. saddr. sfr. SET1 PSWH. manipulation PSWL. saddr. sfr. CLR1 PSWH. PSWL. saddr. sfr. NOT1 PSWH. PSWL. SET1 CLR1 NOT1
µPD78323, 78324
Instruction Group
Mnemonic
Operand
Bytes
Flags Operation (SP-1) (PC+3)H, (SP-2) (PC+3)L, addr16, SP-2 (SP-1) (PC+2)H, (SP-2) (PC+2)L, PC15-1100001, PC10-0addr11,SPSP-2 (SP-1) (PC+1)H, (SP-2) (PC+1)L, PCH(TPF, 00000000, addr5+1), PCL(TPF, 00000000, addr5), SPSP-2 (SP-1) (PC+2)H, (SP-2) (PC+2)L, rp1H, rp1L, SP-2 (SP-1) (PC+2)H, (SP-2) (PC+2)L, (rp1+1), (rp1), SP-2 (SP-1) PSWH, (SP-2) PSWL (SP-3) (PC+1)H, (SP-4) (PC+1)L, (003EH), (003FH), SP-4 (SP), (SP+1), SP+2 (SP), (SP+1) PSWL (SP+2), PSWH (SP+3) SP+4 (SP), (SP+1) PSWL (SP+2), PSWH (SP+3) SP+4 (SP-1) sfrH (SP-2) sfrL SP-2 {(SP-1)postH, (SP-2) postL,SPSP-2} timesNote (SP-1)PSWH, (SP-2)PSWL, SPSP-2 {(UP-1)postH, (UP-2)postL, UPUP-2} timesNote sfrL (SP) sfrH (SP+1) SP+2 {postL (SP), postH (SP+1), SPSP+2} timesNote PSWL(SP), PSWH(SP+1), SPSP+2 {postL (UP), postH (UP+1), UPUP+2} timesNote word SP+1 SP-1 (pin level) (signal level before output buffer) (pin level) (signal level before output buffer)
CALL CALLF
!addr16 !addr11
CALLT
[addr5]
Call-return CALL [rp1]
RETB
RETI
sfrp PUSH post PUSHU Stack manipulation post sfrp post POPU post #word MOVW INCW DECW Special CHKL CHKLA
Note indicates number registers described post.
µPD78323, 78324
Instruction Group
Bytes
Flags Operation addr16 rp1H, rp1L (rp1+1), (rp1) PC+2+jdisp8 PC+2+jdisp8 CY=1
Mnemonic
Operand
Unconditional branch
!addr16 [rp1] addr16 addr16 addr16 addr16 addr16 addr16 addr16 addr16 addr16 addr16 addr16 addr16 addr16 addr16 saddr. bit, addr16 sfr. bit, addr16 bit, addr16 bit, addr16 PSWH. bit, addr16 PSWL. bit, addr16 saddr. bit, addr16 sfr. bit, addr16 bit, addr16 bit, addr16 PSWH. bit, addr16 PSWL. bit, addr16 addr16
PC+2+jdisp8 CY=0
PC+2+jdisp8
PC+2+jdisp8
PC+2+jdisp8 P/V=1
PC+2+jdisp8 P/V=0 PC+2+jdisp8 PC+2+jdisp8 PC+3+jdisp8 (P/V PC+3+jdisp8 PC+3+jdisp8 PC+3+jdisp8 (P/V PC+3+jdisp8 CY=0 PC+3+jdisp8 CY=1 PC+3+jdisp8 (saddr.bit)=1 PC+4+jdisp8 sfr.bit=1 PC+3+jdisp8 A.bit=1 PC+3+jdisp8 X.bit=1 PC+3+jdisp8 PSWH.bit=1 PC+3+jdisp8 PSWL.bit=1 PC+4+jdisp8 (saddr.bit)=0 PC+4+jdisp8 sfr.bit=0 PC+3+jdisp8 A.bit=0 PC+3+jdisp8 X.bit=0 PC+3+jdisp8 PSWH.bit=0 PC+3+jdisp8 PSWL.bit=0
Conditional branch
µPD78323, 78324
Instruction Group
Bytes
Flags Operation PC+4+jdisp8 (saddr.bit)=1
Mnemonic
Operand
saddr.bit, addr16
then reset (saddr.bit) PC+4+jdisp8 sfr.bit=1
sfr.bit, addr16
then reset sfr.bit PC+3+jdisp8 A.bit=1 then reset A.bit PC+3+jdisp8 X.bit=1
A.bit, addr16 BTCLR X.bit, addr16
then reset X.bit PC+3+jdisp8 PSWH.bit=1
PSWH.bit, addr16
then reset PSWH.bit PC+3+jdisp8 PSWL.bit=1
PSWL.bit, addr16 Conditional branch
then reset PSWL.bit PC+4+jdisp8 (saddr.bit)=0
saddr.bit, addr16
then (saddr.bit) PC+4+jdisp8 sfr.bit=0
sfr.bit, addr16
then sfr.bit PC+3+jdisp8 A.bit=0
A.bit, addr16 BFSET X.bit, addr16
then A.bit PC+3+jdisp8 X.bit=0 then X.bit PC+3+jdisp8 PSWH.bit=0
PSWH.bit, addr16
then PSWH.bit PC+3+jdisp8 PSWL.bit=0
PSWL.bit, addr16
then PSWL.bit r2-1,
addr16 DBNZ saddr, addr16
then PC+2+jdisp8 (saddr) (saddr)-1,
then PC+3+jdisp8 (saddr) PSWH,
Context switching
BRKCS
R6PSWL, RBS2-0 RSS0, addr16, PSWH PSWL addr16,
RETCS
!addr16
RETCSB
!addr16
PSWH PSWL
µPD78323, 78324
Instruction Group
Bytes
Flags Operation
Mnemonic
Operand
MOVM
MOVBK
XCHM
XCHBK
String CMPME
CMPBKE
CMPMNE
CMPBKNE
CMPMC
CY=0 CY=0
µPD78323, 78324
Instruction Group
Bytes
Flags Operation
Mnemonic
Operand
CMPBKC
CY=0
CY=0 CY=1
String CMPMNC
CY=1
CMPBKNC STBC, #byte control SWRS RBn, WDM, #byte
CY=1 CY=1 STBC byteNote byteNote RBS2 RBS2 Operation (Enable Interrupt) (Disable Interrupt)
Note
operation code STBC register register operation instructions abnormal, operation code trap interrupt generated. Operation eent trap: (SP-1) PSWH, (SP-2) PSWL, (SP-3) (PC-4)H, (SP-4) (PC-4)L, (003CH), (003DH), SP-4,
µPD78323, 78324
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Supply voltage voltage AVDD AVSS Input voltage Output voltage Output current output pins
Note
Test Conditions
Rating -0.5 -0.5 -0.5 -0.5 -0.5 -1.0 -0.5 -0.5 AVDD -0.5 -0.5 AVDD
Unit
output pins total output pins output pins total
Output current high
Analog input voltage converter reference input voltage Operating ambient temperature Storage temperature
Note
AVDD AVDD AVDD AVDD
Tstg
Notes Except described Note P70/ANI0 P77/ANI7 pins Caution absoute maximum rating parameters exceeded even momentarily, quality product degraded. other words, product physically damaged absolute maximum raings exceeded. sure product without exceeding these rarings. RECOMMENDED OPERATING CONDITION
Oscillation frequency +5.0
CAPACITANCE
Parameter Input capacitance Output capacitance capacitance Symbol Unmeasured pins returned Test Conditions MIN. TYP. MAX. Unit
µPD78323, 78324
OSCILLATOR CHARACTERISTICS
Resonator
Recommended Circuit
Parameter
MIN.
MAX.
Unit
Ceramic resonator crystal resonator
Oscillation frequency (fXX)
input frequency (fX)
HCMOS Invertor
External clock
Open
input rise/fall time (tXR, tXF)
input high/low level width
HCMOS Invertor
(tWXH tWXL)
Caution
When using system clock oscillation circuit, wire part encircled dotted line following manner avoid influence wiring capacity, etc. Make wiring short possible. Avoid intersecting other signal conductors. Avoid approaching lines which very high fluctuating currents run. Make sure that grounding point oscillation circuit capacitor always same electrical potential VSS. Avoid grounding with grand pattern which very high currents run. fetch signals from oscillation circuit.
µPD78323, 78324
RECOMMENDED OSCILLATOR CONSTANT CERAMIC RESONATOR
Manufacturer
Product Name
Frequency [MHz] 12.0 14.74 16.0 12.0 17.74 16.0
Recommended Constant [pF] [pF]
CSA8.00MT CSA12.0MT Murata Mfg. Co., Ltd. CSA14.74MXZ040 CSA16.00MXZ040 CST8.00MTW CST12.0MTW CST14.74MXW0C3 CST16.00MXW0C3
On-chip
On-chip
CRYSTAL RESONATOR
Manufacturer
Product Name
Frequency [MHz]
Recommended Constant [pF] [pF]
HC49/U-S Kinseki Co., Ltd. HC49/U
µPD78323, 78324
CHARACTERISTICS
Parameter Input voltage
Symbol VIH1 Note Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Input voltage high VIH2 Output voltage Output voltage high Input leakage current Output leakage current supply current IDD2 Data retention voltage Data retention current VDDDR IDDDR HALT mode STOP mode VDDDR STOP mode VDDDR IDD1 0.8VDD 0.45 -400 Operating mode
Notes Except descried Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2,P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins.
µPD78323, 78324
CHARACTERISTICS Non-consecutive read/write operation (with general-purpose memory connected)
Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) delay time from address Address float time from Data input time from address Data input time from delay time from ASTB Data hold time (vs. Address active time from low-level width ASTB high-level width delay time from address Data output time from ASTB Data output time from delay time from ASTB Data setup time (vs. Data hold time (vs. ASTB delay time from low-level width Symbol tCYK tSAST tHSTA tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDAW tDSTOD tDWOD tDSTW tSODW tHWOD tDWST tWWL Test Conditions MIN. MAX. Unit
µPD78323, 78324
tCYK Dependent Timing Definition
Parameter tSAST tHSTA tDAR tDAID tDRID tDSTR tDRA tWRL tWSTH tDAW tDSTOD tDSTW tSODW tHWOD tDWST tWWL Expression 0.5T 0.5T (2.5 (1.5 0.5T 0.5T (1.5 0.5T 0.5T 0.5T 1.5T 0.5T 0.5T (1.5 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. Unit
Remarks
tCYK 1/fCLK (fCLK internal system clock frequency) indicates number wait cycles defined user software. Depends tCYK timing shown this table only.
µPD78323, 78324
SERIAL OPERATION
Parameter Serial clock cycle time
Symbol output tCYSK input output
Test Conditions Internal division External clock Internal division External clock Internal division External clock
MIN.
MAX.
Unit
Serial clock low-level width
tWSKL
input output
Serial clock high-level width setup time SCK) hold time (from SCK) delay time from
tWSKH input tSRXSK tHSKRX tDSKTX
OTHER OPERATION
Parameter high/low-level width INTP0 high/low-level width INTP1 high/low-level width INTP2 high/low-evel width NTP3 high/low-level width NTP4 high/low-level width INTP5 high/low-level width INTP6 high/low-level width RESET high/low-level width high/low-level width Symbol tWNIH, tWNIL tWI0H, tWI0L tWI1H, tWI1L tWI2H, tWI2L tWI3H, tWI3L tWI4H, tWI4L tWI5H, tWI5L tWI6H, tWI6L tWRSH, tWRSL tWTIH, tWTIL event counter mode Test Conditions MIN. MAX. Unit
tCYK tCYK tCYK tCYK tCYK tCYK tCYK
tCYK
µPD78323, 78324
CONVERTER CHARACTERISTICS(TA AVSS AVDD VDD)
Parameter Resolution Total error Note AVREF AVDD AVREF AVDD Quantization error Conversion time Sampling time Zero scale error Note tCONV tSAMP AVREF AVDD AVREF AVDD Full scale error Note AVREF AVDD AVREF AVDD Non-linear error
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
±0.4 ±0.7 ±1/2 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 -0.3 ±2.5 ±4.5 ±2.5 ±4.5 ±2.5 ±4.5 AVDD AVDD
%FSR %FSR tCYK tCYK
AVREF AVDD AVREF AVDD
Analog input voltage Reference voltage AVREF current AVDD supply current converter data retention current
Note
VIAN AVREF AIREF AIDD AVDDR AIDDR STOP mode AVDDR
Notes Quantization error excluded. When -0.3 VIAN conversion result becomes 000H. When VIAN AVREF, conversion performed resolution bits. When AVREF VIAN AVDD, conversion result 3FFH.
µPD78323, 78324
Non-Consecutive Read Operation
tCYK
(CLK)
P50-P57 (Output) tDAID tSAST P40-P47 (Input/ Output) ASTB (Output) Hi-Z
Lower Address (Output)
Higher Address
Higher Address
Hi-Z
Data (Input)
Hi-Z
Lower Address (Output)
Hi-Z
tWSTH
tHRID
tHSTA tFRA
(Output) tDSTR tDRID tDAR tWRL tDRA
Non-Consecutive Write Operation
(CLK)
P50-P57 (Output) tSAST P40-P47 (Input/ Output) tWSTH ASTB (Output) tHSTA tDSTOD (Output) tDSTW
Lower Address (Output)
Higher Address
Higher Address
Undefined
Data (Output)
Lower Address (Output)
tHWOD
tDWST
tDWOD tDAW tWWL
tSODW
µPD78323, 78324
Serial Operation
tCYSK tWSKL tDSKTX tWSKH
tSRXSK tHSKRX
Interrupt Input Timing
tWNIH
tWNIL
0.8VDD 0.8V
tWInH
tWInL
INTPn
Remarks
µPD78323, 78324
Reset Input Timing
tWRSH tWRSL
0.8VDD RESET 0.8V
Input Timing
tWTIH
tWTIL
µPD78323, 78324
PACKAGE DRAWINGS
PLASTIC
detail lead
NOTE
ITEM MILLIMETERS 23.2±0.4 20.0±0.2 20.0±0.2 23.2±0.4 0.40±0.10 0.20 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 0.1±0.1 5°±5° MAX. INCHES 0.913 +0.017 -0.016 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.913 +0.017 -0.016 0.079 0.039 0.079 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.146 0.004±0.004 5°±5° 0.158 MAX. S74GJ-100-5BJ-3
Each lead centerline located within 0.20 (0.008 inch) true position (T.P.) maximum material condition.
µPD78323, 78324
PLASTIC mil)
P68L-50A1-2 NOTE Each lead centerline located within 0.12 (0.005 inch) true position (T.P.) maximum material condition. ITEM MILLIMETERS 25.2 24.20 24.20 25.2 1.94 0.15 MIN. 1.27 (T.P.) 0.40 0.12 23.12 0.20 0.15 0.20 +0.10 -0.05 INCHES 0.992 0.008 0.953 0.953 0.992 0.008 0.076+0.007 -0.006 0.024 0.173+0.009 -0.008 0.110+0.009 -0.008 0.035 MIN. 0.134 0.050 (T.P.) 0.016+0.004 -0.005 0.005 0.910+0.009 -0.008 0.006 0.031 0.008+0.004 -0.002
µPD78323, 78324
RECOMMENDED SOLDERING CONDITIONS
µPD78323 78324 should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (IE1-1207). soldering methods conditions other than those recommended below, contact salesman. Table 11-1. Soldering Conditions Surface Mount Type
µPD78323GJ-5BJ 74-pin plastic 74-pin plastic
Recommended Condition Symbol
Soldering Method
Soldering Conditions Package peak temperature: Time: sec. max. above) Number times: Once, Time limit: daysNote (thereafter hours prebaking required Package peak temperature: Time: sec. max. above) Number times: Once, Time limit: daysNote (thereafter hours prebaking required temperature: max, Time: sec. max. (Per side device)
Infrared reflow
IR30-107-1
VP15-107-1
part heating
µPD78323LP 68-pin plastic 68-pin plastic
Soldering Method
mil) mil)
Recommended Condition Symbol
Soldering Conditions Package peak temperature: Time: sec. max. above) Number times: twice less, Time limit: daysNote (thereafter hours prebaking required <Caution> second reflow should started after temperature device which would have been changed first reflow returned normal. Please avoid flux water washing after first reflow. Package peak temperature: Time: sec. max. above), Number times: twice less, Time limit: daysNote (thereafter hours prebaking required <Caution> second reflow should started after temperature device which would have been changed first reflow returned normal. Please avoid flux water washing after first reflow. temperature: max., Time: sec. max. (Per side device))
Infrared reflow
IR30-367-2
VP15-367-2
part heating
Note storage period after dry-pack decompression, storage conditions max. Caution more than soldering method should avoided (except case part heating).
APPENDIX LIST 78K/III SERIES PRODUCTS (1/2)
µPD78324
Basic instruction Minimum instruction execution time Internal memory Memory space Input lines Output (including analog inputs) 32768 bits 1024 bits
µPD78323
µPD78322
µPD78320
µPD78312A
µPD78310A
operation) 16384 bits bits bytes
operation) 8192 bits bits
(including analog inputs)
Pulse unit
Real-time pulse unit 18/16-bit free running timer 16-bit timer/event counter Real-time pulse unit 16-bit compare register 18/16-bit free running timer 18-bit capture register 16-bit timer/event counter 18-bit capture/compare register 16-bit compare register Real-time output port 18-bit capture register 18-bit capture/compare register Real-time output port mode) function available
Multi-function pulse unit 16-bit presettable up-/down-counter 16-bit free running counter capture function 16-bit interval timer High-precision output Real-time output port bits Count unit mode (4-multiplication
Counter start function interval timer external trigger available Dedicated on-chip baud rate generator UART channel channel 3-wire serial bits (full-duplex transmission/ reception) Dedicated on-chip baud rate generator transfer modes (asynchronous mode, interface mode) Four 8-bit resolution inputs external, internal 8-level programmable priority order
Serial communication interface
µPD78323, 78324
converter
Eight 10-bit resolution inputs external, internal (shared with external 3-level programmable priority order processing methods (vectored interrupt, context switching macro service functions)
Interrupt
LIST 78K/III SERIES PRODUCTS (2/2)
µPD78324
Test source Internal Following instructions added µPD78312 78310 MOVW rp1, !addr16 instruction MOVW !addr16, instruction
µPD78323
µPD78322
µPD78320
µPD78312A
µPD78310A
Instruction
Instructions µPD78312 78310 significantly increased.
On-chip watchdog timer Standby function (STOP/HALT) Others 20-bit time base counter Pseudo static refresh function mil) 74-pin plastic 80-pin plastic 68-pin plastic 64-pin 64-pin 64-pin 68-pin plastic plastic plastic plastic shurink (750 mil) QUIP mil)
Package
68-pin plastic mil) 74-pin plastic
µPD78323, 78324
µPD78323, 78324
APPENDIX TOOLS
DEVELOPMENT TOOLS
following development tools available system development using µPD78324. Language Processor
78K/III series relocatable assembler (RA78K/III)
Refers relocatable assembler which used commonly 78K/III series. Equipped with macro function, relocatable assembler aimed improved development efficiency. assembler also accompanied structured assembler which describe program control structure explicitly, thus making possible improve productivity maintainability program. Host machine PC-9800 series PC/ATand compatible machine HP9000 series 700SPARCstationNEWSMS-DOS5-inch 3.5-inch DOS5-inch HP-UXSunOSNEWS-OSDAT Cartridge tape (QIC-24) Supply medium 3.5-inch Part number
µS5A13RA78K3 µS5A10RA78K3 µS7B13RA78K3 µS7B10RA78K3 µS3P16RA78K3 µS3K15RA78K3 µS3R15RA78K3
78K/III series compiler (CC78K/III)
Refers compiler which commonly used 78K/III series. This compiler program converting programs written language those object codes which executable microcontrollers. When using this compiler, 78K/III series relocatable assembler (RA78K/III) required. Part number PC-9800 series PC/AT compatible machine HP9000 series SPARCstation NEWS MS-DOS 5-inch 3.5-inch 5-inch HP-UX SunOS NEWS-OS Cartridge tape (QIC-24) Supply medium 3.5-inch
Host machine
µS5A13CC78K3 µS5A10CC78K3 µS7B13CC78K3 µS7B10CC78K3 µS3P16CC78K3 µS3K15CC78K3 µS3R15CC78K3
Remark
Relocatable assembler compiler operations assured only host machine above.
µPD78323, 78324
PROM Writing Tools
This PROM programmer allows programming, standalone mode operation from host computer, singlechip microcontroller with on-chip PROM connection board provided separately available programmer adapter. program typical 256K-bit 4M-bit PROMs.
PG-1500
UNISITE 2900 Hardware
PROM programmer made Data Japan Corporation.
PA-78P324GJ PA-78P324KC PA-78P324KD PA-78P324LP
PROM programmer adapters writing programs µPD78P324 with general PROM programmer such PG-1500. PA-78P324GJ µPD78P324GJ PA-78P324KC µPD78P324KC PA-78P324KD µPD78P324KD PA-78P324LP µPD78P324LP Connects PG-1500 host machine serial parallel interface, controls PG-1500 host machine. Ordering Code (Product Name)
Host Machine Software PG-1500 controller PC-9800 series PC/AT compatible machine MS-DOS Supply Medium 3.5-inch 5-inch 3.5-inch 5-inch
µS5A13PG1500 µS5A10PG1500 µS7B13PG1500 µS7B10PG1500
Remark
Operation PG-1500 controller guaranteed only host machines operating systems quoted above.
µPD78323, 78324
Debugging Tools
These in-circuit emulators which used development debugging application systems. Debugging performed connecting them host machine. IE-78327-R used commonly both µPD78322 subseries µPD78328 subseries. IE-78320-R used µPD78322 subseries. These emulation probes connecting IE-78327-R IE-78320-R target system. EP-78320GJ-R: 74-pin plastic EP-78320L-R: 68-pin plastic This program controlling IE-78327-R from host machine. execute commands automatically, thus enabling more efficient debugging. Host machine IE-78327-R control program controller) PC-9800 series PC/AT compatible machine MS-DOS 5-inch 3.5-inch 5-inch Supply medium 3.5-inch Part number
IE-78327-R IE-78320-RNote
EP-78320GJ-R EP-78320L-R
Hardware
µS5A13IE78327 µS5A10IE78327 µS7B13IE78327 µS7B10IE78327
This program controlling IE-78320-R from host machine. execute commands automatically, thus enabling more efficient debugging. Host machine Software IE-78320-R control programNote controller) PC-9800 series PC/AT compatible machine MS-DOS 5-inch 5-inch Supply medium 3.5-inch Part number
µS5A13IE78320 µS5A10IE78320 µS7B10IE78320
Remarks
operation each software assured only host machine above. µPD78322 subseries: µPD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1), 78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1), 78323(A2), 78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2)
µPD78328 subseries: µPD78327, 78328, 78P328, 78327(A), 78328(A)
Note existing product IE-78320-R maintenance product. going newly purchase in-circuit emulator, please alternative product IE-78327-R.
Host machine
PC-9800 series PC/AT compatible machine RS-232-C
Development Tool Configurations
Emulation probes
Software
IE-78327-R in-circuit emulator
RS-232-C PROM programmer EP-78320GJ-R EP-78320L-R
Relocatable assembler PG-1500 (With structured assembler) controller
controller
Socket connecting emulation probe target system Note
PG-1500 EV-9200G-74 Socket plastic
PROM-incorporated products
µPD78P324GJ
µPD78P324LP
PD78P324KC PD78P324KD
Programmer adapters
Target system PA-78P324KC PA-78P324KD
PA-78P324GJ
PA-78P324LP
µPD78323, 78324
Note
socket supplied with emulation probe.
Remarks also possible host machine PG-1500 connecting them directly RS-232-C. diagram above, representative software supply media 3.5-inch FDs.
µPD78323, 78324
EVALUATION TOOLS
evaluate functions PD78324, following tools made available.
Part Number Host Machine Function connecting host machine, possible evaluate functions equipped µPD78324 simple manner. command system this product basically conforms that IE-78327-R IE-78320-R. Therefore, easy move development work application systems IE-78327-R IE78320-R. addition turbo access manager (µPD71P301)Note mounted board.
EB-78320-98
PC-9800 series
EB-78320-PC
PC/AT compatible machine
Note
turbo access manager (µPD71P301) maintenance product.
Cautions This product development tool µPD78324 application systems. This product equipped with emulation function executing incorporated µPD78324. EMBEDDED SOFTWARE
following embedded software programs available perform program development maintenance more efficiently. Eeal-time
RX78K/III designed provide multi-task environment field control application where real-time operation required. using this real-time performance whole system improved allocating CPU's idle time other processings. RX78K/III provides system call based µITRON specifications. RX78K/III package provides tools (configurators) creating RX78K/III's nucleus multiple information table. Real-time (RX78K/III) Host machine PC-9800 series MS-DOS 5-inch PC/AT compatible machine 3.5-inch 5-inch Supply medium 3.5-inch Part number
µS5A13RX78320 µS5A10RX78320 µS7B13RX78320 µS7B10RX78320
Caution
purchase operating system above, need fill purchase application form beforehand sign contract allowing software.
Remark
When using real-time RX78K/III, need assembler package RA78K/III (optional) well.
µPD78323, 78324
Fuzzy Inference Development Support System
This program supports inputting/editing/evaluating (through simulation) fuzzy knowledge data (fuzzy rules membership functions). Host machine Fuzzy knowledge data creation tools (FE9000, FE9200) PC-9800 series MS-DOS 5-inch PC/AT compatible machine 3.5-inch Winsows5-inch Supply medium 3.5-inch Part number
µS5A13FE9000 µS5A10FE9000 µS7B13FE9200 µS7B10FE9200
This program converts fuzzy knowledge data obtained with fuzzy knowledge data creation tools assembler source program RA78K/III. Host machine Translator (FT78K3)Note 3.5-inch PC-9800 series PC/AT compatible machine MS-DOS 5-inch 3.5-inch 5-inch Supply medium Part number
µS5A13FT78K3 µS5A10FT78K3 µS7B13FT78K3 µS7B10FT78K3
This program executes fuzzy inference. Fuzzy inference executed being linked fuzzy knowledge data converted translator. Part number Fuzzy inference module (FI78K/III)Note PC-9800 series MS-DOS 5-inch PC/AT compatible machine 3.5-inch 5-inch Supply medium 3.5-inch
Host machine
µS5A13FI78K3 µS5A10FI78K3 µS7B13FI78K3 µS7B10FI78K3
This support software program evaluating adjusting fuzzy knowledge data hardware level using in-circuit emulator.
Host machine Fuzzy inference debugger (FD78K/III) PC-9800 series MS-DOS 5-inch IIBM PC/AT compatible machine 3.5-inch 5-inch Supply medium 3.5-inch
Part number
µS5A13FD78K3 µS5A10FD78K3 µS7B13FD78K3 µS7B10FD78K3
Note
Under development
µPD78323, 78324
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78323, 78324
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative.
License needed customer must judge need license
µPD78323 µPD78324
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customer must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact Sales Representative advance. Anti-radioactive design implemented this product.
94.11
MS-DOS Windows trademarks Microsoft Corporation. PC/AT trademarks Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation. TRON abbreviation Realtime Operating system Nucleus. ITRON abbreviation Industrial TRON.
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