µPD77016 bits, Fixed-point Digital Signal Processor µPD77016

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µPD77016 bits, Fixed-point Digital Signal Processor µPD77016

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INTEGRATED CIRCUIT
µPD77016
bits, Fixed-point Digital Signal Processor
µPD77016 bits fixed-point (Digital Signal Processor) developed digital signal processing with
demand high speed precision.
FEATURES FUNCTIONS
Instruction cycle: (MIN.) with clock Dual load/store Hardware loop function Conditional execution Executes product-sum operation instruction cycle
PROGRAMMING
bits bits bits bits multiply accumulator general registers bits each) ROM/RAM data pointer: each data memory area registers source interrupts (external: internal: operand instructions (example: +R1LR2L) Nonpipeline execution stage
MEMORY AREAS
Program memory area: words bits independent data memory areas: words bits (X/Y memory)
ON-CHIP PERIPHERAL
port: bits Serial bits): channels
CMOS single power supply ORDERING INFORMATION
Part Number Package
PD77016GM-KMD 160-pin plastic (FINE PITCH)
information this document subject change without notice. Document U10891EJ5V0DS00 (5th edition) Date Published April 1998 CP(K) Printed Japan
mark
shows major revised points.
1992, 1994, 1995
X-Bus External Memory Y-Bus Serial Memory Data Pointers Memory 2KW-RAM Memory Data Pointers Memory 2KW-RAM R0-R7 Serial Main (40) Ports Loop Control Stack Instruction Memory (1.5 KW-RAM) Interrupt Control Host Control Stack Wait Controller INT1-INT4 WAIT RESET CLKOUT CLKIN External Instruction Memory
BLOCK DIAGRAM
µPD77016
µPD77016
FUNCTIONAL GROUPS
Serial Interface
SORQ1 SOEN1 SCK1 SIEN1 SIAK1 SORQ2 SOEN2 SCK2 SIEN2 SIAK2
RESET INT1 INT2 INT3 INT4 CLKIN CLKOUT TDO,TICE TCK,TDI,TMS IA15 ID31 HOLDRQ (16) (32)
Interrupts
Serial Interface
Debugging Interface External Instruction Memory
Ports
BSTB HOLDAK
Data Control
Host Interface
HA0,HA1
DA15 WAIT (16) (16) External Data Memory
Functional Differences among Family
Item Internal instruction Internal instruction External instruction memory Data (X/Y memory) Data (X/Y memory) External data memory Instruction cycle (Maximum operation speed) External clock maximum operation speed) Crystal maximum operation speed) Instruction Serial interface Channels)
PD77016
1.5K words None words words each None words each
PD77015
PD77017
PD77018
words
PD77018A
PD77019
PD77019-013
words
words
words None
words
None
words each words each
words each words each
words each words each words each None
MHz) 33/16.5/8.25/4.125 Variable multiple rate mask option.
16.6 MHz) 60/30/20/15/7.5 Variable multiple rate mask option. STOP instruction added. Multiple rate fixed
Channel same functions channel 160-pin plastic
Channel same functions that PD77016. Channel SORQ2 SIAK2 (Channel used CODEC connection). 100-pin plastic TQFP 100-pin plastic TQFP 116-pin plastic 100-pin plastic TQFP
Power supply Package
Remark
µPD77019-013 internal area masked already void code based without mask code ordering process.
µPD77016
µPD77016
CONFIGURATION
PD77016GM-KMD
160-pin plastic (FINE PITCH) (Top View)
RESET INT4 INT3 INT2 INT1 WAIT HOLDRQ CLKIN CLKOUT BSTB HOLDAK DA15 DA14 DA13 DA12 DA11 DA10 IA10 IA11 IA12 IA13 IA14 IA15
SIEN1 SCK1 SIAK1 SORQ1 SOEN1 SOEN2 SORQ2 SIAK2 SCK2 SIEN2
ID10 ID11 ID12 ID13 ID14 ID15 ID16 ID17 ID18 ID19 ID20 ID21 ID22 ID23 ID24 ID25 ID26 ID27 ID28 ID29 ID30 ID31
µPD77016
IDENTIFICATION
BSTB: CLKIN: CLKOUT: D0-D15: DA0-DA15: GND: HA0,HA1: HCS: HD0-HD7: HOLDAK: HOLDRQ: HRD: HRE: HWE: HWR: IA0-IA15: ID0-ID31: INT1-INT4: MRD: MWR: N.C: P0-P3: PWR: RESET: SCK1,SCK2: SI1,SI2: SIAK1,SIAK2: SIEN1,SIEN2: SO1,SO2:
Strobe Clock Input Clock Output Bits Data External Data Memory Address Ground Host Data Access Host Chip Select Host Data Hold Acknowledge Hold Request Host Read Host Read Enable Host Write Enable Host Write Instruction Memory Address Output Instruction Data Input Interrupt Memory Read Output Memory Write Output Connection Port Program Memory Write Strobe Reset Serial Clock Input Serial Data Input Serial Input Acknowledge Serial Input Enable Serial Data Output
SOEN1,SOEN2: Serial Output Enable SORQ1,SORQ2: Serial Output Request TCK: TDI: TDO: TICE: TMS: WAIT: X/Y: Test Clock Input Test Data Input Test Data Output Test In-Circuit Emulator Test Mode Select Power Supply Wait Input Memory Select
µPD77016
Symbol RESET INT4 INT3 INT2 INT1 WAIT HOLDRQ CLKIN CLKOUT BSTB HOLDAK DA15 DA14 DA13 DA12 DA11 DA10 Symbol SIEN1 SCK1 SIAK1 SORQ1 SOEN1 SOEN2 SORQ2 SIAK2 SCK2 SIEN2 Symbol TICE IA15 IA14 IA13 IA12 IA11 IA10 Symbol ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
µPD77016
CONTENTS FUNCTIONS
Functions
Recommended Connection Unused Pins
FUNCTIONS
Pipeline Processing 2.1.1 2.1.2 Outline Instructions with Delay
Program Control Unit Operation Unit 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 General register MAC: Multiply ACcumulator ALU: Arithmetic Logic Unit BSFT: Barrel ShiFTer SAC: Shifter Count Circuit CJC: Condition Judge Circuit Instruction Outline Data Memory Outline Data Memory Addressing Serial Interface Outline Host Interface Outline General Input/output Ports Outline Wait Cycle Register
Memory 2.4.1 2.4.2 2.4.3
On-chip Peripheral Circuit 2.5.1 2.5.2 2.5.3 2.5.4
INSTRUCTIONS
Outline Instruction Operation
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS
µPD77016
FUNCTIONS
Functions Power supply
Symbol 106, 116, 131, 141, 105, 115, 130, 140, power supply Function
Ground
System control
Symbol CLKIN CLKOUT RESET External clock input Internal system clock output Internal system reset signal input Function
Interrupt
Symbol INT4 INT1 Function Maskable external interrupt input Falling edge detection
µPD77016
External data memory interface
Symbol (3S) Function Memory select signal output memory used. memory used. Address external data memory External data memory accessed. During external memory accessed, these pins keep previous level. These pins level; 0x0000, reset. They continue outputting level until first external memory access. bits data external data memory External data memory accessed. Read output Reads external memory Write output Writes external memory Wait signal input Wait cycle input when external memory read. wait Wait Hold request signal input Input level when external data memory expected use. strobe signal output Outputs level while µPD77016 occupying external memory bus. Hold acknowledge signal output Outputs level when µPD77016 permits external device external data memory bus.
DA15
Note
(3S)
Note
(3S) (3S) (3S)
WAIT
HOLDRQ
BSTB
HOLDAK
Note Remark
DA15 pins located pins located state pins added becomes high impedance when external memory accessed release signal (HOLDAK output.
µPD77016
Serial interface
Symbol SCK1 SORQ1 SOEN1 SIEN1 SCK2 SORQ2 SOEN2 SIEN2 SIAK1 SIAK2 (3S) (3S) Clock input serial Serial output request Serial output enable Serial data output Serial input enable Serial data input Clock input serial Serial output request Serial output enable Serial data output Serial input enable Serial data input Serial input acknowledge Serial input acknowledge Function
Remark
state pins added becomes high impedance, when data output have been finished RESET input.
µPD77016
Host interface
Symbol Function Specifies register which access Accesses HST: Host interface status register when Accesses HDT(out): Host transmit data register when Accesses HDT(in): Host receive data register when Specifies bits registers which access Accesses bits 15-8 HST, (out), (in) Accesses bits HST, (out), (in) Chip select input Host read input Host write input Host read enable output Host write enable output bits host data
Remark
(3S)
state pins added becomes high impedance when host does access host interface.
port
Symbol port Function
µPD77016
External instructions memory interface
Symbol IA15 Note (3S) Function Address external instruction memory Even internal instruction memory accessed, address output external instruction memory. this case, µPD77016 ignores data external instruction memory output. bits instruction input Program memory write strobe Write strobe external instruction memory. This loads program external instruction memory (not internal memory) while µPD77016 boot operation.
ID31
Note
(3S) (3S)
Note Remark
IA15 pins located these pins: 104, 114, ID31 pins located these pins: 128, 139, 149, state pins added becomes high impedance when RESET input.
Debugging interface
Symbol TICE debugging debugging debugging debugging debugging Function
µPD77016
Recommended Connection Unused Pins
INT1 INT4 DA15
Note
Note
Recommended connection connect open
connect GND, resistor open connect
MRD, WAIT HOLDRQ BSTB HOLDAK SCK1, SCK2 SI1, SOEN1, SOEN2 SIEN1, SIEN2 SORQ1, SORQ2 SO1, SIAK1, SIAK2 HA0, HRD, HRE, ID31 IA15 TDO, TICE TMS, CLKOUT
open
connect
connect
open
connect connect
open connect GND, resistor
open
connect GND, resistor open open(pull-up internally) open
Notes leave open, access external data memory executed whole program. HALT mode when current consumption reduced, connect recommended connection. leave open, HCS, HRD, fixed high level. HALT mode when current consumption reduced, connect recommended connection. Remark Input pin, Output pin, I/O: Input/Output
µPD77016
FUNCTIONS
Pipeline Processing This section describes PD77016 pipeline processing. 2.1.1 Outline PD77016 basic operations executed following 3-stage pipeline. instruction fetch; Instruction decoding; execution; When PD77016 operates result instruction just executed before, data input parallel with written back general registers. Pipeline processing actualizes programming without delay time execute instructions write back data. Three successive instructions their processing timing shown below. Pipeline Processing Timing
instruction cycle
2.1.2 Instructions with Delay following instructions have delay time execution. Instructions control interrupt instruction cycles have been taken between instruction fetch execution. Inter-register transfer instructions immediate data instructions When data data pointer, needs instruction cycles before data valid.
µPD77016
Program Control Unit Program control unit controls only count program counter normal operation, loop, repeat, branch, halt interrupt. addition loop stack loop level program stack level, software stack used multiloop multi-interrupt/subroutine call. µPD77016 external interruptions internal interruptions from peripheral, specifies interrupt enable disable independently. HALT instruction causes µPD77016 place power standby mode. When HALT instruction executed, power consumption decreases. HALT mode released interrupt input hardware reset input. takes several system clock recover. Operation Unit Operation unit consists following five parts. bits general register data load/store input/output operation data bits bits bits bits multiply accumulator bits Data bits barrel shifter SAC: shifter count circuit. Standard word length bits make overflow check adjustment easy, accumulate result bits bits multiplication correctly.
SSSSSSSS
Head room
Result multiplication among two's complement data
2.3.1 General register PD77016 eight bits registers operation input/output load/store with memory. General register consists following three parts. (bit (bit (bit each RnL, treated register following conditions. General register used bits register General registers treated bits register, when they used following aims. Operand triminal operation (except multiplier input) Operand dyadic operation (except multiplier shift value) Operand monadic operation (except exponent instructions) Operand operation Operand conditional judge Destination load instruction (with sign extension clear)
General register used bits register general register treated bits register, when used operand exponent instruction.
µPD77016
General register used bits register general register treated bits register, when used destination with extended sign load/store instruction. General register used bits register general register treated bits register, when used following aims. Signed operand multiplier Source/destination load/store instruction general register treated bits register, when used following aims. Unsigned operand multiplier Shift value shift instruction Source/destination load/store instruction Source/destination inter-register transfer instruction Hardware loop times Destination immediate data instruction
General register used bits register general register treated bits register, when used source/destination load/ store instruction. 2.3.2 MAC: Multiply ACcumulator multiplies pair bits data, adds subtract result bits data. outputs bits data. operates three types multiplication: signed data signed data, signed data unsigned data unsigned data unsigned data. Result multiplication bits data addition added after bits arithmetic shift right. 2.3.3 ALU: Arithmetic Logic Unit performs arithmetic operation logic operation. Both input/output data bits. 2.3.4 BSFT: Barrel ShiFTer BSFT performs shift right/left operation. Both input/output data bits. There types shift right operations; arithmetic shift right which sign extended, logic shift right which input first. 2.3.5 SAC: Shifter Count Circuit calculates outputs shift value normalization. input bits data outputs bits data. Then, output data always 2.3.6 CJC: Condition Judge Circuit judges whether condition true false with bits input data. conditional instruction executed when result true, executed when result false.
µPD77016
Memory PD77016 instruction memory area (64K words bits) data memory areas (64K words bits each). adopts Harvard-type architecture, with instruction memory area data memory areas separated. PD77016 sets data addressing units, which dedicated addressing data memory area. Each addressing unit consists four data pointers, four index registers, modulo register addressing ALU. Memory areas shown below. memory area addresses specified DP3, memory area addresses specified DP7. After memory access, (with same subscript), modified value. Modulo operation performed with DP3, with DP7.
Data Memory Area (X/Y Memory) 0xFFFF 0xFFFF
Instruction Memory Area
External Data Memory words)
External Instruction Memory words)
0x4000 0x3FFF System 0x3840 0x383F 0x3800 0x37FF
0x4000 0x3FFF
System Peripheral words) 0x0800 0x07FF Internal Instruction (1.5 words) System 0x0240 0x023F 0x0200 0x01FF Data words) 0x0100 0x00FF 0x0000 Vector words) System Bootup (256 words)
0x0800 0x07FF
0x0000
Caution
When data accessed stored system address, normal operation µPD77016 assured.
µPD77016
2.4.1 Instruction Outline µPD77016 instruction (1.5 words bits). system vector area assigned words instruction RAM. Internal initialized rewritten boot program. Additionally external memory expansion available PD77016 interface with external instruction memory. When used external memory, initialized rewritten boot program. Boot contains program loading instruction code internal external instruction RAM. When external instruction memory area accessed, instruction cycle more wait function. 2.4.2 Data Memory Outline PD77016 data memory areas words bits each) memory areas. Each memory areas consists words bits data RAM. Additionally, data memory expansion available PD77016 interface with external data memory. Each data memory area includes on-chip peripheral area which consists words. When external data memory area accessed, instruction cycle more wait function. 2.4.3 Data Memory Addressing There following types data memory addressing. Direct addressing address specified instruction field. Indirect addressing address specified data pointer (DP). reverse before addressing. update value after accessing data memory.
µPD77016
On-chip Peripheral Circuit PD77016 includes serial interface, host interface, general input/output ports wait cycle registers. They mapped both memory areas, accessed memory mapped PD77016 CPU. 2.5.1 Serial Interface Outline PD77016 channel serial interfaces. Serial clock must provided from external. Frame length programmed independently bits bits. first first also selected. Data input/output hand shaking external device, interrupts, polling wait function internal. 2.5.2 Host Interface Outline PD77016 bits parallel ports host interface input/output data from host controller. When external device accesses host interface, pins; which host address input pins; specifies PD77016 includes registers consisting bits, which dedicated input data, output data status. PD77016 three types interface method internal external data; interrupts, polling wait function. 2.5.3 General Input/output Ports Outline General input/output ports consist bits. User each port input output. PD77016 includes registers. bits register input/output data, other bits control. 2.5.4 Wait Cycle Register wait cycle registers consist bits. used wait cycle number when external memory accessed. wait cycle every data area which divided into every memory area which divided into When data area accessed, wait cycle also WAIT pin.
µPD77016
INSTRUCTIONS
Outline PD77016 instructions one-word instructions, consisting bits. they executed (min.) instruction. There following instruction types. Trinomial instructions specify operation. general registers specified optionally operation object. Dyadic operation instructions specify Acc, shifter operation. general registers specified optionally operation object. Some instructions specify general register immediate data. Monadic operation instructions specify operations ALU. general register specified optionally operation object. Load/store instructions transfer bits data from memory general registers, from general registers memory between general registers. Inter-register transfer instructions transfer data between general register other registers. Immediate data instructions immediate data general registers each registers address operation unit. Branch instructions specify direction program flow. Hardware loop instructions specify times instruction repeating. Control Instructions specify control program.
µPD77016
Instruction Operation operation written according rules expressing. expression instructions having more descriptions have only selected. Expressions selectable registers Expression selectable registers shown follows.
Expression ro', dpx_mod dpy_mod dp_imm R0EH R7EH DMX,
Selectable registers
DPn, DPn++, DPn- DPn##, DPn%%, !DPn## DPn, DPn++, DPn- DPn##, DPn%%, !DPn## DPn##imm content memory address Example When content register 1000, shows content memory address 1000.
µPD77016
Modifying data pointers Data pointers modified after memory access. results valid immediately after instruction execution. impossible modify without memory access.
Description DPn++ DPn- DPn##
Operation operation: value does change. DPn+1 DPn-1 DNn: Adds DN0-DN7 corresponding DP0-DP7 Example ((DPL (DMX ((DPL (DMY
DPn%%
!DPn##
Access memory after value bit-reversed After memory access,
DPn##imm
Concurrent processing instructions shows concurrent processing instruction. Instruction names shown abbreviation. DYAD TRANS LOOP Trinomial Dyadic Inter-register transfer Immediate data Branch Hardware loop Control
MONAD Monadic
State Overflow flag (OV) following marks show µPD77016 overflow flag state. affected
Caution
when result operation overflow. overflow does occur after operation, reset, keeps state before operation.
µPD77016 INSTRUCTION
Concurrent Writing Processing Name Mnemonic Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. LOOP. Flag CTL.
Multiply Multiply Sign unsign Multiply Trinomial Unsign unsign Multiply
rhrh' ro-rhrh' rhrl should plus integral number.) ro=ro+rlrl' should plus integral number.) ro=(ro>>1)+rhrh' (ro>>16)+rhrh' ro=rhrh' ro"=ro+ro' ro'=ro+imm ro"=ro-ro' ro'=ro-imm ro'=ro ro'=ro
ro+rhrh' ro-rhrh' ro+rhrl
ro+rlrl'
shift Multiply bits shift Multiply Multiply Immediate Immediate Arithmetic right shift Immediate arithmetic right shift Logic right shift Immediate Logic right shift Logic left shift Immediate logic left shift
+rhrh' +rhrh' rhrh' ro+ro' ro+imm (imm ro-ro' ro-imm (imm
Dyadic
ro'=ro ro'=ro ro'=ro ro'=ro
µPD77016
Concurrent Writing Processing Name Mnemonic if(ro<ro') {ro" 0x0000000001} else {ro" 0x0000000000} 0x0000000000 (ro<0) {ro' -ro} else {ro' (ro>0x007FFFFFFF) {ro' 0x007FFFFFFF] else (ro<0xFF80000000) {ro' 0xFF80000000} else {ro' (ro>0x007FFF0000) {ro' 0x007FFF0000} else (ro>0xFF80000000) {ro' 0xFF80000000} else {ro' 0x8000) 0xFFFFFF0000} log2 Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. LOOP.
Flag CTL.
Immediate Immediate Dyadic Exclusive Immediate exclusive Less than
LT(ro, ro')
Clear Increment Decrement Absolute
CLR(ro) (ro)
One's complement Two's complement Monadic Clip
CLIP (ro)
Round
ROUND (ro)
µPD77016
Exponent Substitution
(ro)
Name Mnemonic Operation TRI. Cumulation Degression Monadic Division ro'+ ro'- ro'/ ro'+ro ro'-ro (sign(ro')==sign(ro)) {ro' (ro'-ro)<<1} else {ro' (ro'+ro)<<1} (sign(ro')==0 {ro' ro'+1} dpx, dpx, dest dpx, dest' dest dpx, source source, dest source, source' Parallel load/store Note1, Note2. ro=dpx_mod ro'=dpy_mod ro=dpx_mod dpy_mod=rh dpx_mod=rh ro=dpy_mod dpx_mod=rh dpy_mod=rh' Load/store Section load/store Note1, Note2, Note dest=dpx_mod dest'=dpy_mod dest=dpx_mod dpy_mod=source dpx_mod=source dest=dpy_mod dpx_mod=source dpy_mod=source'
Concurrent Writing Processing DYAD. MONAD. Load/ store TRANS. IMM. LOOP.
Flag CTL.
Note
both mnemonic pair written. After execution load/store, data modified mod. following mnemonic should selected: dest, dest' {ro, reh, rl}, source, source' {re, rl}.
µPD77016
Concurrent Writing Processing Name Mnemonic Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. LOOP.
Flag CTL.
Direct addressing load/store Note Load/store Immediate index load/store Note
dest addr addr source dest dp_imm dp_imm source
dest addr addr source dest source dest source
Inter-register transfer
Inter-register transfer Note
dest source
Immediate data
(provided 0-0xFFFF) (provided 0-0xFFFF) (provided 0-0xFFFF) (provided 1-0xFFFF)
Immediate data
Note
following mnemonic should selected: dest {ro, reh, rl}, source {re, rl}, following mnemonic should selected: dest {ro, reh, rl}, source {re, rl}. register except general registers should selected dest source.
X-0xFFFF:X memory Y-0xFFFF:Y memory
µPD77016
Name Mnemonic Operation TRI. Jump Inter-register indirect jump Subroutine call CALL Restore interrupt enable flag start repeat count count Branch Inter-register indirect subroutine call CALL Return Return from interrupt RETI Repeat count Loop Hardware loop LOOP count (Mnemonics more than lines) start repeat Loop LPOP LSR3 LSR2 LSR1 LSP-1 stop Conditional judge Control operation Halt Forget interrupt HALT cond) FINT Forget interrupt request
Concurrent Writing Processing DYAD. MONAD. Load/ store TRANS. IMM. LOOP.
Flag CTL.
µPD77016
µPD77016
ELECTRICAL SPECIFICATIONS
Absolute maximum ratings
Parameters Power supply voltage Input voltage Output voltage Storage temperature Operating ambient temperature Symbol Conditions Ratings -0.5 +7.0 -0.5 -0.5 +150 Unit
Caution
Exposure Absolute Maximum Ratings extended periods affect device reliability; exceeding ratings could cause permanent damage. parameters apply independently. device should operated within limits specified under Characteristics.
Capacitance
Parameters Input capacitance Output capacitance Symbol Conditions Unmeasured pins returned MIN. TYP. MAX. Unit
characteristics (TA=-40
Parameters High level input voltage Symbol Conditions except RESET, CLKIN, INT1 INT4, WAIT, HCS, HRD, HWR, TCK, TDI, RESET, INT1 INT4, WAIT, HCS, HRD, HWR, TCK, TDI, except RESET, CLKIN, INT1 INT4, WAIT, HCS, HRD, HWR, TCK, TDI, RESET, INT1 INT4, WAIT, HCS, HRD, HWR, TCK, TDI, MIN. TYP. MAX. Unit
0.7V
level input voltage
-0.5
+0.8
-0.5
0.2V
High level CLKIN voltage level CLKIN voltage High level output voltage level output voltage level input current High level input leak current level input leak current Power supply current
Note -2.5 TDI, TMS, except TDI, TMS, Active mode, load HALT mode, load CLKIN load
0.8V -0.5 0.8V
0.2V
-400
Note
TYP. value measured when general program executed, conditon. MAX. value measured when special program that max. switching required executed, condition
µPD77016
Measurement Standards Common Switching Characteristics
CLKIN
Test points
Input (except CLKIN)
Test points
Output
Test points
Characteristics ±10%,
Clock
Required Timing Condition
Parameters CLKIN cycle time CLKIN high level width CLKIN level width CLKIN rise/fall time Symbol wCIH wCIL rfCI Conditions MIN. 6.75 6.75 TYP. MAX. 0.55 0.55 Unit
Switching Characteristics
Parameters CLKOUT cycle time CLKOUT level width CLKOUT rise/fall time Symbol rfCO Conditions MIN. TYP. MAX. Unit
µPD77016
Reset, Interrupt
Required Timing Condition
Parameters RESET level width RESET recovery time INT1-INT4 level width INT1-INT4 recovery time Symbol w(RL) rec(R) w(INTL) rec(INT) Conditions MIN. TYP. MAX. Unit
Clock Input/Output Timing
tcCI trfCI twCIH CLKIN twCIL trfCI
tcCO twCO CLKOUT twCO trfCO trfCO
Reset, Interrupt Timing
tw(RL) RESET trec(R)
Interrupt Timing
trec(INT) tw(INTL) INT1 INT4
µPD77016
External Data Memory Access
Required Timing Condition
Parameters Read data setup time Read data hold time WAIT setup time WAIT hold time Symbol suDDRD hDDRD suWA Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters Address output delay time output delay time hold time Write data setup time Symbol sDDWD Conditions MIN. wCIH cDWNote wCIH wCIL cDWNote TYP. MAX. Unit
Write data output hold time output delay time setup time level width
hDDWD suDW wDWL
high level width
wDWH
Note Data wait cycle
µPD77016
External Data Memory Read Operation
CLKOUT
tdDA DA15,
tsuDDRD
thDDRD
tdDR
thDR
tsuWA
thWA
tsuWA
thWA
WAIT
External Data Memory Write Operation
CLKOUT
tdDA
DA15,
tsDDWD Hi-Z
thDDWD Hi-Z
tdDW twDWL
tsuDW twDWH
tsuWA
thWA
tsuWA
thWA
WAIT
µPD77016
External Instruction Memory Access Required Timing Condition
Parameters setup time CLKOUT hold time CLKOUT Symbol suID Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters output delay time hold time write setup time write hold time output delay time Address setup time setup time width Symbol sIDW hIDW d(IAV-IWV) suIW wCIH wCIL wCIH Conditions MIN. TYP. MAX. Unit
Remark cIW: Instruction wait cycle
µPD77016
External Instruction Memory Read Operation
CLKOUT
thIA tdIA IA15 Hi-Z
tsuID
thID
ID31
tdIW
Hi-Z
RESET
External Instruction Memory Write Operation
CLKOUT
thIA
IA15
thIDW tsIDW Hi-Z Hi-Z
ID31
td(IAV-IW twIW
tsuIW
µPD77016
Arbitration
Required Timing Condition
Parameters HOLDRQ setup time HOLDRQ hold time Symbol suHRQ hHRQ Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters BSTB hold time BSTB output delay time HOLDAK output delay time HOLDAK hold time Data hold time when arbitration Data valid time after arbitration Symbol dHAK hHAK h(BS-D) v(BS-D) Conditions MIN. TYP. MAX. Unit
Arbitration Timing (Bus idle)
CLKOUT
(Bus busy)
idle
release
idle
(Bus busy)
thBS
tdBS
BSTB tsuHRQ HOLDRQ tdHAK thHAK thHRQ tsuHRQ thHRQ
HOLDAK th(BS-D) X/Y, DA15, MRD, Hi-Z tv(BS-D)
µPD77016
Arbitration Timing (Bus busy)
CLKOUT
(Bus busy)
busy
idle
release
idle
(Bus busy)
thBS
tdBS
BSTB tsuHRQ thHRQ HOLDRQ thHAK tsuHRQ thHRQ
tdHAK HOLDAK th(BS-D) X/Y, DA15, MRD, Hi-Z
tv(BS-D)
µPD77016
Arbitration Timing (Bus slave)
CLKOUT
Load/store External Memory
idle
hold
idle
BSTB
HOLDRQ
X/Y, DA15, MRD,
Hi-Z
Hi-Z
HOLDAK
µPD77016
µPD77016
Serial Interface Required Timing Condition
Parameters input cycle time input high/low level width input rise/fall time SOEN recovery time SOEN hold time SIEN recovery time SIEN hold time setup time hold time Symbol rfSC recSOE hSOE recSIE hSIE suSI Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters SORQ output delay time SORQ hold time valid time hold time SIAK output delay time SIAK hold time Symbol dSOR hSOR dSIA hSIA Conditions MIN. TYP. MAX. Unit
Notes Serial Clock Serial clock inputs SCK1 SCK2 sensitive kind interfering signals (noise power supply, induced voltage, etc.). Spurious signals cause malfunction device. Special care serial clock design should taken. Careful grounding, decoupling short wiring SCK1 SCK2 recommended. Intersection SCK1 SCK2 with other serial interface lines close wiring lines carrying high frequency signals large changing currents should avoided. considers serial clock make waveform stable especially about rising falling.
Example good example Straight rising form falling form
Example good example doesn't bound. doesn't make noise above another.
Example good example doesn't make stair stepping.
Serial Output Timing
tcSC twSC SCK1, SCK2 tdSOR thSOR twSC
trfSC
trfSC
SORQ1, SORQ2 trecSOE trecSOE thSOE thSOE SOEN1, SOEN2
tvSO
tvSO
thSO
SO1,
Hi-Z
Last
Hi-Z
µPD77016
Serial Output Timing (Continual output)
tcSC twSC SCK1, SCK2 tdSOR thSOR twSC
trfSC
trfSC
SORQ1, SORQ2 trecSOE thSOE
SOEN1, SOEN2
tvSO Hi-Z
SO1,
Last
Last
µPD77016
Serial Input Timing
tcSC twSC SCK1, SCK2 tdSIA thSIA twSC
trfSC
trfSC
SIAK1, SIAK2 trecSIE trecSIE thSIE thSIE
SIEN1, SIEN2
tsuSI
thSI
SI1,
µPD77016
Serial Input Timing (Continual input)
tcSC twSC SCK1, SCK2 tdSIA thSIA twSC
trfSC
trfSC
SIAK1, SIAK2 trecSIE thSIE SIEN1, SIEN2
tsuSI
thSI
SI1,
Last-1
Last
µPD77016
µPD77016
Host Interface Required Timing Condition
Parameters delay time width HCS, HA0, read hold time HCS, HA0, write hold time HRD, recovery time delay time width hold time setup time Symbol hHCAR hHCAW recHS hHDW suHDW Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters HRE, output delay time HRE, hold time valid time hold time Symbol vHDR hHDR Conditions MIN. TYP. MAX. Unit
Host Read Interface Timing
CLKOUT
HCS, HA0,
thHCAR tdHR twHR trecHS
thHDR
tvHDR Hi-Z Hi-Z
tdHE
thHE
µPD77016
Host Write Interface Timing
CLKOUT
HCS, HA0,
thHCAW tdHW
twHW
trecHS
thHDW tsuHDW
tdHE thHE
µPD77016
µPD77016
General Input/Output Ports Required Timing Condition
Parameters Port input setup time Port input hold time Symbol suPI Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters Port output delay time Symbol Conditions MIN. TYP. MAX. Unit
General Input/Output Ports Timing
CLKOUT
tdPO (Output) tsuPI thPI (Input)
µPD77016
Debugging Interface (JTAG)
Required Timing Condition
Parameters cycle time high level width level width rise/fall time TMS, setup time TMS, hold time Input setup time Input hold time Symbol cTCK wTCKH wTCKL rfTCK suDI suJIN hJIN Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters output delay time Output output delay time Symbol dJOUT Conditions MIN. TYP. MAX. Unit
Debugging Interface Timing
tcTCK twTCKH twTCKL trfTCK trfTCK
tsuDI TMS,
thDI
Valid
Valid
Valid
tdDO
tsuJIN
thJIN
Capture state
Valid
tdJOUT
Update state
Remark details JTAG, refer "IEEE1149.1."
µPD77016
PACKAGE DRAWING
PLASTIC (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 26.0±0.2 24.0±0.2 24.0±0.2 26.0±0.2 2.25 2.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 0.4±0.1 INCHES 1.024+0.008 -0.009 0.945±0.008 0.945±0.008 1.024+0.008 -0.009 0.089 0.089 0.009±0.002 0.004 0.020 (T.P.) 0.039+0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.106 0.016 +0.004 -0.005
MAX. 0.130 MAX. S160GM-50-JMD,KMD
µPD77016
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, highly recommended observe conditions shown below. other soldering processes used, soldering performed under different conditions, please make sure consult with sales offices. more details, refer document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Surface mount device
PD77016GM-KMD: 160-pin plastic (FINE PITCH)
Process Infrared reflow Conditions Peak temperature: below (Package surface temperature), Reflow time: seconds less higher), Maximum number reflow processes: time, Exposure limitNote days hours pre-baking required afterwards). Peak temperature: below (Package surface temperature), Reflow time: seconds less higher), Maximum number reflow processes: time, Exposure limitNote days hours pre-baking required afterwards). Partial heating method temperature: below, Heat time: seconds less (Per each side device). VP15-207-1 Symbol IR35-207-1
Note Maximum allowable time from taking soldering package pack soldering. Storage conditions: relative humidity less. Caution Apply only kind soldering condition device, except "partial heating method", device will damaged heat stress.
µPD77016
[MEMO]
µPD77016
[MEMO]
µPD77016
[MEMO]
µPD77016
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD77016
[MEMO]
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD77016 bits, Fixed-point Digital Signal Processor µPD77016

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