µPD77015,77017,77018 bits, Fixed-point Digital Signal Processor

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µPD77015,77017,77018 bits, Fixed-point Digital Signal Processor

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INTEGRATED CIRCUIT
µPD77015,77017,77018
bits, Fixed-point Digital Signal Processor
µPD77015, 77017, 77018 bits fixed-point DSPs (Digital Signal Processors) developed digital signal
processing with demand high speed precision.
FEATURES
FUNCTIONS
Instruction cycle: (MIN.) Operation clock: External clock: 16.5, 8.25, 4.125 Crystal: On-chip provide higher operation clock than external clock Dual load/store Hardware loop function Conditional execution Executes product-sum operation instruction cycle
PROGRAMMING
bits bits bits bits multiply accumulator general registers bits each) ROM/RAM data pointer: each data memory area registers source interrupts (external: internal: operand instructions (example: +R1LR2L) Nonpipeline execution stage
MEMORY AREAS
Instruction memory area words bits Data memory areas words bits memory, memory)
CLOCK GENERATOR
Mask option CLKOUT pin: Fixed level. Does output internal system clock. Selectable source clock: external clock input crystal resonator [External clock] On-chip provide higher operation clock MAX.) than external clock. Variable multiple rates mask option. [Crystal resonator] Oscillation frequency corresponds directly system clock frequency (Sure specify mask option frequency multiple "1"). this document, descriptions PD77017 also apply PD77015 PD77018, unless otherwise specified.
information this document subject change without notice. Document U10902EJ3V0DS00 (3rd edition) Date Published June 1997 Printed Japan mark shows major revised points.
1993, 1994
µPD77015, 77017, 77018
ON-CHIP PERIPHERAL
port: bits Serial bits): channels Host bits): channel
CMOS single power supply ORDERING INFORMATION
Part Number Package 100-pin plastic TQFP (FINE PITCH) 100-pin plastic TQFP (FINE PITCH) 100-pin plastic TQFP (FINE PITCH)
Remark indicates code suffix.
BLOCK DIAGRAM
X-Bus
External Memory
Y-Bus
Serial
Memory Data Pointers
Memory
Memory Data Pointers
Memory
R0-R7
Serial Main (40)
Ports Loop Control Stack Instruction Memory
Stack
Interrupt Control Host
µPD77015, 77017, 77018
Control
Wait Controller INT1 INT4
WAIT RESET CLKOUT
µPD77015, 77017, 77018
FUNCTIONAL GROUPS
SORQ1 SOEN1 Serial Interface SCK1 SIEN1 SIAK1 SOEN2 SCK2 SIEN2
RESET INT1 INT2 INT3 INT4 CLKOUT TDO, TICE TCK, TDI, HOLDRQ
Interrupts
Serial Interface
Debugging Interface
Ports
BSTB HOLDAK DA13 WAIT
Data Control
Host Interface
HA0,
(14) (16)
External Data Memory
Functional Differences among Family
Item Internal instruction Internal instruction External instruction memory Data (X/Y memory) Data (X/Y memory) External data memory Instruction cycle (Maximum operation speed) External clock maximum operation speed) Crystal maximum operation speed) Instruction Serial interface Channels)
PD77016
1.5K words None words words each None words each
PD77015
PD77017
words
PD77018
PD77018A
PD77019
words
words
words None
words
words each words each
words each words each words each
words each words each
MHz) 33/16.5/8.25/4.125 Variable multiple rate mask option.
MHz) 17.333/ 13/6.5 Variable multiple rate mask option. STOP instruction added.
Channel same functions channel 160-pin plastic
Channel same functions that PD77016. Channel SORQ2 SIAK2 (Channel used CODEC connection).
Power supply Package
µPD77015, 77017, 77018
100-pin plastic TQFP
µPD77015, 77017, 77018
CONFIGURATION
100-pin plastic TQFP (FINE PITCH) (Top View)
HOLDRQ
HOLDAK
CLKOUT
BSTB
WAIT
TICE
RESET INT4 INT3 INT2 INT1 I.C. DA13 DA12 DA11 DA10
SIEN2 SCK2 SOEN2 SOEN1 SORQ1 SIAK1
SIEN1
SCK1
µPD77015, 77017, 77018
IDENTIFICATION
BSTB: CLKOUT: D0-D15: DA0-DA13: GND: HA0,HA1: HCS: HD0-HD7: HOLDAK: HOLDRQ: HRD: HRE: HWE: HWR: I.C.: INT1-INT4: MRD: MWR: P0-P3: RESET: SCK1,SCK2: SI1,SI2: SIAK1: SIEN1,SIEN2: SO1,SO2: SORQ1: TCK: TDI: TDO: TICE: TMS: WAIT: X/Y:
Strobe Clock Output Bits Data External Data Memory Address Ground Host Data Access Host Chip Select Host Data Hold Acknowledge Hold Request Host Read Host Read Enable Host Write Enable Host Write Internally connection Interrupt Memory Read Output Memory Write Output Port Reset Serial Clock Input Serial Data Input Serial Input Acknowledge Serial Input Enable Serial Data Output Serial Output Request Test Clock Input Test Data Input Test Data Output Test In-Circuit Emulator Test Mode Select Power Supply Wait Input Clock input/crystal connection Crystal connection Memory Select
SOEN1,SOEN2: Serial Output Enable
µPD77015, 77017, 77018
NAME
Symbol RESET INT4 INT3 INT2 INT1 I.C. DA13 DA12 DA11 DA10
Note
Symbol SIEN1 SCK1
Symbol SIAK1 SORQ1 SOEN1 SOEN2 SCK2 SIEN2
Symbol CLKOUT TICE HOLDRQ HOLDAK BSTB WAIT
Note I.C. (Internally Connected): Leave this open.
µPD77015, 77017, 77018
CONTENTS FUNCTIONS
Functions Recommended Connection Unused Pins
FUNCTIONS
Pipeline Processing 2.1.1 2.1.2 Outline Instructions with Delay
Program Control Unit Operation Unit 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 General register MAC: Multiply ACcumulator ALU: Arithmetic Logic Unit BSFT: Barrel ShiFTer SAC: Shifter Count Circuit CJC: Condition Judge Circuit Instruction Outline Data Memory Outline Data Memory Addressing Serial Interface Outline Host Interface Outline General Input/output Ports Outline Wait Cycle Register
Memory 2.4.1 2.4.2 2.4.3
On-chip Peripheral Circuit 2.5.1 2.5.2 2.5.3 2.5.4
INSTRUCTIONS
Outline Instruction Operation
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS
µPD77015, 77017, 77018
FUNCTIONS
Functions Power supply
Symbol Function
power supply
Ground
System control
Symbol Function Clock input crystal connection clock signal connected when using external clock system clock. Crystal connection should left open when using external clock system clock. Internal system clock output Internal system reset signal input
CLKOUT RESET
Interrupt
Symbol INT4 INT1 Function Maskable external interrupt input Falling edge detection
µPD77015, 77017, 77018
External data memory interface
Symbol (3S) Function Memory select signal output memory used. memory used. Address external data memory External data memory accessed. During external memory accessed, these pins keep previous level. These pins level; 0000H, reset. They continue outputting level until first external memory access. bits data external data memory External data memory accessed. Read output Reads external memory Write output Writes external memory Wait signal input Wait cycle input when external memory read. wait Wait Hold request signal input Input level when external data memory expected use. strobe signal output Outputs level while µPD77017 occupying external memory bus. Hold acknowledge signal output Outputs level when µPD77017 permits external device external data memory bus.
DA13
-19,
(3S)
-29,
(3S) (3S) (3S)
WAIT
HOLDRQ
BSTB
HOLDAK
Remark
state pins added becomes high impedance when release signal (HOLDAK output.
µPD77015, 77017, 77018
Serial interface
Symbol SCK1 SORQ1 SOEN1 SIEN1 SCK2 SOEN2 SIEN2 SIAK1 (3S) (3S) Clock input serial Serial output request Serial output enable Serial data output Serial input enable Serial data input Clock input serial Serial output enable Serial data output Serial input enable Serial data input Serial input acknowledge Function
Remark
state pins added becomes high impedance, when data output have been finished RESET input.
µPD77015, 77017, 77018
Host interface
Symbol Function Specifies register which access Accesses HST: Host interface status register when Accesses HDT(in): Host transmit data register when Accesses HDT(out): Host receive data register when Specifies bits registers which access Accesses bits 15-8 HST, HDT(in) HDT(out) Accesses bits HST, HDT(in) HDT(out) Chip select input Host read input Host write input Host read enable output Host write enable output bits host data
Remark
(3S)
state pins added becomes high impedance when host does access host interface.
port
Symbol port Function
µPD77015, 77017, 77018
Debugging interface
Symbol TICE debugging debugging debugging debugging debugging Function
Other
Symbol I.C. Function Internal connected pin. Leave this open.
Caution When signal applied read from this pin, normal operation µPD77017 assured.
µPD77015, 77017, 77018
Recommended Connection Unused Pins
INT1 INT4 DA13 WAIT HOLDRQ BSTB HOLDAK SCK1, SCK2 SI1, SOEN1, SOEN2 SIEN1, SIEN2 SORQ1 SO1, SIAK1 HA0, Note2 Note1 connect GND, resistor open open(pull-up internally) open connect GND, resistor open connect connect open connect connect open connect connect GND, resistor open Recommended connection connect open
TDO, TICE TMS, CLKOUT
Note Remark
leave open, access external data memory executed whole program. leave open, HCS, HRD, fixed high level. Input Output
I/O: Input/Output
µPD77015, 77017, 77018
FUNCTIONS
Pipeline Processing This section describes PD77017 pipeline processing. 2.1.1 Outline µPD77017 basic operations executed following 3-stage pipeline. instruction fetch; Instruction decoding; execution; When PD77017 operates result instruction just executed before, data input parallel with written back general registers. Pipeline processing actualizes programming without delay time execute instructions write back data. Three successive instructions their processing timing shown below. Pipeline Processing Timing
instruction cycle
2.1.2 Instructions with Delay following instructions have delay time execution. Instructions control interrupt instruction cycles have been taken between instruction fetch execution. Inter-register transfer instructions immediate data instructions When data data pointer, needs instruction cycles before data valid.
µPD77015, 77017, 77018
Program Control Unit Program control unit controls only count program counter normal operation, loop, repeat, branch, halt interrupt. addition loop stack loop level program stack level, software stack used multiloop multi-interrupt/subroutine call. µPD77017 external interruptions internal interruptions from peripheral, specifies interrupt enable disable independently. HALT STOP instructions cause PD77017 place power standby mode. When HALT instruction executed, power consumption decreases. HALT mode released interrupt input hardware reset input. takes several system clock recover. When STOP instruction executed, power consumption decreases. STOP mode released hardware reset input. takes recover. Operation Unit Operation unit consists following five parts. bits general register data load/store input/output operation data bits bits bits bits multiply accumulator bits Data bits barrel shifter SAC: shifter count circuit. Standard word length bits make overflow check adjustment easy, accumulate result bits bits multiplication correctly.
SSSSSSSS
Head room
Result multiplication among two's complement data
2.3.1 General register PD77017 eight bits registers operation input/output load/store with memory. General register consists following three parts. (bit (bit (bit each RnL, treated register following conditions. General register used bits register General registers treated bits register, when they used following aims. Operand triminal operation (except multiplier input) Operand dyadic operation (except multiplier shift value) Operand monadic operation (except exponent instructions) Operand operation Operand conditional judge Destination load instruction (with sign extension clear)
µPD77015, 77017, 77018
General register used bits register general register treated bits register, when used operand exponent instruction. General register used bits register general register treated bits register, when used destination with extended sign load/store instruction. General register used bits register general register treated bits register, when used following aims. Signed operand multiplier Source/destination load/store instruction general register treated bits register, when used following aims. Unsigned operand multiplier Shift value shift instruction Source/destination load/store instruction Source/destination inter-register transfer instruction Hardware loop times Destination immediate data instruction
General register used bits register general register treated bits register, when used source/destination load/ store instruction. 2.3.2 MAC: Multiply ACcumulator multiplies pair bits data, adds subtract result bits data. outputs bits data. operates three types multiplication: signed data signed data, signed data unsigned data unsigned data unsigned data. Result multiplication bits data addition added after bits arithmetic shift right. 2.3.3 ALU: Arithmetic Logic Unit performs arithmetic operation logic operation. Both input/output data bits. 2.3.4 BSFT: Barrel ShiFTer BSFT performs shift right/left operation. Both input/output data bits. There types shift right operations; arithmetic shift right which sign extended, logic shift right which input first. 2.3.5 SAC: Shifter Count Circuit calculates outputs shift value normalization. input bits data outputs bits data. Then, output data always
µPD77015, 77017, 77018
2.3.6 CJC: Condition Judge Circuit judges whether condition true false with bits input data. conditional instruction executed when result true, executed when result false. Memory µPD77017 instruction memory area (64K words bits) data memory areas (64K words bits each). adopts Harvard-type architecture, with instruction memory area data memory areas separated. PD77017 sets data addressing units, which dedicated addressing data memory area. Each addressing unit consists four data pointers, four index registers, modulo register addressing ALU. memory area addresses specified DP3, memory area addresses specified DP7. After memory access, (with same subscript), modified value. Modulo operation performed with DP3, with DP7.
µPD77015, 77017, 77018
2.4.1 Instruction Outline PD77015 instruction words bits) instruction RAM( words bits). PD77017 instruction (12K words bits) instruction RAM( words bits). PD77018 instruction (24K words bits) instruction RAM( words bits). system vector area assigned words instruction RAM. Internal instruction initialized rewritten boot program. Boot contains program loading instruction code internal instruction RAM.
PD77015
FFFFH
PD77017
PD77018
System (24K words)
System (36K words) System (44K words) A000H 9FFFH
7000H 6FFFH Internal Instruction (12K words)
Internal Instruction (24K words)
5000H 4FFFH 4000H 3FFFH
Internal Instruction words)
System (15.25K words)
System (15.25K words)
System (15.25K words)
0300H 02FFH 0240H 023FH 0200H 01FFH 0100H 00FFH 0000H
Internal Instruction (256 words) Vector words) System (256 words) Bootup (256 words)
Internal Instruction (256 words) Vector words) System (256 words) Bootup (256 words)
Internal Instruction (256 words) Vector words) System (256 words) Bootup (256 words)
Caution
When data accessed stored system address, normal operation device assured.
µPD77015, 77017, 77018
2.4.2 Data Memory Outline PD77015 data memory areas (64K words bits each) memory areas. Each memory areas consists words bits data words bits data
PD77017 interface with external data memory, words bits external data memory space
memories. PD77017 data memory areas (64K words bits each) memory areas. Each memory areas consists words bits data words bits data
PD77017 interface with external data memory, words bits external data memory space
memories. PD77018 data memory areas (64K words bits each) memory areas. Each memory areas consists words bits data words bits data
PD77018 interface with external data memory, words bits external data memory space
memories. Each data memory area includes on-chip peripheral area which consists words. When external data memory area accessed, instruction cycle more wait function.
PD77015
FFFFH
PD77017
PD77018
External Data Memory (16K words) C000H BFFFH
External Data Memory (16K words)
External Data Memory (16K words)
System (20K words) System (30K words) System (28K words)
7000H 6FFFH 4800H 47FFH 4000H 3FFFH 3840H 383FH 3800H 37FFH Peripheral words) Peripheral words) 5000H 4FFFH Data words) System (1984 words) Data words) System (1984 words) Data (12K words)
System (1984 words) Peripheral words)
System (13K words)
System (12K words) 0C00H 0BFFH Data words)
System (11K words)
0400H 03FFH 0000H
0800H 07FFH Data words)
Data words)
Caution
When data accessed stored system address, normal operation device assured.
µPD77015, 77017, 77018
2.4.3 Data Memory Addressing There following types data memory addressing. Direct addressing address specified instruction field. Indirect addressing address specified data pointer (DP). reverse before addressing. update value after accessing data memory. On-chip Peripheral Circuit PD77017 includes serial interface, host interface, general input/output ports wait cycle registers. They mapped both memory areas, accessed memory mapped µPD77017 CPU. 2.5.1 Serial Interface Outline PD77017 channel serial interfaces. Serial clock must provided from external. Frame length programmed independently bits bits. first first also selected. Data input/output hand shaking external device, interrupts, polling wait function internal. 2.5.2 Host Interface Outline PD77017 bits parallel ports host interface input/output data from host controller. When external device accesses host interface, pins; which host address input pins; specifies µPD77017 includes registers consisting bits, which dedicated input data, output data status. PD77017 three types interface method internal external data; interrupts, polling wait function. 2.5.3 General Input/output Ports Outline General input/output ports consist bits. User each port input output. µPD77017 includes registers. bits register input/output data, other bits control. 2.5.4 Wait Cycle Register wait cycle registers consist bits. used wait cycle number when external memory accessed. When external data memory area (C000H FFFFH) accessed, wait cycle set. When external data memory area accessed, wait cycle also WAIT pin.
µPD77015, 77017, 77018
INSTRUCTIONS
Outline µPD77017 instructions one-word instructions, consisting bits. they executed (min.) instruction. There following instruction types. Trinomial instructions specify operation. general registers specified optionally operation object. Dyadic operation instructions specify Acc, shifter operation. general registers specified optionally operation object. Some instructions specify general register immediate data. Monadic operation instructions specify operations ALU. general register specified optionally operation object. Load/store instructions transfer bits data from memory general registers, from general registers memory between general registers. Inter-register transfer instructions transfer data between general register other registers. Immediate data instructions immediate data general registers each registers address operation unit. Branch instructions specify direction program flow. Hardware loop instructions specify times instruction repeating. Control Instructions specify control program.
µPD77015, 77017, 77018
Instruction Operation operation written according rules expressing. expression instructions having more descriptions have only selected. Expressions selectable registers Expression selectable registers shown follows.
Expression ro', dpx_mod dpy_mod dp_imm
Selectable registers R0EH R7EH DMX, DPn, DPn++, DPn- DPn##, DPn%%, !DPn## DPn, DPn++, DPn- DPn##, DPn%%, !DPn## DPn##imm content memory address Example When content register 1000, shows content memory address 1000.
µPD77015, 77017, 77018
Modifying data pointers Data pointers modified after memory access. results valid immediately after instruction execution. impossible modify without memory access.
Description DPn++ DPn- DPn##
Operation operation: value does change. DPn+1 DPn-1 DNn: Adds DN0-DN7 corresponding DP0-DP7 Example ((DPL )mod (DMX ((DPL )mod (DMY
DPn%%
!DPn##
Access memory after value bit-reversed After memory access,
DPn##imm
Concurrent processing instructions shows concurrent processing instruction. Instruction names shown abbreviation. DYAD TRANS LOOP Trinomial Dyadic Inter-register transfer Immediate data Branch Hardware loop Control
MONAD Monadic
State Overflow flag (OV) following marks show µPD77017 overflow flag state. affected when result operation overflow. overflow does occur after operation, reset, keeps state before operation.
Caution
µPD77017 INSTRUCTION
Concurrent Writing Processing Name Mnemonic Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. LOOP. Flag CTL.
Multiply Multiply Sign unsign Multiply Trinomial Unsign unsign Multiply
rhrh' ro-rhrh' rhrl should plus integral number.) ro=ro+rlrl' should plus integral number.) ro=(ro>>1)+rhrh' (ro>>16)+rhrh' ro=rhrh' ro"=ro+ro' ro'=ro+imm ro"=ro-ro' ro'=ro-imm ro'=ro ro'=ro
ro+rhrh' ro-rhrh' ro+rhrl
ro+rlrl'
shift Multiply bits shift Multiply Multiply Immediate Immediate Arithmetic right shift Immediate arithmetic right shift Logic right shift Immediate Logic right shift Logic left shift Immediate logic left shift
+rhrh' +rhrh' rhrh' ro+ro' ro+imm (imm1) ro-ro' ro-imm (imm1)
Dyadic
µPD77015, 77017, 77018
ro'=ro ro'=ro ro'=ro ro'=ro
Concurrent Writing Processing Name Mnemonic if(ro<ro') {ro" 0000000001H} else {ro" 0000000000H} (ro<0) {ro' -ro} else {ro' (ro>007FFFFFFFH) {ro' 007FFFFFFFH] else (ro<FF80000000H) {ro' FF80000000H} else {ro' (ro>007FFF0000H) {ro' 007FFF0000H} else (ro>FF80000000H) {ro' FF80000000H} else {ro' 8000H) FFFFFF0000H} log2 Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. LOOP.
Flag CTL.
Immediate Immediate Dyadic Exclusive Immediate exclusive Less than
LT(ro, ro')
Clear Increment Decrement Absolute
CLR(ro) (ro)
One's complement Two's complement Monadic Clip
CLIP (ro)
µPD77015, 77017, 77018
Round
ROUND (ro)
Exponent Substitution
(ro)
Name Mnemonic Operation TRI. Cumulation Degression Monadic Division ro'+ ro'- ro'/ ro'+ro ro'-ro (sign(ro')==sign(ro)) {ro' (ro'-ro)<<1} else {ro' (ro'+ro)< (sign(ro')==0 {ro' ro'+1} dpx, dpx, dest dpx, dest' dest dpx, source source, dest source, source' Parallel load/store Note Note ro=dpx_mod ro'=dpy_mod ro=dpx_mod dpy_mod=rh dpx_mod=rh ro=dpy_mod dpx_mod=rh dpy_mod=rh' Load/store Section load/store Note Note Note dest=dpx_mod dest'=dpy_mod dest=dpx_mod dpy_mod=source dpx_mod=source dest=dpy_mod dpx_mod=source dpy_mod=source'
Concurrent Writing Processing DYAD. MONAD. Load/ store TRANS. IMM. LOOP.
Flag CTL.
Note
both mnemonic pair written.
µPD77015, 77017, 77018
After execution load/store, data modified mod. following mnemonic should selected: dest, dest' {ro, reh, rl}, source, source' {re, rl}.
Concurrent Writing Processing Name Mnemonic Operation TRI. DYAD. MONAD. Load/ store TRANS. IMM. LOOP.
Flag CTL.
Direct addressing load/store Note Load/store Immediate index load/store Note
dest addr addr source dest dp_imm dp_imm source
dest addr addr source dest source dest source
Inter-register transfer
Inter-register transfer Note
dest source
Immediate data
(provided 0-0xFFFF) (provided 0-0xFFFF) (provided 0-0xFFFF) (provided 1-0xFFFF)
Immediate data
Note
following mnemonic should selected: dest {ro, reh, rl}, source {re, rl}, following mnemonic should selected: dest {ro, reh, rl}, source {re, rl}. register except general registers should selected dest source.
X-0xFFFF:X memory Y-0xFFFF:Y memory
µPD77015, 77017, 77018
Name Mnemonic Operation TRI. Jump Inter-register indirect jump Subroutine call CALL Restore interrupt enable flag start repeat count count Branch Inter-register indirect subroutine call CALL Return Return from interrupt RETI Repeat count Loop Hardware loop LOOP count (Mnemonics more than lines) start repeat Loop LPOP LSR3 LSR2 LSR1 LSP-1 stop
Note1 Note2
Concurrent Writing Processing DYAD. MONAD. Load/ store TRANS. IMM. LOOP.
Flag CTL.
µPD77015, 77017, 77018
operation Halt Control Stop Forget interrupt
HALT STOP cond) FINT
CPU, PLL, Stop Conditional judge
Forget interrupt requests
µPD77015, 77017, 77018
Note HALT instruction causes function except clock halt. system placed much less power consumption mode. contents internal registers memories maintained. HALT released interrupt input. takes several system clock recover. STOP instruction causes function including clock stop. system placed minimum-power consumption mode. contents internal registers memories maintained. After STOP instruction executed, status maintained. STOP released hardware reset. takes recover.
µPD77015, 77017, 77018
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameters Power supply voltage Input voltage Output voltage Storage temperature Operating ambient temperature Symbol Conditions Ratings -0.5 +4.6 -0.5 +4.1 +0.5 -0.5 +4.6 +150 Unit
Caution
Exposure Absolute Maximum Ratings extended periods affect device reliability; exceeding ratings could cause permanent damage. parameters apply independently. device should operated within limits specified under Characteristics.
Recommended Operating Conditions
Parameters Operating voltage Input voltage Symbol Conditions MIN. TYP. MAX. Unit
Capacitance
Parameters Input capacitance Output capacitance Input/output capacitance Symbol Conditions Unmeasured pins returned MIN. TYP. MAX. Unit
µPD77015, 77017, 77018
Characteristics
Parameters High level input voltage High level input voltage level input voltage High level output voltage Symbol -2.0 -100 level output voltage High level input leak current level input leak current Pull-up current Power supply current DDNote Except TDI, TMS, Except TDI, TMS, TDI, TMS, Active mode, VDD, load HALT mode, VDD, load STOP mode, VDD, load Note Conditions Except input MIN. 0.7VDD 0.8VDD 0.7VDD 0.8V 0.2VDD -250 Note TYP. MAX. 0.2V Unit
Note
Note TYP. value measured when general program executed, condition. MAX. value measured when special program that max. switching required executed, condition. PD77015: PD77017: µPD77018: PD77015: PD77017: µPD77018: PD77015: PD77017: PD77018: Timing Test Points
0.8VDD 0.5VDD 0.2VDD
Test points
0.8VDD 0.5VDD 0.2VDD
Input (except
0.7VDD 0.45VDD 0.2VDD
Test points
0.7VDD 0.45VDD 0.2VDD
Output
0.7VDD 0.45VDD 0.2VDD
Test points
0.7VDD 0.45VDD 0.2VDD
µPD77015, 77017, 77018
Characteristics
Clock
Required Timing Condition
Parameters CLKIN cycle time Symbol Conditions multiple rate: multiple rate: multiple rate: multiple rate: CLKIN high level width wCXH MIN. 13.5 TYP. MAX. 35.7 71.4 13.5 rfCXNote 13.5 rfCXNote Unit
CLKIN level width
wCXL
13.5
CLKIN rise/fall time
rfCX
Note 0.5t rfCX 13.5 (MIN.) Switching Characteristics
Parameters Internal clock cycle time Symbol Conditions Active mode HALT mode CLKOUT cycle time CLKOUT level width CLKOUT rise/fall time rfCO 0.5t MIN. TYP. cCX/N Note cCX/N Note MAX. Unit
Note multiple rate
µPD77015, 77017, 77018
Oscillator Circuit
Resonator Ceramic crystal resonator Recommended Circuit
External clock
External Clock Supply
Use. Leave Open.
Cautions When using system clock oscillator, wire portion enclosed broken lines figure follows avoid adverse influences wiring capacitance: Keep wiring length short possible. cross wiring over other signal lines. route wiring vicinity lines through which high fluctuating current flows. Always keep ground point capacitor oscillator circuit same potential GND. connect power source pattern through which high current flows. extract signals from oscillator. When using ceramic resonator crystal resonator, frequency multiple rate should specified mask option. device does operate other frequency multiple rate.
µPD77015, 77017, 77018
Recommended Oscillator Circuit Constants
Manufacturer Name Ceramic Resonator MURATA Manufacturing Part Number CCR33.0MC6 CSA33.00MXZ040 CST33.00MXW040 CSACV33.00MX040 CSTCV33.00MX040 Crystal Resonator DAISHINKU AT-49 DSX840G Internal Frequency (MHz) 33.0 Internal Recommended Constants [pF] Internal [pF]
Remark Recommended oscillator circuit constants differ wiring capacitance target board customer designed. When using resonator target system, manufacturer evaluate.
Reset, Interrupt
Required Timing Condition
Parameters RESET level width Symbol W(RL) Conditions Crystal resonator input, power STOP mode External clock input, power STOP mode Active mode HALT mode RESET recovery time INT1-INT4 level width INT1-INT4 recovery time rec(R) W(INTL) rec(INT) MIN. Note TYP. MAX. Unit
Note 4tcC Note 3tcC Note
Note w(RL) indicates time between crystal resonator oscillator starts provide clock becomes stable. w(RL) depends rating crystal resonator oscillator. power w(RL) measured after point that power supply voltage reaches Note that, during HALT mode, extended times long that Active mode.
µPD77015, 77017, 77018
Clock Input/Output Timing
tcCX twCXH twCXL
trfCX
trfCX
Internal clock
tcCO twCO CLKOUT twCO
trfCO
trfCO
Reset Timing
tw(RL) RESET
trec(R)
Interrupt Timing
trec(INT) tw(INTL) INT1 INT4
µPD77015, 77017, 77018
External Data Memory Access
Required Timing Condition
Parameters Read data setup time Read data hold time WAIT setup time WAIT hold time Symbol suDDRD hDDRD suWA Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters Address output delay time Address output hold time output delay time hold time Write data output valid time Write data output hold time output delay time setup time level width Symbol vDDWD hDDWD suDW wDWL 0.25t 0.5tcC cDWNote 0.5tcC Conditions MIN. TYP. MAX. Unit
high level width
wDWH
Note Data wait cycle External Data Memory Access Timing (Read)
CLKOUT
tdDA thDA DA13, tsuDDRD thDDRD
tdDR
thDR
tsuWA
thWA
tsuWA
thWA
WAIT
External Data Memory Access Timing (Write)
CLKOUT
tdDA
thDA
DA13,
tvDDWD Hi-Z
tvDDWD
thDDWD Hi-Z
tdDW twDWL
tsuDW twDWH
µPD77015, 77017, 77018
tsuWA
thWA
tsuWA
thWA
WAIT
µPD77015, 77017, 77018
Arbitration
Required Timing Condition
Parameters HOLDRQ setup time HOLDRQ hold time Symbol suHRQ hHRQ Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters BSTB hold time BSTB output delay time HOLDAK output delay time Data hold time when arbitration Data valid time after arbitration Symbol dHAK h(BS-D) v(BS-D) Conditions MIN. TYP. MAX. Unit
Arbitration Timing (Bus idle)
CLKOUT
(Bus busy)
idle
release
idle
(Bus busy)
thBS
tdBS
BSTB tsuHRQ HOLDRQ tdHAK tdHAK thHRQ tsuHRQ thHRQ
HOLDAK
µPD77015, 77017, 77018
th(BS-D) X/Y, DA13, MRD, Hi-Z
tv(BS-D)
Arbitration Timing (Bus busy)
CLKOUT
(Bus busy)
busy
idle
release
idle
(Bus busy)
thBS
tdBS
BSTB tsuHRQ thHRQ HOLDRQ tdHAK tsuHRQ thHRQ
tdHAK HOLDAK
µPD77015, 77017, 77018
th(BS-D) X/Y, DA13, MRD, Hi-Z
tv(BS-D)
µPD77015, 77017, 77018
Serial Interface
Required Timing Condition
Parameters input cycle time input high/low level width input rise/fall time SOEN recovery time SOEN hold time SIEN recovery time SIEN hold time setup time hold time Symbol rfSC recSOE hSOE recSIE hSIE suSI Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters SORQ output delay time SORQ hold time valid time hold time SIAK output delay time SIAK hold time Symbol dSOR hSOR dSIA hSIA Conditions MIN. TYP. MAX. Unit
Notes Serial Clock Serial clock inputs SCK1 SCK2 sensitive kind interfering signals (noise power supply, induced voltage, etc.). Spurious signals cause malfunction device. Special care serial clock design should taken. Careful grounding, decoupling short wiring SCK1 SCK2 recommended. Intersection SCK1 SCK2 with other serial interface lines close wiring lines carrying high frequency signals large changing currents should avoided. considers serial clock make waveform stable especially about rising falling.
Example good example Straight rising form falling form
Example good example doesn't bound. doesn't make noise above another.
Example good example doesn't make stair stepping.
Serial Output Timing
tcSC twSC SCK1, SCK2 tdSOR thSOR twSC
trfSC
trfSC
SORQ1 trecSOE trecSOE thSOE thSOE SOEN1, SOEN2
tvSO
tvSO
thSO
SO1,
Hi-Z
Last
Hi-Z
µPD77015, 77017, 77018
Serial Output Timing (Continual output)
tcSC twSC SCK1, SCK2 tdSOR thSOR twSC
trfSC
trfSC
SORQ1 trecSOE thSOE SOEN1, SOEN2
tvSO
thSO Hi-Z
SO1,
Last
Last
µPD77015, 77017, 77018
Serial Input Timing
tcSC twSC SCK1, SCK2 tdSIA thSIA twSC
trfSC
trfSC
SIAK1
trecSIE trecSIE thSIE thSIE
SIEN1, SIEN2
tsuSI
thSI
SI1,
µPD77015, 77017, 77018
Serial Input Timing (Continual input)
tcSC twSC SCK1, SCK2 tdSIA thSIA twSC
trfSC
trfSC
SIAK1
trecSIE thSIE SIEN1, SIEN2
tsuSI
thSI
SI1,
µPD77015, 77017, 77018
Last-1
Last
µPD77015, 77017, 77018
Host Interface
Required Timing Condition
Parameters delay time width HCS, HA0, read hold time HCS, HA0, write hold time HRD, recovery time delay time width hold time setup time Symbol hHCAR hHCAW recHS hHDW suHDW Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters HRE, output delay time HRE, hold time valid time hold time Symbol vHDR hHDR Conditions MIN. TYP. MAX. Unit
Host Interface Timing (Read)
CLKOUT
HCS, HA0,
thHCAR tdHR twHR trecHS
thHDR
tvHDR Hi-Z Hi-Z
µPD77015, 77017, 77018
tdHE
thHE
Host Interface Timing (Write)
CLKOUT
HCS, HA0,
thHCAW tdHW
twHW
trecHS
thHDW tsuHDW
tdHE thHE
µPD77015, 77017, 77018
µPD77015, 77017, 77018
General Input/Output Ports
Required Timing Condition
Parameters Port input setup time Port input hold time Symbol suPI Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters Port output delay time Symbol Conditions MIN. TYP. MAX. Unit
General Input/Output Ports Timing
CLKOUT
tdPO (Output) tsuPI thPI (Input)
µPD77015, 77017, 77018
Debugging Interface (JTAG)
Required Timing Condition
Parameters cycle time high/low level width rise/fall time TMS, setup time TMS, hold time Input setup time Input hold time Symbol cTCK wTCK rfTCK suDI suJIN hJIN Conditions MIN. TYP. MAX. Unit
Switching Characteristics
Parameters output delay time Output output delay time Symbol dJOUT Conditions MIN. TYP. MAX. Unit
Debugging Interface Timing
tcTCK twTCK twTCK trfTCK trfTCK
tsuDI TMS,
thDI
Valid
Valid
Valid
tdDO
tsuJIN
thJIN
Capture state
Valid
tdJOUT
Update state
Remark details JTAG, refer "IEEE1149.1."
µPD77015, 77017, 77018
PACKAGE DRAWING
PLASTIC TQFP (FINE PITCH)
detail lead
NOTE
ITEM MILLIMETERS 16.0±0.2 14.0±0.2 14.0±0.2 16.0±0.2 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.145 +0.055 -0.045 0.10 1.0±0.1 0.1±0.05 1.27 MAX. INCHES 0.630±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.630±0.008 0.039 0.039 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.006±0.002 0.004 0.039 +0.005 -0.004 0.004±0.002 0.050 MAX. S100GC-50-9EU-1
Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
µPD77015, 77017, 77018
RECOMMENDED SOLDERING CONDITIONS
When soldering these products, highly recommended observe conditions shown below. other soldering processes used, soldering performed under different conditions, please make sure consult with sales offices. more details, refer document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
100-pin plastic TQFP (FINE PITCH) (14mm 14mm)
Process Conditions Peak temperature: below (Package surface temperature), Reflow time: seconds less higher), Maximum number reflow processes times, Exposure limit Note days hours pre-baking required afterwards). Vapor Phase Soldering Peak temperature: below (Package surface temperature), Reflow time: seconds less higher), Maximum number reflow processes times, Exposure limit Note days hours pre-baking required afterwards). Partial heating method temperature below, Heat time seconds less (Per each side device) VP15-107-2 Symbol IR35-107-2
Infrared reflow
Note
Maximum allowable time from taking soldering package pack soldering. Storage conditions: relative humidity less.
Caution
Apply only kind soldering condition device, except "partial heating method", device will damaged heat stress.
µPD77015, 77017, 77018
100-pin plastic TQFP (FINE PITCH) (14mm 14mm) 100-pin plastic TQFP (FINE PITCH) (14mm 14mm)
Process Conditions Peak temperature: below (Package surface temperature), Reflow time: seconds less higher), Maximum number reflow processes times, Exposure limit Note days hours pre-baking required afterwards). Vapor Phase Soldering Peak temperature: below (Package surface temperature), Reflow time: seconds less higher), Maximum number reflow processes times, Exposure limit Note days hours pre-baking required afterwards). Partial heating method temperature below, Heat time seconds less (Per each side device) VP15-103-2 Symbol IR35-103-2
Infrared reflow
Note
Maximum allowable time from taking soldering package pack soldering. Storage conditions: relative humidity less.
Caution
Apply only kind soldering condition device, except "partial heating method", device will damaged heat stress.
µPD77015, 77017, 77018
[MEMO]
µPD77015, 77017, 77018
[MEMO]
µPD77015, 77017, 77018
[MEMO]
µPD77015, 77017, 77018
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD77015, 77017, 77018
[MEMO]
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD77015,77017,77018 bits, Fixed-point Digital Signal Processor

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