ELECTRON DEVICE µPD75517(A) SINGLE-CHIP MICROCOMPUTER µ
|
|
|
Top Searches for this datasheet
INTEGRATED CIRCUIT
ELECTRON DEVICE
µPD75517(A)
SINGLE-CHIP MICROCOMPUTER
µPD75517(A) series four-bit single-chip microcomputer which enables data processing equivalent that performed eight-bit microcomputer. high-performance product, whose minimum instruction execution time 0.67 shorter than 0.95 conventional µPD75516. capacities also larger, throughput series further increased. µPD75517(A) suited controllers electric parts automobiles.
FEATURES
Higher reliable than µPD75517 Capacities program memory, ROM: 24448 bits Capacity data memory, RAM: 1024 bits Function specifying instruction execution time (useful high-speed operation saving power) 0.67 µs/1.33 µs/2.67 µs/10.7 (when main system clock operates MHz) 0.95 µs/1.91 µs/3.82 s/15.3 (when main system clock operates 4.19 MHz) (when subsystem clock operates 32.768 kHz)
Built-in converter operable voltage
8-bit resolution channels (Successive approximation system)
Many lines: Enhanced timer function: channels Built-in 8-bit serial interface: channels
Built-in serial interface (SBI)
Clock operable with ultra-low power consumption (when 5-µA TYP. operates Product with built-in PROM available: PD75P518
APPLICATIONS
Controller electric parts automobiles
ORDERING INFORMATION
Part number Remark Code number Package 80-pin plastic Quality grade Special
Please refer "Quality Grades Semiconductor Devices" (Document number IEI-1209) published Corporation know specification quality grade devices recommended applications.
information this document subject change without notice. Document Date Published Printed Japan IC-3183 IC-8683 November 1992
CORPORATION 1992
µPD75517(A)
FUNCTIONS
Item Built-in memory General registers Instruction cycle 24448 bits 1024 bits (4-bit 8-bit banks 0.67 µs/1.33 µs/2.67 µs/10.7 MHz) 0.95 µs/1.91 µs/3.82 µs/15.3 4.19 MHz) 32.768 kHz) (Shared with INT, SIO, PPO, analog input. Seven lines pulled software.) (Four lines driving) lines pulled software. Four lines pulled down mask option. (Eight lines driving. Withstand voltage lines pulled mask option.) 8-bit resolution channels (Successive approximation system) Capable low-voltage operation: Four channels Timer/event counter Basic interval timer Timer/pulse generator (14-bit output enabled) Clock timer Serial interface channels standard serial interface (SBI)/ three-wire SIO: channel General clock synchronous serial interface (three-wire SIO): channel Functions
ports
Total Number CMOS input lines Number CMOS lines
Number N-ch open-drain lines converter
Timer/counter
Interrupt
Vectored interrupt Seven sources (External: internal: Test input sources (External: internal: Clock test flag provided. Parallel edge detection flag scan input provided.
Instruction
Set/reset/test/Boolean operation data 4-bit data transfer, arithmetic/logical, increment/decrement, comparison instructions 8-bit data transfer, arithmetic/logical, increment/decrement, comparison instructions Ceramic/crystal oscillator main system clock MHz, 4.19 Crystal oscillator subsystem clock 32.768 80-pin plastic
System clock generator
Operating supply voltage Package
µPD75517(A)
CONFIGURATION (TOP VIEW)
AN4/P150
AN5/P151
AN6/P152
AN7/P153
P120
P121
P122
P123
P130
P131
P132
AVREF
Note
P133
AVSS
P140 P141 P142 P143 RESET P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 P11/INT1 P12/INT2 P13/ P20/PTO0 P22/PCL P23/BUZ
P113 P112 P111 P110 P103 P102 P101 P100
SI1/P83 SO1/P82 SCK1/P81 PPO/P80 KR7/P73 KR6/P72 KR5/P71 KR4/P70
KR3/P63
KR2/P62
KR1/P61
KR0/P60
Internally connected. Connect VSS. Note sure supply power both pins.
TI0/P13 PTO0/P20 BUZ/P23 PPO/P80 SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SI1/P83 SO1/P82 SCK1/P81 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 KR7/P73 AN4/P150 AN7/P153 AVREF AVSS
INTERNAL BLOCK DIAGRAM
Basic interval timer INTBT Timer/event counter INTT0 Bank Watch timer Program counter (15) SP(8) SBS(2)
Port Port Port Port Port Port
Note Note P100 P103 P110 P113
INTW General register Timer/pulse generator INTTPG Serial interface INTCSI0 Serial interface program memory 24448 bits
Port Port Port Decode control data memory 1024 bits Port Port Port Port Port Port
P120 P123 Note P130 P133 Note P140 P143 Note P150 P153
Interrupt control
Clock output control
Clock divider
Clock generator Main
Stand control
clock
Port
seq. buffer (16)
PCL/P22
RESET
µPD75517(A)
converter
Note
Port Port Port Port Port N-ch open-drain ports with medium withstand voltage
µPD75517(A)
CONTENTS
FUNCTIONS
PORT PINS NON-PORT PINS INPUT/OUTPUT CIRCUITS CONNECTION UNUSED PINS SELECTION MASK OPTION
ARCHITECTURE MEMORY µPD75517(A)
DATA MEMORY BANK CONFIGURATION ADDRESSING MODES GENERAL REGISTER BANK CONFIGURATION MEMORY-MAPPED
INTERNAL FUNCTIONS
PROGRAM COUNTER (PC) PROGRAM MEMORY (ROM) DATA MEMORY (RAM) GENERAL REGISTERS ACCUMULATORS STACK POINTER (SP) STACK BANK SELECT REGISTER (SBS) PROGRAM STATUS WORD (PSW) BANK SELECT REGISTER (BS)
PERIPHERAL HARDWARE FUNCTIONS
DIGITAL PORTS CLOCK GENERATOR CLOCK OUTPUT CIRCUIT BASIC INTERVAL TIMER CLOCK TIMER TIMER/EVENT COUNTER TIMER/PULSE GENERATOR SERIAL INTERFACE (CHANNEL 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 Serial Interface (Channel Functions Configuration Serial Interface (Channel Register Functions Signals Serial Interface (Channel Operation Transfer Start Each Mode Manipulation SCK0 Output
µPD75517(A)
SERIAL INTERFACE (CHANNEL 4.9.1 4.9.2 4.9.3 4.9.4 4.10 4.11 Serial Interface (Channel Functions Serial Interface (Channel Configuration Serial Interface (Channel Operation
Register Functions
CONVERTER SEQUENTIAL BUFFER
INTERRUPT FUNCTION
CONFIGURATION INTERRUPT CONTROL CIRCUIT HARDWARE INTERRUPT CONTROL CIRCUIT MULTIPLE INTERRUPT PROCESSING CONTROL VECTOR ADDRESS SHARE INTERRUPT PROCESSING
INTERRUPT SEQUENCE
STANDBY FUNCTION
SETTING STANDBY MODES OPERATION STATUSES RELEASE STANDBY MODES OPERATION AFTER STANDBY MODE RELEASED
RESET FUNCTION INSTRUCTION
µPD75517(A) INSTRUCTIONS
INSTRUCTION OPERATION. INSTRUCTION CODES EACH INSTRUCTION
ELECTRICAL CHARACTERISTICS
PACKAGE DIMENSIONS RECOMMENDED SOLDERING CONDITIONS APPENDIX APPENDIX SERIES PRODUCT FUNCTIONS DEVELOPMENT TOOLS
µPD75517(A)
FUNCTIONS
PORT PINS (1/2)
I/ONote circuit type
name
Also used INT4 SCK0 SO0/SB0 SI0/SB1
Function
8-bit
When reset
P30Note P31Note P32Note P33Note P40-P43Note
4-bit input port (Port P03, pull-up resistors provided software units bits.
Input
INT0 INT1 INT2
With noise elimination function 4-bit input port (Port Pull-up resistors provided software units bits. 4-bit port (Port Pull-up resistors provided software units bits.
Input
PTO0
Input
Programmable 4-bit port (Port Input/output specified bit. Pull-up resistors provided software units bits.
Input
N-ch open-drain 4-bit port (Port pull-up resistor provided (mask option). Withstand voltage open-drain mode.
High level (when pull-up resistor provided) high impedance High level (when pull-up resistor provided) high impedance
P50-P53Note
N-ch open-drain 4-bit port (Port pull-up resistor provided (mask option). Withstand voltage open-drain mode.
Programmable 4-bit port (Port Input/output specified bit. Pull-up resistors provided software units bits.
Input
4-bit port (Port Pull-up resistors provided software units bits.
Input
Notes circuits enclosed circles have Schmitt-triggered input. driven directly.
µPD75517(A)
PORT PINS (2/2)
I/ONote circuit type
name P90-P93
Also used SCK1
Function
8-bit
When reset
4-bit input port (Port
Input
4-bit port (Port pull-down resistor provided (mask option). level (when pull-down resistor provided) high impedance Input Input High level (when pull-up resistor provided) high impedance High level (when pull-up resistor provided) high impedance High level (when pull-up resistor provided) high impedance Input
P100-P103 P110-P113 P120-P123
4-bit port (Port 4-bit port (Port N-ch open-drain, 4-bit port (Port 12). Pull-up resistors provided (mask option). Withstand voltage open-drain mode.
P130-P133
N-ch open-drain, 4-bit port (Port 13). Pull-up resistors provided (mask option). Withstand voltage open-drain mode.
P140-P143
N-ch open-drain, 4-bit port (Port 14). Pull-up resistors provided (mask option). Withstand voltage open-drain mode.
P150-P153
AN4-AN7 4-bit input port (Port
Note circuits enclosed circles have Schmitt-triggered input.
µPD75517(A)
NON-PORT PINS
I/ONote When reset circuit type Input Input Input
name
Also used
Function
PTO0
External event pulse input timer/event counter Timer/event counter output Clock output Fixed frequency output (for buzzer system clock trimming) Serial clock Serial data output serial Serial data input serial Edge detection vectored interrupt input (Either rising falling edge detected.) Edge detection vectored interrupt input (The edge detected selectable.) Edge detection testable input rising edge detected.) Synchronous Asynchronous Asynchronous
SCK0 SO0/SB0 SI0/SB1 INT4
Input Input Input
INT0 INT1 INT2
KR0-KR3 KR4-KR7 SCK1 AN0-AN3 AN4-AN7 AVREF
P60-P63 P70-P73 P150-P153
Parallel-falling-edge-sensitive testable input pins Parallel-falling-edge-sensitive testable input pins Serial clock Serial data output Serial data input Analog input pins converter
Input Input Input Input Input
converter reference voltage input converter reference connection crystal/ceramic resonator main system clock generation. When external clock used, input inverted signal input connection crystal resonator subsystem clock generation. When external clock used, input XT1, left open. System reset input Timer/pulse generator pulse output Positive power supply Ground Internally connectedNote
RESET
Input
Notes circuits enclosed circles have Schmitt-triggered input. sure input level this pin.
µPD75517(A)
INPUT/OUTPUT CIRCUITS Fig. shows input/output circuit each µPD75517(A) simplified manner. Fig.
Type Data P-ch Output disable N-ch
Input/Output Circuits (1/3)
Type P-ch
N-ch
CMOS input buffer Type
Push-pull output which high-impedance output (off both P-ch N-ch) Type
Data Type Output disable
IN/OUT
Type
Schmitt trigger input with hysteresis Type
circuit consisting push-pull output type input buffer type Type
P.U.R. P.U.R. enable Data Type Output disable Output disable
P.U.R. P-ch
P-ch
IN/OUT
Type
P.U.R.: Pull-Up Resistor Schmitt trigger input with hysteresis
P.U.R.: Pull-Up Resistor
µPD75517(A)
Fig. Input/Output Circuits (2/3)
Type P.U.R. P.U.R. enable Data Type Output disable P-ch Output disable (P-ch) P.U.R. enable P-ch IN/OUT Data Output disable
Type
Type
P.U.R. P-ch
IN/OUT
N-ch
Output disable (N-ch)
Type
P.U.R.: Pull-Up Resistor Type Type
P.U.R.: Pull-Up Resistor P.U.R.
Data Type Output disable
IN/OUT
P.U.R. enable Data Type Output disable
P-ch
IN/OUT
Type
Type
circuit consisting push-pull output type Schmitt-triggered input type Type P.U.R. P.U.R. enable Data Type Output disable P-ch Data IN/OUT Output disable Type
P.U.R.: Pull-Up Resistor
P.U.R. (Mask option)
IN/OUT
N-ch (Can sustain
Type
Middle-voltage input buffer (Can sustain P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor
µPD75517(A)
Fig.
Type P.U.R. P.U.R. enable P-ch IN/OUT Data Output disable N-ch P-ch N-ch
Input/Output Circuits (3/3)
Type instruction
Sampling AVSS Reference voltage (from voltage serial resistor string)
AVSS
P.U.R.: Pull-Up Resistor Type Type
Input enable
Data Type Output disable
IN/OUT
AVREF
Type
P.D.R. (Mask option)
Reference voltage
AVSS P.D.R.: Pull-Down Resistor
Type
P-ch N-ch Sampling
AVSS AVSS Reference voltage (from voltage serial resistor string) Input enable
µPD75517(A)
CONNECTION UNUSED PINS Table
name P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI1/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80/PPO P81/SCK1 P82/SO1 P83/SI1 P90-P93 P100-P103 P110-P113 P120-P123 P130-P133 P140-P143 P150/AN4-P153/AN7 AN0-AN3 AVREF AVSS connected left open connected connected Input state connected connected Input state connected connected
Recommended Connection Unused Pins
Recommended connection connected connected
Output state left open
Output state left open
µPD75517(A)
SELECTION MASK OPTION following mask options provided pins. Specification built-in pull-up pull-down resistors Table Selection Pull-Up Pull-Down Resistors
Mask option Pull-up resistors provided (Can specified bit.) pull-up resistor provided (Can specified bit.)
name P40-P43, P50-P53, P120-P123, P130-P133, P140-P143 P90-P93
Pull-down resistors provided (Can specified bit.)
pull-down resistor provided (Can specified bit.)
Specification built-in feed-back resistors subsystem clock oscillation Table
name XT1,
Selection Feed-Back Resistors
Mask option
Feed-back resistors provided (when subsystem clock used)
feed-back resistors provided (when subsystem clock used)
Caution Even built-in feed-back resistors provided when subsystem clock used, operation affected except increased power supply current IDD.
µPD75517(A)
ARCHITECTURE MEMORY µPD75517(A)
µPD75517(A) three architectural features: Data memory bank configuration General register bank configuration Memory-mapped Each these features explained below. DATA MEMORY BANK CONFIGURATION ADDRESSING MODES
shown Fig. 2-1, data memory space µPD75517(A) contains static (1024 words bits) addresses 000H 3FFH peripheral hardware (such ports timers) addresses F80H FFFH. address 12-bit address this data memory space, µPD75517(A) uses such memory bank configuration that low-order eight bits specified with instruction directly indirectly, highorder four bits used specify memory bank (MB). specify memory bank (MB), memory bank enable flag (MBE) memory bank select register (MBS) contained, allowing addressing indicated Fig. Table 2-1. (The register used select memory bank, flag used determine whether memory bank selected using register enabled. automatically saved restored time interrupt processing subroutine processing, that freely interrupt processing subroutine processing.) addressing data memory space, usually (MBE static memory bank specified operated. However, mode mode selected each step program processing more efficient programming.
Applicable program processing mode Interrupt processing Processing that repeats internal hardware static operations Subroutine processing Usual program processing
mode
indicated below. Example SET1 CLR1 MB15
µPD75517(A)
Fig. Data Memory Organization Addressing Range Each Addressing Mode
mem.bit mem.bit Stack pmem. address- fmem.bit
Addressing mode
Memory bank enable flag 000H 01FH 020H 07FH General resister area Data area Static (memory bank
0FFH 100H
Data area Static (memory bank
1FFH 200H Stack area Data area Static (memory bank
2FFH 300H
Data area Static (memory bank
3FFH
contained
F80H
FB0H FBFH FC0H FF0H FFFH
Peripheral hardware area (memory bank
Remark Don't care
µPD75517(A)
Table
Representation format mem.bit
Addressing Modes
Addressing mode 1-bit direct addressing
Specified address specified address specified mem. this case: When 00H-7FH, When 80H-FFH, When Address specified mem. this case: When 00H-7FH, When 80H-FFH, When Address specified (mem: even address). this case: When 00H-7FH, When 80H-FFH, When
4-bit direct addressing
8-bit direct addressing
4-bit register indirect addressing
@HL+ @HL-
Address specified this case,
Address specified memory bank Address specified memory bank Address specified (with register holding even number). this case, specified address specified fmem. this case: fmem FB0H-FBFH (interrupt-related hardware) fmem FF0H-FFFH (I/O port) specified low-order bits register address specified high-order bits pmem high-order bits register. this case, pmem FC0H-FFFH
8-bit register indirect addressing manipulation addressing
fmem.bit
pmem.@L
@H+mem.bit specified address specified low-order bits mem. this case, Stack addressing Address specified memory bank selected
µPD75517(A)
summarized Table 2-1, µPD75517(A) allows both direct indirect addressing data memory manipulation 1-bit data, 4-bit data, 8-bit data, that very efficient simple programming performed. Examples 8-bit data port port transferred addresses 21H. CLR1 20H, (21H, 20H) PORT4 Ports
When set. SET1 PORT0.2 PORT3.3 Skip port port
different value output port depending status P10. PORT1.0 #1010B #0101B MB15 PORT6, Skip port 1010B (string effect) 0101B (string effect) CLR1 Port Updating Static Addresses
Fig.
DECS
DECS
DECS
4-bit transfer
DECS INCS DECS
4-bit transfer
INCS
INCS
INCS Direct addressing manipulation 4-bit 8-bit
INCS
DECS
DECS
Automatic decrement DECS DECS
4-bit manipulation 8-bit manipulation
Automatic increment INCS INCS
mem.bit manipulation
INCS
INCS
µPD75517(A)
GENERAL REGISTER BANK CONFIGURATION
µPD75517(A) contains four register banks, each consisting eight general registers: These registers mapped addresses memory bank data memory. (See Fig. 2-3.) specify general register bank, register bank enable flag (RBE) register bank select register (RBS) contained. register used select register bank, flag used determine whether register bank selected using enabled. register bank (RB) enabled instruction execution determined indicated Table 2-2, PD75517(A) enables user create programs very efficient manner selecting register bank from four register banks, depending whether processing normal processing interrupt processing. (The automatically saved time interrupt processing, automatically restored upon completion interrupt processing.) Table Example Register Banks with Normal Routines Interrupt Routines
register banks with register bank with register bank with this case, needs saved restored.) Save registers with PUSH POP.
Normal processing Single interrupt processing Dual interrupt processing
Multiple (triple more) interrupt processing
indicated below. Example SET1 CLR1
general registers allow transfers, comparisons, arithmetic/logical operations, increments decrements only 4-bit basis, also 8-bit basis with register pairs. this case, register pairs register bank that inverted value register bank specified specified XA', HL', DE', BC', thus providing eight 8-bit registers. (See Fig. 2-4.) Example SET1 HL+XA HL'-XA (HL' register bank HL+1
#18H
ADDS SUBS HL', INCS
#00H (string effect) #10H (string effect)
µPD75517(A)
Fig. General Register Configuration (4-Bit Processing)
Register bank Register bank Register bank Register bank
µPD75517(A)
Fig. General Register Configuration (8-Bit Processing)
When
When
When
When
µPD75517(A)
MEMORY-MAPPED
µPD75517(A) employs memory-mapped I/O, which maps peripheral hardware such timers ports addresses F80H FFFH data memory space shown Fig. 2-1. This means that there particular instruction control peripheral hardware, peripheral hardware controlled using memory manipulation instructions. (Some mnemonics hardware control available make programs readable.) manipulate peripheral hardware, addressing modes listed Table used. Table Addressing Modes Applicable Peripheral Hardware
Applicable addressing mode manipulation Direct addressing mode specifying mem.bit with (MBE Direct addressing mode specifying fmem.bit regardless setting Indirect addressing mode specifying pmem.@L regardless setting 4-bit manipulation Direct addressing mode specifying with (MBE Register indirect addressing mode specifying with (MBE 8-bit manipulation Direct addressing mode specifying (even address) with (MBE Register indirect addressing mode specifying (with register containing even number) with (MBE
Applicable hardware hardware allowing manipulation IST0, IST1, MBE, RBE, EOT, hardware allowing 4-bit manipulation
hardware allowing 8-bit manipulation addressing
Fig. summarizes µPD75517(A). items Fig. have following meanings: Symbol: Name representing address incorporated hardware, which coded operand field instruction Indicates whether hardware allows read/write operation. R/W: Both read write operations possible Read only Write only
Number manipulatable bits: Indicates number bits that processed hardware manipulation Bits manipulated indicated (1-, 8-bit) basis. Particular bits manipulated. these bits, Remarks.
Bits cannot manipulated indicated (1-, 8-bit) basis.
manipulation addressing: manipulation addressing applicable hardware manipulation
µPD75517(A)
Fig.
µPD75517(A) (1/4)
Number bits that manipulated
Address F80H
Hardware name (symbol)
bits
bits
manipulation addressing
Remarks fixed
Stack pointer (SP)
F82H F83H
Register bank select register (RBS) Memory bank select register (MBS) Stack bank select register (SBS)
Bank select register (BS)
Note
Bits always mem.bit Only manipulated
F84H
F85H F86H
Basic interval timer mode register (BTM)
Basic interval timer (BT)
F90H Timer pulse generator (TPGM) F94H Timer/pulse generator modulo register (MODL) F96H Timer/pulse generator modulo register (MODH) Clock mode register (WM)
mem.bit
Only allows manipulation.
F98H
FA0H Timer/event counter mode register (TM0) FA2H FA4H Timer/event counter count register (T0) TOE0 Note
mem.bit
Only manipulated
mem.bit
FA6H
Timer/event counter modulo register (TMOD0)
Notes
operated separately during 4-bit manipulation. also operated during 8-bit manipulation. TOE0: Timer/event counter output enable flag
µPD75517(A)
Fig.
µPD75517(A) (2/4)
Number bits that manipulated
Address FB0H IST1
Hardware name (symbol) IST0
bits
bits
manipulation addressing
Remarks
Program status word (PSW)
fmem.bit Manipulated with EI/DI instruction
FB2H FB3H FB4H
Interrupt priority select register (IPS) Processor clock control register (PCC) INT0 mode register (IM0)
FB5H INT1 mode resistor (IM1)
fixed Bits fixed Bits fixed Bits fixed
FB6H
INT2 mode register (IM2)
FB7H FB8H FB9H FBAH FBBH FBCH FBDH FBEH FBFH
System clock control register (SCC) IRQ4 IEBT IRQBT IETPG IET0 IECSI0 IRQ1 IRQW IRQTPG IRQT0 IRQCSI0 IRQ0 IRQ2
fmem.bit
FC0H FC1H FC2H FC3H FC8H
sequential buffer (BSB0) sequential buffer (BSB1) sequential buffer (BSB2) sequential buffer (BSB3) Serial operation mode register (CSIM1)
mem.bit Only allows manipulation. mem.bit pmem.@L
CSIE1 FCCH Serial shift register (SIO1)
Remarks Interrupt enable flag Interrupt request flag
µPD75517(A)
Fig.
µPD75517(A) (3/4)
Address FD0H FD8H
Hardware name (symbol)
Number bits that manipulated
bits
bits
manipulation addressing
Remarks
Clock output mode register (CLOM)
1-bit write 1-bit read
conversion mode register (ADM) FDAH register (SA) FDCH
Pull-up resistor specification register group (POGA)
FE0H
Serial operation mode register (CSIM0) CSIE0 CMDD RELD CMDT control register (SBIC) BSYE ACKD ACKE Serial shift register (SIO0)
RELT ACKT
mem.bit mem.bit 1-bit read bits allow manipulation only
FE2H
FE4H
FE6H Slave address register (SVA) FE8H PM33 PM32 PM31 Port mode register group (PMGA) PM63 PM62 PM61 Port mode register group (PMGB) PM11 PM10 Port mode register group (PMGC) PM14 Note PM13 PM30
PM60 Note PM12
FECH
FEEH
Note When developing program, following bits port mode register group (PMGC): FEEH, (Equivalent PM8) FEFH, (Equivalent PM15) For, while this port chip side used input only, corresponding port emulator port.
µPD75517(A)
Fig.
µPD75517(A) (4/4)
Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H
Note
Hardware name (symbol) Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port (PORT0) (PORT1) (PORT2) (PORT3) (PORT4) (PORT5) (PORT6) (PORT7) (PORT8) (PORT9) (PORT10) (PORT11) (PORT12) (PORT13) (PORT14) (PORT15)
Number bits that manipulated
bits
bits
manipulation addressing
Remerks
FF7H Note FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH
fmem.bit pmem.@L
Note
read-only. 4-bit parallel input processing, PORT6 PORT7 specified.
µPD75517(A)
INTERNAL FUNCTIONS
PROGRAM COUNTER (PC): BITS
program counter 15-bit binary counter holding program memory address information. Fig. Program Counter Format
PC14 PC13 PC12 PC11 PC10
Note that reset start address must within space bytes (0000H 3FFFH). This because RESET input sets low-order bits program memory address 0000H PC13 PC8, contents address 0001H PC0, PC14 initialization. PROGRAM MEMORY (ROM): 24448 WORDS BITS
program memory mask-programmable with configuration 24448 words bits storing programs, table data, forth. Program memory addressed program counter. Table data referenced using table reference instruction (MOVT). Fig. shows allowable branch address ranges branch instructions subroutine call instructions. whole-space branch instruction (BRA !addr1) whole-space call instruction (CALLA !addr1) allow direct branch throughout whole space 0000H-5F7FH. relative branch instruction $addr) allows branch addresses regardless block boundaries. program memory located addresses 0000H 5F7FH containing following specially assigned addresses. (All areas excluding 0000H 0001H used normal program memory.) 0000H 0001H Vector table holding setting values program start address time RESET input. reset start performed arbitrary address within 16K-byte space (0000H 3FFFH). 0002H 000DH Vector table holding setting values program start address time each vectored interrupt occurrence. Interrupt processing started arbitrary address within 16Kbyte space (0000H 3FFFH). 0020H 007FH Table area referenced GETI instructionNote Note GETI instruction represent arbitrary 2-byte 3-byte instruction 1-byte instructions byte, thus reducing number program steps. (See Section 8.1.)
µPD75517(A)
Fig.
0000H Internal reset start address Internal reset start address 0002H INTBT/INT4 start address INTBT/INT4 start address 0004H INT0 start address INT0 start address 0006H INT1 start address INT1 start address 0008H INTCSI0 start address INTCSI0 start address 000AH INTT0 start address INTT0 start address 000CH INTTPG start address INTTPG start address (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) Branch/call address specified GETI insturction GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH 4000H 4FFFH 5000H BRCB !caddr instruction branch address 5F7FH BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BCDE BCXA branch address !addr instruction branch address CALLA !addr instruction branch address $addr instruction relative branch address (-15 +16) CALL !addr instruction branch address BRCB !caddr instruction branch address !addr instruction branch address CALLF !faddr instruction entry address
Program Memory
0020H
Caution start address interrupt vector shown above consists bits. start address must within 16K-byte space (0000H 3FFFH). Remark addition above, PCDE PCXA instructions cause branch address with only low-order bits changed.
µPD75517(A)
DATA MEMORY (RAM)
data memory divided into data area peripheral hardware area shown Fig. 3-3. data memory consists following memory banks, with each bank made words bits: Memory banks (data area) Memory bank (peripheral hardware area) Fig. Data Memory
Data memory General register area 000H 01FH 020H 0FFH 100H Memory bank
Data area Static (1024
Stack area
1FFH 200H
2FFH 300H
contained
F80H Peripheral hardware area FFFH
µPD75517(A)
Data area data area consists static RAM, used storing data stack memory subroutine interrupt execution. memory hold data even operation stopped standby mode, that suitable holding memory contents with battery long time. data area manipulated with memory manipulation instructions. static mapped memory banks with each made bits. Bank used data area, also used general register area (000H 01FH). Whole addresses memory banks (000H 3FFH) used stack area. static configuration four bits address. However, manipulation instructions enables 8-bit manipulation. Note that even address must specified 8-bit manipulation instruction. General register area general register area manipulated with either general register manipulation instructions memory manipulation instructions. 4-bit registers available. general registers, registers used program used data area stack area. Stack memory area stack area allocated within bank with stack pointer (SP). bank stack area selected from memory banks with stack bank select register (SBS). Stack area used save area subroutine interrupt execution. memory manipulation instructions manipulate stack bank select register (SBS) stack pointer (SP). Peripheral hardware area peripheral hardware area mapped addresses F80H FFFH memory bank Memory manipulation instructions used manipulate peripheral hardware area well static area. Note that, however, number bits manipulated time varies according individual addresses. Addresses which peripheral hardware assigned cannot accessed since such address locations contain data memory.
µPD75517(A)
GENERAL REGISTERS: BITS BANKS
general registers mapped particular addresses data memory. Four banks registers provided, with each bank consisting eight 4-bit registers register bank (RB) enabled time instruction execution determined (RBS Each general register allows 4-bit manipulation. addition, serves register pair 8-bit manipulation. also makes register pair well these three register pairs used data pointers. general register area addressed accessed normal RAM, regardless whether used register. Fig. General Register Format
Data memory Address 000H 001H 002H 003H 004H 005H 006H 007H 008H
Fig.
Register Pair Format
register register
register
register Register bank register
register
register register
Same bank
Register bank
00FH 010H
Same bank
Register bank
017H 018H
Same bank
Register bank
01FH
µPD75517(A)
ACCUMULATORS µPD75517(A), register register pair function accumulators. register mainly used 4-bit data processing instructions, register pair mainly used 8-bit data processing instructions. manipulation instruction, carry flag (CY) functions accumulator. Fig. Accumulators
accumulator
4-bit accumulator
8-bit accumulator
STACK POINTER (SP) STACK BANK SELECT REGISTER (SBS)
µPD75517(A) uses static stack memory (LIFO scheme), 8-bit register holding start address stack area stack pointer (SP). stack area located addresses 000H 3FFH memory banks Either memory banks selected according value 2-bit SBS. (See Table 3-1.) Table Stack Area Selected
SBS1
SBS2
Stack area Memory bank Memory bank Memory bank Memory bank
decremented before write (save) operation stack memory, incremented after read (restoration) operation from stack memory. with 4-bit memory manipulation instruction. Note that high-order bits always Fig. show data saved restored from stack memory these stack operations. place stack area given location, initialized with 8-bit memory manipulation instruction, initialized with 4-bit memory manipulation instruction. Both read from well. When initialized 00H, stack operation starts high-order address (nFFH) memory bank specified with SBS. stack area must within memory bank specified with SBS. stack operation exceeds address n00H, operation returns address nFFH same bank. Stacking beyond memory bank boundaries enabled only resetting SBS. RESET signal occurrence causes contents undefined, that must always initialized desired value start program.
µPD75517(A)
Fig.
Address F80H F84H SBS1 SBS0
Stack Pointer Stack Bank Select Register Formats
Symbol
000H 0FFH 100H Memory bank 1FFH 200H Memory bank 2FFH 300H Memory bank 3FFH Memory bank
Example
initialization this example, stack area allocated memory bank stack operation starts address 2FFH. MB15 CLR1 Specify memory bank stack area
SBS, #00H
µPD75517(A)
Fig. Data Saved Stack Memory
PUSH instruction
CALL, CALLA, CALLF instruction
Interrupt
Stack
Lower bits pair register Upper bits pair register
Stack PC11 PC14 PC13 PC12
Note
Stack PC11 PC14 PC13 PC12 IST1 IST0
Fig.
Data Restored from Stack Memory
instruction
RETS instruction
RETI instruction
Stack
Lower bits pair register Upper bits pair register
Stack PC11 PC14 PC13 PC12
Note
Stack PC11 PC14 PC13 PC12 IST1 IST0
Note other than saved/restored. Remark Data marked with undefined.
µPD75517(A)
PROGRAM STATUS WORD (PSW): BITS
program status word (PSW) consists various flags closely associated with processor operations. mapped addresses FB0H FB1H data memory space. four bits address FB0H manipulated with memory manipulation instruction. Fig. 3-10 Program Status Word Format
Address
FB1H IST1
FB0H IST0
Symbol
Cannot manipulated manipulated instruction specifically provided controlling this flag
manipulated
Table
Flags Saved/Restored Stack Operation
Saved/restored flag
Save
When CALL, CALLA, CALLF instruction executed When hardware interrupt occurs
saved. bits saved. restored. bits restored.
Restore
When RETS instruction executed When RETI executed
µPD75517(A)
Carry flag (CY) carry flag 1-bit flag used store overflow underflow occurrence information when arithmetic operation with carry (ADDC, SUBC) executed. carry flag also function accumulator, therefore used store result Boolean operation performed specified data memory address. carry flag manipulated using special instructions, independently other bits. RESET signal occurrence causes carry flag undefined. Table Carry Flag Manipulation Instructions
Instruction (mnemonic) Instruction dedicated carry flag manipulation SET1 CLR1 NOT1 MOV1 mem*.bit,CY MOV1 CY,mem*.bit AND1 CY,mem*.bit CY,mem*.bit XOR1 CY,mem*.bit
Carry flag operation/processing Sets Clears Inverts contents Skips Transfers contents specified bit. Transfers contents specified ANDs, ORs, XORs with contents specified bit, then sets result
transfer instruction
Boolean instruction
Interrupt handling
Saves other bits stack memory parallel. Interrupt execution -Restores together with other bits from stack memory. RETI
Remark
mem*.bit represents following three addressing modes: fmem.bit pmem.@L @H+mem.bit
Example
address ANDed with P33, then result output P50. MOV1 AND1 MOV1 PORT3.3 PORT5.0, high-order bits register @H+0FH.3
Skip flags (SK2, SK1, SK0) skip flags used store skip status, automatically reset when executes instruction. user cannot directly manipulate these flags operands. Interrupt status flag (IST1, IST0) interrupt status flag 2-bit flag used store status processing being performed. (For detailed information, Table 5-3.)
µPD75517(A)
Table Information Indicated Interrupt Status Flag
IST1
IST0
Status processing being performed Status
Processing interrupt control Normal program processing being performed. interrupts acceptable. lower- higher-priority interrupt being serviced. Higher-priority interrupts acceptable. higher-priority interrupt being serviced. interrupts acceptable.
Status
Status
interrupt priority control circuit (see Fig. 5-1) checks this flag control multiple interrupts. contents IST1 IST0 saved part stack memory interrupt accepted, then automatically one-step higher status. RETI instruction restores contents present before interrupt occurs. interrupt status flag manipulated using memory manipulation instruction, status processing being performed changed program control. Caution user must always disable interrupts with instruction before manipulating this flag, must enable interrupts with instruction after manipulating this flag. Memory bank enable flag (MBE) memory bank enable flag 1-bit flag used specify address information generation mode high-order four bits 12-bit data memory address. When data memory address space expanded, allowing data memory space addressed. When reset data memory address space fixed, regardless setting. (See Fig. 2-1.) RESET signal occurrence automatically initializes setting content program memory address vectored interrupt processing, automatically content vector address table servicing interrupt. Usually, interrupt processing, static memory bank used. Register bank enable flag (RBE) register bank enable flag 1-bit flag used determine whether expand general register bank configuration. When general registers selected from register banks depending setting register bank select register (RBS). When reset register bank always selected general registers, regardless setting RBS. RESET signal occurrence automatically initializes setting content program memory address When vectored interrupt occurs, automatically content vector address table servicing interrupt. Usually, interrupt processing. Register bank used 4-bit processing, register banks used 8-bit processing.
µPD75517(A)
BANK SELECT REGISTER (BS)
bank select register consists register bank select register (RBS) memory bank select register (MBS), which specify register bank memory bank used, respectively. using instruction instruction, respectively. contents saved restored from stack area eight bits time using PUSH BS/POP instruction. Fig. 3-11
Address F83H MBS3 MBS2 MBS1 MBS0
Bank Select Register Format
F82H RBS1 RBS0
Symbol
Memory bank select register (MBS) memory bank select register 4-bit register used store high-order four bits 12-bit data memory address. contents this register specify memory bank accessed. Note, however, that µPD75517(A) allows only memory banks specified. with instruction Fig. shows range addressing using settings. RESET signal occurrence initializes Register bank select register (RBS) register bank select register specifies register bank used general registers; register bank selected from register banks with instruction RESET signal occurrence initializes Table Register Bank Selected with
Bank selected. Bank selected. Register bank Bank always selected. Bank selected. Bank selected.
Always
Remark
Don't care
µPD75517(A)
PERIPHERAL HARDWARE FUNCTIONS
DIGITAL PORTS µPD75517(A) employs memory-mapped I/O, enabling ports mapped data memory space. Fig. Data Memory Address Assigned Digital Port
P103 P113 P123 P133 P143 P153 P102 P112 P122 P132 P142 P152 P101 P111 P121 P131 P141 P151 P100 P110 P120 P130 P140 P150 Symbol PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT
Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH
Table lists port manipulation instructions. These instructions provide wide range control including 8-bit manipulation well 4-bit I/O. Examples Test state P13, then output different values ports according test result. PORT1.3 Skip port
#18H #14H MB15
Consecutive
CLR1
PORT4, Ports SET1 PORT4.@L ports specified register
µPD75517(A)
Table Manipulation Instructions
Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port PORTnNote PORTnNote
PORTn.ANote PORTn.XANote
SET1 PORTn.bit SET1 PORTn.@LNote
CLR1 PORTn.bit CLR1 PORTn.@LNote
PORTn.bit PORTn.@LNote
PORTn.bit PORTn.@LNote
MOV1 PORTn.bit MOV1 PORTn.@LNote
MOV1 PORTn.bit, MOV1 PORTn.@L, CYNote
AND1 PORTn.bit AND1 PORTn.@LNote
PORTn.bit PORTn.@LNote
XOR1 PORTn.bit XOR1 PORTn.@LNote
Notes Before instruction executed, must must when lower bits address address specified indirectly with register.
µPD75517(A)
Types, features, configurations digital ports Table lists types digital ports. Fig. through present configurations ports. Table
Port name PORT0 Function 4-bit input
Types Features Digital Ports
Operation feature Remarks
Allows read test time regardless Also used INT4, SCK0, SO0/ operation modes dual function pins. SB0, SI0/SB1. Also used INT0 INT2, TI0.
PORT1
PORT2 PORT3Note PORT4Note PORT5Note PORT6
4-bit
Allows input output mode setting units Also used PTO0, PCL, BUZ. bits. Allows input output mode setting units bits.
4-bit (N-chan- Allows input output Ports pull-up resistors open-drain mode setting units paired, allowing data specified mask options bits. units bits. units bits. 4-bit Allows input output Ports Also used KR3. mode setting units paired, allowing data bits. units bits. Allows input output mode setting units bits. 4-bit input Also used KR7.
PORT7
PORT8
Allows read test time regardless Also used PPO, SCK1, SO1, operation modes dual function pins. SI1. Allows input output mode setting units pull-down resistor bits. specified mask option units bits. Allows input output mode setting units bits.
PORT9
4-bit
PORT10 PORT11 PORT12 PORT13 PORT14 PORT15
4-bit
4-bit (N-chan- Allows input output mode setting units pull-up resistors specified mask options open-drain bits. units bits. 4-bit input Allows read test time regardless Also used AN7. operation modes dual function pins.
Note This port directly drive LED. also used external vectored interrupt input pin. This input provided with noise eliminator. (See Section details.) pull-up resistors specified ports (excluding P00/INT4), software.
µPD75517(A)
Setting mode shown Fig. 4-9, mode each port with port mode register. Each port functions input port when corresponding port mode register functions output port when same 8-bit memory manipulation instruction used port mode register group generation RESET signal clears bits each port mode register This means that output buffers ports function input mode.
µPD75517(A)
Fig.
Configuration Ports
output latch Internal SCK0
SCK0 INT4
Selector CSIM0
Selector
Pull-up resistor P-ch POGA P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1
Input buffer
Output buffer which switched either push-pull output N-ch open-drain output Pull-up resistor
Internal
P-ch POGA Input buffer fX/64 Noise elimination circuit P10/INT0 P11/INT1 P12/INT2 P13/ INT2 INT1 INT0 Input buffer with hysteresis
SCK1
Internal SCK1
CSIM1
P80/PPO P81/SCK1 P82/SO1 P83/SI1 Input buffer
µPD75517(A)
Fig. Configuration Ports
Input buffer PMmn POGA
Internal
PMmn
Pull-up resistor
P-ch
Output buffer Output latch
PMmn port mode register group
Fig.
Configuration Ports
Pull-up resistor P-ch POGA Input buffer
Internal
Output buffer port mode register group
Output latch
µPD75517(A)
Fig. Configuration Ports
Pull-up resistor (mask option) Input buffer
Internal
Open-drain output buffer
Output latch
Port mode registers group Ports group Ports
µPD75517(A)
Fig.
port mode register group
Configuration Port
Output buffer
Output latch
Internal
Input buffer
Pull-down resistors (mask option)
µPD75517(A)
Fig. Configuration Ports
Input buffer
Internal
CMOS output buffer port mode register group
Output latch
Fig.
Input instruction
Configuration Port
Input buffer AN4/P150
Internal
AN5/P151
AN6/P152
AN7/P153
converter
µPD75517(A)
Fig. Port mode register group
Address FE8H Symbol PMGA specification specification specification specification specification specification specification specification
Formats Port Mode Registers
PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30
Port mode register group
Address FECH Symbol PMGB Port (P20-P23) specification Port (P40-P43) specification Port (P50-P53) specification Port (P70-P73) specification
Port mode register group
Address FEEH -Note Symbol PMGC Port (P90 P93) specification Port (P100 P103) specification Port (P110 P113) specification Port (P120 P123) specification Port (P130 P133) specification Port (P140 P143) specification Contents specification Input mode (Output buffer off) Output mode (Output buffer
-Note PM14 PM13 PM12 PM11 PM10
Note develop program, these bits must They correspond PM15. While this chip input-only device, emulator ports.
µPD75517(A)
Operation digital ports When instruction executed, operation port pins depends mode setting, listed Table 4-3. Table Port Operations Instructions
corresponding mode register Input mode corresponding mode register
Input mode
[Output buffer off] When 1-bit test instruction, 8-bit instruction executed When 8-bit output instruction executed When 1-bit output instructionNote executed Receives data certain pins.
[Output buffer Receives contents output latch.
Transfers data accumulator output latch. contents output latch undefined.
Outputs data accumulator output pins. Changes output state according instruction.
Note Instruction such SET1 PORTn.bit CLR1 PORTn.bit
µPD75517(A)
pull-up pull-down resistors Ports (excluding P00/INT4), provided with pull-up resistors software. Ports provided with pull-up resistors mask options. Port also provided with pull-down resistors mask options. Table
Port (pin name) Port (P01-P03)Note
Specifying Pull-Up Pull-Down Resistors
Specifying pull-up pull-down resistor pull-up resistors specified units bits software. pull-up resistors specified units bits software. POGA
Port (P10-P13) Port (P20-P23) Port (P30-P33) Port (P60-P63) Port (P70-P73) Port (P40-P43) Port (P50-P53) Port (P120-P123) Port (P130-P133) Port (P140-P143) Port (P90-P93)
pull-up resistors specified units bits mask options.
pull-down resistors specified units bits mask options.
Note cannot provided with pull-up resistor. Fig. 4-10
Address FDCH
Format Register Group Specifying Pull-Up Resistors
Symbol POGA Port (P01 P03) Port (P10 P13) Port (P20 P23) Port (P30 P33) Port (P60 P63) Port (P70 P73) Specification contents built-in pull-up resistor provided Built-in pull-up resistor provided
µPD75517(A)
CLOCK GENERATOR Configuration clock generator clock generator supplies various clock signals peripheral hardware. Fig. 4-11 shows configuration clock generator. Fig. 4-11 Block Diagram Clock Generator
Subsystem clock generator Clock timer Timer/pulse generator
Basic interval timer (BT) Timer/event counter Serial interface Clock timer Clock output circuit converter
Main system clock generator
1/16
1/4096 Frequency divider
SCC3
Oscillator disable signal
Selector Frequency divider Selector clock
SCC0
Internal
PCC0
PCC1 HALT Note STOP Note PCC2 HALT
PCC3
PCC2, PCC3 clear signal
STOP
Wait release signal from RESET signal
Standby release signal from interrupt control circuit
Note
Instruction execution Main system clock frequency
Remarks
Subsystem clock frequency Processor clock control register SCC: System clock control register
µPD75517(A)
Functions clock generator clock generator generates clock signals listed below, controls standby mode other operation modes. Main system clock Subsystem clock clock Clocks peripheral hardware operation clock generator determined processor clock control register (PCC) system clock control register (SCC). clock generator functions operates described below. generation RESET signal selects lowest-speed modeNote main system clock. (PCC When main system clock selected, select four clocksNote When main system clock selected, standby modes, STOP mode HALT mode, available. select subsystem clock very low-speed, low-current operation (122 32.768 kHz). this case, value does affect clock signal. When subsystem clock selected, main system clock generation stopped with SCC. addition, HALT mode used, STOP mode cannot used. (Subsystem clock generation cannot stopped.) Clocks peripheral hardware produced dividing main system clock signal. Only watch timer, subsystem clock directly supplied that watch buzzer output functions operate continuously even standby mode. When subsystem clock selected, watch timer operate normally, other hardware cannot used because they operate with main system clock. Notes 10.7 MHz) 15.3 4.19 MHz) 0.67 1.33 2.67 10.7 MHz), 0.95 1.91 3.82 15.3 4.19 MHz)
µPD75517(A)
Processor clock control register (PCC) 4-bit register selecting clock with low-order bits selecting operation mode with high-order bits. (See Fig. 4-12.) When standby mode set. When this released standby release signal, these bits automatically cleared return normal operation mode. (See Chapter detailed information.) 4-bit memory manipulation instruction used low-order bits PCC. (The high-order bits using STOP instruction HALT instruction, respectively. STOP instruction HALT instruction executed regardless setting. clock selected only when main system clock used operation. When subsystem clock selected operation, low-order bits invalidated, fXT/4 automatically set. STOP instruction executed only when main system clock used operation. generation RESET signal clears Examples machine cycle 0.95 4.19 MHz). MB15 #0011B PCC, STOP mode set. STOP instruction HALT instruction must always followed instruction.) STOP
µPD75517(A)
Fig. 4-12
Address FB3H PCC3 PCC0
Format Processor Clock Control Register
Symbol
PCC2 PCC1
clock selection Operation with indicates clock frequency (93.7 kHz) (375 kHz) (750 kHz) (1.5 MHz) machine cycle 10.7 2.67 1.33 0.67 indicates 32.768 clock frequency fXT/4 (8.192 kHz) fXT/4 (8.192 kHz) machine cycle
Operation with 4.19 indicates 4.19 clock frequency (65.5 kHz) (262 kHz) (524 kHz) (1.05 MHz) machine cycle 15.3 3.82 1.91 0.95 indicates 32.768 clock frequency fXT/4 (8.192 kHz) fXT/4 (8.192 kHz) machine cycle
Remarks
Output frequency from main system clock oscillator Output frequency from subsystem clock oscillator
operation mode control bits Normal operation mode HALT mode STOP mode
µPD75517(A)
System clock control register (SCC) 4-bit register selecting clock with least significant controlling termination main system clock generation with most significant bit. (See Fig. 4-13.) SCC.0 SCC.3 located same data memory address, both bits cannot changed same time. Accordingly, SCC.0 SCC.3 using manipulation instructions. SCC.0 SCC.3 manipulated regardless setting. Main system clock generation terminated setting SCC.3 only when subsystem clock used operation. STOP instruction must used generation termination when main system clock used operation. generation RESET signal clears Fig. 4-13
Address FB7H SCC3 SCC0
Format System Clock Control Register
Symbol
SCC3 SCC0
clock frequency Main system clock Subsystem clock Subsystem clock
Main system clock operation oscillate
Oscillation stopped
Cautions time period 1/fXT needed change system clock. This means that terminate main system clock generation, SCC.3 must when machine cycles indicated Table more have elapsed after clock switched from main system clock subsystem clock. When main system clock used operation, setting SCC.3 stop clock generation does enter normal STOP mode. When SCC.3 input connected (GND electric potential) prevent leakage crystal oscillator. When external clock used main system clock, never SCC.3 When four bits 0001B fX/16), SCC.0 Before switching main system clock subsystem clock, sure manipulate bits other than 0001B set. When system operates subsystem clock, bits must also other than 0001B.
µPD75517(A)
System clock oscillator main system clock oscillator operates with crystal (6.0 standard) ceramic resonator connected pins. external clock also input. Fig. 4-14 External Circuitry Main System Clock Oscillator External clock
Crystal/ceramic oscillation
PD75517(A)
External clock
PD75517(A)
Crystal oscillator ceramic oscillator
subsystem clock oscillator operates with crystal resonator (32.768 standard) connected pins. external clock also input. Fig. 4-15 Crystal oscillation External Circuitry Subsystem Clock Oscillator External clock
PD75517(A)
External clock
PD75517(A)
32.768
Open
caution connecting oscillator described next page.
µPD75517(A)
Caution When main system clock subsystem clock oscillator used, conform following guidelines when wiring shaded portions Fig. 4-14 4-15 eliminate influence wiring capacity. wiring must short possible. Other signal lines must these areas. line carrying high fluctuating current must kept away possible. grounding point capacitor oscillator must have same potential that VSS. must grounded ground patterns carrying large current. signal must taken from oscillator. When subsystem clock used, special attention wiring; subsystem clock oscillator amplification minimize current consumption more likely malfunction noise than main system clock oscillator.
µPD75517(A)
Time required change system clock clock system clock clock changed using least significant loworder bits PCC. This switching performed immediately after contents registers rewritten, system operates with previous clock some machine cycles. Accordingly, after this time period, STOP instruction must executed SCC.3 must terminate main system clock generation. Table
Setting before switching
Maximum Time Required Change System Clock Clock
Setting after switching
SCC0 PCC1 PCC0
SCC0 PCC1 PCC0 machine cycle
SCC0 PCC1 PCC0 machine cycle
SCC0 PCC1 PCC0 machine cycle
SCC0 PCC1 PCC0 /64fXT machine cycles machine cycles)
machine cycles
machine cycles
machine cycles
fX/8fXT machine
machine cycles
machine cycles
machine cycles
cycles machine cycles) fX/4fXT machine
machine cycles machine cycles machine cycles
cycles machine cycles)
machine cycle
machine cycle
machine cycle
Remarks Time enclosed parentheses required when 32.768 kHz. Don't care clock supplied CPU. reciprocal this frequency minimum instruction time (defined machine cycle this manual). Caution When four bits 0001B fX/16), SCC.0 Before switching main system clock subsystem clock, sure manipulate bits other than 0001B set. When system operates subsystem clock, bits must also other than 0001B.
µPD75517(A)
Procedure changing system clock clock procedure changing system clock clock explained using Fig. 4-16. Fig. 4-16 Changing System Clock Clock
Commercial power line voltage
voltage
RESET signal Wait (31.3 System clock clock 15.3 Internal reset operation 0.95 0.95
4.19 32.768
generation RESET signal starts operation lowest speed main system clockNote after wait timeNote stable oscillation. rewritten highest-speed operation after time elapse which sufficient voltage high enough highest-speed operation. removal commercial power detected using, example, interrupt input (INT4 useful), then SCC.0 operate with subsystem clock. this case, start subsystem clock generation must confirmed beforehand.) After time machine cycles) required switch subsystem clock elapses, SCC.3 terminate main system clock generation.
After detecting input commercial power using interrupt, SCC.3 cleared start main system clock generation. After time required stable generation, SCC.0 cleared operate highest speed.
Notes 10.7 MHz) 15.3 4.19 MHz) 21.8 MHz) 31.3 4.19 MHz)
µPD75517(A)
CLOCK OUTPUT CIRCUIT
Configuration clock output circuit Fig. 4-17 shows configuration clock output circuit.
Functions clock output circuit clock output circuit outputs clock pulse signal P22/PCL remote control supplying clock pulses peripheral device. procedure outputting clock pulse signal follows:
Select clock output frequency, disable clock output. Write output latch. output mode port Enable clock output.
Fig. 4-17
From clock generator X/23 Selector X/24
Configuration Clock Output Circuit
Output buffer PCL/P22
PORT2.2
CLOM3 CLOM1 CLOM0 CLOM
PMGB
Port input/ output mode specification
output latch
Internal
Remark clock output circuit designed that pulses with short widths appear enabling disabling clock output.
µPD75517(A)
Clock output mode register (CLOM) CLOM 4-bit register control clock output. CLOM with 4-bit memory manipulation instruction. read operation allowed this register. clock output PCL/P22 pin. MB15 CLR1 #1000B CLOM,
Example
generation RESET signal clears CLOM disabling clock output.
Fig. 4-18
Address FD0H
Format Clock Output Mode Register
Symbol CLOM
CLOM3
CLOM1 CLOM0
Clock output frequency selection (Frequency when MHz) Output
Note
(1.50 MHz, kHz, kHz, 93.7 kHz)
Output fX/2 (750 kHz) Output fX/24 (375 kHz) Output fX/26 (93.7 kHz)
(Frequency when 4.19 MHz) Output Note (1.05 MHz, kHz, kHz, 65.5 kHz) Output fX/23 (524 kHz) Output fX/24 (262 kHz) Output fX/2 (65.5 kHz)
Note clock supply selected PCC. Clock output enable/disable Output disable Output enable
Caution
sure write CLOM.
µPD75517(A)
Application remote control output clock output function µPD75517(A) applicable remote control output. frequency carrier remote control output selected clock frequency select clock output mode register. Pulse output enabled disabled controlling clock output enable/disable software. clock output circuit designed that pulses with short widths appear enabling disabling clock output.
Fig. 4-19
CLOM3
Application Remote Control Output
output
µPD75517(A)
BASIC INTERVAL TIMER
Configuration basic interval timer Fig. 4-20 shows configuration basic interval timer.
Basic interval timer functions basic interval timer provides following functions:
Interval timer operation that generates reference time interrupt Application watchdog timer detecting program crashes Selection wait time releasing standby mode, counting Reading count value
Fig. 4-20
From clock generator fX/25 fX/27 fX/2
Configuration Basic Interval Timer
Clear signal
Clear signal
Basic interval timer (8-bit frequency divider circuit)
signal
interrupt request flag
fX/212
IRQBT
Vectored interrupt request signal
Wait release signal standby release BTM0 Internal
BTM3 SET1 Note
BTM2
BTM1
Note Instruction execution
µPD75517(A)
Basic interval timer mode register (BTM) 4-bit register that controls operation basic interval timer. Bcontents using 4-bit memory manipulation instruction. independently using manipulation instruction. When contents basic interval timer cleared, basic interval timer interrupt request flag (IRQBT) also cleared start basic interval timer). generation RESET signal clears contents longest interrupt request signal generation interval time set.
Examples
interrupt generation interval 1.95 (4.19 MHz). MB15 #1111B BTM, MB15 BTM.3 1111B CLR1 CLR1
Clear IRQBT (application watchdog timer) SET1
µPD75517(A)
Fig. 4-21
Address F85H
Format Basic Interval Timer Mode Register
Symbol B
BTM3
BTM2
BTM1
BTM0
(Frequency when MHz) Input clock specification /212 (1.46 kHz) (11.7 kHz) (46.9 kHz) (188 kHz)
Interrupt interval time (wait time releasing standby) (175 217/fX (21.8 215/fX (5.46 213/fX (1.37
Other setting
(Frequency when 4.19 MHz) Input clock specification
Interrupt interval time (wait time releasing standby) (250 217/fX (31.3 215/fX (7.82 213/fX (1.95
(1.02 kHz) (8.18 kHz) (32.768 kHz) (131 kHz)
Other setting
Basic interval timer start control When written this bit, basic interval timer operation starts (the counter interrupt request flag cleared). When operation starts, this automatically reset
µPD75517(A)
Operation basic interval timer basic interval timer (BT) always incremented clock supplied from clock generator, when overflows, interrupt request flag (IRQBT) set. count operation cannot stopped. four interrupt generation intervals selected setting BTM. (See Fig. 4-21.) basic interval timer interrupt request flag cleared setting (instruction starting interval timer). count status read using 8-bit manipulation instruction. data loaded timer. Caution When reading count value basic interval timer, execute read instruction twice that unstable data which been counted will read. read values reasonable, second result. read values apart, retry from beginning.
Example
Read count value SET1 LOOP: MB15 address First read Second read LOOP
allow system clock stabilize after releasing STOP mode, wait function available which stops operation until basic interval timer overflows. wait time after generation RESET signal fixed. other hand, wait time selected setting Bwhen releasing STOP mode with interrupt occurrence. this case, wait times same interval times shown Fig. 4-21. Bmust before STOP mode set. (For details, Chapter
µPD75517(A)
CLOCK TIMER
Clock timer µPD75517(A) contains channel clock timer. Fig. 4-22 shows configuration timer.
Clock timer functions clock timer sets test flag (IRQW) every seconds. standby mode released with IRQW. Either main system clock subsystem clock produce 0.5-second intervals. fast-forward mode produces interval times faster (3.91 ms), which useful program debugging testing. fixed frequency (2.048 kHz) output P23/BUZ pin, that used sounding buzzer system clock frequency trimming. frequency divider cleared, clock start from zero seconds.
Caution
When main system clock operates MHz, time interval cannot produced. Before producing this time interval, main system clock must changed subsystem clock.
Fig. 4-22
Block Diagram Clock Timer
(256 3.91
From clock generator
(32.768 kHz) (32.768 kHz)
(32.768 kHz) Selector Frequency divider
Selector
INTW IRQW signal
(2.048 kHz) Clear signal Output buffer P23/BUZ
PORT2.3 output latch
PMGB
Port input/ output mode
Internal
Remark values parentheses 4.194304 32.768
µPD75517(A)
Clock mode register clock mode register (WM) 8-bit register that controls clock timer, that with 8-bit memory manipulation instruction. Fig. 4-23 shows format. generation RESET signal clears bits
Example
main system clock (4.19 MHz) setting time, enable buzzer output. CLR1 #84H
Fig. 4-23
Address F98H
Format Clock Mode Register
Symbol
Count clock (fW) selection Selects subsystem clock: Selects divided system clock output:
Operation mode selection Normal clock mode sets IRQW
Advanced clock mode
sets IRQW 3.91
Clock operation enable/disable Enables clock operation Disables clock operation (clears frequency dividing circuit)
output enable/disable Enables output Disables output
µPD75517(A)
TIMER/EVENT COUNTER
Configuration timer/event counter µPD75517(A) contains channel timer/event counter, which configured shown Fig. 4-24.
Functions timer/event counter timer/event counter following functions.
Programmable interval timer operation Output square wave given frequency PTO0 Event counter operation Frequency divider operation that divides input outputs result PTO0 Supply serial shift clock signal serial interface circuit Function reading state counting
Timer/event counter mode register (TM0) timer/event counter output enable flag (TOE0) timer/event counter mode register (TM0) 8-bit register controlling timer/event counter. Fig. 4-25 shows format. 8-bit memory manipulation instruction used timer/event counter mode register. timer start bit, independently other bits. automatically reset when timer starts operation.
Examples
timer started interval timer mode with 4.09 kHz. MB15 #01001100B TM0, MB15 TM0.3 CLR1 TM0.bit3 CLR1
timer restarted according setting timer/event counter mode register. SET1
generation RESET signal clears bits timer/event counter output enable flag (TOE0) enables disables output timer (TOUT F/F) status PTO0 pin. timer (TOUT F/F) inverted match signal transmitted from comparator. timer reset when instruction sets timer mode register (TM0). generation RESET signal clears TOE0 TOUT
PORT1.3 Input buffer P13/ From clock generator
Fig. 4-24
Block Diagram Timer/Event Counter
Internal SET1 Note TMOD0 Modulo register TOE0
enable flag
PORT2.0
output latch signal
PGMB
TM06 TM05 TM04 TM03 TM02
Port input/ output mode
Match
serial interface TOUT Reset INTT0 Output buffer P20/PTO0
Comparator
Count register Clear signal
IRQT0 signal
Timer operation start signal RESET IRQT0 clear signal
(See Fig. 4-11.)
Note Instruction execution
µPD75517(A)
µPD75517(A)
Fig. 4-25
Address FA0H
Format Timer/Event Counter Mode Register
TM06 Symbol
TM05 TM04 TM03 TM02
Operation mode Count operation Halts (retains contents counting) Count operation
Timer start specification When written this bit, counter IRQT0 flag cleared. Count operation starts been
Count pulse (CP) select (Frequency when MHz) TM06 TM05 TM04 Count pulse (CP) input rising edge input falling edge /210 (5.86 kHz) (23.4 kHz) (93.8 kHz) (375 kHz)
Other setting
(Frequency when 4.19 MHz) TM06 TM05 TM04 Count pulse (CP) input rising edge input falling edge /210 (4.09 kHz) (16.4 kHz) (65.5 kHz) (262 kHz)
Other setting
µPD75517(A)
Fig. 4-26
Address FA2H
Format Timer/Event Counter Output Enable Flag
TOE0 Timer/event counter output enable flag Disables Enables
Operation mode timer/event counter timer/event counter operates count operation disable mode count operation mode, depending setting mode register. following operations possible, regardless setting mode register:
P13/TI0 signal input test Output timer status PTO0 Setting modulo register (TMOD0) Reading from count register (T0) Setting, clearing, testing interrupt request flag (IRQT0)
Count operation disable mode This mode when this mode, count operation performed because count pulse (CP) supply count register stopped.
µPD75517(A)
Count operation mode This mode when this mode, count pulse signal selected with bits supplied count register count operation shown Fig. 4-28. Timer operation usually started following steps: count value modulo register (TMOD0). operation mode, count clock, start instruction mode register (TM0).
8-bit data transfer instruction used modulo register.
Caution value other than must modulo register.
Example value modulo register channel MB15 #3FH TMOD0, CLR1
value modulo register matches contents count register, match signal generated. Then, TOUT inverted, counter register cleared. interval time generation match signal calculated follows: (Set value modulo register resolution resolution 1/count pulse frequency. Table indicates resolution maximum time (when modulo register), depending selected count pulse.
Table (When MHz)
Mode register TM06 TM05 TM04
Resolution Maximum Time
Timer channel Resolution 42.7 10.7 2.67 Maximum time 43.7 10.9 2.73
(When 4.19 MHz)
Mode register TM06 TM05 TM04 Resolution 61.1 15.3 3.81 Timer channel Maximum time 62.5 15.6 3.91
µPD75517(A)
Fig. 4-27 Operation Count Operation Mode
INTT0 (IRQT0 signal)
Internal clock
Count register (T0)
Clear signal
Comparator
Match
TOUT
PTO0
Modulo register (TMOD0) (Only channel
Fig. 4-28
Timing Count Operation
Count pulse (CP)
Modulo register
Count register
Match
Match
TOUT
Reset
Timer start specification
µPD75517(A)
TIMER/PULSE GENERATOR
Timer/pulse generator functions µPD75517(A) contains channel timer/pulse generator that used timer pulse generator. following functions:
Functions available when timer/pulse generator used timer mode 8-bit interval timer operation using five clock sources (occurrence IRQTPG) Square wave output
Functions available when timer/pulse generator used pulse generation mode pulse output with accuracy bits (applicable electronic tuning when used converter) Generation interrupts regular intervals (215/fX)Note Note 15/fX 5.46 MHz) 7.81 4.19 MHz)
pulse output unnecessary, used 1-bit output port.
Caution
timer/pulse generator operating when STOP mode set, malfunction. timer/pulse generator must disabled with mode register advance.
µPD75517(A)
Timer/pulse generator mode register (TPGM) timer/pulse generator mode register (TPGM) 8-bit register that controls operation timer/ pulse generator. Fig. 4-29 shows format register. TPGM with 8-bit memory manipulation instruction. enables disables transfer (reloading) timer/pulse generator modulo register (MODH MODL) contents modulo latch. manipulated independently other bits. setting TPGM1 timer/pulse generator operation stopped decrease current consumption. generation RESET signal clears bits
Fig. 4-29
Address F90H
Format Timer/Pulse Generator Mode Register
Symbol TPGM
TPGM7
TPGM5 TPGM4 TPGM3
TPGM1 TPGM0
Timer/pulse generator operation mode selection TPGM0 Select pulse generation mode Select timer mode
Timer/pulse generator operation enable/disable TPGM1 Disable timer/pulse generator operation Enable timer/pulse generator operation
Modulo register reload enable/disable TPGM3 Disable reloading modulo register Enable reloading modulo register
output latch data TPGM4 Output output latch Output output latch
output selection static/pulse TPGM5 Static output Pulse output (square wave/PWM)
output enable/disable TPGM7 Disable output (high-impedance) Enable output
µPD75517(A)
Configuration operation when timer/pulse generator used timer mode Fig. 4-30 shows configuration when timer/pulse generator used timer mode. timer mode selected setting TPGM timer mode, TPGM3 must allowing modulo register reloaded time. timer mode, prescaler selected with modulo register (MODL), frequency interrupt interval value modulo register (MODH). timer starts when TPGM1 changed from Fig. 4-31 shows operation timing MODH setting, Table shows setting frequency interrupt interval. output switched between square wave output static output. output square wave, TPGM5 TPGM7
Fig. 4-30
Block Diagram Timer/Pulse Generator (Timer Mode)
Internal
MODL Modulo register TPGM3 (Set
MODH Modulo register
Modulo latch Match Comparator Frequency divider TPGM1 Clear Clear Prescaler select latch Selector
INTTPG IRQTPG signal Output buffer
Count register
TPGM4 TPGM5 TPGM7
µPD75517(A)
Example IRQTPG every 1.95 output high pin. CLR1 MODL, #0FFH MODH, #10011011B TPGM, Timer start, MB15 #00100000B
Caution
When timer operating timer operation mode stopped, IRQTPG because set. timer must stopped with interrupt being disabled, then IRQTPG must cleared.
Example
CLR1 CLR1 TPGM, IRQTPG
µPD75517(A)
Fig. 4-31
Timer Mode Operation Timing
MODH Count register (PPO)
TPGM1.
Generate IRQTPG.
Table (When MHz)
MODL bits
Modulo Register Settings
Interrupt generation interval MHz) (N+1)/fX 85.3 10.9 (N+1)/fX 42.7 5.46 (N+1)/fX 21.3 2.73 (N+1)/fX 10.7 1.37 (N+1)/fX 5.33
Square wave output frequency MHz) fX/256 (N+1) 91.6 11.7 fX/128 (N+1) 23.4 fX/64 (N+1) 46.9 fX/32 (N+1) 93.8 fX/16 (N+1) 1465
(When 4.19 MHz)
MODL bits Interrupt generation interval 4.19 MHz) (N+1)/fX 15.6 (N+1)/fX 61.0 7.81 (N+1)/fX 30.5 3.91 (N+1)/fX 15.3 1.95 (N+1)/fX 7.63 Square wave output frequency 4.19 MHz) fX/256 (N+1) fX/128 (N+1) fX/64 (N+1) fX/32 (N+1) fX/16 (N+1) 1024
Cautions value other than above cannot MODL. Bits must value MODH. must sure value from
µPD75517(A)
Configuration operation when timer/pulse generator used pulse generation mode Fig. 4-32 shows configuration when timer/pulse generator used pulse generation mode. pulse generation mode selected setting TPGM0 TPGM5 TPGM7 enable pulse output. mode, pulse signal output pin, IRQTPG intervals fixed time period (215/fX 5.46 7.81 4.19 MHz). pulses output µPD75517(A) active-low have accuracy bits. This pulse signal applicable electronic tuning control motor when integrated external low-pass filter converted analog voltage. (See Fig. 4-33.) pulse signal generated combining basic period determined 210/fX secondary period 215/fX that time constant external low-pass filter decreased. Table lists basic secondary periods oscillator frequency.
Table
Basic Secondary Periods
4.19 7.81
Basic period
(210/fX) (215/fX)
5.46
Secondary period
low-level width pulse depends 14-bit modulo latch value. upper bits modulo latch transferred from bits MODH, lower bits latch transferred from upper bits MODL. When pulse signal converted analog form, voltage level analog output obtained follows:
Vref
Value modulo latch
Vref: Reference voltage external switching circuitry
prevent incorrect pulse from being output unstable modulo latch data being rewritten,
µPD75517(A) allows correct data written MODH MODL beforehand with 8-bit manipulation
instructions, then 14-bit data which transferred modulo latch time. This transfer referred reloading, controlled TPGM3. TPGM3 reloading disabled, reloading enabled. Follow procedure below rewrite modulo latch contents:
(ii) (iii)
Clear TPGM3 disable reloading. Change MODH MODL contents. TPGM3 enable reloading.
Cautions
modulo register (MODH) pulse generator cannot function normally. sure MODH value from 255. lower bits modulo register (MODL) read, read result unpredictable. modulo latch changed shorter period than pulse basic period (171 4.19 MHz), pulses change.
µPD75517(A)
Example Decrease analog output voltage lowest level, then increase highest level. CLR1
#01H MODH, #00H MODL, #10101010B TPGM, Enable pulse output MODL MODH
CLR1 SET1
TPGM.3 #0FFH MODH, #0FCH MODL, TPGM.3
Disable reloading
Enable reloading
Static output When pulse output unnecessary, used normal static output. this case, output data TPGM4 with TPGM5 being TPGM7
µPD75517(A)
Fig. 4-32 Block Diagram Timer/Pulse Generator (PWM Pulse Generation Mode)
Internal
MODH Modulo register
MODL Modulo register
TPGM3
MODH Modulo latch (14) TPGM1 Frequency divider
MODL7-2 Output buffer Selector
pulse generator
INTTPG (IRQTPG signal) (215/fX 5.46 MHz) Note
TPGM5
TPGM7
Note
4.19 MHz: 7.81
Fig. 4-33
Sample Configuration Conversion Using PD75517(A)
Vref
PD75517
signal
Switching circuit
Low-pass filter
(analog voltage)
µPD75517(A)
SERIAL INTERFACE (CHANNEL
µPD75517(A) channels serial interface: Channel channel Table lists differences between channel channel
Table
Serial transfer mode, function 3-wire serial Clock selection Transfer method Transfer flag
Differences between Channel Channel
Channel fX/24 fX/23, TOUT F/F, external clock Start switchable: MSB/LSB Serial transfer interrupt request flag (IRQCSI0) Available Channel fX/24 fX/23, external clock Start bit: Serial transfer flag (EOT)
2-wire serial Serial interface (SBI)
available
µPD75517(A)
4.8.1 Serial Interface (Channel Functions clock synchronous 8-bit serial interface contained µPD75517(A) four modes. functions four modes outlined below.
Operation halt mode This mode used when serial transfer performed. This mode reduces power consumption.
Three-wire serial mode this mode, 8-bit data transferred through three lines: Serial clock (SCK0), serial output (SO0), serial input (SI0). three-wire serial mode allows full-duplex transmission, data transfer performed higher speed. user choose 8-bit data transfer starting with LSB, devices starting with either connected. three-wire serial mode enables connections made with series, series, many other types peripheral devices.
Two-wire serial mode this mode, 8-bit data transferred through lines: Serial clock (SCK0) serial data (SB0 SB1). controlling output levels lines software, communication with multiple devices enabled. output levels SCK0 SB1) controlled software, user match arbitrary transfer format. This means that line that been required handshaking connect multiple lines eliminated more efficient port utilization.
Serial interface (SBI) mode this mode, communication with multiple devices performed using lines: Serial clock (SCK0) serial data (SB0 SB1). This mode conforms serial format. this mode, transmitter output, serial data bus, address selecting device subject serial communication, commands directed remote device, data. receiver identify address, commands, data from received data hardware. This function enables more efficient port utilization case two-wire serial mode. addition, this function simplify serial interface control portion application program.
4.8.2
Configuration Serial Interface (Channel
Fig. 4-34 shows block diagram serial interface (channel
Fig. 4-34
Block diagram Serial Interface (Channel
Internal CSIM0 test Slave address register (SVA) Coincidence RELT signal Address comparator P03/SI/SB1 latch Selector Shift register (SIO0) CMDT SBIC manipulation test
ACKE
ACKT
P02/SO/SB0 Selector release/ command/ acknowledge detection circuit P01/SCK0 RELD CMDD ACKD
Busy/ acknowledge output circuit
BSYE
INTCSI0 Serial clock counter INTCSI0 control circuit IRQCSI0 signal fX/2 fX/2 fX/2 TOUT (from timer/event counter) External SCK0
output latch
Serial clock control circuit
µPD75517(A)
µPD75517(A)
4.8.3 Register Functions
Serial operation mode register (CSIM0) Fig. 4-35 shows format serial operation mode register (CSIM0). CSIM0 8-bit register which specifies serial interface (channel operation mode, serial clock, wakeup function, forth. CSIM0 manipulated using 8-bit memory manipulation instruction. higher three bits manipulated bit. Each manipulated using name. Each allow read and/or write operation. (See Fig. 4-35.) allows test operation only; data written this invalid. When RESET signal input, this register 00H.
Fig. 4-35
Address FE0H CSIE0
Format Serial Operation Mode Register (CSIM0) (1/3)
Symbol CSIM0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
Serial clock selection Serial interface operation mode selection Wake-up function specification Signal from address comparator Serial interface operation enable/disable specification
Remark
Read only Write only
µPD75517(A)
Fig. 4-35 Serial clock selection
Serial clock CSIM01 CSIM00 3-wire serial mode fX/24 mode 2-wire serial mode Input Output fX/26 (65.5 93.8 kHz) Note External clock applied SCK0 Time/event counter output (T0) (262 kHz)Note SCK0 mode
Format Serial Operation Mode Register (CSIM0) (2/3)
fX/23 (524 kHz)Note
Note values parentheses 4.19 MHz. Serial interface operation mode selection
sequence shift register SIO07-0 (Transfer starting with MSB) SIO00-7 (Transfer starting with LSB) SIO07-0 (Transfer starting with MSB)
CSIM04
CSIM03
CSIM02
Operation mode 3-wire serial mode
function SO0/P02 (CMOS output)
function SI0/P03 (Input)
mode
SB0/P02 (N-ch open-drain input/output) input
input
SB1/P03 (N-ch open-drain input/output) input
2-wire serial mode
SIO07-0 (Transfer starting with MSB)
SB0/P02 (N-ch open-drain input/output) input
SB1/P03 (N-ch open-drain input/output)
Remark Don't care Wake-up function specification
Sets IRQCSI0 each time serial transfer completed each mode. Used mode only IRQCSI0 only when address received after release matches data slave address register (wake-up state). SB0/SB1 goes high-impedance state.
Caution When during BUSY signal output, BUSY released. mode, BUSY signal output until next falling edge serial clock (SCK0) appears after release BUSY directed. Before setting sure confirm that SB1) high after releasing BUSY.
µPD75517(A)
Fig. 4-35 Format Serial Operation Mode Register (CSIM0) (3/3)
Signal from address comparator
COINote Condition being cleared (COI When slave address register (SVA) does match data shift register Condition being (COI When slave address register (SVA) matches data shift register
Note read only before serial transfer started after serial transfer completed. undefined value read during transfer. data written 8-bit manipulation instruction ignored.
Serial interface operation enable/disable specification
Shift register operation CSIE0 Shift operation disabled Shift operation enabled Serial clock counter Cleared Count operation IRQCSI0 flag Held set. SO0/SB0, SI0/SB1 Used only port Used each mode well port
Remarks Each mode selected setting CSIE0, CSIM03, CSIM02.
CSIE0 CSIM03 CSIM02 Operation mode Operation halt mode Three-wire serial mode mode Two-wire serial mode
P01/SCK0 assumes following state according setting CSIE0, CSIM01, CSIM00:
CSIE0 CSIM01 CSIM00 Serial clock output (High level output) Input port High impedance High level output P01/SCK0 state
µPD75517(A)
Remarks When clearing CSIE0 during serial transfer, following procedure:
Disable interrupts clearing interrupt enable flag. Clear CSIE0. Clear interrupt request flag.
Examples fX/2 selected serial clock, serial interrupt IRQCSI0, generated each time serial transfer completed, serial transfer performed mode with used serial data bus. MB15 CLR1
#10001010B CSIM0, CSIM0 10001010B
Serial transfer dependent contents CSIM0 enabled. MB15 CLR1
SET1 CSIE0
µPD75517(A)
Serial interface control register (SBIC) Fig. 4-36 shows format serial interface control register (SBIC). SBIC 8-bit register consisting bits controlling serial flags indicating states input data from serial bus. SBIC used mainly mode. SBIC manipulated using manipulation instruction. SBIC cannot manipulated using 4-bit 8-bit memory manipulation instruction. Each allow read and/or write operation. (See Fig. 4-36.) When RESET signal input, this register 00H.
Caution
Only following bits used three-wire two-wire serial modes:
release trigger (RELT): Sets latch. Command trigger (CMDT): Clears latch.
Fig. 4-36
Address FE2H BSYE
Format Serial Interface Control Register (SBIC) (1/3)
Symbol ACKE ACKT CMDD RELD CMDT RELT SBIC release trigger Command trigger release detection flag Command detection flag Acknowledge trigger Acknowledge enable (R/W) Acknowledge detection flag
ACKD
Busy enable (R/W)
Remark
Read only Write only
(R/W) Read/write
µPD75517(A)
Fig. 4-36 release trigger
RELT Control release signal (REL) trigger output. setting RELT latch Then RELT automatically cleared
Format Serial Interface Control Register (SBIC) (2/3)
Caution Never clear SB1) during serial transfer. sure clear SB1) before after serial transfer. Command trigger
CMDT Control command signal (CMD) trigger output. setting CMDT latch cleared Then CMDT automatically cleared
Caution Never clear SB1) during serial transfer. sure clear SB1) before after serial transfer. release detection flag
RELD Condition being cleared (RELD transfer start instruction executed. RESET signal entered. CSIE0 (See Fig. 4-35.) does match SIO0 when address received. Condition being (RELD release signal (REL) detected.
Command detection flag
CMDD Condition being cleared (CMDD transfer start instruction executed. release signal (REL) detected. RESET signal entered. CSIE0 (See Fig. 4-35.) Condition being (CMDD command signal (CMD) detected.
Acknowledge trigger
ACKT When after transfer, output phase with next SCK0. After signal output, this automatically cleared
Cautions
Never ACKT before during serial transfer. ACKT cannot cleared software. Before setting ACKT, ACKE
Acknowledge enable (R/W)
ACKE Disables automatic output acknowledge signal (ACK). (Output ACKT possible.) When before transfer When after transfer output phase with clock SCK0. output phase with SCK0 immediately following instruction execution.
µPD75517(A)
Fig. 4-36 Format Serial Interface Control Register (SBIC) (3/3)
Acknowledge detection flag
ACKD Condition being cleared (ACKD transfer start instruction executed. RESET signal entered. Condition being (ACKD acknowledge signal (ACK) detected phase with rising edge SCK0).
Busy enable (R/W)
busy signal automatically disabled. Busy signal output stopped phase with falling edge SCK0 immediately after clear instruction execution.
BSYE
busy signal output after acknowledge signal phase with falling edge SCK0.
Examples command signal output. SET1 accordingly. setting this interrupt routine processed only when address match found. DATA ADRS MB15 RELD !ADRS CMDD !DATA
MB15 CMDT
CLR1
RELD CMDD tested identify types received data types processing
RELD test CMDD test Command analysis Data processing Address decode
µPD75517(A)
Shift register (SIO0) Fig. 4-37 shows configuration peripheral hardware shift register SIO0 8-bit register which performs parallel-serial conversion serial transfer (shift) operation phase with serial clock. Serial transfer started writing data SIO0. transmission, data written SIO0 output serial output (SO0) serial data (SB0/SB1). reception, data read from serial input (SI0) SB0/SB1 into SIO0. Data read from written SIO0 using 8-bit manipulation instruction. When RESET signal entered during operation, value SIO0 undefined. When RESET signal entered standby mode, value SIO0 preserved. Shift operation stopped after 8-bit transmission reception completed.
Fig. 4-37
Peripheral Hardware Shift Register
Internal
Address comparator
RELT CMDT
Shift register (SIO0) CSIM0 Shift clock
latch
BUSY/ACK N-ch open-drain output
timing reading SIO0 start serial transfer (writing SIO0) follows: When serial interface operation enable/disable (CSIE0) However, case where CSIE0 after data written shift register excluded. When serial clock masked after 8-bit serial transfer SCK0 high.
µPD75517(A)
Slave address register (SVA) slave address register (SVA) functions described below. manipulated using 8-bit manipulation instruction. allows only write operation. When RESET signal entered, value undefined. However, value preserved when RESET signal entered standby mode.
Slave address detection mode] used when µPD75517(A) connected slave device serial bus. 8-bit register slave slave address (number assigned it). master outputs slave address connected slaves select particular slave. data values slave address output from master value SVA) compared with each other address comparator. match found, slave selected. this time, (COI) serial operation mode register (CSIM0)
Cautions Slave selection nonselection state detected detecting match slave address received after release state RELD this match detection, address match interrupt (IRQCSI0) generated when usually used. detect selection/nonselection state slave address when When detecting selection/nonselection state without using interrupt when address match detection method. Instead, transfer commands advance program.
Error detection two-wire serial mode mode] detects error either following cases: When addresses, commands, data transferred with PD75517(A) operating master When data transferred with µPD75517(A) operating slave
4.8.4 Signals Table 4-10 lists signals. Fig. 4-38 4-43 show operations signals flags.
Table 4-10
Various Signals (1/2)
Signal name
Output device Master
Definition
Timing chart
Condition output RELT set.
Flag operation RELD set. CMDD cleared.
Meaning signal Indicates that signal follows data transmitted address data.
release signal (REL)
Rising edge (SB1) when SCK0
SCK0 (SB1)
Command signal (CMD)
Master
Falling edge (SB1) when SCK0
CMDT set. SCK0 (SB1)
CMDD set.
Data transmitted after signal output address. (Data transmitted, with signal being output, command. Indicates completion reception.
Acknowledge signal (ACK)
Master/ slave
level signal output (SB1) during SCK0 clock cycle after serial reception completed SCK0
ACKE ACKT set.
ACKD set.
BUSY READY BUSY READY BSYE
Busy signal (BUSY)
Slave
level signal output (SB1) after acknowledge signal High level signal output (SB1) before serial transfer started after serial transfer completed
(SB1) (SB1)
Indicates that serial transfer disabled because processing progress.
µPD75517(A)
Ready signal (READY)
Slave
BSYE Execution instruction write data SIO0 (Transfer start request)
Indicates that serial transfar enabled.
Signal name Output device Master Definition Serial clock (SCK0) Synchronous clock outputting address/ command/data, signal, synchronous BUSY signal, Address/command/data output during first clock cycles. Address Master 8-bit data transferred phase with SCK0 after signal signal output Command Master 8-bit data transferred phase with SCK0 after only signal output, with signal being output Data Master/ slave 8-bit data transferred phase with SCK0, with neither signal signal being output SCK0 (SB1) SCK0 (SB1) SCK0 (SB1) SCK0 (SB1)
Table 4-10
Various Signals (2/2)
Timing chart
Condition output Execution instruction write data SIO0 when CSIE0 (serial transfer start request) Note
Flag operation IRQCSI0 rising edge clock) Note
Meaning signal Timing signal output serial data
Address slave device serial
Directions messages slave device
Data processed slave master
Notes When IRQCSI0 always rising edge SCK0. When IRQCSI0 rising edge SCK0 only received address matches value slave address register (SVA). BUSY state present, data transfer started after READY state set.
µPD75517(A)
µPD75517(A)
Fig. 4-38 Operations RELT, CMDT, RELD, CMDD (Master)
Transfer start request SIO0
SCK0
(SB1)
RELT
CMDT
RELD
CMDD
Fig. 4-39
Operations RELT, CMDT, RELD, CMDD (Slave)
Write SIO0.
Transfer start request SIO0
SCK0
latch
RELT (Master) CMDT (Master) When address match found RELD When address mismatch found CMDD
Fig. 4-40
SCK0
Operation ACKT
(SB1)
signal output during first clock cycle immediately after ACKT set.
ACKT
When during this period
Caution ACKT until transfer completed.
µPD75517(A)
Fig. 4-41 Operation ACKE
When ACKE time transfer completion
SCK0
signal output during ninth clock cycle
SB0/SB1
ACKE When ACKE this point
When ACKE after transfer completion
SCK0
signal output during first clock cycle immediately after ACKT set.
SB0/SB1
ACKE
When ACKE during this period ACKE falling edge next SCK0
When ACKE time transfer completion
SCK0
signal output
SB0/SB1
ACKE
When ACKE this point
When ACKE period short
SCK0 signal output
SB0/SB1
ACKE
When ACKE cleared during this period, ACKE falling edge SCK0
µPD75517(A)
Fig. 4-42 Operation ACKD
When signal output during ninth SCK0 clock
Transfer start request SIO0 Transfer start SCK0
SB0/SB1
ACKD
When signal output after ninth SCK0 clock
Transfer start request SIO0 Transfer start SCK0
SB0/SB1
ACKD
Clear timing case where start transfer requested during BUSY
Transfer start request SIO0
SCK0
SB0/SB1
BUSY
ACKD
Fig. 4-43
SCK0
Operation BSYE
SB0/SB1
BUSY
BSYE
When BSYE this point
When reset operation executed during this period BSYE falling edge SCK0.
µPD75517(A)
4.8.5 Serial Interface (Channel Operation
Operation halt mode operation halt mode used when serial transfer performed. This mode reduces power consumption. shift register does perform shift operation this mode, shift register used normal 8-bit register. When RESET signal entered, operation halt mode set. P02/SO0/SB0 P03/SI0/SBI function input-only port pins. P01/SCK0 used input port setting serial operation mode register
Three-wire serial mode operations three-wire serial mode compatible with other modes used series, µPD7500 series, series. Communication performed using three lines: Serial clock (SCK0), serial output (SO0), serial input (SI0).
Communication operation three-wire serial mode transfers data, with eight bits block. Data transferred phase with serial clock. shift register performs shift operation falling edge serial clock (SCK0). Transmit data latched latch, output pin. Receive data applied latched shift register rising edge SCK0. When eight bits have been transferred, shift register operation automatically terminates setting interrupt request flag (IRQCSI0).
Fig. 4-44
Timing Three-Wire Serial Mode
SCK0
IRQCSI0 Completion transfer Transfer started phase with falling edge SCK0. Execution instruction that writes data SIO0 (Transfer start request)
µPD75517(A)
becomes CMOS output outputs state latch. output state manipulated setting RELT CMDT bit. However, this manipulation must performed during serial transfer.
output state SCK0 controlled manipulating output latch output mode (internal system clock mode). (See Section 4.8.7.)
Switching between first transfer three-wire serial mode function that switch between first transfer. Fig. 4-45 shows configuration shift register (SIO0) internal bus. shown Fig. 4-45, read write operation performed switching between LSB. This switching specified using serial operation mode register (CSIM0).
Fig. 4-45
Internal first first
Transfer Switching Circuit
Read/write gate
Read/write gate
latch Shift resister0 (SIO0)
SCK0
first switched changing order data bits written shift register (SIO0). shift operation order SIO0 always same. Accordingly, first must switched between before writing data shift register
µPD75517(A)
Two-wire serial mode two-wire serial mode made compatible with communication format programming. this mode, communication basically performed using lines: Serial clock (SCK0) serial data input/output (SB0 SB1).
Communication operation two-wire serial mode transfers data, with eight bits block. Data transferred phase with serial clock. shift register performs shift operation falling edge serial clock (SCK0). Transmit data latched latch, output SB0/P02 SB1/P03 starting with MSB. Receive data applied latched shift register rising edge SCK0. When eight bits have been transferred, shift register operation automatically terminates setting interrupt request flag (IRQCSI0).
Fig. 4-46
Timing Two-Wire Serial Mode
SCK0
SB0/SB1
IRQCSI0 Completion transfer Transfer started phase with falling edge SCK0. Execution instruction that writes date SIO0 (Transfer start request)
becomes N-ch open-drain when specified serial data bus, voltage level that must pulled externally. state latch output pin, output states controlled setting RELT CMDT bit. However, this operation must performed during serial transfer.
output state SCK0 controlled manipulating output latch output mode (internal system clock mode). (See Section 4.8.7.)
µPD75517(A)
mode operation (serial interface) high-speed serial interface that conforms serial format. allow communication with multiple devices single-master high-speed serial using signal lines, configuration function added clock synchronous serial method. reduce ports wires boards when multiple microcomputers peripheral used configure serial bus. Fig. 4-47 example system configuration.
Fig. 4-47
Example System Configuration
+VDD
(SB1) Master SCK0
Serial data Serial clock
(SB1) SCK0
Slave Address
(SB1) SCK0
Slave Address
(SB1) SCK0
Slave Address
Cautions mode, serial data SB1) open-drain output. serial data line placed wired state. pull-up resistor required serial data line. switch between master slave, pull-up resistor required also serial clock line (SCK0), because SCK0 input/output switching performed between master slave asynchronously.
µPD75517(A)
functions Address/command/data identification function Serial data classified into three types: Address, command, data. Address-based chip select function master selects chip address transfer. Wake-up function slave easily check address reception (for chip select identification) with wake-up function. This function released software. When wake-up function set, interrupt (IRQCSI0) generated when match address received. this reason, communication with multiple devices, other than selected slave operate independently serial communication. Acknowledge signal (ACK) control function acknowledge signal, which used confirm reception serial data, controlled. Busy signal (BUSY) control function busy signal, which used post busy state slave, controlled.
µPD75517(A)
Fig. 4-48 Address transfer
SCK0
Timing Transfer
SB0/SB1 release signal
BUSY
Command transfer
SCK0
Command signal
SB0/SB1
BUSY
READY
Data transfer
SCK0
SB0/SB1
BUSY
READY
Communication operation mode, master usually selects slave device communicate with from multiple devices outputting address slave serial bus. After selecting device communicate with, master exchanges commands data with slave device, thus establishing serial communication. Fig. 4-49 4-52 show timing charts data communication operations. mode, shift register performs shift operation falling edge serial clock (SCK0). Transmit data held latch, output SB0/P02 SB1/P03 starting with MSB. Receive data applied SB1) latched shift register rising edge SCK0.
Master device processing (transmitter) Program processing Hardware operation Transfer line SCK0 Slave device processing (receiver) Program processing Hardware operation
Fig. 4-49
Address Transmission from Master Device Slave Device (WUP
CMDT
RELT CMDT
Write SIO0
Interrupt handling (preparation next serial transfer)
Serial transmission
Generate IRQCSI0
ACKD
Stop SCK0
BUSY
READY
Address
WUP0
ACKT
Clear BUSY
Clear CMDD CMDD CMDD RELD
Serial reception
Generate IRQCSI0
Output Output BUSY
Clear BUSY
(When SIO0)
µPD75517(A)
Fig. 4-50
Command Transmission from Master Device Slave Device
Master device processing (transmitter)
CMDT
Program processing
Write SIO0
Interrupt handling (preparation next serial transfer)
Hardware operation
Serial transmission
Generate IRQCSI0
ACKD
Stop SCK0
Transfer line SCK0
BUSY
READY
Command Slave device processing (receiver) Read SIO0
Analyze command
Program processing
ACKT
Clear BUSY
Hardware operation
CMDD
Serial reception
Generate IRQCSI0
Output Output BUSY
Clear BUSY
µPD75517(A)
Master device processing (transmitter) Program processing Hardware operation Transfer line SCK0 Slave device processing (receiver) Program processing Hardware operation
Fig. 4-51
Data Transmission from Master Device Slave Device
Write SIO0
Interrupt handling (preparation next serial transfer)
Serial transmission
Generate IRQCSI0
ACKD
Stop SCK0
Data
BUSY
READY
Read SIO0
ACKT
Clear BUSY
Serial reception
Generate IRQCSI0
Output Output BUSY
Clear BUSY
µPD75517(A)
Fig. 4-52
Data Transmission from Master Device Slave Device
Master device processing (receiver)
Write SIO0 Read Write SIO0 SIO0 ACKT
Program processing
Receive data processing
Hardware operation
Stop SCK0
Serial reception
Generate IRQCSI0
Output
Serial reception
Transfer line SCK0
BUSY
READY
Data
BUSY READY
Slave device processing (transmitter) Write SIO0 Write SIO0
Program processing
Hardware operation
Clear BUSY
Serial transmission
Generate IRQCSI0
ACKD
Output BUSY
Clear BUSY
µPD75517(A)
µPD75517(A)
4.8.6 Transfer Start Each Mode each three-wire serial I/O, two-wire serial I/O, modes, serial transfer started writing transfer data shift register (SIO0). However, following conditions must satisfied:
serial interface operation enable/disable (CSIE0) internal serial clock operating after 8-bit serial transfer, SCK0 high.
Caution Transfer cannot started setting CSIE0 after writing data shift register
When eight bits have been transferred, serial transfer automatically terminates setting interrupt request flag (IRQCSI0).
two-wire serial mode] Caution N-ch transistor needs turned when data received. must written SIO0 beforehand.
mode] Cautions N-ch transistor needs turned when data received. must written SIO0 beforehand. However, when wake-up function specification (WUP) N-ch transistor always off. need written SIO0 beforehand reception. data written SIO0 when slave busy, data lost. Transfer started when busy state released input SB1) goes high.
Example When data specified register transferred SIO0, SIO0 data loaded into accumulator same time, serial transfer started.
MB15 SIO0
Extracts transmit data from CLR1 Exchanges transmit data with receive data starts transfer
µPD75517(A)
4.8.7 Manipulation SCK0 Output SCK0/P01 built-in output latch, that this allows static output software manipulation addition normal serial clock output. number SCK0s software-set arbitrarily manipulating output latch. (The SO0/SB0/ controlled manipulating RELT CMDT bits SBIC.) procedure manipulating SCK0/P01 output explained below.
serial operation mode register (CSIM0) (SCK0 pin: output mode). When serial transfer halted, SCK0 from serial clock control circuit
Manipulate output latch using manipulation instruction.
Example output clock cycle SCK0/P01 software CLR1 SET1 MB15 CLR1 #10000011B SCK0 (fX/23), output mode CSIM0, 0FF0H.1 0FF0H.1 SCK0/P01 SCK0/P01
Fig. 4-53
SCK0/P01 Circuit Configuration
Address FF0H.1 output latch From serial clock control circuit
P01/SCK0
internal circuit
SCK0 When CSIE0=1 CSIM01 CSIM00
output latch mapped address FF0H. RESET signal sets output latch
Cautions
During normal serial transfer, output latch must output latch cannot addressed specifying PORT0.1 described below). address latch (0FF0H.1) must coded operand instruction directly. However, must specified before instruction executed. CLR1 PORT0.1 SET1 PORT0.1 CLR1 0FF0H.1 SET1 0FF0H.1 Allowed allowed
µPD75517(A)
4.9.1 SERIAL INTERFACE (CHANNEL Serial Interface (Channel Functions
µPD75517(A) modes. functions modes outlined below. Operation halt mode This mode used when serial transfer performed. This mode reduces power consumption. Three-wire serial mode 8-bit data transfer performed using three lines: Serial clock (SCK1), serial output (SO1), serial input (SI1). three-wire serial mode allows full-duplex transmission, data transfer performed higher speed. Eight-bit data transfer always starts MSB. three-wire serial mode enables connections made with series, series, many other types peripheral devices. 4.9.2 Serial Interface (Channel Configuration Fig. 4-54 shows block diagram serial interface (channel
Fig. 4-54
Block Diagram Serial Interface (Channel
Internal manipulation P83/SI1 Shift register SIO1 write signal (serial start signal) SIO1 Serial operation mode register CSIM1 manipulation
P82/SO1
Clear Serial clock counter Overflow Serial transfer flag (EOT)
Clear P81/SCK1 fX/23 fX/24
µPD75517(A)
µPD75517(A)
4.9.3 Register Functions
Serial operation mode register (CSIM1) Fig. 4-55 shows format serial operation mode register (CSIM1). CSIM1 8-bit register which specifies serial interface (channel operation mode serial clock. CSIM1 manipulated using 8-bit memory manipulation instruction. Only high-order manipulated independently. Each manipulated using name. When RESET signal input, this register 00H. Fig. 4-55
Address FC8H CSIE1 CSIM1 CSIM11 CSIM10
Format Serial Operation Mode Register (CSIM1)
Symbol
Serial clock selection Serial interface operation enable/disable specification
Remark
(W): Write only
Serial clock selection
CSIM11 CSIM10 Serial clock (3-wire serial mode) External clock applied SCK1 fX/24 (262 kHz)Note fX/23 (524 kHz)Note Output SCK1 mode Input
Note
values 4.19 indicated parentheses.
Serial interface operation enable/disable specification
Shift register operation CSIE1 Shift operation disabled Shift operation enabled
Serial clock counter Cleared Count operation Held
flag
SO1, Used only port Used serial interface well port
set.
Caution
sure write bits serial operation mode register (CSIM1).
µPD75517(A)
Example select fX/24 serial clock, serial transfer flag each time serial transfer terminates MB15 CLR1 CSIM1 10000010B #10000010B CSIM1, Shift register (SIO1) SIO1 8-bit register which performs parallel-serial conversion serial transfer (shift) operation phase with serial clock. Serial transfer started writing data SIO1. used first transfer. transmission, data written SIO1 output serial output (SO1). reception, data read from serial input (SI1) into SIO1. Data read from written SIO1 using 8-bit manipulation instruction. When RESET signal entered during operation, value SIO1 undefined. When RESET signal entered standby mode, value SIO1 preserved. Shift operation stopped after 8-bit transmission reception completed. timing reading SIO1 start serial transfer (writing SIO1) follows: When serial interface operation enable/disable (CSIE1) However, case where CSIE1 after data written shift register excluded. When serial clock masked after 8-bit serial transfer When SCK1 high 4.9.4 Serial Interface (Channel Operation
Operation halt mode operation halt mode used when serial transfer performed, which setting CSIE1. This mode reduces power consumption. Shift register does perform shift operation this mode, shift register used normal 8-bit register. When RESET signal entered, operation halt mode set. P82/SO1 P83/SI1 function input-only port pins. P81/SCK1 used input port setting serial operation mode register
µPD75517(A)
Three-wire serial mode operations three-wire serial mode compatible with other modes used series, µPD7500 series, series. This mode setting CSIE1 Communication performed using three lines: Serial clock (SCK1), serial output (SO1), serial input (SI1). three-wire serial mode transfers data with eight bits block. Data transferred phase with serial clock. Shift register performs shift operation falling edge serial clock (SCK1). Transmit data latched latch, output pin. Receive data applied latched shift register rising edge SCK1. When eight bits have been transferred, operation shift register automatically terminates setting serial transfer flag (EOT). Setting serial transfer flag (EOT) cannot release standby function. Fig. 4-56 Timing Three-Wire Serial Mode
SCK1<b
Other recent searches
SPP04N60C3 - SPP04N60C3 SPP04N60C3 Datasheet
SPB04N60C3 - SPB04N60C3 SPB04N60C3 Datasheet
SPA04N60C3 - SPA04N60C3 SPA04N60C3 Datasheet
RV3049C2 - RV3049C2 RV3049C2 Datasheet
PCA1292B-LF - PCA1292B-LF PCA1292B-LF Datasheet
MTB1306 - MTB1306 MTB1306 Datasheet
MIC2778 - MIC2778 MIC2778 Datasheet
L1034HD - L1034HD L1034HD Datasheet
L1034ID - L1034ID L1034ID Datasheet
L1034GD - L1034GD L1034GD Datasheet
L1034YD - L1034YD L1034YD Datasheet
ISL8489E - ISL8489E ISL8489E Datasheet
ISL8491E - ISL8491E ISL8491E Datasheet
BPF-1-2-3-4-5 - BPF-1-2-3-4-5 BPF-1-2-3-4-5 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
