4369.4 75A, 55V, 0.014 Ohm, N-Channel UltraFET Power MOSFETs

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

4369.4 75A, 55V, 0.014 Ohm, N-Channel UltraFET Power MOSFETs

Datasheet Thumbnail

Top Searches for this datasheet

HUF75337G3, HUF75337P3, HUF75337S3S
4369.4
75A, 55V, 0.014 Ohm, N-Channel UltraFET Power MOSFETs
These N-Channel power MOSFETs manufactured using innovative UltraFETprocess. This advanced process technology achieves lowest possible on-resistance silicon area, resulting outstanding performance. This device capable withstanding high energy avalanche mode diode exhibits very reverse recovery time stored charge. designed applications where power efficiency important, such switching regulators, switching converters, motor drivers, relay drivers, lowvoltage switches, power management portable battery-operated products. Formerly developmental type TA75337.
Features
75A, Simulation Models Temperature Compensated PSPICE® SABER© Models SPICE SABER Thermal Impedance Models Available Peak Current Pulse Width Curve Rating Curve Related Literature TB334, "Guidelines Soldering Surface Mount Components Boards"
Symbol
Ordering Information
PART NUMBER HUF75337G3 HUF75337P3 HUF75337S3S PACKAGE TO-247 TO-220AB TO-263AB BRAND 75337G 75337P 75337S
NOTE: When ordering, entire part number. suffix obtain TO-263AB variant tape reel, e.g., HUF75337S3ST.
Packaging
JEDEC STYLE TO-247
SOURCE DRAIN GATE DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE
DRAIN (TAB)
JEDEC TO-263AB
DRAIN (FLANGE) GATE SOURCE
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. UltraFETis trademark Intersil Corporation. PSPICE® registered trademark MicroSim Corporation. SABER© Copyright Analogy, Inc. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
HUF75337G3, HUF75337P3, HUF75337S3S
Absolute Maximum Ratings
25oC, Unless Otherwise Specified Figure Figures 1.17 UNITS
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note VDGR Gate Source Voltage Drain Current Continuous (Figure Pulsed Drain Current Pulsed Avalanche Rating Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief Tpkg
W/oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: 25oC 150oC.
Electrical Specifications
PARAMETER STATE SPECIFICATIONS
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
Drain Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
250µA, (Figure 50V, 45V, 150oC
±100
Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Case Thermal Resistance Junction Ambient
IGSS
±20V
VGS(TH) rDS(ON)
VDS, 250µA (Figure 75A, (Figure
0.011
0.014
(Figure TO-247 TO-220AB, TO-263AB
0.85
oC/W oC/W oC/W
SWITCHING SPECIFICATIONS (VGS 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Reverse Transfer Capacitance Qg(TOT) Qg(10) Qg(TH) 30V, 75A, Ig(REF) 1.0mA (Figure td(ON) td(OFF) tOFF 30V, 75A, 0.4, 10V,
HUF75337G3, HUF75337P3, HUF75337S3S
Electrical Specifications
PARAMETER CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure 1775 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL 75A, dISD/dt 100A/µs 75A, dISD/dt 100A/µs TEST CONDITIONS 1.25 UNITS
Typical Performance Curves
POWER DISSIPATION MULTIPLIER DRAIN CURRENT CASE TEMPERATURE (oC) CASE TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01
NOTES: DUTY FACTOR: t1/t2 PEAK 10-3 10-2 RECTANGULAR PULSE DURATION 10-1
0.01 10-5
SINGLE PULSE 10-4
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
HUF75337G3, HUF75337P3, HUF75337S3S Typical Performance Curves
1000
(Continued)
25oC
IDM, PEAK CURRENT
TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS:
TRANSCONDUCTANCE LIMIT CURRENT THIS REGION 10-5 10-4 10-3 10-2 PULSE WIDTH 10-1
FIGURE PEAK CURRENT CAPABILITY
1000
100µs
IAS, AVALANCHE CURRENT
RATED 25oC
DRAIN CURRENT
(L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED BVDSS VDD) STARTING 25oC
OPERATION THIS AREA LIMITED rDS(ON) VDSS(MAX)
10ms
STARTING 150oC
0.001
0.01
VDS, DRAIN SOURCE VOLTAGE
tAV, TIME AVALANCHE (ms)
NOTE: Refer Intersil Application Notes AN9321 AN9322. FIGURE FORWARD BIAS SAFE OPERATING AREA FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
ID(ON), DRAIN CURRENT
DRAIN CURRENT
PULSE DURATION 80µs DUTY CYCLE 0.5%
-55oC
25oC 175oC
PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC VDS, DRAIN SOURCE VOLTAGE
VGS, GATE SOURCE VOLTAGE
FIGURE SATURATION CHARACTERISTICS
FIGURE TRANSFER CHARACTERISTICS
HUF75337G3, HUF75337P3, HUF75337S3S Typical Performance Curves
NORMALIZED DRAIN SOURCE RESISTANCE PULSE DURATION 80µs DUTY CYCLE 0.5% 10V, NORMALIZED GATE THRESHOLD VOLTAGE
(Continued)
VDS, 250µA
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 250µA CAPACITANCE (pF)
3000 1MHz CISS CRSS COSS CISS 1800
2400
1200 COSS CRSS
JUNCTION TEMPERATURE (oC)
DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
GATE SOURCE VOLTAGE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER:
GATE CHARGE (nC)
NOTE: Refer Intersil Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
HUF75337G3, HUF75337P3, HUF75337S3S Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
IG(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORM
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE RESISTIVE SWITCHING WAVEFORMS
HUF75337G3, HUF75337P3, HUF75337S3S PSPICE Electrical Model
.SUBCKT HUF75337
2.4e-9 2.4e-9 1.63e-9
August 1997
LDRAIN DPLCAP RLDRAIN DBREAK EBREAK DRAIN RSLC1 ESLC
RSLC2
EBREAK 58.5 EVTHRES EVTEMP LDRAIN 1e-9 LGATE 3.58e-9 LSOURCE 7.7e-10 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK RBREAKMOD RDRAIN RDRAINMOD 2.3e-3 RGATE RLDRAIN RLGATE 35.8 RLSOURCE RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 6.0e-3 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
GATE
LGATE EVTEMP RGATE EVTHRES
RLGATE
MSTRO LSOURCE RSOURCE RLSOURCE SOURCE
VBAT ESLC .MODEL DBODYMOD 1.8e-12 3e-3 0.99 TRS1 2e-3 TRS2 9e-9 2.6e-9 1.1e-7 0.48) .MODEL DBREAKMOD 9.6e-2 9e-6 TRS1 1.5e-3 TRS2 -4.7e-5) .MODEL DPLCAPMOD (CJO 2.5e-9 1e-30 0.97 1.45) .MODEL MMEDMOD NMOS (VTO 1e-30 .MODEL MSTROMOD NMOS (VTO 3.71 1e-30 .MODEL MWEAKMOD NMOS (VTO =8e-3 1e-30 .MODEL RBREAKMOD (TC1 1.17e-3 -1.25e-6) .MODEL RDRAINMOD (TC1 1.9e-2 5e-6) .MODEL RSLCMOD (TC1 2.8e-3 1e-9) .MODEL RSOURCEMOD (TC1 1e-3 1e-5) .MODEL RVTHRESMOD (TC1 -3e-3 -3e-6) .MODEL RVTEMPMOD (TC1 -2.8e-3 1e-6) .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2BMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF VOFF= VOFF= VOFF= 1.5) =1.5 VOFF=
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD
RDRAIN
DBODY
MWEAK MMED
RBREAK RVTEMP
VBAT
RVTHRES
HUF75337G3, HUF75337P3, HUF75337S3S SABER Electrical Model
August 1997 template huf75337 electrical iscl d.model dbodymod 1.8e-12, 4.5, 2.6e-9, 1.1e-7, 0.99, 0.48) d.model dbreakmod d.model dplcapmod (cjo 2.5e-9, 1e-30, 0.97, 1.45) m.model mmedmod (type=_n, 3.2, 1e-30, DPLCAP m.model mstrongmod (type=_n, 3.71, 1e-30, m.model mweakmod (type=_n, 2.7, 8e-3, 1e-30, sw_vcsp.model s1amod (ron 1e-5, roff 0.1, voff sw_vcsp.model s1bmod (ron 1e-5, roff 0.1, voff sw_vcsp.model s2amod (ron 1e-5, roff 0.1, voff 1.5) RSLC2 sw_vcsp.model s2bmod (ron 1e-5, roff 0.1, 1.5, voff c.ca 2.4e-9 c.cb 2.4e-9 c.cin 1.63e-9 d.dbody model=dbodymod d.dbreak model=dbreakmod d.dplcap model=dplcapmod i.it l.ldrain 1e-9 l.lgate 3.58e-9 l.lsource 7.7e-10 m.mmed model=mmedmod, m.mstrong model=mstrongmod, m.mweak model=mweakmod, res.rbreak 1.17e-3, -1.25e-6 res.rdbody 3e-3, 2e-3, 9e-9 res.rdbreak 9.6e-2, 1.5e-3, -4.7e-5 res.rdrain 2.3e-3, 1.9e-2, 5e-6 res.rgate res.rldrain res.rlgate 35.8 res.rlsource res.rslc1 1e-6, 2.8e-3, 1e-9 res.rslc2 res.rsource 6e-3, 1e-3, 1e-5 res.rvtemp -2.8e-3, 1e-6 res.rvthres -3e-3, -3e-6 spe.ebreak 58.5 spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat equations (n51->n50) iscl iscl: v(n51,n50) 5.3))
LDRAIN RLDRAIN RDBREAK DBREAK MWEAK MMED MSTRO EBREAK RDBODY DRAIN RSLC1 ISCL
LGATE GATE RLGATE EVTEMP RGATE EVTHRES
RDRAIN
DBODY
LSOURCE RLSOURCE
SOURCE
RSOURCE RBREAK RVTEMP
VBAT
RVTHRES
HUF75337G3, HUF75337P3, HUF75337S3S SPICE Thermal Model
February 1999 HUF75337 CTHERM1 8.0e-7 CTHERM2 1.6e-6 CTHERM3 4.8e-3 CTHERM4 7.6e-3 CTHERM5 2.4e-2 CTHERM6 RTHERM1 1.3e-4 RTHERM2 1.8e-3 RTHERM3 3.7e-2 RTHERM4 2.3e-1 RTHERM5 3.4e-1 RTHERM6 6.4e-2
JUNCTION
RTHERM1
CTHERM1
RTHERM2
CTHERM2
SABER Thermal Model
SABER thermal model HUF75337 template thermal_model thermal_c ctherm.ctherm1 8.0e-7 ctherm.ctherm2 1.6e-6 ctherm.ctherm3 4.8e-3 ctherm.ctherm4 7.6e-3 ctherm.ctherm5 2.4e-2 ctherm.ctherm6 rtherm.rtherm1 1.3e-4 rtherm.rtherm2 1.8e-3 rtherm.rtherm3 3.7e-2 rtherm.rtherm4 2.3e-1 rtherm.rtherm5 3.4e-1 rtherm.rtherm6 6.4e-2
RTHERM3
CTHERM3
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
CASE
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site http://www.intersil.com

4369.4 75A, 55V, 0.014 Ohm, N-Channel UltraFET Power MOSFETs

Top Searches for this datasheet

Other recent searches