ELECTRON DEVICE µPD75238 SINGLE-CHIP MICROCOMPUTER µPD7
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INTEGRATED CIRCUIT
ELECTRON DEVICE
µPD75238
SINGLE-CHIP MICROCOMPUTER
µPD75238 single-chip microcomputer which contains capable 8-bit data processing, ROM, RAM, ports. addition, contains fluorescent display tube (FIP;) controller/driver, converter, clock timer, timer/pulse generator capable 14-bit output, serial interface, vectored interrupt function. comparison with PD75217, µPD75238 larger capacity been enhanced such peripheral facilities display function controller/driver, ports, converter, serial interface. µPD75238 finds best such applications timer/tuner VCRs from advanced type common type, configuration one-chip system control microcomputer, advanced player, advanced microwave ovens, etc. With PD75238, µPD75P238, which PROM product, various development tools including IE-75001-R assemblers available. They used evaluation during system development small-volume production.
FEATURES
Mass-storage built-in
Program memory (ROM) Data memory (RAM) FIP)
port: lines (excluding pins dedicated Minimum instruction execution time:
0.67 MHz)
8-bit converter: channels Enhanced timer/counter function: channels 8-bit serial interface: channels Application-oriented interrupt functions PROM version device: µPD75P238
Instruction execution time specification function allow wide range operating voltages
Programmable controller/driver contained
Number segments segments Number digits digits
ORDERING INFORMATION
Part number Package 94-pin plastic Quality grade Standard
Please refer "Quality Grade Semiconductor Devices" (Document number IEI-1209) published Corporation know specification quality grade devices recommended applications.
information this document subject change without notice. Document (O.D. Date Published Printed Japan IC-2777A IC-8177A) February 1993 Major changes this revision indicated stars margins.
Corporation 1992
µPD75238
FUNCTIONS
Item On-chip memory lines (Excluding pins dedicated FIP) Function ROM: 32640 bits, RAM: 1024 bits lines Input lines lines Output lines
Instruction cycle
0.67 µs/1.33 µs/2.67 µs/10.7 MHz) 0.95 µs/1.91 µs/3.82 µs/15.3 4.19 MHz) 32.768 kHz) Number segments segments Number digits digits Dimmer function levels Pull-down resistors provided mask option scan interrupt generator Basic interval timer Usable watchdog timer
Fluorescent display tube (FIP) controller/driver
Timer/counter channels
Timer/event counter Clock timer With buzzer output function Timer/pulse generator With 14-bit output function Event counter 3-wire mode 3-wire mode
Serial interface
channels
Interrupt
System clock oscillator
Allows multiple hardware interrupts. Detection both edges External interrupts Detection edge programmable (with noise elimination) Detection edge programmable External test input Rising edge detection Timer/pulse generator Timer/event counter Internal interrupts Basic interval timer Serial interface scanning Internal test inputs: Clock timer Serial interface Main system clock MHz, 4.19 Subsystem clock 32.768 kHz, standard High-voltage port Pull-down resistor open-drain output Ports Pull-up resistor Port Pull-down resistor
Mask option
Operating temperature Operating voltage Package
(Data held standby mode: 94-pin plastic
µPD75238
CONFIGURATION
AVREF AVDD S16/P100 S17/P101 S18/P102 S19/P103 S20/P110 S21/P111 S22/P112 S23/P113 S0/P120 S1/P121 S2/P122 S3/P123
AN4/P90 AN5/P91 AN6/P92 AN7/P93 AVSS RESET P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P22/PCL P23/BUZ
P80/PPO P81/SCK1 P82/SO1 P83/SI1
Caution sure supply power AVDD, VDD, VSS, AVSS pins (pins 87). Remark Internally connected grounded)
S4/P130 S5/P131 S6/P132 S7/P133 S8/P140 S9/P141 LOAD T15/S10/P142 T14/S11/P143 PH0/T13/S12/P150 PH1/T12/S13/P151 PH2/T11/S14/P152 PH3/T10/S15/P153
TI0/P13 PTO0/P20 BUZ/P23 PPO/P80 SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SI1/P83 SO1/P82 SCK1/P81 INT0/P10 INT1/P11 INT2/P12 INT4/P00 AN0-AN3 AN4/P90-AN7/P93 AVDD AVREF AVSS
BLOCK DIAGRAM
Basic interval timer INTBT Timer/event counter INTT0 Watch timer Bank Program counter (15)
Port Port Port Port Port Port Port Port program memory 32640 Port Decode control data memory 1024 Port
P00-P03 P10-P13 P20-P23 P30-P33 P40-P43Note P50-P53Note P60-P63 P70-P73 P80-P83 P90-P93 T0-T9
INTW Timer/pulse generator INTTPG Serial interface INTCSI0
General register
Serial interface controller/ driver Interrupt control Clock output control
T14/S11/P143 T15/S10/P142 S0/P120-S9/P141 S16/P100-S23/P113 VLOAD
Clock divider
Clock generator Main
Stand control
clock Port 10-15
P100-P153
Event counter
PCL/P22
XT1XT2 RESET
converter
µPD75238
sequential buffer (16)
Note Port port N-ch open-drain ports with medium withstand voltage
µPD75238
CONTENTS
FUNCTIONS
PORT PINS NON-PORT PINS INPUT/OUTPUT CIRCUITS CONNECTION UNUSED µPD75238 PINS
ARCHITECTURE MEMORY µPD75238
DATA MEMORY BANK CONFIGURATION ADDRESSING MODES GENERAL REGISTER BANK CONFIGURATION MEMORY-MAPPED
INTERNAL FUNCTIONS
PROGRAM COUNTER (PC) PROGRAM MEMORY (ROM) DATA MEMORY (RAM) GENERAL REGISTERS ACCUMULATORS STACK POINTER (SP) STACK BANK SELECT REGISTER (SBS) PROGRAM STATUS WORD (PSW) BANK SELECT REGISTER (BS)
PERIPHERAL HARDWARE FUNCTIONS
4.10 4.11 4.12 DIGITAL PORTS CLOCK GENERATOR CLOCK OUTPUT CIRCUIT BASIC INTERVAL TIMER TIMER/EVENT COUNTER CLOCK TIMER TIMER/PULSE GENERATOR EVENT COUNTER SERIAL INTERFACE CONVERTER SEQUENTIAL BUFFER CONTROLLER/DRIVER
INTERRUPT FUNCTION
CONFIGURATION INTERRUPT CONTROL CIRCUIT HARDWARE INTERRUPT CONTROL CIRCUIT MULTIPLE INTERRUPT PROCESSING CONTROL VECTOR ADDRESS SHARE INTERRUPT PROCESSING
INTERRUPT SEQUENCE
µPD75238
STANDBY FUNCTION
SETTING STANDBY MODES OPERATION STATUSES OPERATION AFTER STANDBY MODE RELEASED RELEASE STANDBY MODES
RESET FUNCTION INSTRUCTION
µPD75238 INSTRUCTIONS
INSTRUCTION OPERATION INSTRUCTION CODES EACH INSTRUCTION
SPECIFICATION MASK OPTIONS
APPLICATION BLOCK DIAGRAM ELECTRICAL CHARACTERISTICS
CHARACTERISTIC CURVES (FOR REFERENCE) PACKAGE DIMENSIONS RECOMMENDED SOLDERING CONDITIONS APPENDIX APPENDIX
µPD75238 SERIES PRODUCT FUNCTION LIST
DEVELOPMENT TOOLS
µPD75238
FUNCTIONS
PORT PINS (1/2)
I/ONote circuit type
name
Also used INT4 SCK0 SO0/SB0 SI0/SB1
Function
8-bit
When reset
P30Note P31Note P32Note P33Note P40-P43Note
4-bit input port (port P03, pull-up resistors provided software units bits.
Input
INT0 INT1 INT2
With noise elimination function 4-bit input port (port Pull-up resistors provided software units bits. 4-bit port (port Pull-up resistors provided software units bits.
Input
PTO0
Input
Programmable 4-bit port (port Input/output specified bit. Pull-up resistors provided software units bits.
Input
N-ch open-drain 4-bit port (port pull-up resistor provided (mask option). Withstand voltage open-drain mode.
High level (when pull-up resistor provided) high impedance High level (when pull-up resistor provided) high impedance
P50-P53Note
N-ch open-drain 4-bit port (port pull-up resistor provided (mask option). Withstand voltage open-drain mode.
Programmable 4-bit port (port Input/output specified bit. Pull-up resistors provided software units bits.
Input
4-bit port (port pull-down resistor provided (mask option).
level (when pull-down resistor provided) high impedance
Notes circuits enclosed circles have Schmitt-triggered input. driven directly.
µPD75238
PORT PINS (2/2)
I/ONote circuit type
name P100 P101 P102 P103 P110 P111 P112 P113 P120 P121 P122 P123 P130 P131 P132 P133 P140 P141 P142 P143 P150 P151 P152 P153
Also used SCK1
Function
8-bit
When reset
4-bit input port (port
Input
4-bit input port (port Input
P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors provided (mask option).
VLOAD level
(when pulldown resistor VLOAD
provided), level (when pulldown resistor pro-
P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors provided (mask option).
vided), highimpedance P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors provided (mask option). VLOAD level (when pulldown resistor VLOAD provided) highimpedance
P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors provided (mask option).
S10/T15 S11/T14
P-ch open-drain, 4-bit high-voltage output port. Pull-down resistors provided (mask option). P142 P143 drive directly.
S12/T13/PH0 P-ch open-drain, 4-bit high-voltage output port. S13/T12/PH1 Pull-down resistors provided (mask S14/T11/PH2 S15/T10/PH3
option). driven directly.
S12/T13/P150 P-ch open-drain, 4-bit high-voltage output port. S13/T12/P151 Pull-down resistors provided (mask option). S14/T11/P152 S15/T10/P153
Note circuits enclosed circles have Schmitt-triggered input.
µPD75238
NON-PORT PINS (1/2)
circuit type
name
Also used Output pins controller/ PH3/P153driver. PH0/P150 Allows pulldown resistor P143 provided (mask P142 option). P120-P123 P130-P133 P140 P141 P100-P103
Function
When reset
T0-T9
High-voltage, large-current output digit output High-voltage, large-current output usable digit/segment output well. unused pins used port Usable port static mode. High-voltage, large-current output usable digit/segment output well. Usable port static mode. High-voltage output segment output. Usable port port static mode.
T10/S15T13/S12
T14/S11 T15/S10 S0-S3 S4-S7 S16-S19
VLOAD level (when pull-down resistor VLOAD provided) highimpedance
High-voltage output segment output. Usable port port static mode.
S20-S23
P110-P113
VLOAD level (when pull-down resistor VLOAD provided), level (when pull-down resistor provided), highimpedance
µPD75238
NON-PORT PINS (2/2)
I/ONote When reset circuit type
name
Also used
Function
External event pulse input timer/event counter event counter Timer/event counter output Clock output Fixed frequency output (for buzzer system clock trimming) Serial clock Serial data output serial Serial data input serial Edge detection vectored interrupt input (Either rising falling edge detected.) Edge detection vectored interrupt input (The edge detected selectable.) Edge detection testable input rising edge detected.) Serial clock Serial data output Serial data input Analog input converter Synchronous Asynchronous Asynchronous
PTO0 SCK0 SO0/SB0 SI0/SB1 INT4
Input Input Input Input Input Input
INT0 INT1 INT2
SCK1 AN0-AN3 AN4-AN7 AVDD AVREF AVSS
P90-P93
Input Input Input
Power supply converter converter reference voltage input converter reference Connection crystal/ceramic resonator main system clock generation. When external clock used, input inverted signal input Connection crystal resonator subsystem clock generation. When external clock used, input XT1, left open. System reset input Timer/pulse generator pulse output Positive power supply potential Pull-down resistor connection controller/driver, power supply
RESET pins) pins) VLOAD
Input
Note
circuits enclosed circles have Schmitt-triggered input.
µPD75238
INPUT/OUTPUT CIRCUITS (1/4)
Type
Type
Data P-ch Output disable
P-ch
N-ch
N-ch
CMOS input buffer Type
Push-pull output which high-impedance output (off both P-ch N-ch) Type
Data Type Output disable
IN/OUT
Type
Schmitt trigger input with hysteresis Type
circuit consisting push-pull output type input buffer type Type
P.U.R. P.U.R. enable Data Type Output disable Output disable
P.U.R. P-ch
P-ch
IN/OUT
Type
P.U.R.: Pull-Up Resistor Schmitt trigger input with hysteresis
P.U.R.: Pull-Up Resistor
µPD75238
INPUT/OUTPUT CIRCUITS (2/4)
Type P.U.R. P.U.R. enable Data Type Output disable P-ch
Type
P.U.R.
P.U.R. enable Output disable (P-ch)
P-ch
P-ch IN/OUT
IN/OUT Data Output disable
Type
N-ch
Output disable (N-ch)
Type
P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor Type Type P.U.R. P.U.R. enable Data Type Output disable Output disable Data Type P-ch
IN/OUT
IN/OUT
Type
Type
circuit consisting push-pull output type Schmitt-triggered input type Type Type
P.U.R.: Pull-Up Resistor
P.U.R.
P.U.R. enable Data Type Output disable
P-ch
IN/OUT
Data
P-ch
P-ch
N-ch
Type
P.D.R. (Mask option) VLOAD
P.U.R.: Pull-Up Resistor
P.D.R.: Pull-Down Resistor
µPD75238
INPUT/OUTPUT CIRCUITS (3/4)
Type
Type
Data Type IN/OUT
Data
P-ch
P-ch
Output disable
N-ch
P.D.R. (Mask option) VLOAD
Type
P.D.R. (Mask option)
P.D.R.: Pull-Down Resistor
P.D.R.: Pull-Down Resistor
Type P.U.R. (Mask option)
Type AVDD IN/OUT P-ch AVDD N-ch AVSS AVSS AVSS Reference voltage (from voltage serial resistor string) Middle-voltage input buffer P.U.R.: Pull-Up Resistor Sampling
Data Output disable
N-ch
Type P.U.R. P.U.R. enable P-ch IN/OUT Data Output disable N-ch
Type
AVDD P-ch AVDD N-ch Sampling AVSS AVSS AVSS Reference voltage (from voltage serial resistor string)
Type
P.U.R.: Pull-Up Resistor
µPD75238
INPUT/OUTPUT CIRCUITS (4/4)
Type
AVSS
µPD75238
CONNECTION UNUSED µPD75238 PINS
name P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI1/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80/PPO P81/SCK1 P82/SO1 P83/SI1 P90/AN4-P93/AN7 P100/S16-P103/S19 P110/S20-P113/S23 P120-P123 P130-P133 P140-P143 P150-P153 AN0-AN3 AVREF AVDD AVSS VLOAD
Recommended connection connected connected
connected
Input state connected Output state left open
connected
left open
connected
connected connected connected left open connected
µPD75238
ARCHITECTURE MEMORY µPD75238
µPD75238 three architectural features: Data memory bank configuration General register bank configuration Memory-mapped Each these features explained below. DATA MEMORY BANK CONFIGURATION ADDRESSING MODES
shown Fig. 2-1, data memory space µPD75238 contains static (928 words bits) addresses 000H 19FH 200H 3FFH, display data memory words bits) addresses 1A0H 1FFH, peripheral hardware (such ports timers) addresses F80H FFFH. address 12bit address this data memory space, µPD75238 uses such memory bank configuration that loworder eight bits specified with instruction directly indirectly, high-order four bits used specify memory bank (MB). specify memory bank (MB), memory bank enable flag (MBE) memory bank select register (MBS) contained, allowing addressing indicated Fig. Table 2-1. (The register used select memory bank, flag used determine whether memory bank selected using register enabled. automatically saved restored time interrupt processing subroutine processing, that freely interrupt processing subroutine processing.) addressing data memory space, usually (MBE static memory bank specified operated. However, mode mode selected each step program processing more efficient programming.
Applicable program processing mode Interrupt processing Processing that repeats internal hardware static operations Subroutine processing Usual program processing
mode
µPD75238
Fig. Data Memory Organization Addressing Range Each Addressing Mode
mem.bit mem.bit Stack pmem. address- fmem.bit
Addressing mode
Memory bank enable flag 000H 01FH 020H 07FH Data area Static (memory bank General resister area
0FFH 100H Data area Static (memory bank 19FH 1A0H Display data memory area 1FFH 200H Stack area Data area Static (memory bank
2FFH 300H
Data area Static (memory bank
3FFH
contained
F80H
Peripheral hardware area (memory bank FC0H
FFFH
Remark Don't care
µPD75238
Table Addressing Modes
Addressing mode 1-bit direct addressing
Representation format mem.bit
Specified address specified address specified mem. this case: When 00H-7FH, When 80H-FFH, When Address specified mem. this case: When 00H-7FH, When 80H-FFH, When Address specified (mem: even address). this case: When 00H-7FH, When 80H-FFH, When
4-bit direct addressing
8-bit direct addressing
4-bit register indirect addressing
@HL+ @HL-
Address specified this case, Address specified this case, MBS. automatically increments register after addressing. automatically decrements register after addressing. Address specified memory bank Address specified memory bank Address specified this case, MBS. resister ignored. specified address specified fmem. this case: fmem FB0H-FBFH (interrupt-related hardware) fmem FF0H-FFFH (I/O port) specified low-order bits register address specified high-order bits pmem high-order bits register. this case, pmem FC0H-FFFH
8-bit register indirect addressing manipulation addressing
fmem.bit
pmem.@L
@H+mem.bit specified address specified low-order bits mem. this case, Stack addressing Address specified memory bank selected
summarized Table 2-1, µPD75238 allows both direct indirect addressing data memory manipulation 1-bit data, 4-bit data, 8-bit data, that very efficient simple programming performed.
µPD75238
GENERAL REGISTER BANK CONFIGURATION
µPD75238 contains four register banks, each consisting eight general registers: These registers mapped addresses memory bank data memory. (See Fig. 2-2.) specify general register bank, register bank enable flag (RBE) register bank select register (RBS) contained. register used select register bank, flag used determine whether register bank selected using enabled. register bank (RB) enabled instruction execution determined indicated Table 2-2, µPD75238 enables user create programs very efficient manner selecting register bank from four register banks, depending whether processing normal processing interrupt processing. (The automatically saved time interrupt processing, automatically restored upon completion interrupt processing.) Table Recommended Register Banks with Normal Routines Interrupt Routines
register banks with register bank with register bank with this case, needs saved restored.) Save restore registers with PUSH POP.
Normal processing Single interrupt processing Dual interrupt processing
Multiple (triple more) interrupt processing
general registers allow transfers, comparisons, arithmetic/logical operations, increments decrements only 4-bit basis, also 8-bit basis with register pairs. this case, register pairs register bank that inverted value register bank specified specified XA', HL', DE', BC', thus providing eight 8-bit registers. (See Fig. 2-3.)
µPD75238
Fig. General Register Configuration (4-Bit Processing)
Register bank Register bank Register bank Register bank
µPD75238
Fig. General Register Configuration (8-Bit Processing)
When
When
When
When
µPD75238
MEMORY-MAPPED
µPD75238 employs memory-mapped I/O, which maps peripheral hardware such timers ports addresses F80H FFFH data memory space shown Fig. 2-1. This means that there particular instruction control peripheral hardware, peripheral hardware controlled using memory manipulation instructions. (Some mnemonics hardware control available make programs readable.) manipulate peripheral hardware, addressing modes listed Table used. display data memory, scan registers, port mapped addresses 1A0H 1FFH manipulated specifying memory bank Table Addressing Modes Applicable Peripheral Hardware Mapped Addresses F80H FFFH
Applicable addressing mode manipulation Direct addressing mode specifying mem.bit with (MBE Direct addressing mode specifying fmem.bit regardless setting Indirect addressing mode specifying pmem.@L regardless setting 4-bit manipulation Direct addressing mode specifying with (MBE Register indirect addressing mode specifying with (MBE 8-bit manipulation Direct addressing mode specifying (even address) with (MBE Register indirect addressing mode specifying (with register containing even number) with (MBE
Applicable hardware hardware allowing manipulation IST0, IST1, MBE, RBE, PORTn.0-3 PORTn.
hardware allowing 4-bit manipulation
hardware allowing 8-bit manipulation addressing
Table summarizes µPD75238. items Table have following meanings: Symbol: Name representing address incorporated hardware, which coded operand field instruction Indicates whether hardware allows read/write operation. R/W: Both read write operations possible Read only Write only
Number manipulatable bits: Indicates number bits that processed hardware manipulation manipulation addressing: manipulation addressing applicable hardware manipulation
µPD75238
Table
µPD75238 (1/4)
manipulation bits bits dressing Number manipulatable bits
Address F80H
Hardware name (symbol)
Remarks always
Stack pointer (SP)
F82H F83H F84H
Resister bank select register (RBS) Memory bank select register (MBS) Stack bank select register (SBS)
RNote
Note
mem.bit Bits always Only allows manipulation.
F85H
Basic interval timer mode register (BTM)
F86H
Basic interval timer (BT)
F88H F89H F8AH
Display mode register (DSPM) Dimmer select register (DIMS) Digit select register (DIGS)
mem.bit Only allows test. Only allows manipulation.
F90H
Timer pulse generator mode register (TPGM)
mem.bit
F94H
Timer pulse generator modulo register (MODL)
F96H
Timer pulse generator modulo register (MODH)
F98H
Clock mode register (WM)
FA0H
Timer/event counter mode register (TM0)
Only allows manipulation.
FA2H FA4H
TOE0 Timer/event counter count register (T0)
FA6H
Timer/event counter modulo register (TMOD0)
FA8H
Event counter mode register (TM1)
Only allows manipulation.
FABH FACH
Gate control register (GATEC) Count register (T1)
Notes
instruction, these registers both readable writable. operated separately during 4-bit manipulation. also operated during 8-bit manipulation.
µPD75238
Table
µPD75238 (2/4)
Number manipulatable bits
Address FB0H IST1
Hardware name (symbol) IST0
manipulation bits bits dressing fmem.bit
Remarks
Program status word (PSW)
FB2H FB3H FB4H FB5H
Interrupt priority select register (IPS) Processor clock control register (PCC) INT0 mode register (IM0) INT1 mode register (IM1)
always Bits always
FB7H
System clock control register (SCC)
Only bits allow manipulation. fmem.bit
FB8H FB9H FBAH FBBH FBCH FBDH FBEH FBFH FC0H FC1H FC2H FC3H FC8H
IRQ4
IEBT
IRQBT
IEKS IRQKS IRQT1 IETPG IET0 IECSI0 IRQ1 sequential buffer (BSB0) sequential buffer (BSB1) sequential buffer (BSB2) sequential buffer (BSB3) CSIM11 CSIE1 Serial shift register (SIO1)
IRQW IRQTPG IRQT0 IRQCSI0 IRQ0 IRQ2
CSIM10
FC9H FCCH
µPD75238
Table
PD75238 (3/4)
Number manipulatable bits
Address FD0H FD4H
Hardware name (symbol)
manipulation bits bits dressing
Remarks
Clock output mode register (CLOM) Static mode register (STATB)
FD6H
Static mode register (STATA)
FD8H
conversion mode register (ADM) FDAH register (SA)
write only during 8-bit manipulation.
FDCH
Pull-up resistor specification register group (POGA)
FE0H
Serial operation mode register (CSIM0) CSIE0 RELD CMDT RELT
mem.bit mem.bit
CSIM0 write only during 8-bit manipulation.
FE2H
CMDD
control register (SBIC) BSYE FE4H ACKD ACKE ACKT
Serial shift register (SIO0)
FE6H
Slave address register (SVA)
FE8H
PM33
PM32
PM31
PM30
Port mode register group (PMGA) PM63 FECH PM62 PM61 PM60
Port mode register group (PMGB)
µPD75238
Table
µPD75238 (4/4)
Number manipulatable bits
Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH
Hardware name (symbol)
manipulation bits bits dressing fmem.bit pmem.@L
Remarks
Port (PORT0) Port (PORT1) Port (PORT2) Port (PORT3) Port (PORT4) Port (PORT5) Port (PORT6) Port (PORT7) Port (PORT8) Port (PORT9) Port (PORT10) Port (PORT11) Port (PORT12) Port (PORT13) Port (PORT14) Port (PORT15)
1A0H+4n Display data memory: S16-S23 1A1H+4n 1BEH 1BFH 1C0H+4n Display data memory: S0-S7 1C1H+4n 1C2H+4n Display data memory: S8-S15 1C3H+4n 1FCH 1FDH 1FEH 1FFH scan register (KS1) Port (PORTH) scan register (KS0) scan register (KS2)
mem.bit
µPD75238
INTERNAL FUNCTIONS
PROGRAM COUNTER (PC): BITS
program counter 15-bit binary counter holding program memory address information. Fig. Program Counter Format
PC14 PC13 PC12 PC11 PC10
Note that reset start address must within space bytes (0000H 3FFFH). This because RESET input sets low-order bits program memory address 0000H PC13 PC8, contents address 0001H initialization. PROGRAM MEMORY (ROM): 32640 WORDS BITS
program memory mask-programmable with configuration 32640 words bits storing programs, table data, forth. Program memory addressed program counter. Table data referenced using table reference instruction (MOVT). Fig. shows allowable branch address ranges branch instructions subroutine call instructions. whole-space branch instruction (BRA !addr1) whole-space call instruction (CALLA !addr1) allow direct branch throughout whole space 0000H 7F7FH. relative branch instruction $addr) allows branch addresses regardless block boundaries. program memory located addresses 0000H 7F7FH containing following specially assigned addresses. (All areas excluding 0000H 0001H used normal program memory.) 0000H 0001H Vector table holding setting values program start address time RESET input. reset start performed arbitrary address within 16K-byte space (0000H 3FFFH). 0002H 000FH Vector address table holding setting values program start address time each vectored interrupt occurrence. Interrupt processing started arbitrary address within 16K-byte space (0000H 3FFFH). 0020H 007FH Table area referenced GETI instructionNote Note GETI instruction represent arbitrary 2-byte 3-byte instruction 1-byte instructions byte, thus reducing number program bytes. (See Section 8.1.)
µPD75238
Fig. Program Memory
0000H Internal reset start address (high-order bits) Internal reset start address (low-order bits) 0002H INTBT/INT4 start address INTBT/INT4 start address 0004H INT0 start address INT0 start address 0006H INT1 start address INT1 start address 0008H INTSO start address INTSO start address 000AH INTT0 start address INTT0 start address 000CH INTTPG start address INTTPG start address 000EH INTKS start address INTKS start address (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) (high-order bits) (low-order bits) !addr instruction branch address 0020H GETI instruction reference table 007FH 0080H CALL !addr instruction branch address Branch/call address specified GETI instruction BRCB !caddr instruction branch address CALLA !addr instruction branch address $addr1 instruction relative branch address (-15 +16) !addr instruction branch address CALLF !faddr instruction entry address
07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H
BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
3FFFH 4000H 4FFFH 5000H
5FFFH 6000H
6FFFH 7000H 7F7FH
Caution start address interrupt vector shown above consists bits. start address must within 16K-byte space (0000H 3FFFH). Remark addition above, PCDE PCXA instructions cause branch address with only low-order bits changed.
µPD75238
DATA MEMORY (RAM)
data memory consists static peripheral hardware. static consists area words bits memory banks area words bits memory bank area words bits memory bank which used also display data memory. used storing processing data, also used stack memory subroutine interrupt execution. particular memory addresses, general registers, display data memory, peripheral hardware (various registers) mapped. Data these areas manipulated using general register manipulation instructions memory manipulation instructions (See Fig. 2-1). stack area, addresses memory banks (000H 3FFH) used. data memory configuration bits address, allows 8-bit memory manipulation instructions used 8-bit oriented manipulation, also allows manipulation instructions used bit-by-bit manipulation. Even addresses specified 8-bit manipulation instructions. Fig. shows organization display data memory area (1A0H 1FFH). Fig. Data Memory
Data memory General register area 000H 01FH 020H 0FFH 100H Stack area Display data memory, etc. 19FH 1A0H 1FFH 200H
Memory bank
Data area Static (1024
2FFH 300H
contained
F80H Peripheral hardware area FFFH
µPD75238
Fig. Display Data Memory Configuration
Number manipulatable bits
1BEH(KS2)
1FFH(PORTH)
1FEH(KS1)
1FCH(KS0)
bits bits
Remarks KS0, KS1, scan registers. PORTH high-voltage, high-current output port, also used digit output.
µPD75238
GENERAL REGISTERS: BITS BANKS
general registers mapped particular addresses data memory. Four banks registers provided, with each bank consisting eight 4-bit registers register bank (RB) enabled time instruction execution determined RBS: (RBS Each general register allows 4-bit manipulation. addition, serves register pair 8-bit manipulation. also makes register pair well these three register pairs used data pointers. general register area addressed accessed normal RAM, regardless whether used register. Fig.
Address 000H 001H 002H 003H 004H 005H 006H 007H 008H
General Register Format
Fig.
Register Pair Format
Data memory register register register register
Register bank register register register register
Same bank
Register bank
00FH 010H
Same bank
Register bank
017H 018H
Same bank
Register bank
01FH
bank
µPD75238
ACCUMULATORS µPD75238, register register pair function accumulators. register mainly used 4-bit data processing instructions, register pair mainly used 8-bit data processing instructions. manipulation instruction, carry flag (CY) functions accumulator. Fig. Accumulators
accumulator
4-bit accumulator
8-bit accumulator
STACK POINTER (SP) STACK BANK SELECT REGISTER (SBS)
µPD75238 uses static stack memory (LIFO scheme), 8-bit register holding start address stack area stack pointer (SP). stack area located addresses 000H 3FFH memory banks Either memory banks selected according value 4-bit SBS. decremented before write (save) operation stack memory, incremented after read (restoration) operation from stack memory. with 4-bit memory manipulation instruction. Note that high-order bits always Fig. 3-10 show data saved restored from stack memory these stack operations. place stack area given location, initialized with 8-bit memory manipulation instruction, initialized with 4-bit memory manipulation instruction. Both read from well. Table Stack Area Selected
SBS1
SBS2
Stack area Memory bank Memory bank Memory bank Memory bank
When initialized 00H, stack operation starts high-order address (nFFH) memory bank specified with SBS. stack area must within memory bank specified with SBS. stack operation exceeds address n00H, operation returns address nFFH same bank. Stacking beyond memory bank boundaries enabled only resetting SBS. RESET signal occurrence causes contents undefined, that must always initialized desired value start program.
µPD75238
Fig.
Address F80H F84H SBS1 Always SBS0
Stack Bank Select Register Format
Symbol
000H 0FFH 100H Memory bank 1FFH 200H Memory bank 2FFH 300H Memory bank 3FFH Memory bank
µPD75238
Fig.
PUSH instruction
Data Saved Stack Memory
CALL, CALLA, CALLF instruction Interrupt
Stack
Lower bits pair register Upper bits pair register
Stack PC11 PC14 PC13 PC12
Note
Stack PC11 PC14 PC13 PC12 IST1 IST0
Fig. 3-10
Data Restored from Stack Memory
instruction
RETS instruction
RETI instruction
Stack
Lower bits pair register Upper bits pair register
Stack PC11 PC14 PC13 PC12
Note
Stack PC11 PC14 PC13 PC12 IST1 IST0
Note other than saved/restored. Remark Data marked with undefined.
µPD75238
PROGRAM STATUS WORD (PSW): BITS
program status word (PSW) consists various flags closely associated with processor operations. mapped addresses FB0H FB1H data memory space. four bits address FB0H manipulated with memory manipulation instruction. Address FB1H cannot manipulated with normal data memory manipulation instruction. Fig. 3-11
Address FB1H
Program Status Word Format
FB0H Symbol
IST1
IST0
Cannot manipulated manipulated instruction specifically provided controlling this flag
manipulated
Table
Flags Saved/Restored Stack Operation
Saved/restored flag
Save
When CALL, CALLA, CALLF instruction executed When hardware interrupt occurs
saved. bits saved. restored. bits restored.
Restore
When RETS instruction executed When RETI executed
µPD75238
Carry flag (CY) carry flag 1-bit flag used store overflow underflow occurrence information when arithmetic operation with carry (ADDC, SUBC) executed. carry flag also function accumulator, therefore used store result Boolean operation performed specified data memory address. carry flag manipulated using special instructions, independently other bits. RESET signal occurrence causes carry flag undefined. Table Carry Flag Manipulation Instructions
Instruction (mnemonic) Instruction dedicated carry flag manipulation SET1 CLR1 NOT1 MOV1 mem*.bit MOV1 CY,mem*.bit AND1 CY,mem*.bit CY,mem*.bit XOR1 CY,mem*.bit
Carry flag operation/processing Sets Clears Inverts contents Skips Transfers contents specified bit. Transfers contents specified ANDs, ORs, XORs with contents specified bit, then sets result
transfer instruction
Boolean instruction
Interrupt handling
Saves other bits stack memory parallel. Interrupt execution -Restores together with other bits from stack memory. RETI
Remark
mem*.bit represents following three addressing modes: fmem.bit pmem.@L @H+mem.bit
Skip flags (SK2, SK1, SK0) skip flags used store skip status, automatically reset when executes instruction. user cannot directly manipulate these flags operands.
µPD75238
Interrupt status flag (IST1, IST0) interrupt status flag 2-bit flag used store status processing being performed. (For detailed information, Table 5-3.) Table Information Indicated Interrupt Status Flag
IST1
IST0
Status processing being performed Status
Processing interrupt control Normal program processing being performed. interrupts acceptable. lower- higher-priority interrupt being serviced. Higher-priority interrupts acceptable. higher-priority interrupt being serviced. interrupts acceptable.
Status
Status
interrupt priority control circuit (see Fig. 5-1) checks this flag control multiple interrupts. contents IST1 IST0 saved part stack memory interrupt accepted, then automatically one-step higher status. RETI instruction restores contents present before interrupt occurs. interrupt status flag manipulated using memory manipulation instruction, status processing being performed changed program control. Caution user must always disable interrupts with instruction before manipulating this flag, must enable interrupts with instruction after manipulating this flag.
µPD75238
Memory bank enable flag (MBE) memory bank enable flag 1-bit flag used specify address information generation mode high-order four bits 12-bit data memory address. When data memory address space expanded, allowing data memory space addressed. When reset data memory address space fixed, regardless setting. (See Fig. 2-1.) RESET input automatically initializes setting content program memory address vectored interrupt processing, automatically content vector address table servicing interrupt. Usually, interrupt processing, static memory bank used. Register bank enable flag (RBE) register bank enable flag 1-bit flag used determine whether expand general register bank configuration. When general registers selected from register banks depending setting register bank select register (RBS). When reset register bank always selected general registers, regardless setting RBS. RESET input automatically initializes setting content program memory address When vectored interrupt occurs, automatically content vector address table servicing interrupt. Usually, interrupt processing. Register bank used 4-bit processing, register banks used 8-bit processing.
µPD75238
BANK SELECT REGISTER (BS)
bank select register consists register bank select register (RBS) memory bank select register (MBS), which specify register bank memory bank used, respectively. using instruction instruction, respectively. contents saved restored from stack area eight bits time using PUSH BS/POP instruction. Fig. 3-12
Address
Bank Select Register Format
Symbol RBS0
F82H
MBS3 MBS2 MBS1 MBS0
RBS1
Memory bank select register (MBS) memory bank select register 4-bit register used store high-order four bits 12-bit data memory address. contents this register specify memory bank accessed. Memory banks specified. with instruction Fig. shows range addressing using settings. RESET input initializes Register bank select register (RBS) register bank select register specifies register bank used general registers; register bank selected from register banks with instruction RESET input initializes Table Register Bank Selected with
Bank selected. Bank selected. Register bank Bank always selected. Bank selected. Bank selected.
Always
Remark
Don't care
µPD75238
PERIPHERAL HARDWARE FUNCTIONS
DIGITAL PORTS
µPD75238 employs memory-mapped I/O, enabling ports mapped data memory space. Fig.
Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH
Data Memory Address Assigned Digital Port
P103 P113 P123 P133 P143 P153 P102 P112 P122 P132 P142 P152 P101 P111 P121 P131 P141 P151 P100 P110 P120 P130 P140 P150 Symbol PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT
µPD75238
Configurations digital ports Fig. Fig. 4-11 show configurations ports. mode setting mode each port port mode register shown Fig. 4-12. Each port functions input port when corresponding port mode register functions output port when same corresponding 8-bit memory manipulation instruction used port mode register group RESET input clears bits each port mode register This means that output buffers off, ports placed input mode. Operation digital ports When instruction executed, operation port pins depends mode setting, listed Table 4-1. Table Port Operations Instructions
Input mode (corresponding mode register [Output buffer off] When 1-bit test instruction, 1-bit input instruction, 4-/8-bit input instruction executed When 4-/8-bit output instruction executed When 1-bit output instructionNote executed Receives data certain pins. Output mode (corresponding mode register [Output buffer Receives contents output latch.
Transfers data accumulator output latch. contents output latch undefined.
Outputs data accumulator output pins. Changes output state according instruction.
Note Instructions such SET1/CLR1/MOV1 PORTn.bit,
µPD75238
Fig.
SCK0
Configuration Ports
INT4 output latch Internal SCK0
Selector CSIM0
Selector
Pull-up resistor P-ch POGA P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1
Input buffer
Output buffer which switched either push-pull output N-ch open-drain output Pull-up resistor
Internal
P-ch POGA Input buffer fX/64 Noise elimination circuit P10/INT0 P11/INT1 P12/INT2 P13/ INT2 INT1 INT0 Input buffer with hysteresis
SCK1
Internal SCK1
CSIM1
P80/PPO P81/SCK1 P82/SO1 P83/PI1 Input buffer
µPD75238
Fig. Configuration Ports
Input buffer PMmn POGA P-ch PMmn Pull-up resistor
Internal
Output buffer Output latch
PMmn port mode register group
Fig.
Configuration Port
Pull-up resistor P-ch POGA
Input buffer
Internal
Output buffer port mode register group
Output latch
µPD75238
Fig. Configuration Ports
Pull-up resistor
Input buffer
Mask option
Internal
N-ch open-drain output buffer
Output latch
port mode register group
µPD75238
Fig.
Input buffer
Configuration Port
Internal
Output buffer port mode register group Mask option Pull-down resistor
Output latch
Fig.
Configuration Port
Input instruction
Input buffer P90/AN4
Internal
P91/AN5
P92/AN6
P93/AN7
converter
µPD75238
Fig.
P-ch open-drain output buffer SK+1/Pm1
Configuration Ports
/Pm0
SK+1
SK+2
SK+2/Pm2
SK+3
Internal
SK+3/Pm3
Mask option
Pull-down resistor DSPM
Mask option
VLOAD (Specified time)
STATB
Remarks Port Port Fig.
P-ch open-drain output buffer SK+1/Pm1
Configuration Ports
/Pm0
SK+1
SK+2
SK+2/Pm2
SK+3
Internal
SK+3/Pm3
Mask option
Pull-down resistor
DSPM
VLOAD
STATA
Remarks Port Port
µPD75238
Fig. 4-10 Configuration Port
P-ch open-drain output buffer
Output buffer
S8/P140
Note
S9/P141
Internal
S10/T15/P142
Note
S11/T14/P143
DSPM.
Mask option (each pin) Pull-down resistor DIGS VLOAD
STATA
Note Selector Fig. 4-11 Configuration Ports
Output buffer
P-ch open-drain output buffer
Note
S12/T13/P150/PH0
Note
S13/T12/P151/PH1
Internal
Note Note Note Note
Note
S14/T11/P152/PH2
Note
S15/T10/P153/PH3
DSPM.
Mask option (each pin) Pull-down resistor
STATA DIGS VLOAD
Note Selector
µPD75238
Fig. 4-12 Formats Port Mode Registers
Port mode register group Address FE8H PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30 Symbol PMGA
Symbol PM3n, PM6n PMGA specification 0-3) Input mode (output buffers off) Output mode (output buffers
Port mode register group Address FECH Symbol PMGB
Symbol PMGB Port specification Input mode (output buffers off) Output mode (output buffers
Remark
Don't care
Pull-up resistor register group (POGA) Pull-up resistor register group register specify internal pull-up register each port ports port (excluding P00). Fig. 4-13 shows format this register. When pull-up resistor contained, associated bit, when pull-up resistor contained, Fig. 4-13 Format Register Group Specifying Pull-Up Resistors
Address FDCH
Symbol POGA
Port (P01 P03) Port (P10 P13) Port (P20 P23) Port (P30 P33) Port (P60 P63)
Caution mask option, ports contain pull-up resistors, port ports contain pull-down resistors bit. Remark Don't care
µPD75238
CLOCK GENERATOR Configuration clock generator clock generator supplies various clock signals peripheral hardware. Fig. 4-14 shows configuration clock generator. Fig. 4-14
Subsystem clock generator Clock timer Timer/pulse generator
Block Diagram Clock Generator
controller/driver Basic interval timer (BT) Timer/event counter Serial interface Clock timer Clock output circuit INT0 voice eliminator
Main system clock generator
1/16
1/4096 Frequency divider
SCC3
Oscillator disable signal
Selector Frequency divider Selector
INT0 noise
SCC0
Internal
PCC0
eliminator
Clock output
circuit
PCC1 HALT Note STOP Note PCC2 HALT
PCC3
PCC2, PCC3 clear signal
STOP
Wait release signal from RESET signal
Standby release signal from interrupt control circuit
Note Instruction execution Remarks Main system clock frequency fXT: Subsystem clock frequency clock Processor clock control register SCC: System clock control register clock cycle (tCY) clock equal machine cycle instruction. Chapter details
µPD75238
Functions clock generator clock generator generates clock signals listed below, controls standby mode other operation modes. Main system clock: Subsystem clock: clock: Clocks peripheral hardware operation clock generator determined processor clock control register (PCC) system clock control register (SCC). clock generator functions operates described below. RESET input selects lowest-speed mode (10.7 MHz)Note main system clock. (PCC When main system clock selected, select four clocks (0.67
1.33 2.67 10.7 MHz)Note
When main system clock selected, standby modes, STOP mode HALT mode, available. select subsystem clock very low-speed, low-current operation (122 32.768 kHz). When subsystem clock selected, main system clock generation stopped with SCC. addition, HALT mode used, STOP mode cannot used. (Subsystem clock generation cannot stopped.) Clocks peripheral hardware produced dividing main system clock signal. Only watch timer, subsystem clock directly supplied continue clock function. When subsystem clock selected, watch timer operate normally, other hardware cannot used because they operate with main system clock. Notes 15.3 4.19 0.95 1.91 3.82 15.3 4.19
µPD75238
Processor clock control register (PCC) 4-bit register selecting clock with low-order bits selecting operation mode with high-order bits. (See Fig. 4-15.) When standby mode set. When this released standby release signal, these bits automatically cleared return normal operation mode. (See Chapter detailed information.) 4-bit memory manipulation instruction used low-order bits PCC. (The high-order bits using STOP instruction HALT instruction, respectively. STOP instruction HALT instruction executed regardless setting. clock selected only when main system clock used operation. When subsystem clock selected operation, low-order bits invalidated, fXT/4 automatically set. STOP instruction executed only when main system clock used operation. generation RESET signal clears
µPD75238
Fig. 4-15 Format Processor Clock Control Register
Address FB3H
PCC3
PCC0
Symbol
PCC2 PCC1
clock selection (Operation with MHz) indicates clock frequency (93.7 kHz) (375 kHz) (750 kHz) (1.5 MHz) machine cycle indicates 32.768 clock frequency fXT/4 (8.192 kHz) fXT/4 (8.192 kHz) machine cycle
10.7 2.67 1.33
0.67
(Operation with 4.19 MHz) indicates 4.19 clock frequency (65.5 kHz) (262 kHz) (524 kHz) (1.05 MHz) machine cycle 15.3 3.82 1.91 0.95 indicates 32.768 clock frequency fXT/4 (8.192 kHz) fXT/4 (8.192 kHz) machine cycle
Remarks Output frequency from main syem clock oscillator fXT: Output frequency from subsyem clock oscillator
operation mode control bits Normal operation mode HALT mode STOP mode
µPD75238
System clock control register (SCC) 4-bit register selecting clock with least significant controlling termination main system clock generation with most significant bit. (See Fig. 4-16.) SCC.0 SCC.3 located same data memory address, both bits cannot changed same time. Accordingly, SCC.0 SCC.3 using manipulation instructions. SCC.0 SCC.3 manipulated regardless setting. Main system clock generation terminated setting SCC.3 only when subsystem clock used operation. STOP instruction must used generation termination when main system clock used operation. RESET input clears Fig. 4-16
Address FB7H SCC3 SCC0
Format System Clock Control Register
Symbol
SCC3 SCC0
System clock selection Main system clock Subsystem clock Subsystem clock
Main system clock operation oscillate
Oscillation stopped
Cautions time period 1/fXT needed change system clock. This means that terminate main system clock generation, SCC.3 must when machine cycles indicated Table more have elapsed after clock switched from main system clock subsystem clock. When main system clock used operation, setting SCC.3 stop clock generation does enter normal STOP mode. When SCC.3 input connected (GND electric potential) prevent leakage crystal oscillator. When external clock used main system clock, never SCC.3 When four bits 0001B fX/16), SCC.0 Before switching main system clock subsystem clock, sure manipulate bits other than 0001B set. When system operates subsystem clock, bits must also other than 0001B.
µPD75238
System clock oscillator main system clock oscillator operates with crystal (6.0 standard) ceramic resonator connected pins. external clock also input. Fig. 4-17 External Circuitry Main System Clock Oscillator External clock
Crystal/ceramic oscillation
PD75238
External clock
PD75238
Crystal oscillator ceramic oscillator
Caution When external clock used, STOP mode cannot set. This because connected STOP mode.
µPD75238
subsystem clock oscillator operates with crystal resonator (32.768 standard) connected pins. external clock also input. Fig. 4-18 Crystal oscillation External Circuitry Subsystem Clock Oscillator External clock
PD75238
32.768 External clock
PD75238
Open
Caution When main system clock subsystem clock oscillator used, conform following guidelines when wiring shaded portions Fig. 4-17 4-18 eliminate influence wiring capacity. wiring must short possible. Other signal lines must these areas. line carrying high fluctuating current must kept away possible. grounding point capacitor oscillator must have same potential that VSS. must grounded ground patterns carrying large current. signal must taken from oscillator. When subsystem clock used, special attention wiring; subsystem clock oscillator amplification minimize current consumption more likely malfunction noise than main system clock oscillator.
µPD75238
Time required change system clock clock system clock clock changed using least significant loworder bits PCC. This switching performed immediately after contents registers rewritten, system operates with previous clock some machine cycles. Accordingly, after this time period, STOP instruction must executed SCC.3 must terminate main system clock generation. Table
Setting before switching
Maximum Time Required Change System Clock Clock
Setting after switching
SCC0 PCC1 PCC0
SCC0 PCC1 PCC0 machine cycle
SCC0 PCC1 PCC0 machine cycle
SCC0 PCC1 PCC0 machine cycle
SCC0 PCC1 PCC0 /64fXT machine cycles machine cycles)
machine cycles
machine cycles
machine cycles
machine cycles
machine cycles
machine cycles
fX/8fXT machine cycles machine cycles) fX/4fXT machine cycles machine cycles)
machine cycles machine cycles machine cycles
machine cycle
machine cycle
machine cycle
Remarks clock supplied µPD75238. reciprocal this frequency minimum instruction time (defined machine cycle this manual). Time enclosed parentheses required when 32.768 kHz. Caution When four bits 0001B fX/16), SCC.0 Before switching main system clock subsystem clock, sure manipulate bits other than 0001B set. When system operates subsystem clock, bits must also other than 0001B.
µPD75238
Procedure changing system clock clock procedure changing system clock clock explained using Fig. 4-19. Fig. 4-19 Changing System Clock Clock
Commercial power line voltage
voltage
RESET signal Wait 21.8 [31.3 System clock clock 10.7 [15.3 Internal reset operation 0.67 [0.95 0.67 [0.95
Remark values enclosed square brackets 32.768 kHz; values enclosed square brackets 4.19 MHz. RESET input starts operation lowest speed main system clock (10.7 MHz) Note after wait time (21.8 MHz) Note stable oscillation. rewritten highest-speed operation after time elapse which sufficient voltage high enough highest-speed operation. removal commercial power detected using, example, interrupt input (INT4 useful), then SCC.0 operate with subsystem clock. this case, start subsystem clock generation must confirmed beforehand.) After time machine cycles) required switch subsystem clock elapses, SCC.3 terminate main system clock generation. After detecting input commercial power using interrupt, SCC.3 cleared start main system clock generation. After time required stable generation, SCC.0 cleared operate highest speed. Notes 15.3 4.19 31.3 4.19
µPD75238
CLOCK OUTPUT CIRCUIT
Configuration clock output circuit Fig. 4-20 shows configuration clock output circuit.
Functions clock output circuit clock output circuit outputs clock pulse signal P22/PCL remote control supplying clock pulses peripheral device. procedure outputting clock pulse signal follows:
Select clock output frequency, disable clock output. Write output latch. output mode port Enable clock output.
Fig. 4-20
From clock generator X/23 Selector X/24
Configuration Clock Output Circuit
Output buffer PCL/P22
PORT2.2 CLOM3 CLOM1 CLOM0 CLOM output latch
PMGB
Port input/ output mode specification
Internal
Remark clock output circuit designed that pulses with short widths appear enabling disabling clock output.
µPD75238
Clock output mode register (CLOM) CLOM 4-bit register control clock output. CLOM with 4-bit memory manipulation instruction. read operation allowed this register. clock output PCL/P22 pin. MB15 CLR1 #1000B CLOM,
Example
RESET input clears CLOM disabling clock output.
Fig. 4-21
Address FD0H
Format Clock Output Mode Register
Symbol CLOM
CLOM3
CLOM1 CLOM0
Clock output frequency selection (Frequency when MHz) Output
Note
(1.50 MHz, kHz, kHz, 93.7 kHz)
Output fX/2 (750 kHz) Output fX/24 (375 kHz) Output fX/26 (93.7 kHz)
(Frequency when 4.19 MHz) Output Note (1.05 MHz, kHz, kHz, 65.5 kHz) Output fX/23 (524 kHz) Output fX/24 (262 kHz) Output fX/2 (65.5 kHz)
Note clock supply selected PCC. Clock output enable/disable Output disable Output enable
Caution
sure write CLOM.
µPD75238
Application remote control output clock output function µPD75238 applicable remote control output. frequency carrier remote control output selected clock frequency select clock output mode register. Pulse output enabled disabled controlling clock output enable/disable software. clock output circuit designed that pulses with short widths appear enabling disabling clock output.
Fig. 4-22
Application Remote Control Output
CLOM.
output
µPD75238
BASIC INTERVAL TIMER
Configuration basic interval timer Fig. 4-23 shows configuration basic interval timer.
Basic interval timer functions basic interval timer provides following four functions:
Reference time generation (four time intervals) Application watchdog timer detecting program crashes Selection wait time releasing standby mode, counting Reading count value
Fig. 4-23
From clock generator fX/25 fX/27 fX/29 fX/212
Configuration Basic Interval Timer
Clear
Clear
Basic interval timer (8-bit frequency divider circuit) interrupt request flag Vector interrupt request signal
IRQBT
Wait release signal standby release BTM0 Internal
BTM3 SET1 Note
BTM2
BTM1
Note
Instruction execution
µPD75238
Basic interval timer mode register (BTM) 4-bit register that controls operation basic interval timer. Bcontents using 4-bit memory manipulation instruction. independently using manipulation instruction. When contents basic interval timer cleared, basic interval timer interrupt request flag (IRQBT) also cleared start basic interval timer). RESET input clears contents longest interrupt request signal generation interval time set. Fig. 4-24
Address F85H BTM3 BTM2 BTM1
Format Basic Interval Timer Mode Register
Symbol B
BTM0
(Frequency when MHz) Input clock specification /212 (1.46 kHz) (11.7 kHz) (46.9 kHz) (188 kHz)
Interrupt interval time (wait time releasing standby)
(175
217/fX (21.8 (5.46 (1.37
Other setting
(Frequency when 4.19 MHz) Input clock specification
Interrupt interval time (wait time releasing standby) (250
(31.3
(1.02 kHz)
(8.18 kHz)
(32.768 kHz) (131 kHz)
215/fX (7.82
(1.95
Other setting
Basic interval timer start control When written this bit, basic interval timer operation starts (the counter interrupt request flag cleared). When operation starts, this automatically reset
µPD75238
Operation basic interval timer basic interval timer (BT) always incremented clock supplied from clock generator, when overflows, interrupt request flag (IRQBT) set. count operation cannot stopped. four interrupt generation intervals selected setting BTM. (See Fig. 4-24.) basic interval timer interrupt request flag cleared setting (instruction starting interval timer). count status read using 8-bit manipulation instruction. data loaded timer. Caution When reading count value basic interval timer, execute read instruction twice that unstable data which been counted will read. read values reasonable, second result. read values apart, retry from beginning. allow system clock stabilize after releasing STOP mode, wait function available which stops operation until basic interval timer overflows. wait time after RESET input fixed. other hand, wait time selected setting Bwhen releasing STOP mode with interrupt occurrence. this case, wait times same interval times shown Fig. 4-24. Bmust before STOP mode set. (For details, Chapter TIMER/EVENT COUNTER Functions timer/event counter timer/event counter following functions. Programmable interval timer operation Output square wave given frequency PTO0 Event counter operation Frequency divider operation that divides input outputs result PTO0 Supply serial shift clock signal serial interface circuit Function reading state counting
PORT1.3 P13/ TI0Note Input buffer From clock generator Event counter
Fig. 4-25
Block Diagram Timer/Event Counter
Internal SET1
Note
TMOD0 Modulo register
TOE0
enable flag
PORT2.0
output latch
PGMB
TM07 TM06 TM05 TM04 TM03 TM02
Port input/ output mode
Match
serial interface TOUT Reset INTT0 Output buffer P20/PTO0
Comparator
Count register Clear
IRQT0 signal
Timer operation start signal RESET
(See Fig. 4-26.)
IRQT0 clear signal
Notes Instruction execution P13/TI0 external event pulse input shared between timer/event counter event counter.
µPD75238
µPD75238
Timer/event counter mode register (TM0) timer/event counter output enable flag (TOE0) timer/event counter mode register (TM0) 8-bit register controlling timer/event counter. 8-bit memory manipulation instruction. Fig. 4-27 shows format timer/event counter mode register. timer start bit, independently other bits. automatically reset when timer starts operation. RESET input clears bits timer/event counter output enable flag (TOE0) enables disables output timer (TOUT F/F) status PTO0 pin. Fig. 4-26 shows format timer/event counter output enable flag. timer (TOUT F/F) inverted match signal sent from comparator. timer reset when instruction sets TM0. RESET input clears TOE0 TOUT Fig. 4-26
Address FA2H
Format Timer/Event Counter Output Enable Flag
TOE0
Timer/event counter output enable flag Disables Enables
µPD75238
Fig. 4-27
Address FA0H
Format Timer/Event Counter Mode Register
Symbol
TM06
TM05 TM04 TM03 TM02
Operation mode Count operation Halts (retains contents counting) Count operation
Timer start specification When written this bit, counter IRQT0 flag cleared. Count operation starts been
Count pulse (CP) select (Frequency when MHz) TM06 TM05 TM04 Count pulse (CP) input rising edge input falling edge /210 (5.86 kHz) (23.4 kHz) (93.8 kHz) (375 kHz)
Other setting
(Frequency when 4.19 MHz) TM06 TM05 TM04 Count pulse (CP) input rising edge input falling edge /210 (4.09 kHz) (16.4 kHz) (65.5 kHz)
(262 kHz)
Other setting
µPD75238
Operation mode timer/event counter timer/event counter operates count operation disable mode count operation mode, depending setting mode register. following operations possible, regardless setting mode register:
P13/TI0 signal input test (ii) Output timer status PTO0 (iii) Setting modulo register (TMOD0) (iv) Reading from count register (T0) Setting, clearing, testing interrupt request flag (IRQT0)
Count operation disable mode This mode when this mode, count operation performed because count pulse (CP) supply count register stopped. Count operation mode This mode when this mode, count pulse signal selected with bits supplied count register count operation shown Fig. 4-28. Timer operation usually started following steps: count value modulo register (TMOD0). operation mode, count clock, start instruction mode register (TM0).
8-bit data transfer instruction used modulo register. Fig. 4-28 Operation Count Operation Mode
INTT0 (IRQT0 signal)
Internal clock
Count register (T0)
Clear
Comparator
Match
TOUT
PTO0
Modulo register (TMOD0) serial interface (channel
µPD75238
Time setting timer/event counter [Timer time] (period) [value modulo register divided [count pulse frequency] selected timer mode register. T(sec) Timer time (seconds) (Hz) Count pulse frequency (Hz) Value modulo register
T(sec)
(resolution)
Once timer set, interrupt request signal (IRQT0) generated time intervals. Table indicates resolution maximum time (set when modulo register) timer/ event counter each count pulse signal. Table (When MHz)
Mode register TM06 TM05 TM04 Resolution 42.7 10.7 2.67 Timer channel Maximum time 43.7 10.9 2.73
Resolution Maximum Time
(When 4.19 MHz)
Mode register TM06 TM05 TM04 Resolution 61.1 15.3 3.81 Timer channel Maximum time 62.5 15.6 3.91
µPD75238
CLOCK TIMER
Clock timer µPD75238 contains channel clock timer. Fig. 4-29 shows configuration timer.
Clock timer functions clock timer sets test flag (IRQW) every seconds. standby mode released with IRQW. Either main system clock (4.19 MHz) subsystem clock (32.768 kHz) produce 0.5-second intervals. fast-forward mode produces interval times faster (3.91 ms), which useful program debugging testing. fixed frequency (2.048, 4.096, 32.768 kHz) output P23/BUZ pin, that used sounding buzzer system clock frequency trimming. frequency divider cleared, clock start from zero seconds. Fig. 4-29 Block Diagram Clock Timer
(256 3.91
From clock generator
(32.768 kHz) (32.768 kHz)
(32.768 kHz) Selector
Frequency divider (4.096 kHz) Clear
Selector
INTW IRQW signal
Selector
Output buffer P23/BUZ
PORT2.3 output latch
PMGB
Port input/ output mode
Internal
Remark Caution
values parentheses 4.194304 32.768 When main system clock operates MHz, time interval cannot produced. Before producing this time interval, main system clock must changed subsystem clock.
µPD75238
Watch mode register (WM) watch mode register (WM) 8-bit register that controls clock timer, that with 8-bit memory manipulation instruction. Fig. 4-30 shows format. 8-bit memory manipulation instruction used watch mode register. RESET input clears bits Fig. 4-30
Address F98H
Format Clock Mode Register
Symbol
Count clock (fW) selection Selects subsystem clock: Selects divided system clock output:
Operation mode selection Normal clock mode sets IRQW sets IRQW 3.91
Advanced clock mode
Clock operation enable/disable Enables clock operation Disables clock operation (clears frequency dividing circuit)
output frequency selection output frequency
fW/24 (2.048 kHz) fW/23 (4.096 kHz)Note
(32.768 kHz)Note
Note supported IE-75000-R. output enable/disable Enables output Disables output
µPD75238
TIMER/PULSE GENERATOR
Timer/pulse generator functions µPD75238 contains channel timer/pulse generator that used timer pulse generator. following functions:
Functions available when timer/pulse generator used timer mode 8-bit interval timer operation using five clock sources (occurrence IRQTPG) Square wave output
Functions available when timer/pulse generator used pulse generation mode pulse output with accuracy bits (applicable electronic tuning when used converter) Generation interrupts regular intervals (215/fX 5.46 MHz)Note Note 7.81 4.19
pulse output unnecessary, used 1-bit output port.
Caution
timer/pulse generator operating when STOP mode set, malfunction. timer/pulse generator must disabled with mode register advance.
µPD75238
Timer/pulse generator mode register (TPGM) timer/pulse generator mode register (TPGM) 8-bit register that controls operation timer/ pulse generator. Fig. 4-31 shows format register. TPGM with 8-bit memory manipulation instruction. enables disables transfer (reloading) timer/pulse generator modulo register (MODH MODL) contents modulo latch. manipulated independently other bits. setting TPGM1 timer/pulse generator operation stopped decrease current consumption. RESET input clears bits
Fig. 4-31
Address F90H
Format Timer/Pulse Generator Mode Register
Symbol TPGM
TPGM7
TPGM5 TPGM4 TPGM3
TPGM1 TPGM0
Timer/pulse generator operation mode selection TPGM0 Select pulse generation mode Select timer mode
Timer/pulse generator operation enable/disable TPGM1 Disable timer/pulse generator operation Enable timer/pulse generator operation
Modulo register reload enable/disable TPGM3 Disable reloading modulo register Enable reloading modulo register
output latch data TPGM4 Output output latch Output output latch
output selection static/pulse TPGM5 Static output Pulse output (square wave/PWM)
output enable/disable TPGM7 Disable output (high-impedance) Enable output
µPD75238
Configuration operation when timer/pulse generator used timer mode Fig. 4-32 shows configuration when timer/pulse generator used timer mode. timer mode selected setting TPGM timer mode, TPGM3 must allowing modulo register reloaded time. timer mode, prescaler selected with modulo register (MODL), frequency interrupt interval value modulo register (MODH). timer starts when TPGM1 Fig. 4-33 shows operation timing MODH setting, Table shows setting frequency interrupt interval. output switched between square wave output static output. output square wave, TPGM5 TPGM7
Fig. 4-32
Block Diagram Timer/Pulse Generator (Timer Mode)
Internal
MODL Modulo register TPGM3 (Set
MODH Modulo register
Modulo latch Match Comparator Frequency divider TPGM1 Clear Clear Prescaler select latch Selector
INTTPG IRQTPG signal Output buffer
Count register
TPGM4 TPGM5 TPGM7
Caution
When timer operating timer operation mode stopped, IRQTPG because set. timer must stopped with interrupt being disabled, then IRQTPG must cleared.
µPD75238
Fig. 4-33
Timer Mode Operation Timing
MODH Count register (PPO)
TPGM1.
Generate IRQTPG.
Table (When MHz)
MODL bits
Modulo Register Settings
Interrupt generation interval MHz) (N+1)/fX 85.3 10.9 (N+1)/fX 42.7 5.45 (N+1)/fX 21.3 2.73 (N+1)/fX 10.7 1.37 (N+1)/fX 5.33
Square wave output frequency MHz) fX/256 (N+1) 91.6 11.7 fX/128 (N+1) 23.4 fX/64 (N+1) 46.9 fX/32 (N+1) 93.8 fX/16 (N+1) 1465
(When 4.19 MHz)
MODL bits Interrupt generation interval 4.19 MHz) (N+1)/fX 15.6 (N+1)/fX 61.0 7.81 (N+1)/fX 30.5 3.91 (N+1)/fX 15.3 1.95 (N+1)/fX 7.63 Square wave output frequency 4.19 MHz) fX/256 (N+1) fX/128 (N+1) fX/64 (N+1) fX/32 (N+1) fX/16 (N+1) 1024
Cautions value other than above cannot MODL. Bits must value MODH. must sure value from
µPD75238
Configuration operation when timer/pulse generator used pulse generation mode Fig. 4-34 shows configuration when timer/pulse generator used pulse generation mode. pulse generation mode selected setting TPGM0 TPGM5 TPGM7 enable pulse output. mode, pulse signal output pin, IRQTPG intervals fixed time period (215 5.46 MHz)Note pulses output PD75238 active-low have accuracy bits. This pulse signal applicable electronic tuning control motor when integrated external low-pass filter converted analog voltage. (See Fig. 4-35.) pulse signal generated combining basic period determined (171 MHz) Note secondary period (5.46 MHz) Note that time constant external low-pass filter decreased. low-level width pulse depends 14-bit modulo latch value. upper bits modulo latch sent from bits MODH, lower bits latch sent from upper bits MODL. When pulse signal converted analog form, voltage level analog output obtained follows:
Vref
Value modulo latch
Vref: Reference voltage external switching circuitry
prevent incorrect pulse from being output unstable modulo latch data being rewritten,
µPD75238 allows correct data written MODH MODL beforehand with 8-bit manipulation
instructions, then 14-bit data which transferred modulo latch time. This transfer operation referred reloading, controlled TPGM3.
Cautions modulo register (MODH) pulse generator cannot function normally. sure MODH value from 255. lower bits modulo register (MODL) read, read result unpredictable. modulo latch changed shorter period than pulse basic period 210/fX (171 MHz)Note pulses change. Notes 7.81 4.19 4.19
Static output When pulse output unnecessary, used normal static output. this case, output data TPGM4 with TPGM5 being TPGM7
µPD75238
Fig. 4-34 Block Diagram Timer/Pulse Generator (PWM Pulse Generation Mode)
Internal
MODH Modulo register
MODL Modulo register
TPGM3
MODH Modulo latch (14) TPGM1 Frequency divider
MODL7-2 Output buffer Selector
pulse generator
INTTPG (IRQTPG signal) (215/fX 5.46 MHz) Note
TPGM5
TPGM7
Note
7.81 4.19
Fig. 4-35
Sample Configuration Conversion Using µPD75238
Vref
PD75238
signal
Switching circuit
Low-pass filter
(analog voltage)
µPD75238
EVENT COUNTER
Configuration event counter event counter µPD75238 noise eliminator. Fig. 4-36 shows configuration counter. Fig. 4-36 Block Diagram Event Counter
Timer/counter GATEC.0 TM1.4
Selector
Noise eliminator
TM1.2
8-bit counter
Overflow flag
IRQT1
Internal
Caution TI0/P13 external event pulse input shared between timer/event counter event counter Event counter functions event counter provides following functions: Event counter operation Function reading state counting Count pulse edge specification Noise elimination function
Selector
TI0/P13
µPD75238
Event counter mode register event counter mode register (TM1) 8-bit register that controls event counter. Fig. 4-37 shows format register. with 8-bit memory manipulation instruction. event counter start bit, independently other bits. automatically reset when timer starts operation. Fig. 4-37 Format Event Counter Mode Register
Address FA8H
TM14
TM13
TM12
Symbol
Event count operation enable/disable TM12 Enables count operation Disables count operation (count value retained)
Event count start instruction When written, counter IRQ1 flag cleared. TM12 count opertaion starts.
TM13
Count pulse edge specification TM14 input falling edge input rising edge
Overflow flag (IRQT1) overflow flag when event counter (IRQT1) overflows. flag cleared count operation start instruction. Event counter control register (GATEC) This register specifies sampling sampling clock (fX/4). noise eliminator eliminates pulses narrower than sampling clock cycles (8/fX) noise accepts pulses wider than interrupt signals. Fig. 4-38 shows format GATEC. Fig. 4-38
Address FABH
Format Event Counter Control Register
GATEC0 Symbol GATEC
sampling Sampling fX/4
µPD75238
SERIAL INTERFACE
µPD75238 channels clock synchronous 8-bit serial interface: Channel channel Table lists differences between channel channel
Table
Serial transfer mode, function 3-wire serial Clock selection Transfer method Transfer flag
Differences between Channel Channel
Channel fX/24 fX/23, TOUT F/F, external clock Start switchable: MSB/LSB Serial transfer interrupt request flag (IRQCSI0) Available Channel fX/24 fX/23, external clock Start bit: Serial transfer flag (EOT)
2-wire serial Serial interface
available
µPD75238
Serial interface (channel functions serial interface (channel PD75238 following four different modes. functions four modes outlined below. Operation halt mode This mode used when serial transfer performed. This mode reduces power consumption. Three-wire serial mode this mode, 8-bit data transferred through three lines: Serial clock (SCK0), serial output (SO0), serial input (SI0). three-wire serial mode allows full-duplex transmission, data transfer performed higher speed. user choose 8-bit data transfer starting with LSB, devices starting with either connected. three-wire serial mode enables connections made with series, series, many other types peripheral devices. Two-wire serial mode this mode, 8-bit data transferred through lines: Serial clock (SCK0) serial data (SB0 SB1). controlling output levels lines software, communication with multiple devices enabled. output levels SCK0 SB1) controlled software, user match arbitrary transfer format. This means that line that been required handshaking connect multiple lines eliminated more efficient port utilization. Serial interface (SBI) mode this mode, communication with multiple devices performed using lines: Serial clock (SCK0) serial data (SB0 SB1). This mode conforms serial format. this mode, sender output, serial data bus, address selecting device subject serial communication, commands directed remote device, data. receiver identify address, commands, data from received data hardware. This function enables more efficient port utilization case two-wire serial mode. addition, this function simplify serial interface control portion application program. Configuration serial interface (channel Fig. 4-39 shows block diagram serial interface (channel
Fig. 4-39
Block Diagram Serial Interface (Channel
Internal CSIM0 test Slave address register (SVA) Coincidence RELT signal Address comparator P03/SI0/SB1 latch Selector Shift register (SIO0) CMDT SBIC manipulation test
ACKE
ACKT
P02/SO0/SB0 Selector release/ command/ acknowledge detection circuit P01/SCK0 RELD CMDD ACKD
Busy/ acknowledge output circuit
BSYE
Serial clock counter
INTCSI0 control circuit
INTCSI0 RQCSI0 signal
output latch
Serial clock control circuit
Serial clock selector
fX/2 fX/2 fX/2 TOUT (from timer/event counter) External SCK0
µPD75238
µPD75238
Functions serial interface (channel registers
Serial operation mode register (CSIM0) Fig. 4-40 shows format serial operation mode register (CSIM0). CSIM0 8-bit register which specifies serial interface (channel operation mode, serial clock, wake-up function, forth. CSIM0 manipulated using 8-bit memory manipulation instruction. higher three bits manipulated bit. Each manipulated using name. Each allow read and/or write operation. (See Fig. 4-40.) allows test operation only; data written this invalid. RESET input clears bits
Fig. 4-40
Address FE0H CSIE0
Format Serial Operation Mode Register (CSIM0) (1/3)
Symbol CSIM0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
Serial clock selection Serial interface operation mode selection Wake-up function specification Signal from address comparator Serial interface operation enable/disable specification
Remark Read only Write only
µPD75238
Fig. 4-40 Serial clock selection
Serial clock CSIM01 CSIM00 3-wire serial mode fX/24 mode 2-wire serial mode Input Output fX/26 (65.5 93.8 kHz) Note External clock applied SCK0 Time/event counter output (T0) (262 kHz)Note SCK0 mode
Format Serial Operation Mode Register (CSIM0) (2/3)
fX/23 (524 kHz)Note
Note values parentheses 4.19 MHz. Serial interface operation mode selection
sequence shift register SIO07-0 (Transfer starting with MSB) SIO00-7 (Transfer starting with LSB) SIO07-0 (Transfer starting with MSB)
CSIM04
CSIM03
CSIM02
Operation mode 3-wire serial mode
function SO0/P02 (CMOS output)
function SI0/P03 (Input)
mode
SB0/P02 (N-ch open-drain input/output) input
input
SB1/P03 (N-ch open-drain input/output) input
2-wire serial mode
SIO07-0 (Transfer starting with MSB)
SB0/P02 (N-ch open-drain input/output) input
SB1/P03 (N-ch open-drain input/output)
Remark Don't care Wake-up function specification
Sets IRQCSI0 each time serial transfer completed each mode. Used mode only IRQCSI0 only when address received after release matches data slave address register (wake-up state). SB0/SB1 goes high-impedance state.
Caution When during BUSY signal output, BUSY released. mode, BUSY signal output until next falling edge serial clock (SCK0) appears after release BUSY directed. Before setting sure confirm that SB1) high after releasing BUSY.
µPD75238
Fig. 4-40 Format Serial Operation Mode Register (CSIM0) (3/3)
Signal from address comparator
COINote Condition being cleared (COI When slave address register (SVA) does match data shift register Condition being (COI When slave address register (SVA) matches data shift register
Note read only before serial transfer started after serial transfer completed. undefined value read during transfer. data written 8-bit manipulation instruction ignored.
Serial interface operation enable/disable specification
Shift register operation CSIE0 Shift operation disabled Shift operation enabled Serial clock counter Cleared Count operation IRQCSI0 flag Held set. SO0/SB0, SI0/SB1 Used only port Used each mode well port
Remarks Each mode selected setting CSIE0, CSIM03, CSIM02.
CSIE0 CSIM03 CSIM02 Operation mode Operation halt mode Three-wire serial mode mode Two-wire serial mode
P01/SCK0 assumes following state according setting CSIE0, CSIM01, CSIM00:
CSIE0 CSIM01 CSIM00 Serial clock output (High level output) Input port High impedance High level output P01/SCK0 state
µPD75238
Remarks When clearing CSIE0 during serial transfer, following procedure: Disable interrupts clearing interrupt enable flag. Clear CSIE0. Clear interrupt request flag.
Examples fX/2 selected serial clock, serial interrupt IRQCSI0, generated each time serial transfer completed, serial transfer performed mode with used serial data bus. MB15 #10001010B CSIM0, CSIM0 10001010B CLR1
Serial transfer dependent contents CSIM0 enabled. SET1 MB15 CSIE0 CLR1
µPD75238
Serial interface control register (SBIC) Fig. 4-41 shows format serial interface control register (SBIC). SBIC 8-bit register consisting bits controlling serial flags indicating states input data from serial bus. SBIC used mainly mode. SBIC manipulated using manipulation instruction. SBIC cannot manipulated using 4-bit 8-bit memory manipulation instruction. Each allow read and/or write operation. (See Fig. 4-41.) RESET input clears bits
Caution Only following bits used three-wire two-wire serial modes: release trigger (RELT): Sets latch. Command trigger (CMDT): Clears latch.
Fig. 4-41
Format Serial Interface Control Register (SBIC) (1/3)
Address FE2H BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Symbol SBIC release trigger Command trigger release detection flag Command detection flag Acknowledge trigger Acknowledge enable Acknowledge detection flag Busy enable
Remarks
Read only
Write only (R/W): Read/write
µPD75238
Fig. 4-41 release trigger
RELT Control release signal (REL) trigger output. setting RELT latch Then RELT automatically cleared
Format Serial Interface Control Register (SBIC) (2/3)
Caution Never clear SB1) during serial transfer. sure clear SB1) before after serial transfer. Command trigger
CMDT Control command signal (CMD) trigger output. setting CMDT latch cleared Then CMDT automatically cleared
Caution Never clear SB1) during serial transfer. sure clear SB1) before after serial transfer. release detection flag
RELD Condition being cleared (RELD transfer start instruction executed. RESET signal entered. CSIE0 (See Fig. 4-40.) does match SIO0 when address received. Condition being (RELD release signal (REL) detected.
Command detection flag
CMDD Condition being cleared (CMDD transfer start instruction executed. release signal (REL) detected. RESET signal entered. CSIE0 (See Fig. 4-40.) Condition being (CMDD command signal (CMD) detected.
Acknowledge trigger
ACKT When after transfer, output phase with next SCK0. After signal output, this automatically cleared
Cautions
Never ACKT before during serial transfer. ACKT cannot cleared software. Before setting ACKT, ACKE
Acknowledge enable (R/W)
ACKE Disables automatic output acknowledge signal (ACK). (Output ACKT possible.) When before transfer When after transfer output phase with clock SCK0. output phase with SCK0 immediately following instruction execution.
µPD75238
Fig. 4-41 Format Serial Interface Control Register (SBIC) (3/3)
Acknowledge detection flag
ACKD Condition being cleared (ACKD transfer start instruction executed. RESET signal entered. Condition being (ACKD acknowledge signal (ACK) detected phase with rising edge SCK0).
Busy enable (R/W)
busy signal automatically disabled. Busy signal output stopped phase with falling edge SCK0 immediately after clear instruction execution.
BSYE
busy signal output after acknowledge signal phase with falling edge SCK0.
Examples command signal output. SET1 accordingly. setting this interrupt routine processed only when address match found. DATA ADRS MB15 RELD !ADRS CMDD !DATA Command analysis Data processing Address decode CMDD test RELD test MB15 CMDT CLR1
RELD CMDD tested identify types received data types processing
µPD75238
Shift register (SIO0) Fig. 4-42 shows configuration peripheral hardware shift register SIO0 8-bit register which performs parallel-serial conversion serial transfer (shift) operation phase with serial clock. Serial transfer started writing data SIO0. send operation, data written SIO0 output serial output (SO0) serial data (SB0/ SB1). receive operation, data read from serial input (SI0) SB0/SB1 into SIO0. Data read from written SIO0 using 8-bit manipulation instruction. When RESET signal entered during operation, value SIO0 undefined. When RESET signal entered standby mode, value SIO0 preserved. Shift operation stopped after 8-bit send receive operation completed.
Fig. 4-42
Peripheral Hardware Shift Register
Internal
Address comparator
RELT CMDT
Shift register CSIM0 Shift clock
latch
BUSY/ACK N-ch open-drain output
timing reading SIO0 start serial transfer (writing SIO0) follows: When serial interface operation enable/disable (CSIE0) However, case where CSIE0 after data written shift register excluded. When serial clock masked after 8-bit serial transfer SCK0 high. When reading from writing SIO0, make sure that SCK0 high. two-wire serial mode mode, pins specified data used both input output. Because configuration output pins N-ch open-drain, write SIO0 devices that receive data.
µPD75238
Slave address register (SVA) slave address register (SVA) functions described below. manipulated using 8-bit manipulation instruction. allows only write operation. When RESET entered, value undefined. However, value preserved when RESET entered standby mode.
Slave address detection mode] used when µPD75238 connected slave device serial bus. 8-bit register slave slave address (number assigned it). master outputs slave address connected slaves select particular slave. data values slave address output from master value SVA) compared with each other address comparator. match found, slave selected. this time, (COI) serial operation mode register (CSIM0)
Cautions Slave selection nonselection state detected detecting match slave address received after release state RELD this match detection, address match interrupt (IRQCSI0) generated when usually used. detect selection/nonselection state slave address when When detecting selection/nonselection state without using interrupt when address match detection method. Instead, transfer commands advance program.
Error detection two-wire serial mode mode] detects error either following cases: When addresses, commands, data transferred with µPD75238 operating master When data transferred with µPD75238 operating slave
Signals Table lists signals. Fig. 4-43 4-48 show operations signals flags.
Table
Various Signals Used Mode (1/2)
Signal name
Output device Master
Definition
Timing chart
Condition output RELT set.
Flag operation RELD set. CMDD cleared.
Meaning signal Indicates that signal follows data sent address data.
release signal (REL)
Rising edge SB0/SB1 when SCK0
SCK0 SB0/SB1
Command signal (CMD)
Master
Falling edge SB0/SB1 when SCK0 SCK0 SB0/SB1
CMDT set.
CMDD set.
Data sent after signal output address. Data sent, with signal being output, command. Indicates completion receive operation.
Acknowledge signal (ACK)
Master/ slave
level signal output SB0/SB1 during SCK0 clock cycle after serial receive operation completed [Synchronous busy signal] level signal output SB0/SB1 after acknowledge signal High level signal output SB0/SB1 before serial transfer started after serial transfer completed
ACKE ACKT set.
ACKD set.
[Synchronous busy signal output]
Busy signal (BUSY)
Slave
BSYE SCK0 SB0/ SB0/
BUSY READY BUSY READY BSYE Execution instruction write data SIO0 (direction start transfer)
Indicates that serial receive operation disabled because processing progress. Indicates that serial receive operation enabled.
Ready signal (READY)
Slave
µPD75238
Signal name Output device Master Definition Serial clock (SCK0) clock cycles. Address Master Command Master Data Master/ slave
Table
Various Signals Used Mode (2/2)
Timing chart
Condition output Execution instruction write data SIO0 when CSIE0 (direction start serial transfer)Note
Flag operation IRQCSI0 rising edge Note ninth clock)
Meaning signal Timing signal output serial data
Synchronous clock outputting address/ command/data, SCK0 signal, synchronous BUSY signal, SB0/ Address/command/data output during first
8-bit data transferred phase with SCK0 after signal signal output 8-bit data transferred phase with SCK0 after only signal output, with signal being output 8-bit data transferred phase with SCK0, with neither signal signal being output
SCK0 SB0/
Address slave device serial
Directions messages slave device
SCK0 SB0/
SCK0 SB0/
Value processed slave master device
Notes When IRQCSI0 always ninth rising edge SCK0. When IRQCSI0 ninth rising edge SCK0 only received address matches value slave address register (SVA). BUSY state present, data transfer started after READY state set.
µPD75238
µPD75238
Fig. 4-43 Operations RELT, CMDT, RELD, CMDD (Master)
Transfer operation start specification SIO0
SCK0
latch
RELT
CMDT
RELD
CMDD
Fig. 4-44
Operations RELT, CMDT, RELD, CMDD (Slave)
Write SIO0
Transfer operation start specification SIO0
SCK0
latch
RELT (Master) CMDT (Master) When address match found RELD When address mismatch found CMDD
Fig. 4-45
after transfer completion.
Operation ACKT
SCK0
signal output during first clock cycle immediately after ACKT set.
SB0/SB1
ACKT
When during this period
Caution ACKT until transfer completed.
µPD75238
Fig. 4-46 Operation ACKE
When ACKE time transfer operation completion
SCK0
signal output during ninth clock cycle
SB0/SB1
ACKE When ACKE this point
When ACKE after transfer operation completion
SCK0
signal output during first clock cycle immediately after ACKT set.
SB0/SB1
ACKE
When ACKE during this period ACKE falling edge next SCK0
When ACKE time transfer operation completion
SCK0 signal output
SB0/SB1
ACKE
When ACKE this point
When ACKE period short
SCK0 signal output
SB0/SB1
ACKE
When ACKE cleared during this period, ACKE falling edge SCK0
µPD75238
Fig. 4-47 Operation ACKD
When signal output during ninth SCK0 clock
Transfer operation start specification SIO0 Transfer operation start SCK0
SB0/SB1
ACKD
When signal output after ninth SCK0 clock
Transfer operation start specification SIO0 Transfer operation start SCK0
SB0/SB1
ACKD
Clear timing case where start transfer directed during BUSY
Transfer operation start specification SIO0
SCK0
SB0/SB1
BUSY
ACKD
Fig. 4-48
SCK0
Operation BSYE
SB0/SB1
BUSY
BSYE
When BSYE this point
When reset operation executed during this period BSYE falling edge SCK0.
µPD75238
Serial interface (channel operation
Operation halt mode operation halt mode used when serial transfer performed. This mode reduces power consumption. shift register does perform shift operation this mode, shift register used normal 8-bit register. RESET input sets operation halt mode. P02/SO0/SB0 P03/SI0/SB1 function input-only port pins. P01/SCK0 used input port setting serial operation mode register
Three-wire serial mode operations three-wire serial mode compatible with other modes used series series. Communication performed using three lines: Serial clock (SCK0), serial output (SO0), serial input (SI0).
Communication operation three-wire serial mode transfers data, with eight bits block. Data transferred phase with serial clock. shift register performs shift operation falling edge serial clock (SCK0). Send data latched latch, output pin. Receive data applied latched shift register rising edge SCK0. When eight bits have been transferred, shift register operation automatically terminates setting interrupt request flag (IRQCSI0).
Fig. 4-49
Timing Three-Wire Serial Mode
SCK0
IRQCSI0 Completion transfer Transfer operation started phase with falling edge SCK0. Execution instruction that writes data SIO0 (Transfer operation start specification)
µPD75238
becomes CMOS output outputs state latch. output state manipulated setting RELT CMDT bit. However, this manipulation must performed during serial transfer operation. output state SCK0 controlled manipulating output latch output mode (internal system clock mode). (See Section 4.9.)
(ii)
Switching between first transfer three-wire serial mode function that switch between first transfer. Fig. 4-50 shows configuration shift register (SIO0) internal bus. shown Fig. 4-50, read write operation performed switching between LSB. This switching specified using serial operation mode register (CSIM0).
Fig. 4-50
Transfer Switching Circuit
Internal first first Read/write gate Read/write gate
latch Shift resister (SIO0)
SCK0
first switched changing order data bits written shift register (SIO0). shift operation order SIO0 always same. Accordingly, first must switched between before writing data shift register
µPD75238
Two-wire serial mode
two-wire serial mode made compatible with communication format programming.
this mode, communication basically performed using lines: Serial clock (SCK0) serial data input/output (SB0 SB1).
Communication operation two-wire serial mode transfers data, with eight bits block. Data transferred phase with serial clock. shift register performs shift operation falling edge serial clock (SCK0). Send data latched latch, output SB0/P02 SB1/P03 starting with MSB. Receive data applied latched shift register rising edge SCK0. When eight bits have been transferred, shift register operation automatically terminates setting interrupt request flag (IRQCSI0).
Fig. 4-51
Timing Two-Wire Serial Mode
SCK0
SB0/SB1
IRQCSI0 Completion transfer Transfer operation started phase with falling edge SCK0. Execution instruction that writes date SIO0 (Transfer operation start spcification)
becomes N-ch open-drain when specified serial data bus, voltage level that must pulled externally. state latch output pin, output states controlled setting RELT CMDT bit. However, this operation must performed during serial transfer operation. output state SCK0 controlled manipulating output latch output mode (internal system clock mode). (See Section 4.9.)
µPD75238
mode operation (serial interface) high-speed serial interface that conforms serial format. allow communication with multiple devices single-master high-speed serial using signal lines, configuration function added clock synchronous serial method. reduce ports wires boards when multiple microcomputers peripheral used configure serial bus. Fig. 4-52 example system configuration.
Fig. 4-52
Example System Configuration
Master PD75238
Slave PD75238
(SB1) SCK0
(SB1) Address SCK0
Slave
(SB1) Address SCK0
Slave
(SB1) Address SCK0
Cautions mode, serial data SB1) open-drain output. serial data line placed wired state. pull-up resistor required serial data line. switch between master slave, pull-up resistor required also serial clock line (SCK0), because SCK0 input/output switching performed between master slave asynchronously.
µPD75238
functions Address/command/data identification function Serial data classified into three types: Address, command, data. Address-based chip select function master selects chip address transfer. Wake-up function slave easily check address reception (for chip select identification) with wake-up function. This function released software. When wake-up function set, interrupt (IRQCSI0) generated when match address received. this reason, communication with multiple devices, other than selected slave operate independently serial communication. Acknowledge signal (ACK) control function acknowledge signal, which used confirm reception serial data, controlled. Busy signal (BUSY) control function busy signal, which used post busy state slave, controlled. Fig. 4-53 Address transfer
SCK0
Timing Transfer
SB0/SB1 release signal
BUSY
Command transfer
SCK0
Command signal
SB0/SB1
BUSY
READY
Data transfer
SCK0
SB0/SB1
BUSY
READY
µPD75238
(ii) Communication operation mode, master usually selects slave device communicate with from multiple devices outputting address slave serial bus. After selecting device communicate with, master exchanges commands data with slave device, thus establishing serial communication. Fig. 4-54 4-57 show timing charts data communication operations. mode, shift register performs shift operation falling edge serial clock (SCK0). Send data held latch, output SB0/P02 SB1/P03 starting with MSB. Receive data applied SB1) latched shift register rising edge SCK0.
Program processing Hardware operation Transfer line SCK0 Slave device processing (receiver) Program processing Hardware operation
Fig. 4-54
Address Transfer Operation from Master Device Slave Device (WUP
Master device processing (transmitter) Write SIO0
CMDT
RELT CMDT
Interrupt handling (preparation next serial transfer)
Serial send operation
Generate IRQCSI0
ACKD
Stop SCK0
Address
BUSY
READY
WUP0
ACKT
Clear BUSY
Clear CMDD CMDD CMDD RELD
Serial receive operation
Generate IRQCSI0
Output Output BUSY
Clear BUSY
(When SIO0)
µPD75238
Fig. 4-55
Command Transfer Operation from Master Device Slave Device
Master device processing (transmitter)
CMDT
Program processing
Write SIO0
Interrupt handling (preparation next serial transfer)
Hardware operation
Serial send operation
Generate IRQCSI0
ACKD
Stop SCK0
Transfer line SCK0
BUSY
READY
Command Slave device processing (receiver) Read SIO0
Analyze command
Program processing
ACKT
Clear BUSY
Hardware operation
CMDD
Serial receive operation
Generate IRQCSI0
Output Output BUSY
Clear BUSY
µPD75238
Master device processing (transmitter) Program processing Hardware operation Transfer line SCK0 Slave device processing (receiver) Program processing Hardware operation
Fig. 4-56
Data Transfer Operation from Master Device Slave Device
Write SIO0
Interrupt handling (preparation next serial transfer)
Serial send operation
Generate IRQCSI0
ACKD
Stop SCK0
Data
BUSY
READY
Read SIO0
ACKT
Clear BUSY
Serial receive operation
Generate IRQCSI0
Output Output BUSY
Clear BUSY
µPD75238
Fig. 4-57
Data Transfer Operation from Master Device Slave Device
Master device processing (receiver)
Write SIO0
Program processing
Read SIO0
Write ACKT SIO0
Receive data processing
Hardware operation
Stop SCK0
Serial receive operation
Generate IRQCSI0
Output
Serial reception
Transfer line SCK0
BUSY
READY
Data
BUSY
READY
Slave device processing (transmitter) Write SIO0 Write SIO0
Program processing
Hardware operation
Clear BUSY
Serial send operation
Generate IRQCSI0
ACKD
Output BUSY
Clear BUSY
µPD75238
µPD75238
Transfer start each mode each three-wire serial I/O, two-wire serial I/O, modes, serial transfer started writing transfer data shift register (SIO0). However, following conditions must satisfied:
serial interface operation enable/disable (CSIE0) internal serial clock operating after 8-bit serial transfer, SCK0 high.
Caution
Transfer operation cannot started setting CSIE0 after writing data shift register
When eight bits have been transferred, serial transfer automatically terminates setting interrupt request flag (IRQCSI0).
two-wire serial mode] Caution N-ch transistor needs turned when data received. must written SIO0 beforehand.
mode] Cautions N-ch transistor needs turned when data received. must written SIO0 beforehand. However, when wake-up function specification (WUP) N-ch transistor always off. need written SIO0 beforehand reception. data written SIO0 when slave busy, data lost. Transfer operation started when busy state released input SB1) goes high.
Example When data specified register transferred SIO0, SIO0 data loaded into accumulator same time, serial transfer started.
MB15 SIO0
Extracts send data from CLR1 Exchanges send data with receive data starts transfer
µPD75238
Manipulation SCK0 output SCK0/P01 built-in output latch, that this allows static output software manipulation addition normal serial clock output. number SCK0s software-set arbitrarily manipulating output latch. (The SO0/ SB0/SB1 controlled manipulating RELT CMDT bits SBIC.) procedure manipulating SCK0/P01 output explained below.
serial operation mode register (CSIM0) (SCK0 pin: output mode, serial operation: enabled). When serial transfer operation halted, SCK0 from serial clock control circuit Manipulate output latch using manipulation instruction.
Example
output clock cycle SCK0/P01 software CLR1 SET1 MB15 CLR1 #10000011B SCK0 (fX/2 output mode CSIM0, 0FF0H.1 0FF0H.1 SCK0/P01 SCK0/P01
Fig. 4-58
SCK0/P01 Circuit Configuration
P01/SCK0
internal circuit
Address FF0H.1 output latch From serial clock control circuit
SCK0 When CSIE0=1 CSIM01 CSIM00
output latch mapped address FF0H. RESET signal sets output latch
Cautions
During normal serial transfer operation, output latch must output latch cannot addressed specifying PORT0.1 described below). address latch (0FF0H.1) must coded operand instruction directly. However, must specified before instruction executed. CLR1 PORT0.1 SET1 PORT0.1 CLR1 0FF0H.1 SET1 0FF0H.1 Allowed allowed
µPD75238
Serial interface (channel functions serial interface (channel PD75238 following modes. functions modes outlined below. Operation halt mode This mode used when serial transfer performed. This mode reduces power consumption. Three-wire serial mode 8-bit data transfer performed using three lines: Serial clock (SCK1), serial output (SO1), serial input (SI1). three-wire serial mode allows full-duplex transmission, data transfer performed higher speed. Eight-bit data transfer always starts MSB. three-wire serial mode enables connections made with series, series, many other types peripheral devices. Serial interface (channel configuration Fig. 4-59 shows block diagram serial interface (channel
Fig. 4-59
Block Diagram Serial Interface (Channel
Internal manipulation P83/SI1 Shift register SIO1 write signal (serial start signal) SIO1 Serial operation mode register CSIM1 manipulation
P82/SO1
Clear Serial clock counter Overflow Serial transfer flag (EOT)
Clear P81/SCK1 fX/23 Serial clock selector fX/24
µPD75238
µPD75238
(10) Functions serial interface (channel registers Serial operation mode register (CSIM1) Fig. 4-60 shows format serial operation mode register (CSIM1). CSIM1 8-bit register which specifies serial interface (channel operation mode serial clock. CSIM1 manipulated using 8-bit memory manipulation instruction. Only high-order manipulated independently. Each manipulated using name. RESET input clears bits Fig. 4-60 Format Serial Operation Mode Register
Address FC8H
CSIE1
Symbol CSIM1
CSIM11 CSIM10
Serial clock selection
CSIM11 CSIM10 Serial clock (3-wire serial mode) External clock applied SCK1 fX/24 (262 kHz)Note fX/23 (524 kHz)Note Output SCK1 mode Input
Note values parentheses 4.19 MHz. Serial interface operation enable/disable specification
Shift register Serial clock counter Cleared Count operation IRQCSI flag Held set. SO1, Used only port Port shared with serial function
CSIE1
Shift operation disabled Shift operation enabled
Caution sure write bits serial operation mode register.
µPD75238
Shift register (SIO1) SIO1 8-bit register which performs parallel-serial conversion serial transfer (shift) operation phase with serial clock. Serial transfer started writing data SIO1. send operation, data written SIO1 output serial output (SO1). receive operation, data read from serial input (SI1) into SIO1. Data read from written SIO1 using 8-bit manipulation instruction. When RESET signal entered during operation, value SIO1 undefined. When RESET signal entered standby mode, value SIO1 preserved. Shift operation stopped after 8-bit send receive operation completed. timing reading SIO1 start serial transfer (writing SIO1) follows: When serial interface operation enable/disable (CSIE1) However, case where CSIE1 after data written shift register excluded. When serial clock masked after 8-bit serial transfer When SCK1 high
µPD75238
(11) Serial interface (channel operation Operation halt mode operation halt mode used when serial transfer performed. This mode reduces power consumption. Shift register does perform shift operation this mode, shift register used normal 8-bit register. RESET input sets operation halt mode. P82/SO1 P83/SI1 fixed function input ports. P81/SCK1 used input port setting serial operation mode register Three-wire serial mode operations three-wire serial mode compatible with other modes used series series. Communication performed using three lines: Serial clock (SCK1), serial output (SO1), serial input (SI1). three-wire serial mode transfers data with eight bits block. Data transferred phase with serial clock. Shift register performs shift operation falling edge serial clock (SCK1). Send data latched latch, output pin. Receive data applied latched shift register rising edge SCK1. When eight bits have been transferred, operation shift register automatically terminates setting serial transfer flag (EOT). Fig. 4-61 Timing Three-Wire Serial Mode
SCK1
Completion transfer Transfer operation started phase with falling edge SCK1. Execution instruction that writes data SIO1 (Transfer operation start specification)
µPD75238
4.10 CONVERTER
µPD75238 contains 8-bit analog/digital (A/D) converter that eight analog input channels (AN0 AN7). converter employs successive-approximation method. Configuration converter Fig. 4-62 shows configuration converter. Fig. 4-62 Block Diagram Converter
Internal
ADM6 ADM5 ADM4
Control circuit Sample hold circuit
Multiplexer Comparator
register
decoder
AVREF
AVSS
µPD75238
Pins converter input pins eight analog signal channels. Analog signals subject conversion applied these pins. converter contains sample-and-hold circuit, analog input voltages internally maintained during conversion. AVREF, AVSS reference voltage converter applied these pins. using applied voltage across AVREF AVSS, signals applied converted digital signals. AVSS must always VSS. AVDD This supply voltage converter. When converter used standby mode, potential AVDD must equal that pin. conversion mode register conversion mode register (ADM) 8-bit register used select analog input channels, direct start conversion, detect completion conversion. (See Fig. 4-63.) with 8-bit manipulation instruction. conversion completion detection flag (EOC) conversion start direction (SOC) manipulated individually. RESET input initializes 04H. That only with bits cleared
µPD75238
Fig. 4-63
Address FD8H ADM6 ADM5 ADM4
Format Conversion Mode Register
Symbol
conversion flag Conversion completed Conversion under
Start conversion Setting this starts conversion. After conversion started, reset automatically.
Analog channel selection ADM6 ADM5 ADM4 Analog channel
Caution conversion started maximum 24/f seconds (2.67 MHz)Note after set. (See Section 4.10.) Note 3.81 4.19
µPD75238
register (SA) register (successive approximation register) 8-bit register hold result conversion successive approximation. read with 8-bit manipulation instruction. data written software. RESET input sets 7FH. converter operation Analog input signals subject conversion specified setting bits conversion mode register (ADM6, ADM5, ADM4). conversion started setting (SOC) After that, automatically cleared conversion performed hardware using successive-approximation method. resultant 8-bit data loaded into register. Upon completion conversion, (EOC) Fig. 4-64 shows timing chart conversion. converter used follows: Select analog input channels setting ADM6, ADM5 ADM4). Direct start conversion setting SOC)3 Wait completion conversion (wait wait using software timer). Read result conversion (read register).
Cautions above performed same time. There delay 24/fX seconds (2.67 MHz)Note from setting clearing after conversion started. must tested when time indicated Table elapsed after setting SOC. Table also indicates conversion times. Note 3.81 4.19 Table
Setting values SCC, conversion time SCC3 SCC0 PCC1 PCC0 Conversion stopped 168/fX (28.0 MHz)Note
Setting
Wait time from setting Wait time from setting conversion completo test tion Waiting required machine cycles machine cycles Waiting required machine cycles machine cycles machine cycles Waiting required
Note
40.1 4.19 Don't care
Remark
µPD75238
Fig. 4-64 Timing Chart Conversion
register Previous data Undefined Result conversion
Time elapsed before conversion starts (Maximum 24/fX
Sampling time conversion 168/
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