V850/SV1 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS INTEGRATED CIRCU
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µPD70F3040, 70F3040Y
V850/SV1 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
INTEGRATED CIRCUIT
DESCRIPTION
µPD70F3040 µPD70F3040Y products that substitute flash memory mask
µPD703039, 703040, 703041 µPD703039Y, 703040Y, 703041Y, respectively. Since µPD70F3040
70F3040Y read written while mounted board, these products ideal evaluation during system development, multiple-version small-scale production quick product release. Detailed function descriptions provided following user's manuals. sure read them before designing. V850/SV1 User's Manual Hardware: U14462E U10243E V850 Family User's Manual Architecture: FEATURES compatible with µPD703039, 703040, 703041, 703039Y, 703040Y, 703041Y mass production, these replaced mask version.
µPD70F3040
µPD703039, 703040, 703041
µPD70F3040Y µPD703039Y, 703040Y, 703041Y
ORDERING INFORMATION
Part Number Package 176-pin plastic LQFP (fine-pitch) 176-pin plastic LQFP (fine-pitch)
µPD70F3040GM-UEU µPD70F3040YGM-UEU
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
Internal Internal None Provided (mask ROM) None Provided None Provided (mask ROM) None Provided None
Provided
µPD70F3040 µPD70F3040Y µPD703039 µPD703039Y µPD703040 µPD703040Y µPD703041 µPD703041Y
(flash memory)
information contained this document being issued advance production cycle device. parameters device change before final production Corporation, discretion, withdraw device prior production. devices/types available every country. Please check with local representative availability additional information.
Document U14622EJ1V0DS00 (1st edition) Date Published March 2000 CP(K) Printed Japan
2000
µPD70F3040, 70F3040Y
CONFIGURATION
176-pin plastic LQFP (fine-pitch)
µPD70F3040GM-UEU µPD70F3040YGM-UEU
P12/SCK0/SCL0Note P13/SI1/RXD0 P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note P21/SO2 P22/SCK2/SCL1Note P23/SI3/RXD1 P24/SO3/TXD1 P25/SCK3/ASCK1 P26/TI2/TO2 P27/TI3/TO3 P30/TI000 P31/TI001 P32/TI010 P33/TI011 P34/TO0 P35/TO1 P36/TI4/TO4 P37/TI5/TO5 P120/SI4 P121/SO4 P122/SCK4 P123/CLO P124/TI6/TO6 P125/TI7/TO7 P126/TI10/TO10 P127/TI11/TO11 P180 P181 P182 P183 P184 P185 P186 P187 P190 P191 P192 P193
P11/SO0 P10/SI0/SDA0Note P113 P112 P111 P110 WAIT CLKOUT P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P96/HLDRQ P95/HLDAK P94/ASTB P93/DSTB/RD P92/R/W/WRH P91/UBEN P90/LBEN/WRL AVDD AVSS AVREF
P87/ANI15 P86/ANI14 P85/ANI13 P84/ANI12 P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 P147 P146 P145/RTPTRG1 P144/TI9/INTTI9 P143/INTCP93 P142/INTCP92 P141/INTCP91 P140/INTCP90 P137/TO81 P136/TO80 P135/TCLR8/INTTCLR8 P134/TI8/INTTI8 P133/INTCP83 P132/INTCP82 P131/INTCP81 P130/INTCP80 P07/INTP6 P06/INTP5/RTPTRG0 P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P157/RTP17 P156/RTP16
Notes Connect normal operation mode. SCL0, SCL1, SDA0, SDA1 valid only µPD70F3040Y.
P194 P195 P196 P197 P170/KR0 P171/KR1 P172/KR2 P173/KR3 P174/KR4 P175/KR5 P176/KR6 P177/KR7 P160/PWM0 P161/PWM1 P162/PWM2 P163/PWM3 P164/CSYNCIN P165/VSOUT P166/HSOUT0 P167/HSOUT1 VPPNote RESET P100/RTP00 P101/RTP01 P102/RTP02 P103/RTP03 P104/RTP04 P105/RTP05 P106/RTP06 P107/RTP07 P150/RTP10 P151/RTP11 P152/RTP12 P153/RTP13 P154/RTP14 P155/RTP15
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
IDENTIFICATION
A21: AD15: ADTRG: ANI0 ANI15: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: CLO: CSYNCIN: DSTB: HLDAK: HLDRQ: Address Address/Data Trigger Input Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Interface Power Supply Interface Ground Clock Output Clock Output (divided) Csync Input Data Strobe Hold Acknowledge Hold Request P120 P127: P130 P137: P140 P147: P150 P157: P160 P167: P170 P177: P180 P187: P190 P197: PWM0 PWM3: RESET: RTP00 RTP07,: RTP10 RTP17 RTPTRG0, RTPTRG1: Trigger Input R/W: RXD0, RXD1: SCK0 SCK4: SCL0, SCL1: SDA0, SDA1: SI4: SO4: TCLR8: Return Lower Byte Enable Non-Maskable Interrupt Request Port Port Port Port Port Port Port Port Port Port Port Port TI011, TI11 TO7, TO80,: TO81, TO10, TO11 TXD0, TXD1: UBEN: VDD: VPP: VSOUT: VSS: WAIT: WRH: WRL: XT1, XT2: Transmit Data Upper Byte Enable Power Supply Programming Power Supply Vsync Output Ground Wait Write Strobe High Level Data Write Strobe Level Data Crystal Main System Clock Crystal Subsystem Clock Timer Output Read/Write Status Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Timer Clear Port Port Port Port Port Port Port Port Pulse Width Modulation Read Reset Real-time Output Port
HSOUT0, HSOUT1: Hsync Output INTCP80 INTCP83,: Interrupt Request from Peripherals INTCP90 INTCP93, INTP0 INTP6, INTTCLR8, INTTI8, INTTI9 KR7: LBEN: NMI: P07: P15: P27: P37: P47: P57: P65: P77: P87: P96: P100 P107: P110 P113:
TI000, TI001, TI010,: Timer Input
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
INTERNAL BLOCK DIAGRAM
INTP0 INTP6 INTCP80 INTCP83, INTCP90 INTCP93 INTTCLR8 INTTI8, INTTI9 TI000, TI001, TI010, TI011 TO0, TO80, TO81 TI8, TCLR8 TI2/TO2, TI3/TO3 TI4/TO4, TI5/TO5 TI6/TO6, TI7/TO7 TI10/TO10, TI11/TO11 CSYNCIN HSOUT0, HSOUT1, VSOUT SI0/SDA0Note SCK0/SCL0Note SI2/SDA1Note SCK2/SCL1Note SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SCK4
INTC
correction Multiplier
Instruction queue
HLDRQ HLDAK ASTB DSTB/RD R/W/WRH UBEN LBEN/WRL WAIT AD15
Note Timer/counter 16-bit timers: TM0, 8-bit timers: TM7, TM10, TM11 24-bit timers: TM8,
32-bit barrel shifter System register General registers bits
Vsync/Hsync CSI0/I2C0Note Ports CSI2/I2C1Note CSI1/UART0 CSI3/UART1 Variable length CSI4 return function DMAC:
P190 P197 P180 P187 P170 P177 P160 P167 P150 P157 P140 P147 P130 P137 P120 P127 P110 P113 P100 P107
converter
AVDD AVREF AVSS ANI0 ANI15 ADTRG
CLKOUT RESET
Watch timer Watchdog timer RTP00 RTP07, RTP10 RTP17 RTPTRG0, RTPTRG1
BVDD BVSS
PWM0 PWM3
Notes (Flash memory) SDA0, SDA1, SCL0, SCL1 valid only µPD70F3040Y.
function valid only µPD70F3040Y.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
CONTENTS
FUNCTIONS.
Port Pins. Non-Port Pins. Circuits, Buffer Supply, Recommended Connection Unused Pins
ELECTRICAL SPECIFICATIONS. PACKAGE DRAWING RECOMMENDED SOLDERING CONDITION.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
FUNCTIONS Port Pins
(1/4)
Name Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 6-bit port Input/output mode specified 1-bit units. PULL Function Port 8-bit port Input/output mode specified 1-bit units. Alternate Function INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG0 INTP6 SI0/SDA0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3 TI000 TI001 TI010 TI011 TI4/TO4 TI5/TO5
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
(2/4)
Name Port 7-bit port Input/output mode specified 1-bit units. Input Port 8-bit input port Input Port 8-bit input port Port 6-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. PULL Function Port 8-bit port Input/output mode specified 1-bit units. Alternate Function AD10 AD11 AD12 AD13 AD14 AD15 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 LBEN/WRL UBEN R/W/WRH DSTB/RD
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
(3/4)
Name P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 P120 P121 P122 P123 P124 P125 P126 P127 P130 P131 P132 P133 P134 P135 P136 P137 P140 P141 P142 P143 P144 P145 P146 P147 Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. SCK4 TI6/TO6 TI7/TO7 TI10/TO10 TI11/TO11 INTCP80 INTCP81 INTCP82 INTCP83 TI8/INTTI8 TCLR8/INTTCLR8 TO80 TO81 INTCP90 INTCP91 INTCP92 INTCP93 TI9/INTTI9 RTPTRG1 Port 4-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. PULL Function Port 7-bit port Input/output mode specified 1-bit units. Alternate Function ASTB HLDAK HLDRQ RTP00 RTP01 RTP02 RTP03 RTP04 RTP05 RTP06 RTP07
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
(4/4)
Name P150 P151 P152 P153 P154 P155 P156 P157 P160 P161 P162 P163 P164 P165 P166 P167 P170 P171 P172 P173 P174 P175 P176 P177 P180 P181 P182 P183 P184 P185 P186 P187 P190 P191 P192 P193 P194 P195 P196 P197 Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. Port 8-bit port Input/output mode specified 1-bit units. PULL Function Port 8-bit port Input/output mode specified 1-bit units. Alternate Function RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 RTP16 RTP17 PWM0 PWM1 PWM2 PWM3 CSYNCIN VSOUT HSOUT0 HSOUT1
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Non-Port Pins
(1/4)
Name AD15 ADTRG ANI0 ANI7 ANI8 ANI15 ASCK0 ASCK1 ASTB AVDD Output External address strobe signal output Positive power supply converter ports used alternate functions Reference voltage input converter Ground potential converter ports used alternate functions Positive power supply interface ports used alternate functions Ground potential interface ports used alternate functions Internal system clock output output signal Csync signal input External data strobe signal output hold acknowledge output hold request input Hsync signal output before compensation Hsync signal output after compensation Input External capture input CC80 CC83 P123 P164 P93/RD P166 P167 P130 P133 Input Input Input Input Baud rate clock input UART0 UART1 converter external trigger input Analog input converter Output PULL Address Address/data multiplexed Function Alternate Function P05/INTP4 P15/SCK1 P25/SCK3
AVREF AVSS
Input
BVDD
BVSS
CLKOUT CSYNCIN DSTB HLDAK HLDRQ HSOUT0 HSOUT1 INTCP80 INTCP83 INTCP90 INTCP93 INTP0 INTP3 INTP4 INTP5 INTP6
Output Output Input Output Output Input Output
Input
External capture input CP90 CP93
P140 P143
Input
External interrupt request input (analog noise elimination) External interrupt request input (digital noise elimination)
P05/ADTRG P06/RTPTRG0
External interrupt request input (digital noise elimination supporting remote controller)
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
(2/4)
Name INTTCLR8 INTTI8 INTTI9 LBEN PWM0 PWM3 RESET RTP00 RTP07 RTP10 RTP17 RTPTRG0 RTPTRG1 RXD0 RXD1 SCK0 SCK1 SCK2 SCK3 SCK4 SCL0 SCL1 SDA0 SDA1 TCLR8 Input Variable-length CSI4 serial transmit data output External clear input Output Variable-length CSI4 serial receive data input (3-wire mode) Serial transmit data output CSI0 CSI3 Input Variable-length CSI4 serial clock Serial clock (µPD70F3040Y) Serial transmit/receive data (µPD70F3040Y) Serial receive data input CSI0 CSI3 (3-wire mode)
Input Input
PULL
Function External interrupt request input (digital noise elimination)
Alternate Function P135/TCLR8 P134/TI8 P144/TI9
Input Output Input Output Output Input Output
return input Lower byte enable signal output external data Non-maskable interrupt request input Output channels read strobe signal output System reset input Real-time output port
P170 P177 P90/WRL P160 P163 P93/DSTB P100 P107 P150 P157
Input
external trigger input
P146
Output Input
External read/write status output Serial receive data input UART0 UART1
P92/WRH P13/SI1 P23/SI3
Serial clock CSI0 CSI3 (3-wire mode)
P12/SCL0 P15/ASCK0 P22/SCL1 P25/ASCK1 P122 P12/SCK0 P22/SCK2 P10/SI0 P20/SI2 P10/SDA0 P13/RXD0 P20/SDA1 P23/RXD1 P120 P14/TXD0 P24/TXD1 P121 P135/INTTCLR8
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
(3/4)
Name TI000 TI001 TI010 TI011 TI10 TI11 TO80 TO81 TO10 TO11 TXD0 TXD1 UBEN VSOUT WAIT Output Output Input Output Higher byte enable signal output external data Positive power supply High voltage application program write/verify Vsync signal output Ground potential External WAIT signal input Higher byte write strobe signal output external data Lower byte write strobe signal output external data P92/R/W P90/LBEN P165 Output Output Input PULL Function External count clock input/external capture trigger input External capture trigger input External count clock input/external capture trigger input External capture trigger input External count clock input External count clock input External count clock input External count clock input External count clock input External count clock input External count clock input External count clock input External count clock input TM10 External count clock input TM11 Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output Pulse signal output TM10 Pulse signal output TM11 Serial transmit data output UART0 UART1 Alternate Function P26/TO2 P27/TO3 P36/TO4/A15 P37/TO5 P124/TO6 P125/TO7 P134/INTTI8 P144/INTTI9 P126/TO10 P127/TO11 P26/TI2 P27/TI3 P36/TI4 P37/TI5 P124/TI6 P125/TI7 P136 P137 P126/TI10 P127/TI11 P14/SO1 P24/SO3
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
(4/4)
Name Input Input Resonator connection subsystem clock PULL Function Resonator connection main system clock Alternate Function
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Circuits, Buffer Supply, Recommended Connection Unused Pins
Table shows input/output circuit type each recommended connection unused pins. input/output configuration each type, refer Figure 1-1. Table 1-1. Types Circuit Recommended Connection Unused Pins (1/2)
Alternate Function Circuit Type Buffer Power Supply Input: Output: Recommended Connection Method
P26, P30, P32, P34, P100 P107 P110 P113 P120
INTP0 INTP3 INTP4/ADTRG INTP5/RTPTRG0 INTP6 SI0/SDA0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2, TI3/TO3 TI000, TI001 TI010, TI011 TO0, TI4/TO4 TI5/TO5 AD15 ANI0 ANI7 ANI8 ANI15 LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ RTP00 RTP07
Independently connect resistor Leave open
10-F 10-E 10-F 10-E 10-F 10-F 10-E 10-F 10-E 10-F
BVDD BVDD BVDD AVDD AVDD BVDD
Input: Output:
Independently connect BVDD BVSS resistor Leave open
Connect AVSS
Input: Output:
Independently connect BVDD BVSS resistor Leave open
10-E
Input: Output:
Independently connect resistor Leave open
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Table 1-1. Types Circuit Recommended Connection Unused Pins (2/2)
Alternate Function Circuit Type 10-G 10-H Output: Buffer Power Supply Input: Recommended Connection Method
P121 P122 P123 P124 P125 P126 P127 P130 P133 P134 P135 P136, P137 P140 P143 P144 P145 P146, P147 P150 P157 P160 P163 P164 P165 P166 P167 P170 P177 P180 P187 P190 P197 CLKOUT WAIT RESET AVREF AVDD AVSS BVDD BVSS
SCK4 TI6/TO6 TI7/TO7 TI10/TO10 TI11/TO11 INTCP80 INTCP83 TI8/INTTI8 TCLR8/INTTCLR8 TO80, TO81 INTCP90 INTCP93 TI9/INTTI9 RTPTRG1 RTP10 RTP17 PWM0 PWM3 CSYNCIN VSOUT HSOUT0 HSOUT1
Independently connect resistor Leave open
BVDD BVDD Connect Leave open Connect Leave open Connect AVSS Connect Leave open Connect resistor
Connect Connect Connect
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Figure 1-1. Input/Output Circuits (1/2)
Type
Type P-ch N-ch Output disable N-ch Data P-ch IN/OUT
Input enable
Type
Type
Pullup enable Data Output disable Input enable Type Data Data P-ch Output disable N-ch Output disable
P-ch P-ch IN/OUT N-ch
Schmitt-triggered input with hysteresis characteristics Type
P-ch IN/OUT N-ch
Push-pull output that high impedance output (both P-ch N-ch off)
Input enable
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Figure 1-1. Input/Output Circuits (2/2)
Type
Type 10-F
Pullup enable Data
P-ch P-ch IN/OUT
Pullup enable Data
P-ch P-ch IN/OUT
Output disable Input enable Type
N-ch
Open Output disable Input enable Type 10-G
N-ch
P-ch N-ch
Data Comparator
P-ch IN/OUT
Open drain VREF (Threshold voltage) Output disable N-ch
Input enable
Input enable
Type 10-E
Type 10-H
Pullup enable Data
P-ch
Data
P-ch IN/OUT
P-ch IN/OUT
Open Output disable Input enable
Open drain Output disable
N-ch
N-ch Input enable
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C,
Parameter Supply voltage Symbol AVDD BVDD AVSS BVSS Input voltage Clock input voltage Analog input voltage Analog reference input voltage Output current, VIAN AVREF Note (VDD) Note (BVDD) XT1, Note (AVDD) AVREF Total P150 P157 Total P100 P107 P160 P167 Total P170 P177 P190 P197 Total P124 P127 P180 P187 Total P120 P123 Total P15, P110 P113 Total P57, P65, CLKOUT Total Total P130 P137 P140 P147 Output current, high Total P150 P157 Total P100 P107 P160 P167 Total P170 P177 P190 P197 Total P124 P127 P180 P187 Total P120 P123 Total P15, P110 P113 Total P57, P65, CLKOUT Total Total P130 P137 P140 P147 Output voltage Operating ambient temperature Note (VDD) Note (BVDD) Normal operation mode Flash programming mode Storage temperature Tstg Conditions Ratings -0.5 +4.6 -0.5 +4.6 -0.5 +4.6 -0.5 +0.5 -0.5 +0.5 -0.5
Note Note
Unit
Note
-0.5 BVDD -0.5 +8.5 -0.5
-0.5 AVDD -0.5 AVDD -4.0 -0.5
Note
Note
Note
-0.5 BVDD +125
Note
Notes Ports RESET (including alternate-function pins) Ports WAIT (including alternate-function pins) Ports (including alternate-function pins) sure exceed each absolute maximum rating (MAX.).
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Cautions Avoid direct connections among device output I/O) pins between GND. However, direct connections among open-drain open-connector pins possible, direct connections external circuits that have timing designed prevent output contention with pins that become high-impedance. Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. ratings conditions indicated characteristics characteristics represent quality assurance range during normal operation.
Capacitance 25°C,
Parameter Input capacitance capacitance Output capacitance Symbol Conditions Unmeasured pins returned MIN. TYP. MAX. Unit
Operating Conditions
Operation Frequency
Parameter operation frequency Symbol fCPU Conditions When main system clock operating When subsystem clock operating MIN. 32.768 TYP. MAX. Unit
Supply Voltage
Parameter Supply voltage Symbol AVDD BVDD Conditions MIN. TYP. MAX. Unit
Operating Frequency Each Supply Voltage
Internal Operating Clock Frequency 32.768 Supply Voltage (VDD AVDD BVDD)
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Recommended Oscillator
Main System Clock Oscillator +85°C)
Parameter Oscillation frequency Oscillation stabilization time
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
After reset release After STOP mode release
/fXX Note
Note Values vary depending settings oscillation stabilization selection register (OSTS). Remarks Place oscillator close possible wire other signal lines within broken lines. resonator selection oscillation constants, customers advised either evaluate oscillation themselves, apply resonator manufacturer evaluation.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Subsystem Clock Oscillator +85°C)
Parameter Oscillation frequency Oscillation stabilization time
Symbol
Conditions
MIN.
TYP. 32.768
MAX.
Unit
Remarks Place oscillator close possible XT2. wire other signal lines within broken lines. resonator selection oscillation constants, customers advised either evaluate oscillation themselves, apply resonator manufacturer evaluation.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Characteristics +85°C, AVDD BVDD AVSS BVSS
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage, VIL1 VIL2 VIL3 VIL4 VIL5 Output voltage, high VOH1 VOH2 Output voltage, VOL1 VOL2 Conditions Pins Note WAIT Pins Note Pins Note RESET Pins Note XT1, Pins Note WAIT Pins Note Pins Note RESET Pins Note XT1, Note CLKOUT Notes Note CLKOUT Notes (excluding P10, VOL3 Input leakage current, high ILIH1 P10, AVDD BVDD Other than XT1, XT1, Other than XT1, XT1, AVDD BVDD Normal operation (fXX MHz) HALT mode (fXX MHz) IDLE mode (fXX MHz) STOP mode (subsystem clock operation: 32.768 kHz, watch timer operation STOP mode (subsystem clock stopped) Pull-up resistor MIN. 0.7BVDD 0.7VDD 0.75VDD 0.7AVDD 0.8VDD BVSS AVSS 0.8BVDD 0.8VDD TYP. MAX. BVDD AVDD 0.3BVDD 0.3VDD 0.3VDD 0.3AVDD 0.2VDD Unit
ILIH2 Input leakage current, ILIL1
ILIL2 Output leakage current, high Output leakage current, Supply current ILOH ILOL IDD1 IDD2 IDD3 IDD4
Notes Ports (including alternate-function pins) P11, P14, P21, P24, P34, P35, P100 P107, P110 P113, P121, P123, P136, P137, P146, P147, P150 P157, P160 P163, P165 P167, P180 P187, P190 P197 (including alternate-function pins) P07, P10, P12, P13, P15, P20, P22, P23, P27, P33, P36, P37, P120, P122, P124 P127, P130 P135, P140 P145, P164, P170 P177 (including alternate-function pins) Ports (including alternate-function pins) Caution TYP. value current that consumed output buffers included.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Data Retention Characteristics +85°C, AVDD BVDD AVSS BVSS
Parameter Data retention voltage Data retention current Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) STOP release signal input time Data retention high-level input voltage Data retention low-level input voltage Symbol VDDDR IDDDR tRVD tFVD tHVD Conditions STOP mode VDDDR MIN. TYP. MAX. Unit
tDREL VIHDR VILDR input ports input ports
VIHn VDDDR VILn
Remark
Setting STOP mode
tFVD
tRVD
tHVD VDDDR tDREL
RESET (input)
VIHDR
NMI, INTP0 INTP3 (input)
VIHDR
STOP release interrupt (NMI) (when STOP mode released rising edge)
VILDR
Caution sure shift return from STOP mode when higher.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Characteristics Test Input Waveforms (VDD, BVDD, AVDD)
Test points
Test Output Test Point (BVDD)
Test points
Load Conditions
(Device under test)
Caution load capacitance exceeds circuit configuration, bring load capacitance device less inserting buffer some other means.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Clock Timing Operating Condition +85°C, AVDD BVDD AVSS BVSS
Parameter input cycle input cycle input high-level width input high-level width input low-level width input low-level width input rise time input fall time CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time tCYK tWKH tWKL <10> 62.5 (T-20) (T-20) tWXL tWXH Symbol tCYX Conditions MIN. 62.5 28.6 31.2 14.3 31.2 14.3 MAX. 31.2 15.6 15.6
Unit
31.2
Remark tCYK Clock Timing
(input)
CLKOUT (output)
<10>
Timing Pins Other Than CLKOUT Pins +85°C, AVDD BVDD AVSS BVSS Output Load Capacitance:
Parameter Output rise time Output fall time Symbol Conditions MIN. MAX. Unit
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Timing (CLKOUT Asynchronous) +85°C, AVDD BVDD AVSS BVSS
Parameter Address setup time ASTB) Address hold time (from ASTB) Address float from DSTB Setup time from address data input Setup time from DSTB data input Delay time from ASTB DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB ASTB Delay time from DSTB ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time DSTB) Data output hold time (from DSTB) WAIT setup time address) Symbol tSAST tHSTA tFDA tDAID tDDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 HLDRQ high-level width HLDAK low-level width Delay time from HLDAK output Delay time from HLDRQ HLDAK Delay time from HLDRQ HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> <36> <37> <38> 1.5T 0.5T 7.5)T 1.5T (0.5 (1.5 1.5T 1.5T (1.5 0.5T 0.5T (1.5 Conditions MIN. 0.5T 0.5T MAX. Unit
Remarks 1/fCPU (fCPU: operation clock frequency) Number wait clocks inserted cycle. Sampling timing changes when programmable wait inserted. Number idle states inserted after read cycle specifications described above values when clock with duty ratio input from
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Timing (CLKOUT Synchronous) +85°C, AVDD BVDD AVSS BVSS
Parameter Delay time from CLKOUT address Delay time from CLKOUT address float Delay time from CLKOUT ASTB Delay time from CLKOUT DSTB Data input setup time CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT data output WAIT setup time CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT address float Delay time from CLKOUT HLDAK Symbol tDKA tFKA <39> <40> Conditions MIN. MAX. Unit
tDKST tDKD tSIDK tHKID tDKOD
<41> <42> <43> <44> <45>
tSWTK tHKWT tSHQK tHKHQ tDKF
<46> <47> <48> <49> <50>
tDKHA
<51>
Remark specifications described above values when clock with duty ratio input from
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Read Cycle (CLKOUT Synchronous/Asynchronous, Wait)
CLKOUT (output) <39> (output), Note <14> <43> <40> AD15 (I/O) Address <41> <12> <11> ASTB (output) <22> <42> <16> <13> <15> <42> <19> <18> <20> <21> <46> Hi-Z Data <41> <17> <44>
DSTB (output), (output) <30> <46> <32> <31> <33> <47> <47>
WAIT (input) <26> <28> <27> <29>
Note (output), UBEN (output), LBEN (output) Remark high level.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Write Cycle (CLKOUT Synchronous/Asynchronous, Wait)
CLKOUT (output) <39> (output), Note <45> AD15 (I/O) Address <41> <12> <11> Data <41>
ASTB (output) <22> <42> <16> DSTB (output), (output), (output) <30> <46> <32> <31> <33> <47> <21> <46> <47> <23> <42> <24> <25> <19>
WAIT (input) <26> <28> <27> <29>
Note (output), UBEN (output), LBEN (output) Remark high level.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Hold
CLKOUT (output) <48> <49>
<48> <34>
HLDRQ (input)
<51> <37> <38>
<51>
HLDAK (output) <50> <35> (output), Note Hi-Z <36>
AD15 (I/O)
Data
Hi-Z
ASTB (output)
Hi-Z
DSTB (output), (output), (output), (output)
Hi-Z
Note (output), UBEN (output), LBEN (output)
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Reset/Interrupt Timing +85°C, AVDD BVDD AVSS BVSS
Parameter RESET high-level width RESET low-level width high-level width low-level width INTPn high-level width Symbol tWRSH tWRSL tWNIH tWNIL tWITH <52> <53> <54> <55> <56> analog noise elimination digital noise elimination digital noise elimination INTPn low-level width tWITL <57> analog noise elimination digital noise elimination digital noise elimination Conditions MIN. 3Tsmp 3Tsmp MAX. Unit
Remarks 1/fXX Tsmp Noise elimination sampling clock frequency Reset
<52>
<53>
RESET (input)
Interrupt
<54>
<55>
(input)
<56>
<57>
INTPn (input)
Remark
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Input Timing +85°C, AVDD =BVDD AVSS BVSS
Parameter Tln0, Tln1 High-level width High-level width Tln0, Tln1 Low-level width Low-level width 3/fXX tTIL <59> 2Tsam
Note
Symbol tTIIH <58>
Conditions
MIN. 2Tsam
Note
MAX.
Unit
3/fXX
Note Tsam selected setting PRMn1 PRMn0 bits prescaler mode registers (PRMn0, PRMn1) (PRM00, PRM01 registers): Tsam 2/fXX, 4/fXX, 16/fXX, 64/fXX, 256/fXX, 1/INTWTI period (PRM10, PRM11 registers): Tsam 2/fXX, 4/fXX, 16/fXX, 32/fXX, 128/fXX, 256/fXX However, when TIn0 valid edge selected count clock, Tsam 4/fXX
<58>
<59>
Remark 000, 001, 010, 011,
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
3-Wire Timing Master Mode +85°C, AVDD BVDD AVSS BVSS
Parameter SCKn cycle time SCKn high-level width SCKn low-level width setup time SCKn) hold time (from SCKn) Delay time from SCKn output Symbol tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 <60> <61> <62> <63> <64> <65> Conditions MIN. MAX. Unit
Remark Slave Mode +85°C, AVDD BVDD AVSS BVSS
Parameter SCKn cycle time SCKn high-level width SCKn low-level width setup time SCKn) hold time (from SCKn) Delay time from SCKn output Symbol tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 <60> <61> <62> <63> <64> <65> Conditions MIN. MAX. Unit
Remark
<60> <61> <62> <63> (input) <65> (output) <64>
SCKn (I/O)
Remark
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
3-Wire Variable-Length Timing Master Mode +85°C, AVDD BVDD AVSS BVSS
Parameter SCK4 cycle time SCK4 high-level width SCK4 low-level width setup time SCK4) hold time (from SCK4) Delay time from SCK4 output Symbol tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 <66> <67> <68> <69> <70> <71> Conditions MIN. MAX. Unit
Slave Mode +85°C, AVDD BVDD AVSS BVSS
Parameter SCK4 cycle time SCK4 high-level width SCK4 low-level width setup time SCK4) hold time (from SCK4) Delay time from SCK4 output Symbol tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 <66> <67> <68> <69> <70> <71> Conditions MIN. MAX. Unit
<66> <67> <68> <69> (input) <71> (output) <70>
SCK4 (I/O)
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
UART Timing +85°C, AVDD BVDD AVSS BVSS
Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Symbol tKCY13 tKH13 tKL13 <72> <73> <74> Conditions MIN. MAX. Unit
Remark
<72> <73> <74>
ASCKn (input)
Remark
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Mode (Only µPD70F3040Y)
+85°C, AVDD BVDD AVSS BVSS
Parameter Symbol Standard Mode MIN. SCLn clock frequency free time (between stop/start conditions) Hold time
Note
High-Speed Mode MIN. MAX.
Unit
MAX.
fCLK tBUF <75>
tLOW tHIGH
<76> <77> <78> <79> <80>
Note
1000
Note
Note
SCLn clock low-level width SCLn clock high-level width Setup time start/restart conditions Data hold time Data setup time Rising time SDAn SCLn signals Falling time SDAn SCLn signals Setup time stop condition Pulse width spike suppressed input filter Load capacitance line
CBUS-compatible master mode
<81> <82> <83> <84> <85>
Note
Note
0.1Cb 0.1Cb
Note
Notes first clock pulse start condition generated after hold time. system must internally provide least 300-ns hold time SDAn signal VIHmin. SCLn signal) order fill undefined period that appears SCLn falling edge. system does extend hold time (tLOW), required satisfy only maximum data hold time (tHD: DAT).
high-speed available standard mode system. this case, following
conditions should satisfied. When system does extend low-state hold time SCLn signal tSU: When system extends low-state hold time SCLn signal Before SCLn line released (tRmax. tSU: Total capacitance line (Unit: Remark
1000 1250 Standard mode
specification), send next data SDAn line.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Mode (µPD70F3040Y only)
<77> SCLn
<82>
<80> <76>
<78>
<83> <79> <81> <76> <85> <84>
SDAn <75> Stop Strat condition condition Restart condition Stop condition
Remark
Converter +85°C, AVDD AVREF AVSS Output Load Capacitance:
Parameter Resolution Overall error
Note
Symbol
Conditions
MIN.
TYP.
MAX. ±0.8
Unit %FSR
Conversion time Zero-scale error Full-scale error
Note
tCONV
±0.4 ±0.4
%FSR %FSR
Note
Integral linearity error
Note
±4.0 ±4.0 AVREF VIAN AIREF AIDD AVREF AVDD AVSS AVREF
Differential linearity error
Note
Analog reference voltage Analog input voltage AVREF current Supply current
Notes Excluding quantization error (±0.05%FSR) Excluding quantization error (±0.5LSB) Remark LSB: Least Significant FSR: Full Scale Range
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Flash Memory Programming Mode Write/Erase Characteristics 40°C,
Parameter Write current Symbol IDDW IPPW Erase current IDDE IPPE Unit erase time Total erase time Rewrite count
Note
Conditions When VPP1 When VPP1
MIN.
TYP.
MAX.
Unit times
tERT
VPP0 VPP1 normal operation mode flash memory programming mode
0.2VDD
supply voltage
Operation frequency
Note Write/erase regarded cycle.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
PACKAGE DRAWING
176-PIN PLASTIC LQFP (FINE PITCH) (24x24)
detail lead
NOTE Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 26.0±0.2 24.0±0.2 24.0±0.2 26.0±0.2 1.25 1.25 0.22±0.05 0.08 (T.P.) 1.0±0.2 0.17 +0.03 -0.07 0.08 0.1±0.05 1.5±0.1 S176GM-50-UEU
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
RECOMMENDED SOLDERING CONDITIONS
T.B.D.
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
[MEMO]
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
Related document Reference document
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Data Sheet (U13953E)
Electrical Characteristics Microcomputer (IEI-601)
Note
Note This document number that Japanese version. documents indicated this publication include preliminary versions. versions marked such. V850 Family V850/SV1 trademarks Corporation. However, preliminary
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
Regional Information
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Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
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Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
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Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
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United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
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Milano, Italy Tel: 02-66 Fax: 02-66
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Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Preliminary Data Sheet U14622EJ1V0DS00
µPD70F3040, 70F3040Y
information contained this document being issued advance production cycle device. parameters device change before final production Corporation, discretion, withdraw device prior production. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. Descriptions circuits, software, other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software, information design customer's equipment shall done under full responsibility customer. Corporation assumes responsibility losses incurred customer third parties arising from these circuits, software, information. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance.
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