4-BIT SINGLE CHIP MICROCONTROLLER REMOTE CONTROL TRANSMISSION INT

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4-BIT SINGLE CHIP MICROCONTROLLER REMOTE CONTROL TRANSMISSION INT

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PD6125A, 6126A
4-BIT SINGLE CHIP MICROCONTROLLER REMOTE CONTROL TRANSMISSION
INTEGRATED CIRCUIT
DESCRIPTION
µPD6125A 6126A 4-bit single-chip microcontrollers infrared remote controllers TVs, VCRs, stereos, cassette decks, conditioners, etc. These microcontrollers consist ROM, RAM, 4-bit parallel-processing ALU, programmable timer, input/ output ports, transmit output ports. Functioning controlled software.
FEATURES
Transmitter programmable infrared remote controller types instructions Instruction execution time: ceramic oscillator) 17.6 (with 455-kHz
Transmission-in-progress indication (S-OUT): Transmit carrier frequency (REM) fOSC/12, fOSC/8 Standby operation (HALT/STOP mode) power consumption Current consumption STOP mode 25°C) MAX. Low-voltage operation:
Program memory (ROM) capacity: 1002 bits Data memory (RAM) capacity: bits 9-bit programmable timer: channel pins (KI/O): pins pins (I/O) µPD6125A: pins µPD6126A: pins
Input pins (KI): pins Serial input pins (S-IN): Caution transmission format, supply custom code. mask option (PLA data) setting µPD6125A, µPD6126A different from that µPD6125, 6126. When register used operand branch instruction,
information this document subject change without notice. Document U12392EJ4V0DS00 (4th edition) (Previous IC-2014B) Date Published 1997 Printed Japan
mark
shows major revised points.
1989
µPD6125A, 6126A
ORDERING INFORMATION
Part Number Package 24-pin plastic shrink (300 mil) 24-pin plastic (300 mil) 28-pin plastic (375 mil)
µPD6125ACA-XXX µPD6125AG-XXX µPD6126AG-XXX
Remark indicates code suffix.
CONFIGURATION (Top View)
PD6125A PD6126A
I/O03 I/O02 I/O01 I/O00 S-IN S-OUT OSC-OUT OSC-IN
KI/O0 KI/O1 KI/O2 KI/O3 KI/O4 KI/O5 KI/O6 KI/O7
I/O11 I/O10 I/O03 I/O02 I/O01 I/O00 S-IN S-OUT OSC-OUT OSC-IN
I/O12 I/O13 KI/O0 KI/O1 KI/O2 KI/O3 KI/O4 KI/O5 KI/O6 KI/O7
µPD6125A, 6126A
BLOCK DIAGRAM
D.P. D.P. PC(L) PC(H)
1002
CNTL CNTL
TIMER TIMER
OUT(L) OUT(H)
Watchdog timer function
OSC-IN S-OUT OSC-OUT
S-IN
KI/O0-KI/07
-KI3
Note
Note
µPD6125A: I/O00-I/O03 µPD6126A: I/O00-I/O03, I/O10-I/O13
DIFFERENCES AMONG PRODUCTS
Part Number Item capacity capacity pins S-IN pins Current consumption (fOSC STOP) (MAX.) S-IN high level input current (MAX.) Transmit carrier frequency Low-voltage detection (reset) circuit Supply voltage Package 24-pin plastic (300 mil) 24-pin plastic shrink (300 mil) (KI/O0-7, I/O00-03) Provided fOSC/12, fOSC/8 provided 28-pin plastic (375 mil)
µPD6125A
1002 bits (Mask ROM) bits
µPD6126A
(KI/O0-7, I/O00-03, I/O10-13)
µPD6125A, 6126A
PROGRAM COUNTER (PC) BITS
program counter (PC) binary counter, which holds address information program memory. Figure 1-1. Program Counter Organization
Normally, program counter contents automatically incremented each time instruction executed, according number instruction bytes. When executing jump instruction (JMP0, JF), program counter indicates jump destination. Immediate data data memory contents loaded some bits When executing call instruction (CALL0), contents incremented (+1) saved into stack memory. Then, value needed each jump instruction will loaded. When executing return instruction (RET), stack memory contents double incremented (+2) loaded into When "all clear" input reset, contents cleared "000H".
STACK POINTER (SP) BITS
This 2-bit register holds start address information stack area. stack area shared with data memory. contents incremented, when call instruction (CALL0) executed. They decremented, when return instruction (RET) executed. stack pointer cleared "00B" after reset "all clear" input, indicates highest address data memory stack area. figure below shows relationship stack pointer data memory area.
Data memory
(SP)
stack pointer overflows underflows, determined that overflows, internal reset signal will generated.
µPD6125A, 6126A
PROGRAM MEMORY (ROM) 1002 STEPS BITS
program memory (ROM) configured bits steps. addressed program counter. Program table data stored program memory. Figure 3-1. Program Memory
000H 0FFH 100H 1FFH 200H 2FFH 300H 3E9H 3EAH 3FFH Test program area
DATA MEMORY (RAM) WORDS BITS
data memory words bits. data memory stores processing data. some cases, data memory processed 8-bit units. used data pointer ROM. After power application, will undefined. retains previous data reset. Figure 4-1. Data Memory Organization
SP-3 SP-2 SP-1 SP-0
Caution
Avoid using areas CALL routine much possible because these areas also used stack memory areas prevent program hang-up case value destroyed some reason such noise). When using these areas general-purpose areas, sure include stack pointer checking main routine.
µPD6125A, 6126A
DATA POINTER (R0)
(R10, R00) data memory serve data pointer ROM. specifies low-order bits address. high-order bits address specified control register. Table referencing data easily executed calling contents setting address data pointer. When "all clear" input reset, becomes undefined. Figure 5-1. Data Pointer Organization
Control registers
ACCUMULATOR BITS
accumulator 4-bit register. accumulator plays major role each operation. When "all clear" input reset, becomes undefined. Figure 6-1. Accumulator Organization
ARITHMETIC LOGIC UNIT (ALU) BITS
arithmetic logic unit (ALU) 4-bit operation circuit, executes simple operations, such arithmetic operations.
FLAGS
Status flag When status each checked STTS instruction, condition coincides with condition specified STTS instruction, status flag When "all clear" input reset, becomes undefined. Carry flag When (increment) instruction (rotate left) instruction executed, carry generated from accumulator, carry flag carry flag also contents accumulator "FH", when SCAF instruction executed. When "all clear" input reset, becomes undefined.
µPD6125A, 6126A
SYSTEM CLOCK GENERATION CIRCUIT
system clock generation circuit consists oscillation circuit, which uses ceramic resonator (400kHz 500kHz). Figure 9-1. System Clock Generation Circuit
OSC-IN
STOP mode
OSC-OUT
System clock
STOP mode (oscillation stop HALT instruction), oscillation circuit system clock generation circuit stops operation, system clock stopped.
µPD6125A, 6126A
TIMER
timer block determines transmission output pattern. timer consists bits, which bits serve 9-bit down counter remaining serves 1-bit latch, which determines carrier output validity. 9-bit down counter decremented (-1) every 8/fOSC(s) synchronization with machine cycle, after starting down count operation. Down counting stops after bits become When down counting stopped, signal indicating that timer operation stopped, output. standby (HALT TIMER) timer operation completion, standby (HALT) condition released next instruction will executed. next instruction again sets value down counter, down counting continues without error (the carrier output affected). down count time according following calculation; (set value (HEX) 8/fOSC. Setting value timer done timer manipulation instruction. When down counter operating, remote control transmission carrier output pin. Whether output carrier selected timer register block. "1", when outputting carrier, "0", when outputting carrier. down counter bits become "0", when outputting carrier, carrier output will stopped. When outputting carrier, output will become level. signal synchronization with output output S-OUT pin. However, waveform SOUT low, when carrier being output pin, high, when carrier being output pin. HALT instruction, which initiates oscillation stop mode, executed when down counter operating, oscillation stop mode initiated after down counting stopped (after Timer operation STOP/RUN controlled control register (P1). (Refer CONTROL REGISTER (P1).) When "all clear" input reset, goes S-OUT goes high. bits timer cleared 000H. Caution Because timer clock synchronized with carrier output, pulse width shortened beginning carrier output. Figure 10-1. Timer Block Organization
timer mainpulation instruction Clear Zero detection circuit 9-bit down counter fosc
S-OUT Carrier (fosc/12, fosc/8) Selected control register
control register (Timer RUN/STOP)
µPD6125A, 6126A
FUNCTIONS
11.1 KI/O (P0) This 8-bit key-scan output. When control register (P1) input port, port used 8-bit input pin. When port input mode, these pins pulled down level inside LSI. When "all clear" input reset, input/output mode goes into effect, value output latch becomes undefined. Figure 11-1. KI/O Organization
Countrol register
KI/O7
KI/O6
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
11.2 KI/O Pull-Down Resistor Organization
Input/output selection P-ch
N-ch CMOS
Output signal Input signal
Pull-down resistor N-ch
When KI/O input mode, pull-down resistor turned
µPD6125A, 6126A
11.3 (P3,
Note
P3/P4 input/output pins adding matrix. control registers switches between input output modes. When input mode, pins pulled down level. When "all clear" input reset, input mode goes into effect, output latch value becomes undefined. Figure 11-2. Organization
P13,
Note
P03,
Note
P3/P4
IN/OUT
I/O3
I/O2
I/O1
I/O0
IN/OUT Input mode Output mode
I/O00 I/O03, I/O10 I/O13
Note µPD6125A equipped with P13, P14, P03, P04. 11.4 Pull-Down Resistor Organization
Input/output selection
P-ch
Output signal Input signal CMOS
N-ch pull-down resistor switch (Mask option) Pull-down resistor
pull-down resistors selected using mask option. When pull-down resistor switch turned set) mask option, pull-down resistor turned only input mode. Caution When using pins switches, turn pull-down resistor switch mask option.
µPD6125A, 6126A
11.5 (P12) This 4-bit input. these pins pulled down level mask option. Figure 11-3. Organization
Mask option
11.6 Pull-Down Resistor Organization
P-ch
pull-down resistor switch (Mask option) Pull-down resistor
Input signal
N-ch
When pull-down resistor switch turned (set mask option, pull-down resistor turned Caution When using switch, turn pull-down resistor switch mask option.
µPD6125A, 6126A
11.7 S-OUT going whenever carrier frequency output from pin, S-OUT indicates that communication progress. S-OUT CMOS output pin. S-OUT goes high reset. 11.8 S-IN input serial data, S-IN pin. When control register (P1) serial input mode, S-IN connected input accumulator. S-IN pulled down level mask option from within LSI. this state, rotate-left accumulator instruction executed, data S-IN copied accumulator. control register released from serial input mode, S-IN goes into high-impedance state, through current flows internally. When instruction executed, copied LSB. When "all clear" input reset, S-IN goes into high-impedance state. Figure 11-4. S-IN Organization
Mask option
S-IN
Control register
µPD6125A, 6126A
PORT REGISTER
KI/O, I/O, control register handled port registers. table below shows relations between port registers pins. Table 12-1. Relations between Port Registers Pins
Input Mode Read status status status Write Output latch Output latch Read status status Output Mode Write Output latch Output latch Reset Undefined [I/O mode, output latch] Input mode Input mode Output latch undefined. status read instruction when register High impedance register
Name KI/O I/O0 I/O1 S-IN
I/O7-4 Control register I3-0 IN/OUT IN/OUT
I/O3-0
Control register
Caution
µPD6125A equipped with I/O10-I/O13 pins.
µPD6125A, 6126A
CONTROL REGISTER (P1)
control register contains bits. controllable items shown Table 13-1. Table 13-1. Control Register (P1)
Name
HALT
D.P.
D.P.
Timer
S-IN
Test mode
Value sure reset
STOP
OSC/8 OSC/12
STOP
Specifies data input when accumulator shifted left. S-IN Specifies status KI/O, follows: input mode, output mode Specifies status timer, follows: Count stop, Count execution Specifies carrier frequency output from pin. fOSC/8, fOSC/12 Specify high-order bits data pointer. Determines what happen oscillation circuit when HALT instruction executed. Oscillation does stop Oscillation stops (STOP mode) sure reset this These bits specify test modes. sure reset them Remark reset, other bits undefined.
µPD6125A, 6126A
STANDBY FUNCTION (HALT INSTRUCTION)
µPD6600A provided with standby mode (HALT instruction), order reduce power consumption, when executing program. Clock oscillation stopped standby mode (STOP mode). standby mode, program execution stops. However, contents internal registers data memory retained. 14.1 STOP Mode (Oscillation Stop HALT Instruction) STOP mode, operation system clock generation circuit (ceramic resonator oscillation circuit) stops. Therefore, operations requiring system clock will stop. HALT instruction executed during timer operation, program counter stops. oscillation stop mode will initiated, after timer count down operation completed. 14.2 HALT Mode (Oscillation Continue HALT Instruction) stops operation, until HALT release condition satisfied. system clock operation continues this mode. 14.3 Standby Release Conditions S-IN input KI/O input input Timer count down operation completion input input Remark Either high level level specified setting release condition input. Table 14-1. Standby Mode Releasing Condition
Releasing Condition S-IN
Remarks When selected, standby mode always released. Valid only mode.
Timer Released when
Valid only mode.
I/O0, I/O1 Judged error initialized even mode.
Releasing condition:
level detection level detection
Caution
µPD6125A equipped with I/O10 I/O13 pins.
µPD6125A, 6126A
(ALL CLEAR PIN)
Internal part including program counter reset setting level. Watchdog Timer Function power-on reset function watchdog timer function, that controlled program, realized connecting capacitor across VSS.
Charge mode
Charge start instruction
Execute HALT instruction immediately before NOP. (Charge more)
Discharge mode Discharge start instruction
Discharge starts after instruction execution. (Discharge time about from
Charge-discharge pattern
pattern must controlled program, such manner that charge level will below
Caution
When watchdog timer function used, switch charging mode executing instruction immediately before HALT instruction beginning program. sure connect capacitor.)
µPD6125A, 6126A
MASK OPTIONS (PLA DATA)
following items selected mask option selection: Provide/not provide I/O, S-IN pull-down resistor Carrier duty selection (1/2, 1/3) fOSC/12 Hang-up detection specification Mask option data should registered object code end. Assignment Switch Selection
Address Corresponding Portion pull-down resistor
Duty S-IN
Duty selection
S-IN pull-down resistor I/O0
Hang detection
KI/O
HALT S-IN
HALT KI/O
HALT
HALT I/O0
HALT I/O1
I/O1
I/O0 pull-down resistor
I/O00
I/O01
I/O02
I/O03
I/O1 pull-down resistor
I/O10
I/O11
I/O12
I/O13
Caution
µPD6125A equipped with I/O10 I/O13 pins.
Switch Data Pull-down resistor When provided (OFF) When Provided (ON) Modulation duty fOSC/12) When duty When duty Hang-up detection KI/O ALL, I/O0 ALL, I/O1 switch hang-up detection KI/O (I/O0 ALL, I/O1 ALL) mask option, system reset, oscillation HALT (STOP) mode, KI/O (I/O0, I/O1) input mode, least KI/O (I/O0, I/O1) pins discharge mode). When reset function (OFF) When Reset function (ON) Caution source matrix, sure switch mask option.
µPD6125A, 6126A
Figure 16-1. Hang-up Detection KI/O Organization
I/O0 output signal I/O1 output signal I/O2 output signal I/O3 output signal I/O4 output signal I/O5 output signal I/O6 output signal I/O7 output signal Hang-up detection KI/O switch (Mask option) RESET circuit
KI/O input/output selection
Remark
above also applicable I/O0 ALL, I/O1 ALL.
HALT releasing condition specification (S-IN, KI/O, I/O0, I/O1) condition specified mask option unused satisfied HALT mode, system reset. When Used When Unused Caution sure specify HALT mode unused releasing condition unused (set).
µPD6125A, 6126A
PROGRAM DEVELOPMENT TOOLS
develop programs µPD6125A, 6126A, assembler emulator µPD612X series available from I.C. Corp. details, contact Corp.
ORDERING CODE
generate data required ordering mask ROM, after assembling program, convert file file using PROM utility program "UPDPROM". Caution When using "UPDPROM" select "27256" PROM TYPE.
Confirm that instruction code data stored addresses through 7D3H PROM. Also confirm that mask option code data stored following addresses.
µPD6125A: Addresses 7FF0H through 7FF3H µPD6126A: Addresses 7FF0H through 7FF4H
µPD6125A, 6126A
INSTRUCTION
Accumulator Manipulation Instructions
#data #data #data
Input/Output Instructions
#data
operate pair format Data Transfer Instructions
#data
#data
operate pair format
µPD6125A, 6126A
Branch Instructions
JMP0 JMP0 addr Note addr Note addr Note addr Note addr
Note
Pair register
Note
r=1-F cannot used.
Subroutine Instructions
CALL0 addr
Timer/Counter Manipulation Instructions
#data T0-1
Other Instructions
HALT #data STTS STTS #data SCAF
µPD6125A, 6126A
TYPICAL APPLICATION CIRCUIT EXAMPLE
µPD6125A application circuit example
SE303A-C SE307-C SE313 SE1003-C carrier) 2SC2001, 3616 2SD1513, 1614 2SD1616 (with carrier)
I/O03 I/O02 I/O01 I/O00 S-IN
KI/O0 KI/O1 KI/O2 KI/O3 KI/O4 KI/O5 KI/O6
Mode selection matrix keys) switch
S-OUT PD6125A
KI/O7
OSC-OUT OSC-IN
Caution
ceramic resonator start-up capacitor value must determined, taking voltage level oscillation start-up characteristics ceramic resonator into consideration.
µPD6125A, 6126A
µPD6126A application circuit example
SE303A-C SE307-C SE313 SE1003-C 2SC2001, 3616 2SD1513, 1614 2SD1616 (with carrier)
I/O11 I/O10 I/O03 I/O02 I/O01 I/O00
I/O12 I/O13
KI/O0 KI/O1 KI/O2 KI/O3
carrier)
S-IN
KI/O4 KI/O5
PD6126A KI/O6
KI/O7 S-OUT Mode selection switch
matrix keys)
OSC-OUT
OSC-IN
Caution
ceramic resonator start-up capacitor value must determined, taking voltage level oscillation start-up characteristics ceramic resonator into consideration.
µPD6125A, 6126A
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Operating ambient temperature Storage temperature Symbol Tstg Ratings -0.3 +7.0 -0.3 VDD+0.3 +125 Unit
Caution
rated value even above parameters exceeded even momentarily, quality product degraded. Absolute maximum ratings therefore specify values exceeding which product physically damaged. Never exceed these values when using product.
Recommended Operating Range
Parameter Supply voltage Oscillation frequency Symbol fOSC MIN. TYP. MAX. Unit
µPD6125A, 6126A
Characteristics (VDD 3.0V, fOSC 455kHz,
Parameter Supply voltage Current dissipation Current dissipation high level output current level output current S-OUT high level output current S-OUT level output current high level input current high level input current level input current KI/O, high level input current KI/O, high level input current KI/O, level input current KI/O, high level output current KI/O, level output current high level input voltage level input voltage KI/O high level input voltage KI/O level input voltage pull-up resistor pull-down resistor high level input voltage level input voltage Symbol IDD1 IDD2 IOH1 IOL1 IOH2 IOL2 IIH1 IIH1' IIL1 IIH2 IIH2' IIL2 IOH3 IOL3 VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 fOSC fOSC= STOP without pull-down resistor without pull-down resistor -1.5 -2.0 -0.3 -1.0 -0.2 -0.2 -4.0 1500 -2.0 Conditions MIN. TYP. MAX. Unit
Recommended Ceramic Resonator
External Capacitance (pF) Manufacturer Product CSB375P CSB400P Murata Mfg. Co., Ltd. CSB455E CSB480E CSB500E CRK400 Toko Ceramic Co., Ltd. CRK455 CRK500 Oscillation Voltage Range MIN. MAX. Remarks
µPD6125A, 6126A
CHARACTERISTICS CURVE (Target Value)
characteristic examples (REM) High-level output current [mA] Low-level output current [mA] -10.0 characteristic examples (REM)
-5.0
Low-level output voltage
High-level output voltage
Low-level output current [mA]
characteristic examples (S-OUT) High-level output current [mA] -3.0
characteristic examples (S-OUT)
-2.0
-1.0
low-level output voltage
High-level output voltage
characteristic examples I/O0 I/O3 I/O) Low-level output current Low-level output current
characteristic examples I/O0 I/O7
Low-level output voltage
Low-level output voltage
µPD6125A, 6126A
characteristic examples I/O, I/O) High-level output current [mA]
-4.0 -3.0
-2.0
-1.0
High-level output voltage
µPD6125A, 6126A
PACKAGE DRAWINGS
µPD6125A package drawings (1/2) 16-Pin Plastic (300 mil) (units
PLASTIC SHRINK (300 mil)
fig. blank
NOTE Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 23.12 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 0.85 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 7.62 (T.P.) 0.25 +0.10 -0.05 0.17 0~15°
INCHES 0.911 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.033 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.300 (T.P.) 0.256 0.010 +0.004 -0.003 0.007 0~15° S24C-70-300B-1
µPD6125A, 6126A
PLASTIC (300 mil)
detail lead
NOTE Each lead centerline located within 0.12 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 15.54 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.1±0.1 MAX. 1.55 7.7±0.3 0.20 +0.10 -0.05 0.6±0.2 0.12 0.10
INCHES 0.612 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.004±0.004 0.071 MAX. 0.061 0.303±0.012 0.220 0.043 0.008 +0.004 -0.002 0.024 +0.008 -0.009 0.005 0.004 P24GM-50-300B-4
µPD6125A, 6126A
µPD6125A package drawings (2/2) 24-PIN SHRINK (REFERENCE) (Unit fig. blank
µPD6125A, 6126A
24-PIN CERAMIC MINI FLAT PACKAGE (REFERENCE) (Unit
µPD6125A, 6126A
µPD6126A package drawings (1/2) 20-Pin Plastic (300 mil) (units
PLASTIC (375 mil)
fig. blank
detail lead
NOTE
ITEM
MILLIMETERS 18.07 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.1±0.1 MAX. 2.50 10.3±0.3 0.15 +0.10 -0.05 0.8±0.2 0.12 0.15
INCHES 0.712 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.004±0.004 0.115 MAX. 0.098 0.406 +0.012 -0.013 0.283 0.063 0.006 +0.004 -0.002 0.031 +0.009 -0.008 0.005 0.006 P28GM-50-375B-3
Each lead centerline located within 0.12 (0.005 inch) true position (T.P.) maximum material condition.
µPD6125A, 6126A
µPD6126A package drawings (2/2) 28-PIN CERAMIC (REFERENCE) (Unit fig. blank
µPD6125A, 6126A
RECOMMENDED SOLDERING CONDITIONS
recommended that µPD6125A 6126A soldered under following conditions. details recommended soldering conditions, refer Information Document Semiconductor Device Mounting Technology Manual (C10535E). other soldering methods conditions, consult NEC. Table 24-1. Surface-Mount Type Soldering Conditions µPD6125AG-XXX: 24-pin plastic (300 mil)
Symbol Recommended Condition IR30-00-1
Soldering Method
Soldering Conditions Package peak temperature: time: seconds max. (210 min.), number times: Package peak temperature: time: seconds max. (200 min.), number times: temperature: max., time: seconds max. (per device side)
Infrared reflow
VP15-00-1
Partial heating
µPD6126AG-XXX: 28-pin plastic (375 mil)
Symbol Recommended Condition IR30-00-1
Soldering Method
Soldering Conditions Package peak temperature: time: seconds max. (210 min.), number times: Package peak temperature: time: seconds max. (200 min.), number times: Solder bath temperature: max., time: seconds max., number times: Pre-heating temperature: max. (package surface temperature) temperature: max., time: seconds max. (per device side)
Infrared reflow
VP15-00-1
Wave soldering
WS60-00-1
Partial heating
Caution
more than soldering method should avoided (except case partial heating). Table 24-2. Insertion Type Soldering Conditions
µPD6125ACA-XXX: 24-pin plastic shrink (300 mil)
Soldering Method Wave soldering (Only pin) Partial heating Soldering Conditions Solder bath temperature: max., time: seconds max. temperature: max., time: seconds max. (per pin)
Caution
Wave soldering only pins order that solder contact with chip directly.
µPD6125A, 6126A
APPENDIX µPD612X SERIES PRODUCTS
Part Number Item capacity
µPD6124A
1002 bits (Mask ROM) bits pins (KI/O0-7)
µPD6600A
bits (Mask ROM)
µPD61P24
1002 bits (One-time PROM)
µPD6125A
1002 bits (Mask ROM)
µPD6126A
capacity pins
pins (KI/O0-7, I/O00-03)
pins (KI/O0-7, I/O00-03, I/O10-13)
S-IN pins Current consumption (fOSC STOP) (MAX.) S-IN high level input current (MAX.) Transmit carrier frequency Low-voltage detector (reset) circuit Mask option
Provided
fOSC/12, fOSC/8 Provided provided
Provided
provided (Fixed)
Provided
Supply voltage Package
24-pin plastic (300 mil) 24-pin plastic shrink (300 mil) 28-pin plastic (375 mil)
20-pin plastic (300 mil) 20-pin plastic shrink (300 mil)
µPD6125A, 6126A
[MEMO]
µPD6125A, 6126A
[MEMO]
µPD6125A, 6126A
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD6125A, 6126A
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD6125A, 6126A
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative. application circuits their parameters reference only intended actual design-ins.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

4-BIT SINGLE CHIP MICROCONTROLLER REMOTE CONTROL TRANSMISSION INT

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