DUAL 13X16 MATRIX HEAD DRIVER DRIVES 13X16 MATRIX HEADS HEAD TEMP
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L6452
DUAL 13X16 MATRIX HEAD DRIVER
DRIVES 13X16 MATRIX HEADS HEAD TEMPERATURE SENSING POWER SYSTEM ELECTRICAL NOZZLE CHECK PROTECTED OUTPUTS DESCRIPTION L6452 device designed drive 13x16 matrix printheads printer applications. output stage able source simultaneously each power lines (columns) with duty cycle normal printing head pre-heating. address lines (rows), load only capacitive (MOS driving capability). driver control printheads, only active time. address scanning counter included disabled allow different scanning scheme. Figure Block Diagram
PQFP100
order avoid output activation during supply transient, internal power-up system implemented. supporting function, L6452 capable sensing head silicon temperature electrically check each nozzle. device also integrating thermal protection.
POWER LOGICAL SUPPLIES PRINT HEAD DRIVER
POWER LINES
CONTROL LINES
ADDRESS LINES CHANNEL
PRINT HEAD
ADDRESS LINES CHANNEL
PRINT HEAD
PRINT HEAD TEMPERATURE CONTROL LINES
PRINT HEAD TEMPERATURE CONTROL
ANALOG INPUTS
D97IN523
March 1999
1/16
L6452
CONNECTION (Top view)
STEPUP_GND STEPUP_BO _ONENABLE VSTEP-UP CRCLOCK
CRDATA
CS_GND
RESCS1
CLKCS0
_ENCH
CRLATCH OUTPUT15 POWGND OUTPUT14 OUTPUT13 OUTPUT12 OUTPUT11 OUTPUT10 OUTPUT9 OUTPUT8 POWGND OUTPUT7 OUTPUT6 OUTPUT5 OUTPUT4 OUTPUT3 OUTPUT2 OUTPUT1 POWGND OUTPUT0 LATCH_CLEAR NCEN
D97IN489B
CHSEL
UPC52
REXT
ENLC HSA1 HSA2 HSA3 HSA4 HSA5 HSA6 HSA7 HSA8 HSA9 HSA10 HSA11 HSA12 HSA13 HSB13 HSB12 HSB11 HSB10 HSB9 HSB8 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1
LATCH_DATA
LONG_PULSE
ADCGND
_RESET
CONV_START
ANALOGND
CH0_BUF
ADDATA
NCOUT
SHORT_PULSE
FUNCTIONS
2/16 Name CRlatch Output 15.0 Function rising edge latches information present into control register High side DMOS outputs. active, Short Pulse and/or Long Pulse Nozzle Check Enable must have level
Outputs Power Supply
Latch Clear
logic power ground high level resets latch
ADCK
VREF
L6452
FUNCTIONS (continued)
Name NCEn Function high level enables internal current sources disables DMOS outputs. active, internal current sources must have their corrsponding latch Long Pulse must level. level enables internal HSA/B short circuit detection rising edge latches stored shift register latch Serial data input shift register data presented Serial Data Input stored into register rising edge this level activates outputs having their coresponding latch (this internal pull-up resistor) level activates outputs having their coresponding latch reset (this internal pull-up resistor) level disables functions clears registers high level enables start conversion clock signal; ADDATA signal valid falling edge this Nozzle Check Enable high this output provides high level when open load detected output. Nozzle Check Enable this output provides high level when short circuit detected HSA/B output Analog output signal (CH0 buffered) serial data output Analog ground connection Ground internal Power supply Reference voltage generator input signals Head selector address output channel Head Select Power Supply Head selector address output channel high level enables counter internal decoder will activate outputs according counter's outputs. Signal becomes Clock Counter becomes Reset Counter level enables channel high level enables channel Decoder input signals when Enable Counter high level enables internal counter counting. level enables down counting level resets internal counter level enables selected channel (this input internal pull resistor) high level clocks internal counter Ground step block Boost voltage Driving voltage power DMOS stage logic supply external resistor connected versus ground fixes internal current source value Current source outputs RxA, voltage after optional external filter level enables current source generator according _A/B ON/_OFF control register Data CRdata stored into register rising edge this Control register serial data input 3/16
Latch Data Long Pulse Short Pulse _Reset ConvStart ADCK NCOut
CH0_buf ADDATA AnalogGND ADCGND Vref CH5.CH1 HSB1.HSB13 HSA13.HSA1 EnlC
ChSel UpC/ ResC/S1 _EnCh ClkC/S0 Step Step boost Vstep Rext RxB, VxA, _ONenable CRclock CRdata
L6452
Figure Block Diagram: Nozzle activation part.
LONG PULSE SHORT PULSE OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT SERIAL INPUT PARALLEL OUTPUT OUTPUT LATCH POWER OUTPUT STAGES OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT SERIAL DATA INPUT SERIAL DATA CLOCK LATCH CLEAR LATCH DATA NOZZLE CHECK ENABLE NOZZLE CHECK OUTPUT
DRIVERS CHANNEL UP/DOWN COUNTER LINES DECODER
SELECTOR
ENABLE INTERNAL COUNTER COUNTING/SEL *RESET COUNTER/SEL CLOCK COUNTER/SEL
DRIVERS CHANNEL
*SELECT CHANNEL *ENABLE CHANNEL
D97IN524
4/16
L6452
Figure Block Diagram: Power Line Output Stage.
POWER SUPPLY 10mA
DATA
OUTPUT
DATA FROM DATA LATCH
OUTPUT
DATA
*LONG PULSE SHORT PULSE TRIGGER NOZZLE CHECK ENABLE
D97IN525
OUTPUT
NOZZLE CHECK OUTPUT
5/16
L6452
ABSOLUTE MAXIMUM RATINGS
Symbol Vstep_up Iout Tamb Tstg Parameter Power line supply voltage Address line supply voltage Analog supply voltage Logic supply voltage Driving voltage power DMOS stage Logic input voltage range Output continuous current Junction temperature Operating temperature range Storage temperature range Value -0.3 Vdd+0.3 Unit
ELECTRICAL CHARACTERISTICS 25°C)
Symbol Vref Irefext Icss Icss/Icss Vampout Vstep-up Parameter Power Line Supply voltage Address line supply voltage Analog supply voltage Logic supply voltage sleep supply current sleep supply current sleep supply current supply current supply current supply current supply current Reference Voltage Reference current (external) Programmed constant current Constant current regulation Output voltage integrated amplifier Operating input voltage pins Amp. Voltage gain Amp.A2 Voltage gain Driving Voltage power DMOS Test Condition ONenable Reset Min. 10.5 10.5 10.5 Typ. 11.5 11.5 11.5 Max. 12.5 12.5 12.5 5.15 13.5 Unit
IRext sleep normal condition Tamb 55°C Iccs Vref Tamb 55°C
4.85
0.33
2Rext
=11V
Vref g1=1.2 g2=3 1.188 2.95 3.02
Va-1 1.212 3.10
three supply voltage independent inside specified value; value Power line could decreased (under evaluation); Vstep
CONVERTER input voltage
exch
input current
Selected Channel: CH1toCH5 Selected Ch=CH0 Input Channel selected Vref Vref step N>=4
Vref Vref
OFFSET VOLTAGE GENERATION Voffset Offset Voltage Voltage increment (1LSB) Vstep Voffset/Vref Kdac
2.5+ e***
7.34
6/16
L6452
ELECTRICAL CHARACTERISTICS 25°C)
Symbol Parameter CONVERTER TIMINGS Conv. start time Tcscks Conv. Start hold time csckh Falling edge clock data Tckou valid delay ConvStart falling edge output Tcsz Hi-Z delay Clock frequency Fadck Conv. Start level time Tcslow Theoretical acquisition time Tacq Real acquisition time Tacq DIGITAL INTERFACE INPUT Schmitt Trigger positive-going Threshold Schmitt Trigger negative-going Vinm Threshold Scmitt Trigger Hysteresis Vhys Input Current (Vin=0; Vdd=5)* Test Condition Min. Cload 20pF fadck fadck 32.4 2/3Vdd 1/3Vdd Typ. Max. Unit
This applies input pins having internal pull-up (ENABLE_CHANNEL, LONG_PULSE, SHORT_PULSE)
Selected channel: CH1.CH5 control register (driving signals CRdata, CRclock) accessed with same timing specifications data shift register (signals Serial data, Serial clock) SHIFT REGISTER LATCH TIMING time Hold time Serial clock time Serial clock high time Serial clock period Latch time Latch data high time Long Pulse set_up time with Tset respect NCEn Long Pulse hold time with Thold respect NCEn OUTPUTS ELECTRICAL CHARACTERISTICS Iout Output Current (outputs 0.15) DC=33%; preheating DC=66% Resistance 25°C (ON) Turn Time (Tdelay Trise) From Long Pulse power output rising edge Load parallel with 1.5nF Toff Toff delay time From Long Pulse power output falling edge Load parallel with 1.5nF
LATCH TIMINGS Latch time Latch high time Tlhigh Latch data valid input Tlconv valid delay
7/16
L6452
ELECTRICAL CHARACTERISTICS 25°C)
Symbol Parameter HEAD ADDRESS SELECTOR OUTPUT Counting, Reset Counter, Select Channel, Clock Counter Enable Internal Counter set-up time with respect Enable channel Counting, Reset Counter, Select Channel, Clock Counter Enable Internal Counter hold time with respect Enable channel Counting with respect Clock Counter hold time counting with respect Clock Counter set_up time Enable input active output delay time Clock active output delay time Disable input inactive output delay time Counter Clock Frequency fclk-counter Clock duty cycle ClKdc Turn on/off time Ton/off Test Condition Min. Typ. Max. Unit
From Clock counter selector signal address output variation Load: fig.
COUNTER TRUTH TABLE Enable internal counter Counting Reset Counter
Clock Counter
8/16
L6452
COUNTER TRUTH TABLE (continued) Enable internal counter Counting Reset Counter
Clock Counter
DECODER TRUTH TABLE
OUTPUTS (HS) ACTIVE inactive inactive inactive
This table valid both Channel Channel when Enable Channel level.
9/16
L6452
PRINT HEAD TEMPERATURE CONTROL PART Introduction quality printing, necessary know control temperature printhead. Thus, latter built aluminium resistor, whose value changes slightly with temperature. temperature determination done injecting constant current resistor, measuring voltage drop across Since high printers have heads, must also possible switch quikly measurement process from other. function foreseen integrated into head driver, described hereafter. Print Head Block Diagram (fig. first have constant current source, which disabled external (ONenable) control register, described later. value current programmed external resistor, given ICCS Vref Rext
This current injected either into aluminium resistor head (Ralu. (Ralu. depending switch SW3. alu. resistors grounded, voltage their side Figure Print Head Block Diagram
(Vx) re-entered pins Vxb. Using separate pins from permits more flexible, filter eventually added shown drawing. voltage amplified then converted digital value. compatible with input range converter, necessary subtract offset voltage Voffset from Moreover, initial value alu. resistor very unprecise. Voffset must adjustable; this done means converter, giving different values. Finally, voltage input converter VCH0 VOFFSET VCH0 Ralu ICCS VOFFS VOFFSET VREF/2 VREF/32 reference voltage generator (VREF) integrated, used current source both converters. this way, system performance independent from precision VREF; this should, however, stable. Vref also available #45, used consumption purposes. (The external sinked current current) system under control register, accessed serially transparent latch, which used trying latch signal latch VCC).
VREF VOLT VREF VREF CONV START ADCK ADDATA VOFFSET VREF CH0_BUF INPUTS
REXT
HIGH-SIDE CONSTANT CURRENT SOURCE
VREF/2
ONENABLE
LATCH
CRLATCH CONTROL REGISTER CRCLOCK CRDATA
SHIFT REG. ON/OFF
RXA,
VXA,
ANALOG
RALU
RALU Note; analog ground separated from digital ground remaining part driver
D97IN533B
10/16
L6452
Figure Control Register details.
SHIFT DIRECTION
ON/OFF
SELECTION RESISTOR (A/B (A/B TEMPERATURE MEASUREMENT
INPUTS OFFSET COMPENSATION POSITIVE LOGIC
CHANNEL SELECTION INPUT
D97IN534A
INTERNAL CHANNEL MEASUREMENT) FIVE UNCOMMITTED, GENRAL-PURPOSE EXTERNAL CHANNELS
SWITCHES CURRENT SOURCE OFF; LINKED WITH ONENABLE INPUT
SELECTED CHANNEL
(INTERNAL) (EXTERNAL) (EXTERNAL) (EXTERNAL) (EXTERNAL) (EXTERNAL)
ON/OFF
ONENABLE
ACTION
Figure Latch Timings
CRDATA
CRCLOCK
tlhigh
CRLATCH
tlconv
CONVSTART
D97IN535
Figure Converter Timings
CONVSTART
ADCK
ADDATA
HIGH IMPEDANCE
cscks tcsckh
ckout
HIGH IMPEDANCE
D97IN536
tcsx
11/16
L6452
Figure Power Output Timing
LONG PULSE SHORT PULSE
POWER OUTPUT
D97IN526
Figure Trigger Nozzle Check Signal
VPOWER FROM COMMON CONNECTION ANALOG MULTIPLEXERS
VLOGIC NOZZLE CHECK OUTPUT
INTERNAL REFERENCE NCEM
HSA/B SHORT CIRCUIT DETECTION
D97IN527
12/16
L6452
Figure Address Output Timing
OUTPUT 250pF
CLOCK SIGNAL COUNTER SELECTOR SIGNAL
ADDRESS OUTPUT MEASURED POINT
D97IN528A
Figure Mode Counter
COUNTING
RESET COUNTER
SELECT CHANNEL
ENABLE INTERNAL COUNTER
CLOCK COUNTER
ENABLE CHANNEL
OUTPUT HSB)
D97IN529A
13/16
L6452
Figure Mode
SELECT CHANNEL
ENABLE INTERNAL COUNTER
ENABLE CHANNEL
OUTPUT HSB)
D97IN530
Figure Sequence Shift Register Data Loading
SERIAL DATA
SERIAL CLOCK LATCH DATA LONG PULSE SHORT PULSE OUTPUT OUTPUT CORRESPONDING DATA CORRESPONDING DATA RESET
D97IN531
Figure Latch Timing
SERIAL DATA
SERIAL CLOCK
LATCH DATA
D97IN532
14/16
L6452
DIM. MIN. 0.65 16.95 13.90 0.25 2.55 0.22 0.13 22.95 19.90
TYP. MAX. 3.40 0.010 2.80 3.05 0.38 0.23 23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60 0°(min.), 7°(max.) 0.95 0.026 17.45 14.10 0.667 0.547 23.45 20.10 0.100 0.0087 0.005 0.903 0.783 MIN.
inch TYP. MAX. 0.134
OUTLINE MECHANICAL DATA
0.110
0.120 0.015 0.009
0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063
0.923 0.791
0.687 0.555
0.037
PQFP100
15/16
L6452
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specification mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics 1999 STMicroelectronics Printed Italy Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A. http://www.st.com
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