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Edition March 2001 6251-563-1PD 5650/X Revision History: Previous


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5650/X VPS/PDC-Plus Decoder
Edition March 2001 6251-563-1PD
5650/X Revision History: Previous Version: Page Page previous current Version) Version)
Current Version: 02.97
Subjects (major changes since last revision)
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5650/X
Preliminary Data Sheet
Table Contents 2.2.1 2.2.2 2.2.3 2.2.4
Page
General Description Features Configurations Description
System Description Functions General Information Chip Address Write Mode Read Mode Order Data Output Allocation PDC/VPS Operating Modes Order Data Output Allocation Header Time Mode (MAB Description DAVN Outputs Electrical Characteristics PDC/VPS-Receiver Appendix Control Register Write (I2C-Bus Write) Data Register Read (I2C-Bus Read) DAVN Timing Position Teletext Data Lines within Vertical Blanking Interval Definition Voltage Levels Data Line BDSP 8/30 Format Allocation Structure Teletext Data Packet 8/30 Format BDSP 8/30 Format Allocation Data Format Programme Delivery Data Dedicated Line (VPS)
Package Outlines
Purchase Micronas components conveys license under Philips patent components system provided system conforms specifications defined Philips.
Micronas
5650/X
Preliminary Data Sheet
CMOS General Description
plus 5650 decoder chip receives 8/30 Format data together with teletext header information easy identification broadcast transmitter. 5650 includes storage capacity bytes which used different ways depending selected modes. P-DIP-14-1 Features Single chip receiver data Broadcast Data Service Packet (BDSP 8/30/2) according CCIR teletext system Data dedicated line vertical blanking interval (VBI) Reception BDSP packet 8/30/1 P-DSO-20-1 Unified Date Time (UDT) Network indentification code (NIC) Short program label (SPL) Reception teletext header Bytes containing date, clock time identification chip data slicer external component count I2C-Bus interface Communication with external microcontroller PDC/VPS operation mode selectable I2C-Bus register software compatible PDC/VPS decoder 5649 supply voltage Video input signal level: Technology: CMOS P-DIP-14-1 P-DSO-20-1 package Type 5650 5650X
Micronas
Ordering Code Q67100-H5164 Q67106-H5163
Package P-DIP-14-1 P-DSO-20-1 (SMD)
5650/X
Preliminary Data Sheet
Configurations
P-DIP-14-1
P-DSO-20-1
Figure
Micronas
5650/X
Preliminary Data Sheet
Description Symbol Function
P-DIP-14-1 P-DSO-20-1
VSSA VSSD
Ground Analog ground Digital ground connected Serial clock input Bus. Serial data input Bus. Chip select input determining I2C-Bus addresses: 21H, when pulled 23H, when pulled high. Video Composite Sync output from sync slicer used based clock generation. Data available output active low, when data received. Output signaling presence first field active high. Test input; activates test mode when pulled high. Connect ground operating mode. Phase detector/charge pump output data (DAPLL). Connector loop filter SYSPLL. Input voltage controlled oscillator DAPLL. Reference current input on-chip analog circuit. Composite video signal input. Positive supply voltage nom.). Positive supply voltage digital circuits nom.). Positive supply voltage analog circuits nom.).
N.C.
DAVN PD2/ VCO2 VCO1
IREF
CVBS
VDDD VDDA
Micronas
5650/X
Preliminary Data Sheet
Block Diagram
Figure
Micronas
5650/X
Preliminary Data Sheet
System Description Functions
Referring functional block diagram decoder, composite video signal with negative going sync pulses coupled CVBS through capacitor which used clamping bottom sync pulses internally fixed level. signal passed slicer, analogue circuitry separating sync data parts CVBS signal, thus yielding digital composite sync signal digital data signal further processing comparing those signals internally generated slicing levels. output sync separator forwarded, hand, output VCS, other hand, clock generator timing block. signal represents signal that used deriving system clock signal means other timing signal. data slicer separates data signal from CVBS signal comparing video voltage internally generated slicing level which found averaging data signal during line mode averaging data signal during clock run-in period teletext lines during data entry window (DEW) mode. clock generator delivers system clock needed basic timing well regeneraton dataclock. based phase locked loops (PLL's) parts which integrated chip with exception loop filter components. Each PLL's composed voltage controlled relaxation oscillator (VCO), phase/ frequency detector (PFD), charge pump which converts digital output signals analogue current. That current transformed control voltage off-chip loop filter. generated frequencies 13.875 mode mode, respectively. signals necessary control sync data slicing well data acquisition generated Timing block. 5650 operated three different modes: Depending selected operating mode, either teletext lines carrying 8/30 packages, dedicated line (VPS) teletext header bytes 38-45, 30-37, 22-29 14-21 acquired. mode, only teletext rows 8/30 containing Broadcast Data Service Package (BDSP) information acquired. relevant bytes 8/30 format (8/30/1) 8/30 format (8/30/2) extracted. 8/30/1-bytes stored acquisition register transparent without manipulation, whereas Hamming coded bytes packet 8/30/2 Hamming-checked bytes with error corrected. storage error free corrected 8/30/2-data bytes transfer register signalled DAVN output going low.
Micronas
5650/X
Preliminary Data Sheet
mode, extracted data bits line checked biphase errors. With biphase errors encountered, acquired bytes stored transfer register Bus. That transfer signalled transition DAVN output, well. header mode bytes 38-45 30-37 accessed this order. This assures software compatibility 5649. mode bytes 22-29 14-21 accessed this order. three operating modes data updated when data line been received, provided that chip accessed same time. micro controller read stored bytes I2C-Bus interface time. However, must aware that storage data from acquisition interface inhibited long decoder being accessed Bus. Note: order achieve maximum system performance recommended start 5650 mode (state after power read register check whether line received. After reception data inline 5650 switched 8/30 mode waiting packet 8/30 data. Since data line transmitted every frame data packet 8/30 transmitted nearly every second recognition both 8/30 packets done within PDC-system constraints (about sec). 2.2.1 General Information
I2C-Bus interface implemented decoder slave transmitter/receiver, both reading from writing decoder possible. clock line controlled only master usually being micro controller, whereas line controlled either master slave. data transfer only initiated master when free, both lines high state. general rule Bus, line changes state only when line low. only exception that rule Start Condition Stop Condition. Further Details given below. following abbreviations used: START: NAM: STOP: Start Condition generated master Acknowledge slave Acknowledge master Acknowledge master Stop condition generated master
Micronas
5650/X
Preliminary Data Sheet
2.2.2
Chip Address
There pairs chip addresses, which selected CS0-input according following table: Input High 2.2.3 Write Mode Write Mode (hex) (hex) Read Mode (hex) (hex)
writing decoder, following format used: Start Chipaddress Write Mode Byte Control Register Stop
Description Data Transfer (Write Mode) Step1: Step Step Step Step Step order start data transfer master generates Start Condition pulling line while line held high. master puts chip address line during next eight pulses. master releases line during ninth clock pulse. Thus slave generate acknowledge (AS) pulling line level. controller transmits data byte Control register slave acknowledges reception byte. master concludes data communication generating Stop Condition.
write mode used I2C-Bus control register which determines operating mode:
Micronas
5650/X
Preliminary Data Sheet
Control Register: Number: PDC/ FOR1/ FOR2
Default: bits power-up. Bits through used test purposes must changed normal operation user software! determines, which kind data accessed when mode active: Value BDSP data accessible BDSP header data accessible (refer description
determines operating mode: Value
mode active
mode active determines whether BDSP 8/30/1-data header data accessible: Value
BDSP 8/30/1 data accessible
Bytes teletext header mode (see
determines mode teletext header access: Value
Mode header bytes order 38-45, 30-37
Mode header bytes order 22-29, 14-21
Micronas
5650/X
Preliminary Data Sheet
2.2.4
Read Mode
reading from decoder, following format used Start Chipaddress Read Mode Byte Last Byte Stop
contents registers (bytes) read starting with byte (refer table Order Data Output and.) depending selected operating mode. Description Data Transfer (Read Mode) Step1: start data transfer master generates Start Condition pulling line while line held high. byte address counter decoder reset points first byte output. master puts chip address line during next eight pulses. master releases line during ninth clock pulse. Thus slave generate acknowledge (AS) pulling line level. this moment, slave switches transmitting mode. During next eight clock pulses slave puts addressed data byte onto line. reception byte acknowledged master device which, turn, pulls down line during next clock pulse. acknowledging byte, master prompts slave increment internal address counter provide output next data byte. Steps repeated, until desired amount bytes have been read. last byte output slave since will acknowledged master. conclude read operation, master doesn't acknowledge last byte received. Acknowledge master (NAM) causes slave switch from transmitting receiving mode. Note that master prematurely cease reading operation acknowledging byte. master gains control over line concludes data transfer generating Stop Condition bus, producing low/high transition line while line high state. With lines being both high state, free ready another data transfer started.
Step Step
Step Step
Step Step Step
Step
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation PDC/VPS Operating Modes Format Byte byte Packet 8/30 Format byte byte Mode
byte
Byte
byte
byte
byte
byte
Byte
byte
byte
byte
byte
Byte
byte
byte
byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation PDC/VPS Operating Modes (cont'd) Format Byte byte Packet 8/30 Format byte byte Mode
byte
Byte
byte
byte
byte
byte
Byte
byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation PDC/VPS Operating Modes (cont'd) Format Byte byte Packet 8/30 Format Mode
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation PDC/VPS Operating Modes (cont'd) Format Byte bit7 byte Packet 8/30 Format Mode
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation Header Time Mode (MAB Header Time Mode byte
Byte
Byte
byte
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation Header Time Mode (MAB (cont'd) Header Time Mode byte
Byte
Byte
byte
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation Header Time Mode (MAB (cont'd) Header Time Mode byte
Byte
Byte
byte
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation Header Time Mode (MAB (cont'd) Header Time Mode byte
Byte
Byte
byte
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation Header Time Mode (MAB (cont'd) Header Time Mode byte
Byte
Byte
byte
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation Header Time Mode (MAB (cont'd) Header Time Mode byte
Byte
Byte
byte
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation Header Time Mode (MAB (cont'd) Header Time Mode byte
Byte
Byte
byte
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
Order Data Output Allocation Header Time Mode (MAB (cont'd) Header Time Mode byte
Byte
Byte
byte
Byte
byte
Byte
byte
Message numbers according specification system. Transmission number.
Micronas
5650/X
Preliminary Data Sheet
DAVN
Description DAVN Outputs (Data Valid active low) (First Field active high)
Signal Output
Mode 8/30/2 Mode
Mode 8/30/1 Mode Header Time
DAVN H/L-transition (set low) line when line valid data carrying received valid 8/30/2 data start line line carrying valid 8/30/1 data line carrying valid header data
L/H-transition (set high) always high
beginning next field i.e., start next data entry window
power-up during I2C-Bus accesses when master doesn't acknowledge order generate stop condition
L/H-transition H/L-transition beginning first field beginning second field
test mode (i.e. high), both DAVN controlled reproduce state input.
Micronas
5650/X
Preliminary Data Sheet
Electrical Characteristics
Absolute Maximum Ratings Parameter Ambient temperature Storage temperature Total power dissipation Power dissipation output Input voltage Supply voltage Thermal resistance Symbol min. Limit Values typ. max. Unit Test Condition operation storage
Tstg Ptot
Note: Maximum ratings absolute ratings; exceeding these values cause irreversible damage integrated circuit. Operating Range Supply voltage Supply current Ambient temperature range
Note: operating range functions given circuit description fulfilled.
Micronas
5650/X
Preliminary Data Sheet
Electrical Characteristics Parameter Symbol min. Input Signals SDA, SCL, H-input voltage L-input voltage Input capacitance Input current Input Signal H-input voltage L-input voltage Input capacitance Input current Limit Values typ. max. Unit Test Condition
Input Signals CVBS (pos. Video, neg. Sync) Video input signal level Synchron signal amplitude Data amplitude Coupling capacitor
VCVBS
with VSYNC VDAT only related signal generation
VSYNC
0.15
(1.0)
VDAT
0.25 VSYNC
H-input current L-input current Source impedance Leakage resistance
coupling capacitor
1000 0.91
Micronas
5650/X
Preliminary Data Sheet
Electrical Characteristics (cont'd) Parameter Symbol min. Output Signals DAVN, EHB, H-output voltage L-output voltage Limit Values typ. max. Unit Test Condition
Output Signals (Open-Drain-Stage) L-output voltage Permissible output voltage
PLL-Loop Filter Components (see application circuit) Resistance PD2/ VCO2 Attenuation resistance Resistance PD2/ VCO2
1200 1200
Resistance VCO1
Integration capacitor Integration capacitor Frequence Range Adjustment Resistance IREF (for bias current adjustment)
Note: listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage.
Micronas
5650/X
Preliminary Data Sheet
Stop Start HIGH Stop
UET00130
Figure I2C-Bus Timing Parameter Clock frequency Inactive time prior transmission start-up Hold time during start condition Low-period clock High-period clock Set-up time data Rise time signal Fall time signal Set-up time clock during stop condition values referred levels. Symbol Limit Values min. max. Unit
fSCL tBUF tHD; tLOW tHIGH tSU;DAT tTLH tTHL tSU;
Micronas
5650/X
Preliminary Data Sheet
PDC/VPS-Receiver
Figure
Micronas
5650/X
Preliminary Data Sheet
Appendix Control Register Write (I2C-Bus Write)
Figure Data Register Read (I2C-Bus Read)
Figure
Micronas
5650/X
Preliminary Data Sheet
DAVN Timing
Figure
Micronas
5650/X
Preliminary Data Sheet
Position Teletext Data Lines within Vertical Blanking Interval
Figure Definition Voltage Levels Data Line
Figure
Micronas
5650/X
Preliminary Data Sheet
BDSP 8/30 Format Allocation Network Identification Network Identification Weight Weight Sign Modified Julian Date (MJD) Byte Modified Julian Date Byte Modified Julian Date (MJD) Byte Universal Time Coordinated (UTC) Byte Universal Time Coordinated Byte Universal Time Coordinated Byte Short Programme Label Byte Short Programme Label Byte Short Programme Label Byte Short Programme Label Byte Time Offset Code Byte Byte Contents
Byte
Digit Weight Digit Weight Digit Weight Hours Units Minutes Units Seconds Units
Digit Weight Digit Weight Hours Tens Minutes Tens Seconds Tens
Note: This corresponds coding adopted CCIR teletext system BDSP 8/30 format received bytes output transparent way, i.e., bit-first-in-first-out basis. manipulation performed chip this operating mode. Concerning bytes through When evaluating numbers, note that each 4-bit-digit been incremented prior transmission, least significant bits transmitted first.
Micronas
5650/X
Preliminary Data Sheet
Structure Teletext Data Packet 8/30 Format
Figure
byte
BDSP 8/30 Format Allocation reserved undefined label update flag label channel identifier
four message bits byte used follows
Micronas
5650/X
Preliminary Data Sheet
BDSP 8/30 Format Allocation (cont'd)
message bits bytes 14-25 used similar coding label dedicated television line follows: byte byte byte byte byte byte hour month network programme provider) reserved undefined country status analogue sound
Micronas
5650/X
Preliminary Data Sheet
byte
BDSP 8/30 Format Allocation (cont'd) programme type network programme provider) country minute
byte
byte
byte
byte
byte
Micronas
5650/X
Preliminary Data Sheet
Data Format Programme Delivery Data Dedicated Line (VPS)
Figure
Micronas
5650/X
Preliminary Data Sheet
Figure
Micronas
5650/X
Preliminary Data Sheet
Package Outlines P-DIP-14-1 (Plastic Dual In-line Package)
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Dimensions Micronas
GPD05005
5650/X
Preliminary Data Sheet
P-DSO-20-1 (Plastic Dual Small Outline Package)
0.35
+0.09
2.65
2.45 -0.2
-0.1
-0.2
1.27 0.35 +0.15
+0.8 10.3 ±0.3
GPS05094
12.8 -0.2 Index Marking Does include plastic metal protrusions 0.15 side Does include dambar protrusion 0.05 side
GPS05094
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Surface Mounted Device Micronas
0.23
Dimensions
5650/X
Micronas GmbH Hans-Bunte-Strasse D-79108 Freiburg (Germany) P.O. D-79008 Freiburg (Germany) Tel. +49-761-517-0 +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed Germany Order 6251-563-1PD
information data contained this data sheet without commitment, considered offer conclusion contract, shall they construed create liability. issue this data sheet invalidates previous issues. Product availability delivery exclusively subject respective order confirmation form; same applies orders based development samples delivered. this publication, Micronas GmbH does assume responsibility patent infringements other rights third parties which result from use. Further, Micronas GmbH reserves right revise this publication make changes content, time, without obligation notify person entity such revisions changes. part this publication reproduced, photocopied, stored retrieval system, transmitted without express written consent Micronas GmbH.
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