Fast Throughput Rate: 1.25 MSPS KSPS Wide Analog Channel Input: AVDD E

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Fast Throughput Rate: 1.25 MSPS KSPS Wide Analog Channel Input: AVDD E

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TLV1570 8-CHANNEL 10-BIT 1.25-MSPS SERIAL ANALOG-TO-DIGITAL CONVERTER
Fast Throughput Rate: 1.25 MSPS KSPS Wide Analog Channel Input: AVDD Eight Analog Input Channels Channel Auto-Scan Differential Nonlinearity Error: Integral Nonlinearity Error: Signal-to-Noise Distortion Ratio: Single 2.7-V 5.5-V Supply Operation Very Power: Auto-Power Down: Software Power Down: Glueless Serial Interface TMS320 DSPs (Q)SPI Compatible Microcontrollers Programmable Internal Reference Voltage: 3.8-V Reference Operation, 2.3-V Reference Operation
applications
Mass Storage Hard Disk Drive Automotive Digital Servos Process Control General Purpose Image Sensor Processing
PACKAGE (TOP VIEW)
DVDD DGND SCLK SDIN
AVDD AGND SDOUT
description
TLV1570 10-bit data acquisition system that combines 8-channel input multiplexer (MUX), high-speed 10-bit ADC, on-chip reference, high-speed serial interface. device contains on-chip control register allowing control channel selection, conversion start, reference voltage levels, power down serial port. independently accessible, which allows user insert signal conditioning circuit such anti-aliasing filter amplifier, required, between ADC. Therefore signal conditioning circuit used eight channels. TLV1570 operates from single 2.7-V 5.5-V power supply. device accepts analog input range from AVDD digitizes input maximum 1.25 MSPS throughput rate. Power dissipation only with 2.7-V supply with 5.5-V supply. device features auto-power down mode that automatically powers down after conversion performed. With software power down enabled, device further powered down only TLV1570 communicates with digital microprocessors simple 5-wire serial port that interfaces directly Texas Instruments TMS320 DSPs, SPIand QSPIcompatible microcontrollers without using additional glue logic. very high throughput rate, simple serial interface, power consumption make TLV1570 ideal choice high-speed digital signal processing requiring multiple analog inputs.
AVAILABLE OPTIONS PACKAGED DEVICES 70°C 40°C 85°C SMALL OUTLINE (DW) TLV1570CDW TLV1570IDW SMALL OUTLINE (PW) TLV1570CPW TLV1570IPW
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. QSPI trademarks Motorola, Inc.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1998, Texas Instruments Incorporated
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functional block diagram
AVDD DVDD
REFERENCE
REF+
10-BIT
REF- AGND SCLK SDIN SDOUT
REGISTERS CONTROL LOGIC
AGND
DGND
Terminal Functions
TERMINAL NAME AGND AVDD DGND DVDD 5,4,3,2,1, 18,17,16 Analog ground analog input Analog supply voltage, Analog input channels Chip Select. level signal enables TLV1570. high level signal disables device disconnects power TLV1570. Digital ground Digital supply voltage, Frame sync. falling edge frame sync pulse from indicates start serial data frame shifted TLV1570. pulled high when interfaced microcontroller. On-chip analog output Reference voltage input. voltage applied defines input span TLV1570. external reference mode, decoupling capacitor must placed between reference AGND. This required internal reference mode. Serial clock input. SCLK synchronizes serial data transfer also used internal data conversion. Serial data input used configure internal control register. Serial data output. conversion results output SDOUT. DESCRIPTION
SCLK SDIN SDOUT
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detailed description
analog-to-digital converter TLV1570 uses architecture described this section. CMOS threshold detector successive-approximation conversion system determines value each examining charge series binary-weighted capacitors (see Figure first phase conversion process, analog input sampled closing switch switches simultaneously. This action charges capacitors input voltage.
Threshold Detector Output Latches Node REF+ REF+ REF+ REF+ REF+ REF+ REF+
NOTE: REF- tied AGND
Figure Simplified Model Successive-Approximation System next phase conversion process, switches opened threshold detector begins identifying bits identifying charge (voltage) each capacitor relative reference (REF-) voltage (REF- tied AGND). switching sequence, capacitors examined separately until bits identified then charge-convert sequence repeated. first step conversion phase, threshold detector looks first capacitor (weight 512). Node this capacitor switched REF+ voltage, equivalent nodes other capacitors ladder switched REF-. voltage summing node greater than trip point threshold detector (approximately one-half VCC), placed output register 512-weight capacitor switched REF-. voltage summing node less than trip point threshold detector, placed register 512-weight capacitor remains connected REF+ through remainder successive-approximation process. process repeated 256-weight capacitor, 128-weight capacitor, forth down line until bits counted. With each step successive-approximation process, initial charge redistributed among capacitors. conversion process relies charge redistribution count weigh bits from LSB. case TLV1570, REF- tied ground REF+ connected input. TLV1570 programmed on-chip internal reference (DI6=1). user select between values internal reference, using control DI5. During internal reference mode, reference voltage output pin. Therefore cannot decoupled analog ground (AGND), which acts negative reference ADC, using external capacitor. Hence this mode requires ground noise very low. left open this mode.
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sampling frequency, TLV1570 requires SCLKs each sampling conversion, therefore equivalent maximum sampling frequency achievable with given SCLK frequency fs(MAX) (1/16)fSCLK power down TLV1570 offers different power-down options. With auto power-down mode enabled, (DI4=0) proceeds power down detected 17th falling SCLK edge cycle cycle starts with being detected falling edge SCLK) mode after SCLKs mode. TLV1570 will recover from auto power down when goes high mode when next SCLK comes mode. case software power down, goes software power-down state cycle after CR.DI15 Unlike auto power down which recovers SCLK, software power down takes SCLKs recover.
DESCRIPTION Maximum power down dissipation current Comparator Clock buffer Reference Register Minimum power down time Minimum resume time Power down Power mode Microprocessor mode mode Microprocessor mode Power down Power down Active saved SCLK SCLK present SCLK after previous conversion completed SCLK stopped after previous conversion completed present SCLK present AUTO POWER DOWN SOFTWARE POWERDOWN DVDD Powerdown Powerdown Powerdown saved CR.DI15 CR.DI15 CR.DI15
CR.DI15 Only mode input buffer clock power-down mode. software power down enable/disable acted until start next cycle (see section configuring TLV1570 more information.
configuring TLV1570 TLV1570 configured writing control bits SDIN. configuration will take affect until next cycle. configuration needed each conversion. Once channel input other options selected, conversion takes place next cycle. Conversion results shifted conversion progresses Figure
Cycle SCLK tconv
Second Cycle
tconv
SDIN
Configure Data
Configure Data
SDOUT
Result
Result
Figure TLV1570 Configuration Cycle Timing
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configuration register (CR) definition
Software power down: DI15 DI14 Normal Power down enabled DESCRIPTION
Reads values internal register, read. Only DI15 read out. These bits select self-test voltage applied input during next clock cycle: Allow come normally Apply AGND Apply VREF/2
DI13, DI12
Choose speed application DI11 DI10 High speed (higher power consumption) speed (lower power consumption)
This enables channel auto-scan function. Auto-scan disabled Auto-scan enabled
These three bits select which eight DI9, These bits select channel swept channels used DI10 sequence used auto scan mode DI10 000: 001: 010: 011: 100: 101: 110: 111: Channel selected input Channel selected input Channel selected input Channel selected input Channel selected input Channel selected input Channel selected input Channel selected input Analog inputs CH0, CH1, CH2, sequentially selected Analog inputs CH1, CH3, CH5, sequentially selected Analog inputs CH0, CH2, CH4, sequentially selected Analog inputs CH7, CH6, CH5, sequentially selected
DI9, DI8,
Auto-scan reset reset Reset autoscan sequence
Selects Internal external reference voltage: External Internal Enable Disable
Selects internal reference voltage value applied during next conversion cycle.
Enables/disables auto-power down function:
Performance optimizer linearity AVDD AVDD Always write (reserved bit) Always write (reserved bit) Always write (reserved bit)
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initialization-software sequence
This sequence shows default settings, unless otherwise specified. requires that user write every cycle. There cycle delay before control bits implemented. Example Normal Sample Mode With Internal Reference
CYCLE Wait 0140h 0040h Invalid From Channel WRITE SDIN 0040h 01C0h 0040h 8040h 0040h CHANNEL SAMPLED OUPUT FROM SDOUT Invalid Invalid From Channel From Channel Invalid Software power down enabled Software power down mode, analog input channel sampled Recovery time, analog input channel sampled SCLKs AVDD fCLK MHz) Recovery time, analog input channel sampled analog input channel sampled analog input channel sampled COMMENT
Example Auto Scan Mode
CYCLE 10th 11th WRITE SDIN 0480h 0480h 0400h 0400h 0400h 0400h 0400h 0400h 0400h 0400h 0400h CHANNEL SAMPLED OUTPUT FROM SDOUT Invalid Invalid From Channel From Channel From Channel From Channel From Channel From Channel From Channel From Channel From Channel COMMENT Auto-scan reset enabled, analog input channel sampled analog input channel sampled
NOTE: software power down enabled during auto-scan mode, next channel sequence skipped.
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initialization-software sequence (continued)
Example Auto-Scan Mode This example shows change sequence middle current sequence. following shows that after initial auto-scan reset, reset necessary again when switching channel sequences.
CYCLE 10th 11th 12th WRITE SDIN 0480h 0480h 0400h 0700h 0700h 0700h 0700h 0700h 0700h 0700h 0700h 0700h CHANNEL SAMPLED OUTPUT FROM SDOUT From Channel From Channel From Channel From Channel From Channel From Channel From Channel From Channel From Channel From Channel analog input channel sampled Auto-scan reset enabled, analog input channel sampled Start sequence Enable channel sequence auto-scan reset required) Start sequence COMMENT
Example Auto-Scan Mode This example shows switch sequence course sequence. following shows that particular sequence does have continued remaining channels need sampled (i.e., only channel through channel sampled, channels
CYCLE 10th 11th WRITE SDIN 0480h 0480h 0400h 0400h 0400h 0400h 0400h 0480h 0400h 0400h 0400h CHANNEL SAMPLED OUPUT FROM SDOUT From Channel From Channel From Channel From Channel From Channel From Channel From Channel From Channel From Channel Auto-scan reset enabled Sequence reset channel analog input channel sampled Auto-scan reset enabled, analog input channel sampled COMMENT
TLV1570 800-ns 10-bit 8-analog input channel analog-to-digital converter with throughput 1.25 MSPS KSPS respectively. fastest conversion rate, must clocked 3-V. TLV1570 easily interfaced microcontrollers, ASICs, DSPs, shift registers. TLV1570 serial interface designed fully compatible with Serial Peripheral Interface (SPI) TMS320 serial ports. additional hardware required interface between TLV1570 microcontroller (µCs) with serial port TMS320 DSP. However, speed limited SCLK rate DSP.
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initialization-software sequence (continued)
TLV1570 interfaces over five lines: SCLK, SDOUT, SDIN, interfaces over four lines: SCLK, SDOUT, SDIN. input should pulled high mode. device 3-state power-down mode when high. After falls, TLV1570 checks input falling edge determine operation mode. low, mode set, otherwise mode set.
TLV1570 SCLK SDIN SDOUT TMS320 CLKX CLKR
Figure TLV1570 Interface
TLV1570 SCLK SDIN SDOUT DVDD Terminal SCLK
Figure TLV1570 Interface
grounding decoupling considerations
General practices should apply design limit high frequency transients noise that back into supply reference lines (see Figure This requires that supply reference pins sufficiently bypassed. most cases ceramic chip capacitors adequate keep impedance over wide frequency range. Since their effectiveness depends largely proximity individual supply pin. They should placed close supply pins possible. reduce high frequency noise coupling, highly recommended that digital analog ground shorted immediately outside package. This accomplished running impedance line between DGND AGND, under package.
TLV1570 DVDD DGND AGND AVDD
Figure Placement Decoupling Capacitors
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power supply ground layout
Printed circuit boards that separate analog digital ground planes offer best system performance. Wire-wrap boards perform well should used. ground planes should connected together low-impedance power-supply source. best ground connection achieved connecting AGND terminal system analog ground plane making sure that analog ground currents well managed.
simplified analog input analysis
Using equivalent circuit Figure time required charge analog input capacitance from within LSB, tch(1/2 LSB), derived follows: capacitance charging voltage given where Ri(ADC) Ri(MUX) Charge time input impedance higher 1.25 final voltage given (1/2 LSB) /2048) Equating equation equation solving cycle time gives: C(t)
1-e-tch RtCi
2048
1-e-tch RtCi
time change (minimum sampling time) (1/2 LSB) ln(2048) where ln(2048) 7.625 Therefore, with values given, time analog input signal settle (1/2 LSB) ln(2048) This time must less than converter sample time shown timing diagrams. Which SCLK. (1/2 LSB) 1/f(SCLK) Therefore maximum SCLK frequency Max(f(SCLK) (1/2 LSB) 6/(ln(2048)
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simplified analog input analysis (continued)
Driving Source Ri(MUX) TLC1570 Ri(ADC) Input Voltage External Driving Source Voltage Source Resistance Ri(ADC)= Input Resistance Ri(MUX)= Input Resistance (MUX resistance) Input Capacitance Capacitance Charging Voltage
Driving source requirements: Noise distortion source must equivalent resolution converter. must real input frequency.
Figure Equivalent Input Circuit Including Driving Source
definitions specifications terminology
integral nonlinearity (INL) Integral nonlinearity refers deviation each individual code from line drawn from zero through full scale. point used zero occurs before first code transition. full scale point defined level beyond last code transition. deviation measured from center each particular code true straight line between these points. differential nonlinearity (DNL) ideal exhibits code transitions that exactly apart. deviation from this ideal value. differential nonlinearity error less than ensures missing codes. zero offset major carry transition should occur when analog input zero volts. Zero error defined deviation actual transition from that point. gain error first code transition should occur analog value above negative full scale. last transition should occur analog value below nominal full scale. Gain error deviation actual difference between first last code transitions ideal difference between first last code transitions. signal-to-noise ratio distortion (SINAD) SINAD ratio value measured input signal other spectral components below Nyquist frequency, including harmonics excluding value SINAD expressed decibels. effective number bits (ENOB) sine wave, SINAD expressed terms number bits. Using following formula, (SINAD 1.76)/6.02 possible measure performance expressed effective number bits. Thus, effective number bits device sine wave inputs given input frequency calculated directly from measured SINAD.
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definitions specifications terminology (continued)
total harmonic distortion (THD) Total harmonic distortion ratio first harmonic components value measured input signal expressed percentage decibels. spurious free dynamic range (SFDR) Spurious free dynamic range difference between amplitude input signal peak spurious signal.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, AGND AVDD, DGND DVDD Analog input voltage range AVDD+0.3 Reference input voltage AVDD+0.3 Digital input voltage range DVDD+0.3 Operating virtual junction temperature range, 40°C 150°C Operating free-air temperature range, TLV1570C 70°C TLV1570I -40°C 85°C Storage temperature range, Tstg 65°C 150°C Lead temperature (1/16 inch) from case seconds 260°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
recommended operating conditions
power supplies
Analog supply voltage, AVDD (see Note Digital supply voltage, DVDD (see Note NOTE (AVDD DVDD) UNIT
analog inputs
Analog input voltage, Reference input voltage voltage, DVDD DVDD AGND AVDD AVDD VREF AVDD AVDD UNIT
digital inputs
High-level input voltage, Low-level input voltage, Input SCLK frequency SCLK pulse duration clock high tw(SCLKH) duration, high, (SCLKH) SCLK pulse duration, clock low, tw(SCLKL) duration (SCLKL) control rise time, SCLK, SDIN control fall time, SCLK, SDIN DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD UNIT
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electrical characteristics,over recommended operating free-air temperature range, supply voltages, reference voltages (unless otherwise noted)
digital specifications (SDOUT
PARAMETER Logic inputs IOZH IOZL High-level input current Low-level input current Input capacitance High-level output voltage Low-level output voltage High-impedance-state output current Low-impedance-state output current Output capacitance DVDD DVDD Control inputs DVDD-0.4 TEST CONDITIONS UNIT
Logic outputs
specifications
PARAMETER Resolution Accuracy Integral nonlinearity, Differential nonlinearity, Analog input Ilkg Ri(MUX) Ri(ADC) Input capacitance Input leakage current Input resistance Input resistance VAIN AVDD DVDD AVDD DVDD DVDD DVDD AVDD AVDD AVDD 2.08 3.48 2.26 3.82 External reference mode External reference mode 2.48 4.15 ppm/°C Offset error Gain error Best 0.65 0.15 %FSR %FSR TEST CONDITIONS UNIT Bits
Voltage reference Internal reference voltage Temperature coefficient Ci(VR) Input resistance Input capacitance Internal reference mode, Internal reference mode,
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electrical characteristics, over recommended operating free-air temperature range, supply voltages, reference voltages (unless otherwise noted) (continued)
specifications (continued)
PARAMETER Power supply IREF Operating supply current Power dissi ation dissipation AVDD AVDD AVDD AVDD DVDD fSCLK DVDD fSCLK DVDD DVDD AVDD Software Supply current power down Auto IREF typ. IREF typ. IREF AVDD IREF AVDD 2.7V AVDD 5.5V AVDD AGND AVDD AGND 2000 TEST CONDITIONS UNIT
specifications
PARAMETER TEST CONDITIONS 1.25 MSPS, AVDD MSPS KSPS AVDD KSPS, MSPS, AVDD 1.25 MSPS KSPS AVDD KSPS, MSPS, AVDD 1.25 MSPS KSPS, AVDD KSPS 1.25 MSPS, AVDD MSPS KSPS AVDD KSPS, 1.25 MSPS, AVDD MSPS KSPS AVDD KSPS, 1.25 MSPS, AVDD MSPS KSPS AVDD KSPS, External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference UNIT
kHz, Signal-to-noise ratio kHz,
kHz, SINAD Signal-to-noise ratio distortion kHz,
kHz, Total harmonic distortion
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specifications (continued)
PARAMETER TEST CONDITIONS 1.25 MSPS, AVDD MSPS KSPS AVDD KSPS, 1.25 MSPS, AVDD MSPS KSPS AVDD KSPS, 1.25 MSPS, AVDD MSPS KSPS AVDD KSPS, 1.25 MSPS, AVDD MSPS KSPS AVDD KSPS, Analog Input Channel-tochannel crosstalk Full-power bandwidth Small-signal bandwidth Sampling rate full-scale input sine wave full-scale input sine wave AVDD AVDD 0.0625 0.0625 1.25 0.625 MSPS External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference UNIT
kHz, SFDR Spurious-free dynamic range kHz,
kHz, ENOB Effective number bits kHz,
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timing requirements
PARAMETER tc(SCLK) (SCLK) tconv SCLK cycle time Pulse duration, chip select Sampling period Conversion period Setup time, SCLK falling edge mode Hold time, SCLK falling edge mode Setup time, falling edge mode Hold time, falling edge mode Delay time, falling edge next SCLK falling edge mode Delay time, SCLK rising edge after falling edge mode Delay time, output after SCLK rising edge mode mode Setup time, serial input data SCLK falling edge Hold time, serial input data SCLK falling edge TEST CONDITIONS DVDD DVDD SLCK cycles SLCK cycles UNIT
Rise time Specifications subject change without notice.
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PARAMETER MEASUREMENT INFORMATION
tc(SCLK) SCLK
SDIN
DI15
DI14 DI13
SDOUT
Figure Mode Timing Diagrams
SCLK
SDIN DI15 SDOUT DI14 DI13 DI12
Figure Mode Timing Diagrams
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TYPICAL CHARACTERISTICS
ANALOG INPUT RESISTANCE FREE-AIR TEMPERATURE
Analog Input Resistance AVDD AVDD Supply Current
TOTAL SUPPLY CURRENT FREE-AIR TEMPERATURE
AVDD
AVDD
Free-Air Temperature
Free-Air Temperature
Figure
SUPPLY CURRENT CLOCK FREQUENCY (SCLK)
Figure
GAIN INPUT FREQUENCY
Supply Current
Gain 25°C
12.5 15.4 Frequency Frequency
Figure
Figure
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TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Differential Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 Internal SCLK MHz, 25°C
Figure
INTEGRAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Integral Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 Internal SCLK MHz, 25°C
Figure
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TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Differential Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 External SCLK MHz, 25°C
Figure
INTEGRAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Integral Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 External SCLK MHz, 25°C
Figure
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TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Differential Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 Internal SCLK MHz, 25°C
Figure
INTEGRAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Integral Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 Internal SCLK MHz, 25°C
Figure
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TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Differential Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 External SCLK MHz, 25°C
Figure
INTEGRAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Integral Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 External SCLK MHz, 25°C
Figure
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TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Differential Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 External SCLK MHz, 25°C
Figure
INTEGRAL NONLINEARITY ERROR DIGITAL OUTPUT CODE
Integral Nonlinearity -0.2 -0.4 -0.6 -0.8 Samples 1023 External SCLK MHz, 25°C
Figure
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TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER BITS INPUT FREQUENCY
ENOB Effective Number Bits BITS ENOB Effective Number Bits BITS AVDD DVDD External AVDD DVDD External
EFFECTIVE NUMBER BITS INPUT FREQUENCY
Frequency
Frequency
Figure
EFFECTIVE NUMBER BITS INPUT FREQUENCY
ENOB Effective Number Bits BITS ENOB Effective Number Bits BITS Frequency AVDD DVDD Internal
Figure
EFFECTIVE NUMBER BITS INPUT FREQUENCY
AVDD DVDD Internal
Frequency
Figure
Figure
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TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM FREQUENCY
Fast Fourier Transform kHz, SCLK MHz, AVDD DVDD Internal
-100 -120
Frequency
Figure
FAST FOURIER TRANSFORM FREQUENCY
Fast Fourier Transform kHz, SCLK MHz, AVDD DVDD Internal
-100 -120
Frequency
Figure
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TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM FREQUENCY
Fast Fourier Transform kHz, SCLK MHz, AVDD DVDD External
-100 -120
Frequency
Figure
FAST FOURIER TRANSFORM FREQUENCY
Fast Fourier Transform kHz, SCLK MHz, AVDD DVDD External
-100 -120
Frequency
Figure
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TYPICAL CHARACTERISTICS
DI15 DI14 DI13 DI12 DI11 DI15 DI14 DI13 DI12 DI11 DI10 SCLK
Figure Typical Timing Diagram Application
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SDOUT
SDIN
Previous Conversion Output
conv
Configure
TLV1570 8-CHANNEL 10-BIT 1.25-MSPS SERIAL ANALOG-TO-DIGITAL CONVERTER
TYPICAL CHARACTERISTICS
DI11 Previous Conversion Output SDOUT
conv
Configure SCLK
Figure Typical Timing Diagram Application
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SDIN
DI15 DI14 DI13 DI12 DI11 DI10
DI15
DI14
DI13
DI12
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

Fast Throughput Rate: 1.25 MSPS KSPS Wide Analog Channel Input: AVDD E

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