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TLC555, TLC555Y LinCMOS TIMERS

D, DB, JG, P, OR PW PACKAGE (TOP VIEW)

TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
D, DB, JG, P, OR PW PACKAGE (TOP VIEW)
GND TRIG OUT RESET
VDD DISCH THRES CONT
FK PACKAGE (TOP VIEW)
NC TRIG NC OUT NC
NC GND NC VDD NC NC DISCH NC THRES NC NC RESET NC
description
The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The NC - No internal connection timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage. Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering. While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555. The TLC555C is characterized for operation from 0°C to 70°C. The TLC555I is characterized for operation from - 40°C to 85°C. The TLC555M is characterized for operation over the full military temperature range of - 55°C to 125°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015 however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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CONT NC
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
AVAILABLE OPTIONS PACKAGED DEVICES TA 0°C to 70°C - 40°C to 85°C - 55°C to 125°C VDD RANGE 2 V to 15 V 3 V to 15 V 5 V to 15 V SMALL OUTLINE (D) TLC555CD TLC555ID TLC555MD SSOP (DB) TLC555CDBLE - - CHIP CARRIER (FK) - - TLC555MFK CERAMIC DIP (JG) - - TLC555MJG PLASTIC DIP (P) TLC555CP TLC555IP TLC555MP TSSOP (PW) TLC555CPWLE - - TLC555Y CHIP FORM (Y)
As previously established
For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics.
functional block diagram
Pin numbers are for all packages except the FK package. RESET can override TRIG, which can override THRES.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
TLC555Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC555. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS CONT VDD (5) (8) THRES (6) R RESET (4)
R TRIG
R (1) GND 64
DISCH
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Template Release Date: 7-11-94
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
DISCH
COMPONENT COUNT
Transistors Resistors
GND TRIG RESET
equivalent schematic (each channel)
THRES
POST OFFICE BOX 655303 · DALLAS, TEXAS 75265
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
recommended operating conditions
MIN Supply voltage, VDD TLC555C Operating free-air temperature range, TA TLC555I TLC555M 2 0 - 40 - 55 MAX 15 70 85 125 °C UNIT V
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
Full range is 0°C to 70°C for the TLC555C and - 40°C to 85°C for the TLC555I. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
POST OFFICE BOX 655303
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TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
IIT VI(TRIG)
Threshold voltage
II(TRIG)
VI(RESET)
II(RESET)
25°C Full range 25°C MAX 25°C Full range 25°C Full range 25°C Full range 25°C Full range 25°C Full range 4.1 4.1
V 0.4 0.6
Supply current
See Note 2
Full range is 0°C to 70°C the for TLC555C, - 40°C to 85°C for the TLC555I, and - 55°C to 125°C for the TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
VIT IIT VI(TRIG) II(TRIG) VI(RESET) II(RESET)
Threshold voltage
MAX 25°C Full range 25°C MAX 25°C Full range 25°C Full range 25°C Full range 25°C Full range 25°C Full range 25°C Full range 25°C Full range 12.5 12.5 13.5 13.5 14.2 14.2
Full range is 0°C to 70°C for TLC555C, - 40°C to 85°C for TLC555I, and - 55°C to 125°C for TLC555M. For conditions shown as MAX, use the appropriate value specified in the recommended operating conditions table. NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. NOTE 3: RA, RB, and CT are as defined in Figure 1.
IDD Supply current See Note 2 170 350 NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
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TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES TO DISCHARGE OUTPUT FROM TRIGGER AND THRESHOLD SHORTED TOGETHER vs SUPPLY VOLTAGE
DISCHARGE SWITCH ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE
tPHL tPLH
0 - 25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 18 20 TA - Free-Air Temperature - °C VDD - Supply Voltage - V The effects of the load resistance on these values must be taken into account separately.
Figure 1
Figure 2
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TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
APPLICATION INFORMATION
0.1 µF RA 0.1 µF 4 7 RB 6 THRES 2 CT TRIG GND 1 GND tPLH TRIGGER AND THRESHOLD VOLTAGE WAVEFORM VDD tPHL RL 3 Output CL 1 / 3 VDD 2 / 3 VDD tc(L)
tc(H)
5 8 CONT VDD RESET TLC555 DISCH OUT
Pin numbers shown are for all packages except the FK package. CIRCUIT
Figure 3. Astable Operation Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor CT charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through RB only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle (tc(H)) and low during the discharge cycle (tc(L)). The duty cycle is controlled by the values of RA, RB, and CT as shown in the equations below. t c(H) t c(L) Period
CT (RA ) RB) In 2 (In 2 + 0.693) CT RB In 2 + tc(H) ) tc(L) CT (RA ) 2RB) In 2 t R c(L) Output driver duty cycle + 1 - R )B2R t ) tc(L) c(H) A B +t
t c(H) c(H) t
Output waveform duty cycle
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
APPLICATION INFORMATION
The equations below provide better agreement with measured values. t
) ron)
) tPHL ) tPLH
+ CT (RB ) ron) In c(L)
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
MECHANICAL DATA
D (R-PDSO-G)
14 PIN SHOWN PINS DIM 0.020 (0, 51) 0.014 (0, 35) 14 8 A MIN 0.244 (6, 20) 0.228 (5, 80) 0.157 (4, 00) 0.150 (3, 81) 0.008 (0, 20) NOM 0.189 (4, 80) 0.337 (8, 55) 0.386 (9, 80) 0.010 (0, 25) M A MAX
PLASTIC SMALL-OUTLINE PACKAGE
Gage Plane
Seating Plane 0.069 (1, 75) MAX 0.010 (0, 25) 0.004 (0, 10) 0.004 (0, 10) 4040047 / D 10 / 96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0, 15). Falls within JEDEC MS-012
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
DB (R-PDSO-G)
28 PIN SHOWN 0, 65 28 0, 38 0, 22 15 0, 15 M
PLASTIC SMALL-OUTLINE PACKAGE
0, 15 NOM 5, 60 5, 00 8, 20 7, 40
Gage Plane 1 A 14 0°- 8° 0, 25 1, 03 0, 63
Seating Plane 2, 00 MAX 0, 05 MIN 0, 10
PINS DIM A MAX
12, 30 4040065 / C 10 / 95
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0, 15. Falls within JEDEC MO-150
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TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
FK (S-CQCC-N)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
NO. OF TERMINALS 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8, 69) 0.442 (11, 23) 0.640 (16, 26) 0.739 (18, 78) 0.938 (23, 83) 1.141 (28, 99) MAX 0.358 (9, 09) 0.458 (11, 63) 0.660 (16, 76) 0.761 (19, 32) 0.962 (24, 43) 1.165 (29, 59) MIN 0.307 (7, 80) 0.406 (10, 31) 0.495 (12, 58) 0.495 (12, 58) 0.850 (21, 6) 1.047 (26, 6)
B MAX 0.358 (9, 09) 0.458 (11, 63) 0.560 (14, 22) 0.560 (14, 22) 0.858 (21, 8) 1.063 (27, 0)
4040140 / D 10 / 96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
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TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.020 (0, 51) MIN
0.200 (5, 08) MAX Seating Plane 0.130 (3, 30) MIN
4040107 / C 08 / 96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL-STD-1835 GDIP1-T8
POST OFFICE BOX 655303
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TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
4 0.070 (1, 78) MAX 0.020 (0, 51) MIN 0.310 (7, 87) 0.290 (7, 37)
0.200 (5, 08) MAX Seating Plane 0.125 (3, 18) MIN
0.100 (2, 54) 0.021 (0, 53) 0.015 (0, 38) 0.010 (0, 25) M 0.010 (0, 25) NOM
4040082 / B 03 / 95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
POST OFFICE BOX 655303
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TLC555, TLC555Y LinCMOS TIMERS
SLFS043C - SEPTEMBER 1983 - REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
PW (R-PDSO-G)
14 PIN SHOWN 0, 30 0, 19 14 8
PLASTIC SMALL-OUTLINE PACKAGE
0, 15 NOM 4, 50 4, 30 6, 60 6, 20 Gage Plane 0, 25 1 A 7 0°- 8° 0, 75 0, 50
Seating Plane 1, 20 MAX 0, 05 MIN 0, 10
PINS DIM A MAX 8 14 16 20 24 28
9, 60 4040064 / E 08 / 96
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0, 15. Falls within JEDEC MO-153
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· DALLAS, TEXAS 75265