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Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Available 1.13 1.26GHz 512KB Advanced Transfer Cache (on-die, full speed Level (L2) cache with Error Correcting Code (ECC)) Dual Independent (DIB) architecture: Separate dedicated external System dedicated internal high-speed cache Internet Streaming SIMD Extensions enhanced video, sound performance Binary compatible with applications running previous members Intel microprocessor line Dynamic execution micro architecture Power Management capabilities System Management mode Multiple low-power states
Optimized 32-bit applications running advanced 32-bit operating systems Flip Chip Grid Array (FC-PGA2) packaging technology; FC-PGA2 processors deliver high performance with improved handling protection socketability Integrated high performance instruction data, nonblocking, level cache 512KB Integrated Full Speed level cache allows latency read/store operations Quad Quadword Wide (256 bit) cache data provides extremely high throughput read/ store operations. 8-way cache associativity provides improved cache rate reads/store operations. Error-correcting code System data Data Prefetch Logic
Pentium® Processor with 512KB Cache designed high-performance workstations servers. binary compatible with previous Intel Architecture processors. Pentium® Processor with 512KB Cache provides great performance applications running advanced operating systems such Windows* Windows* Windows* 2000, Windows* Linux. This achieved integrating best attributes Intel processors-the dynamic execution, Dual Independent architecture plus Intel MMXtechnology Internet Streaming SIMD Extensions-bringing level performance systems buyers. Pentium® Processor with 512KB Cache extends power Pentium® processor with performance headroom business media, communication internet capabilities. Systems based Pentium® Processor with 512KB Cache also include latest features simplify system management lower cost ownership large small business environments. Pentium® Processor with 512KB Cache offers great performance today's tomorrow's applications.
FC-PGA2 Package
August 2001 Order Number: 249657-002
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
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Copyright Intel Corporation, 2001 Other names brands claimed property others.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Contents
Introduction. Terminology. 1.1.1 Package Processor Terminology 1.1.2 Processor Naming Convention.9 Related Documents.10 Processor System VREF Clock Control Power States.12 2.2.1 Normal State-State 2.2.2 AutoHALT Powerdown State-State 2.13 2.2.3 Stop-Grant State-State 2.2.4 HALT/Grant Snoop State-State 2.2.5 Sleep State-State 5.14 2.2.6 Deep Sleep State-State 2.2.7 Clock Control.15 Power Ground Pins 2.3.1 Phase Lock Loop (PLL) Power.16 Decoupling Guidelines 2.4.1 Processor VCCCORE Decoupling.17 Processor System Clock Processor Clocking Voltage Identification Processor System Unused Pins.21 Processor System Signal Groups 2.8.1 Asynchronous Synchronous System Signals 2.8.2 System Frequency Select Signals Test Access Port (TAP) Connection.24 Maximum Ratings.24 Processor Voltage Level Specifications AGTL System Specifications.29 System Timing Specifications BCLK/BCLK# PICCLK Signal Quality Specifications Measurement Guidelines AGTL Signal Quality Specifications Measurement Guidelines.43 AGTL Signal Quality Specifications Measurement Guidelines.44 3.3.1 Overshoot/Undershoot Guidelines 3.3.2 Overshoot/Undershoot Magnitude 3.3.3 Overshoot/Undershoot Pulse Duration.45 3.3.4 Activity Factor 3.3.5 Reading Overshoot/Undershoot Specification Tables.46 3.3.6 Determining System meets Overshoot/Undershoot Specifications
Electrical Specifications.11
2.10 2.11 2.12 2.13
Signal Quality Specifications
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Non-AGTL Signal Quality Specifications Measurement Guidelines. 3.4.1 Overshoot/Undershoot Guidelines 3.4.2 Ringback Specification. 3.4.3 Settling Limit Guideline Thermal Specifications. 4.1.1 THERMTRIP# Requirement. 4.1.2 Thermal Diode. Thermal Metrology FC-PGA2 Mechanical Specifications Recommended Mechanical Keep-Out Zones Processor Markings Processor Signal Listing. Mechanical Specifications. 6.1.1 Mechanical Specifications FC-PGA2 Package 6.1.2 Boxed Processor Heatsink Weight. Thermal Specifications. 6.2.1 Boxed Processor Cooling Requirements 6.2.2 Boxed Processor Thermal Cooling Solution Clip Electrical Requirements Boxed Pentium® Processor with 512KB Cache. 6.3.1 Electrical Requirements Alphabetical Signals Reference Signal Summaries
Thermal Specifications Design Considerations.
Mechanical Specifications.
Boxed Processor Specifications.
Processor Signal Description
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
List Figures
Integrated Heat Spreader (IHS) AGTL Topology Uniprocessor Configuration.12 Stop Clock State Machine Filter Specification.16 Differential/Single-Ended Clocking Example.18 Power Good Select Interconnect Diagram BSEL[1:0] Example System Design.23 Static Transient Tolerance Clock Waveform BCLK/BCLK#, PICCLK, Generic Clock Waveform System Valid Delay Timings System Setup Hold Timings.38 System Reset Configuration Timings.39 Platform Power-On Sequence Timings Power-On Reset Configuration Timings.40 Test Timings (TAP Connection) Test Reset Timings BCLK/BCLK#, PICCLK Generic Clock Waveform Processor Pins High AGTL Receiver Ringback Tolerance.44 Maximum Acceptable AGTL Overshoot/Undershoot Waveform Non-AGTL Overshoot/Undershoot, Settling Limit, Ringback Package Dimensions.55 FC-PGA2 Flatness Specification.57 Volumetric Keep-Out Component Keep-Out Side Processor Markings Pentium® Processor with 512KB Cache Pinout Conceptual Boxed Pentium® Processor with 512KB Cache PGA370 Socket Comparison between FC-PGA FC-PGA2 package.72 Side View Space Requirements Boxed Processor Dimensions Mechanical Step Feature Heatsink Base.73 Thermal Airspace Requirement Boxed Pentium® Processor with 512KB Cache Heatsink PGA370 Socket Boxed Processor Heatsink Power Cable Connector Description.75 Motherboard Power Header Placement Relative Boxed Pentium® Processor with 512KB Cache
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
List Tables
Processor Identification. System Clock Deep Sleep Mode Voltage Identification Definition System Signal Groups Frequency Select Truth Table BSEL[1:0] Absolute Maximum Ratings Voltage Current Specifications Power Supply Current Slew Rate (dIcccore/dt) Static Transient Tolerance AGTL Signal Group Levels Specifications Non-AGTL Signal Group Levels Specifications Volt CMOS Output Signal Group Specifications Processor AGTL Specifications System Timing Specifications (Single-Ended Clock) System Timing Specifications (Differential Clock) System Timing Specifications (AGTL Signal Group) System Timing Specifications (CMOS Signal Group) System Timing Specifications (Reset Conditions) System Timing Specifications (APIC Clock APIC I/O) System Timing Specifications (TAP Connection) Platform Power-On Timings BCLK (Single-Ended Clock Mode) Signal Quality Specifications Simulation Processor Pins. BCLK/BCLK# (Differential Clock Mode) PICCLK Signal Quality Specifications Simulation Processor Pins. AGTL Signal Groups Ringback Tolerance Specifications Processor Pins Example Platform Information. AGTL Signal Group Overshoot/Undershoot Tolerance CMOS Signal Group Overshoot/Undershoot Tolerance. Signal Ringback Specifications Non-AGTL Signal Simulation Processor Pins Pentium® Processor with 512KB Cache Thermal Design Power. THERMTRIP# Time Requirement Thermal Diode Parameters Thermal Diode Interface. Pentium® Processor with 512KB Cache Package Dimensions Processor Case Loading Parameters Signal Listing Order Signal Name Signal Listing Order Number Boxed Processor Heatsink Spatial Dimensions. Heatsink Power Signal Specifications. Signal Description Output Signals Input Signals Input/Output Signals (Single Driver) Input/Output Signals (Multiple Driver)
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Introduction
Intel® Pentium® processor with 512KB Cache PGA370 socket next member family, Intel IA-32 processor line hereafter will referred simply "the processor". Intel® Pentium® processor with 512KB Cache will continue package technology called flip-chip grid array will contain Integrated Heat Spreader (IHS) (see Figure flip-chip with package will labeled FC-PGA2 will utilize same 370-pin zero insertion force socket (PGA370). Thermal solutions contact directly FC-PGA2 package bare-die with FC-PGA attachment. Intel® Pentium® processor with 512KB Cache, like predecessors family processors, implements Dynamic Execution microarchitecture-a unique combination multiple branch prediction, data flow analysis, speculative execution. This enables these processors deliver higher performance than Intel® Pentium® processor, while maintaining binary compatibility with previous Intel Architecture processors. processor also executes Intel® MMXtechnology instructions enhanced media communication performance just predecessor, Intel® Pentium® processor (CPUID 068xh). Additionally, Intel® Pentium® processor with 512KB Cache executes Streaming SIMD (single-instruction, multiple data) Extensions enhanced floating point application performance. Data Prefetch Logic adds functionality that anticipates data needed application pre-loads into Advanced Transfer Cache, further increasing processor application performance. processor utilizes multiple low-power states such Sleep, Deep Sleep conserve power during idle times. processor includes integrated on-die 512KB 8-way associative level-two (L2) cache. cache implements Advanced Transfer Cache Architecture with 256-bit wide bus. processor also includes level (L1) instruction cache data cache. These cache arrays full speed processor core. Intel® Pentium® processor with 512KB Cache PGA370 socket dedicated cache bus, thus maintaining dual independent architecture deliver high bandwidth performance. Memory cacheable addressable memory space, allowing significant headroom desktop systems. Refer Specification Update document this processor determine cacheability cache configuration options specific processor. Please contact your nearest Intel Sales Representative latest Processor Specification Update.
Figure Integrated Heat Spreader (IHS)
FC-PGA2 w/IHS
FC-PGA
Intel® Pentium® processor with 512KB Cache will support lower voltage differential single-ended clocking system bus. Intel® Pentium® processor with 512KB Cache will function previous generation platform incompatible system signal levels clock type. Care must taken ensure correct processors installed correct PGA370 socket platforms.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Terminology
this document, symbol after signal name refers active signal. This means that signal active state (based name signal) when driven level. example, when FLUSH# low, flush been requested. When high, nonmaskable interrupt occurred. case signals where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D[3:0]# `LHLH' also refers High logic level, logic level). term "system bus" refers interface between processor, system core logic (a.k.a. chipset components), other agents.
1.1.1
Package Processor Terminology
following terms used often this document explained here clarification:
Intel® Pentium® processor with 512KB Cache entire product including
internal components.
PGA370 socket 370-pin Zero Insertion Force (ZIF) socket which FC-PGA packaged
processor plugs into.
FC-PGA Flip Chip Grid Array. package technology used Intel® Pentium®
processor (CPUID 068xh) PGA370 socket. FC-PGA package processor exposed.
FC-PGA2 Flip Chip Grid Array package technology used Intel®
Pentium® processor with 512KB Cache PGA370 socket. FC-PGA2 package contains Integrated Heat Spreader which covers processor die.
Advanced Transfer Cache (ATC) cache architecture used Intel® Pentium®
processors. consists microarchitectural improvements that provide higher data bandwidth interface into processor core that completely scaleable with processor core frequency.
Keep-out zone area near FC-PGA2 packaged processor that system designs
utilize.
Keep-in zone area FC-PGA2 packaged processor that thermal solutions utilize. Processor this document, term processor generic form Intel® Pentium®
processor with 512KB Cache PGA370 socket FC-PGA2 package.
Processor core processor's execution engine. Integrated Heat Spreader (IHS) Integrated Heat Spreader (IHS) metal cover
integral part CPU. promotes heat spreading away from backside ease thermal constraints. cache cache industry designated names.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
1.1.2
Processor Naming Convention
Table
Processor Identification
Processor 1.13 1.26 Core Frequency (GHz) 1.13 1.26 System Frequency (MHz) Cache Size (Kbytes) Cache Type2 CPUID1 06Bxh 06Bxh
NOTES: Refer Pentium Processor Specification Update exact CPUID each processor. Advanced Transfer Cache. Cache integrated same processor core. With ATC, interface between processor core Cache 256-bits wide, runs same frequency processor core enhanced buffering.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Related Documents
reader this specification should also familiar with material concepts presented following documents 1,2:
Document AP-485, Intel Processor Identification CPUID Instruction AP-589, Design Intel® Architecture Software Developer's Manual Volume Basic Architecture Volume Instruction Reference Volume III: System Programming Guide Family Processors Hardware Developer's Manual IA-32 Processors Related Products 1999 Databook 370-Pin Socket (PGA370) Design Guidelines PGA370 Heat Sink Cooling MicroATX Chassis CK-408B Clock Synthesizer/Driver Specification DC-DC Converter Design Guidelines Intel® Pentium® processor with 512KB Cache Buffer Models Extensions Pentium® Processor BIOS Writer's Guide3 Intel® Pentium® processor with 512KB Cache Dual Processor Design Guide Intel® Pentium® processor FC-PGA2, Thermal Design Guidelines 249658 249660 249659
Intel Order Number 241618 243334 243193 243190 243191 243192 244001 243565 244410 245025
NOTES: Unless otherwise noted, this reference material found Intel Developer's Website located http://developer.intel.com. complete listing Intel® Pentium® processor reference material, please refer Intel Developer's Website This material available through Intel Field Sales Representative.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Electrical Specifications
Processor System VREF
Intel® Pentium® processor with 512KB Cache uses original voltage signaling Gunning Transceiver Logic (GTL) technology system bus. system operates 1.25V signal levels versus GTL+ which operates 1.5V signal levels. GTL+ signal technology used Intel® Pentium® Pro, Intel® Pentium® legacy Intel® Pentium® processors. Current family processors vary from Intel® Pentium® processor their output buffer implementation. buffers that drive system signals Intel® Pentium® processor with 512KB Cache actively driven clock cycle after high transition improve rise times. These signals open-drain require termination supply. Because this specification different from standard specification, referred AGTL, Assisted this other documentation related Intel® Pentium® processor. AGTL logic AGTL+ logic compatible with each other differences with signal switching levels. Intel® Pentium® processors with 512KB Cache cannot installed into platforms where chipset only supports AGTL+ signal levels. more information AGTL AGTL+ routing, please refer appropriate platform design guide. AGTL inputs differential receivers which requires reference voltage (VREF). VREF used differential receivers determine input signal logical logical VREF signal typically implemented voltage divider platform. Noise decoupling critical VREF signal. Refer platform design guide recommended decoupling requirements. Another important item AGTL system termination. System termination used pull each signal high voltage level control reflections transmission line. processor contains on-die termination resistors that provide termination system bus. other system should also terminated near chipset resistors placed platform on-die termination within chipset. recommended that system implemented using Dual-End Termination (DET) meet timings signal integrity specified Intel® Pentium® processor with 512KB Cache. Figure schematic representation AGTL topology Intel® Pentium® processor with 512KB Cache, when chipset does have on-die termination. Note: RESET# signal requires discrete external termination resistor system board. Note: AGTL depends incident wave switching. Therefore, timing calculations AGTL signals based flight time opposed capacitive deratings. Analog signal simulations
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
system bus, including trace lengths, highly recommended especially when following recommended layout guidelines. Figure AGTL Topology
AGTL Topology UniProcessor Configuration
Processor
Chipset
AGTL Topology Dual-Processor Configuration
Processor
Chipset
Processor
Note: RESET# requires external termination
Note:
Please refer appropriate design guide platform specific termination.
Clock Control Power States
Processors allow Sleep, Deep Sleep states reduce power consumption stopping clock internal sections processor, depending each particular state. Figure visual representation processor power states.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Stop Clock State Machine
HALT Instruction HALT Cycle Generated Auto HALT Power Down State BCLK running. Snoops interrupts allowed. INIT#, INIT#, INTR, RESET# Norm State Norm execution.
STPCLK Asserted Snoop Event Occurs Snoop Event Serviced TPCLK# De-asserted STPCLK# Asserted STPCLK# De-asserted
Stop-Grant State entered from AutoHALT
Snoop Event Occurs Snoop Event erviced
HALT/Grant Snoop tate BCLK running. Service snoops caches.
Stop Grant State BCLK running. Snoops interrupts allowed.
SLP# Asserted
De-asserted
Sleep tate BCLK running. snoops interrupts allowed. BCLK Input Stopped BCLK Input Restarted
Deep leep State BCLK stopped. snoops interrupts allowed.
PCB757a
processor fully realize current consumption Stop-Grant, Sleep Deep Sleep states, Model Specific Register (MSR) must set. 02AH (Hex), must (this power default setting) processor stop internal clocks during these modes. more information, Intel Architecture Software Developer's Manual, Volume System Programming Guide.
2.2.1
Normal State-State
This normal operating state processor.
2.2.2
AutoHALT Powerdown State-State
AutoHALT power state entered when processor executes HALT instruction. processor transitions Normal state upon occurrence SMI#, INIT#, LINT[1:0] (NMI, INTR). RESET# causes processor immediately initialize itself. return from System Management Interrupt (SMI) handler either Normal Mode AutoHALT Power Down state. Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide more information. FLUSH# serviced during AutoHALT state, processor will return AutoHALT state.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
system generate STPCLK# while processor AutoHALT Power Down state. When system deasserts STPCLK# interrupt, processor returns execution HALT state.
2.2.3
Stop-Grant State-State
Stop-Grant state processor entered when STPCLK# signal asserted. Since AGTL signal pins receive power from system bus, these pins should driven (allowing level return VTT) minimum power drawn termination resistors this state. addition, other input pins system should driven inactive state. BINIT# FLUSH# serviced during Stop-Grant state. RESET# causes processor immediately initialize itself, processor stays Stop-Grant state. transition back Normal state occurs with deassertion STPCLK# signal. transition HALT/Grant Snoop state occurs when processor detects snoop system (see Section 2.2.4). transition Sleep state (see Section 2.2.5) occurs with assertion SLP# signal. While Stop-Grant State, SMI#, INIT#, LINT[1:0] latched processor, only serviced when processor returns Normal state. Only occurrence each event recognized serviced upon return Normal state.
2.2.4
HALT/Grant Snoop State-State
processor responds snoop transactions system while Stop-Grant state AutoHALT Power Down state. During snoop transaction, processor enters HALT/Grant Snoop state. processor stays this state until snoop system been serviced (whether processor another agent system bus). After snoop serviced, processor returns Stop-Grant state AutoHALT Power Down state, appropriate.
2.2.5
Sleep State-State
Sleep state very power state which processor maintains context, maintains phase-locked loop (PLL), stopped internal clocks. Sleep state only entered from Stop-Grant state. Once Stop-Grant state, SLP# asserted, causing processor enter Sleep state. SLP# recognized Normal AutoHALT states. Snoop events that occur while Sleep State during transition into Sleep state will cause unpredictable behavior. Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals (with exception SLP# RESET#) allowed system while processor Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior. RESET# driven active while processor Sleep state, held active specified RESET# specification, then processor will reset itself, ignoring transition through Stop-Grant State. RESET# driven active while processor Sleep State, SLP# STPCLK# signals should deasserted immediately after RESET# asserted ensure processor correctly executes reset sequence.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
While Sleep state, processor capable entering lowest power state, Deep Sleep state, stopping BCLK input (see Section 2.2.6). Once Sleep state, SLP# deasserted another asynchronous system event occurs. SLP# minimum assertion BCLK period.
2.2.6
Deep Sleep State-State
Deep Sleep state lowest power state processor enter while maintaining context. Deep Sleep state entered stopping BCLK input (after Sleep state entered from assertion SLP# pin). processor Deep Sleep state immediately after BCLK stopped. BCLK BCLK# have separated least 0.2V during Deep Sleep State. Stopping BCLK input lowers overall current consumption leakage levels. re-enter Sleep state, BCLK input must restarted. period allow stabilization) must occur before processor considered Sleep state. Once Sleep state, SLP# deasserted re-enter Stop-Grant state. While Deep Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals allowed system while processor Deep Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior.
Table
System Clock Deep Sleep Mode (Differential Mode only)1
Symbol VBCLK VBCLK-VBCLK# Parameter BCLK Voltage Level when active BCLK# Voltage Level when active 1.45 VBCLK
Units
Notes
NOTES: values this table based differential probe measurement Bclk. voltage level specified must maintained when system clock active, e.g. Deep Sleep Mode. VBCLK# less than VBCLK.
2.2.7
Clock Control
BCLK provides clock signal processor on-die cache. During AutoHALT Power Down Stop-Grant states, processor will process system snoop. processor does stop clock cache during AutoHALT Power Down Stop-Grant states. Entrance into Halt/Grant Snoop state allows cache snooped, similar Normal state. When processor Sleep Deep Sleep states, does respond interrupts snoop transactions. During Sleep state, internal clock cache stopped. During Deep Sleep state, internal clock cache stopped. internal clock cache restarted only after internal clocking mechanism processor stable (i.e., processor re-entered Sleep state). PICCLK should removed during AutoHALT Power Down Stop-Grant states. PICCLK removed during Sleep Deep Sleep states. When transitioning from Deep Sleep state Sleep state, PICCLK must restarted with BCLK.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Power Ground Pins
operating voltage Intel® Pentium® processor with 512KB Cache same core cache. VCCCORE defined power pins that supply voltage processor's core cache. voltage regulator module (VRM) voltage regulator controlled five voltage identification (VID) signals driven processor. signals specify voltage required processor core. Refer Section further details voltage settings. Intel® Pentium® processor VCCCORE, VREF, VTT, VCCCMOS1.5, VCCCMOS1.8, VCCCMOS2.0 inputs. VREF inputs used AGTL reference voltage processor. inputs (1.25V) used provide AGTL termination voltage processor. VCCCMOS1.5 VCCCMOS1.8 VCCCMOS2.0 voltage input pins processor rather voltage sources pullup resistors which connected CMOS (nonAGTL) input/output signals driven to/from processor. inputs ground pins processor core cache. platform, VCCCORE pins must connected voltage island island portion power plane that been divided, entire plane) minimize voltage drop that occur trace impedance. also highly recommended platform provide either voltage island wide trace pins. Similarly, pins must connected system ground plane. These recommendations found platform design guide layout section.
2.3.1
Phase Lock Loop (PLL) Power
highly critical that phase lock loop power delivery processor meets Intel's requirements. pass filter required power delivery pins PLL1 PLL2. This serves isolated, decoupled power source internal PLL. Please refer Phase Lock Loop Power section appropriate platform design guide recommended filter implementation.
Figure Filter Specification
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Decoupling Guidelines
large number transistors high internal clock speeds, processor capable generating large average current swings between full power states. fluctuations cause voltages power planes below their nominal values bulk decoupling adequate. Care must taken board design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations event voltage sag) reduced lifetime component event voltage overshoot).
2.4.1
Processor VCCCORE Decoupling
regulator VCCCORE input must capable delivering dICCCORE/dt (defined Table while maintaining required tolerances (also defined Table Failure meet these specifications result timing violations (during VCCCORE sag) reduced lifetime component (during VCCCORE overshoot). processor requires both high frequency bulk decoupling system motherboard proper AGTL operation. minimum recommendation processor decoupling requirement listed below. capacitors should placed next within PGA370 socket cavity mounted primary side motherboard. capacitors arranged minimize overall inductance between VCCCORE power pins. Decoupling Recommendations: VCCCORE decoupling minimum sixteen 4.7uF capacitors 1206 package. decoupling Twenty 0.1uF capacitors 0603 packages. VREF decoupling 0.1uF 0.001uF capacitors 0603 package placed near VREF pins. additional decoupling requirements, please refer appropriate platform design guide recommended capacitor component value/quantity placement.
Processor System Clock Processor Clocking
Intel® Pentium® processor with 512KB Cache will implement auto-detect mechanism that will allow processor either single-ended differential signaling system processor clocking. processor checks signal toggling. this signal toggling then processor operates differential mode. Refer Figure example differential clocking. Resistor values clock topology listed appropriate platform design guide differential implementation. Note: References BCLK throughout this document will also imply it's complement signal, BCLK# differential implementations, when noted otherwise. BCLK input directly controls operating speed system interface. AGTL system timing parameters specified with respect crossing point rising edge BCLK falling edge BCLK# inputs differential implementation. Family Processors Hardware Developer's Manual further details. reference voltage BCLK Family Processors Hardware Developer Manual re-defined crossing point BCLK BCLK# differential implementation.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Differential/Single-Ended Clocking Example
BCLK Clock Driver BCLK#
BCLK
Processor Chipset
Clock Driver
Processor Chipset
Voltage Identification
There five voltage identification (VID) pins PGA370 socket. These pins used support automatic selection VCCCORE voltages. pins Intel® Pentium® processor with 512KB Cache open drain signals versus opens shorts found previous Intel® Pentium® processors FC-PGA package. Refer Table level specifications signals. This pull-up resistor either external logic motherboard internal Voltage Regulator. signals rely 3.3V pull-up resistor signal logic high level. pins needed fully support voltage specification variations current future processors. voltage selection range processor defined Table VID25mV signal signal that allows voltage regulator voltage regulator module (VRM) output voltage levels 25mV increment necessary Intel® Pentium® processor with 512KB Cache only. legacy Pentium® processor FC-PGA package will have this VID25mV signal. VID25mV location actually Pentium® processor (CPUID 068xh). connecting VID25mV signal pin, will disable 25mV stepping granularity output regulator will resort 50mV stepping increment. voltage regulator must supply voltage that requested disable itself. addition signal "VID25mV", Intel® Pentium® processor with 512KB Cache will introduce second signal labeled "VTT_PWRGD". VTT_PWRGD signal informs platform that BSEL signals stable should sampled. During power-up, signals will indeterminate state small period time. voltage regulator should latch signals until VTT_PWRGD signal asserted sampled active. assertion VTT_PWRGD signal indicates signals stable driven final state processor. Refer Figure power-up timing sequence VTT_PWRGD signals.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table
Voltage Identification Definition
VID25mV VID3 VID2 VID1 VID0 VccCORE 1.05 1.075 1.10 1.125 1.15 1.175 1.20 1.225 1.25 1.275 1.30 1.3252 1.35 1.375 1.40 1.425 1.45 1.475 1.50 1.525 1.55 1.575 1.60 1.625 1.65 1.675 1.70 1.725 1.75 1.775 1.80 1.825
NOTES: Processor connected VSS. Open processor; pulled (3.3V max) baseboard. VID[25mV, 3:0] `11111' used Core' setting Pentium® processor with 512KB Cache platforms detect absence processor core particular PGA370 socket.
pins should pulled 3.3V level. This accomplished with pull-ups internal voltage regulator, which ensures valid pull-up voltage during power-up powerdown sequences. external resistors used VID[3:0, 25mV] signal, then power source must guaranteed stable whenever supply voltage regulator stable. This will prevent possibility processor supply going above specified VCCCORE event failure supply lines. case DC-to-DC converter, this accomplished using input voltage converter line pull-ups. resistor equal Ohms used connect signals voltage regulator input.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Intel requires that designs utilize specifications meet Intel® Pentium® processor with 512KB Cache requirements. re-emphasize, introduces signals [VID25mV VTT_PWRGD] that utilized Intel® Pentium® processor with 512KB Cache platform. Ignoring connecting these pins, documented Platform Design Guidelines, will prevent Intel® Pentium® processor with 512KB Cache from operating specified voltage levels core frequency. Figure provides high-level interconnection schematic. Please refer DC-DC Converter Design Guideline appropriate Platform Design Guidelines further detailed information voltage identification select implementation. Refer Figure power-up sequence timing requirements. Figure Power Good Select Interconnect Diagram
VID[3:0,25mV]
Voltage Regulator
Vcc_core
VTT_PWRGD (output)
Vcc_core
Pentium® processor with 512KB Cache
VTT_PWRGD (input)
BSEL [1:0] Clock Driver
Note: Please refer Intel® Pentium® Processor with 512KB Cache Dual Processor Platform Design Guide VTT_PWRGD implementation Pentium® processor with 512KB Cache platform.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Processor System Unused Pins
RESERVED pins must remain unconnected unless specifically noted. Connection these pins VCCCORE, VREF, VSS, other signal (including each other) result component malfunction incompatibility with future processors. Section listing processor location each RESERVED pin. PICCLK must driven with valid clock input PICD[1:0] signals must pulled-up VCCCMOS1.5 even when APIC will used. separate pull-up resistor must provided each PICD signal. reliable operation, always connect unused inputs bidirectional signals their deasserted signal level. pull-up pull-down resistor values system dependent should chosen such that logic high (VIH) logic (VIL) requirements met. Table level specifications non-AGTL signals. unused AGTL inputs, on-die termination will sufficient. external necessary motherboard unused CMOS inputs, active signals should connected through pull-up resistor VCCCMOS1.5 meet requirements. Unused active high CMOS inputs should connected through pull-down resistor ground (VSS) meet requirements. Unused CMOS outputs left unconnected. resistor must used when tying bidirectional signals power ground. When tying signal power ground, resistor will also allow system testability.
Processor System Signal Groups
simplify following discussion, processor system signals have been combined into groups buffer type. family processor system outputs open drain require high-level source provided termination resistors. However, Intel® Pentium® processor with 512KB Cache includes on-die termination AGTL signals termination resistors placed platform necessary except RESET# signal which still requires external termination. AGTL input signals have differential input buffers which VREF reference signal. AGTL output signals require termination 1.25 this document, term "AGTL Input" refers AGTL input group well AGTL group when receiving. Similarly, "AGTL Output" refers AGTL output group well AGTL group when driving. PWRGOOD signal input 1.8V signal level must pulled VCCCMOS1.8. VTT_PWRGD 1.8V tolerant must connected (1.25V). Other CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, STPCLK#) only tolerant must pulled VCCCMOS1.5. CMOS, APIC, outputs open drain must pulled appropriate level meet input specifications interfacing device. groups signals contained within each group shown Table Refer Section description these signals.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table
System Signal Groups
Group Name AGTL Input AGTL Output AGTL CMOS Input (1.25V)3 CMOS Input (1.5V)4 CMOS Input (1.8V)5 CMOS Output (1.5V)4 CMOS Output8 (3.3V) System Clock10 (1.25V/2.5V) APIC Clock9 APIC
Signals BPRI#, DEFER#, RESET#, RSP# PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#2, BR1#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#, RS[2:0]#, TRDY# VTT_PWRGD A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#, STPCLK# PWRGOOD FERR#, IERR#, THERMTRIP# VID[3:0,25mV], BSEL[1:0]
BCLK0, BCLK0# PICCLK PICD[1:0] TCK, TDI, TMS, TRST#
Input4 Output
CPUPRES#, DYN_OE, NCHTRL, PLL[2:1], SLEWCTRL, RTTCTRL7,THERMDN, THERMDP, VCCCORE, VREF, VSS, VTT, Reserved,
Power/Other6
NOTES: Section information these signals. BR0# only BREQ# signal that bidirectional. Section more information. This signal 1.25V. These signals 1.5V. This signal 1.8V. VCCCORE power supply processor core described Section 2.6. VID[3:0,25mV] described Section 2.6. used terminate system generate VREF motherboard. system ground. BSEL[1:0] described Section 2.8.2 Section 7.0. other signals described Section 7.0. This signal used control value processor on-die termination resistance. Refer platform design guide recommended pulldown resistor value. These signals 3.3V. These signals 2.0V. 1.25V signal Differential clock application 2.5V Single-ended clock application.
2.8.1
Asynchronous Synchronous System Signals
AGTL signals synchronous BCLK (BCLK/BCLK#). CMOS, Clock, APIC, signals applied asynchronously BCLK (BCLK/BCLK#). APIC signals synchronous PICCLK. signals synchronous TCK.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
2.8.2
System Frequency Select Signals
System Frequency Select Signals (BSEL [1:0]) used select system frequency Intel® Pentium® processor. BSEL signals also used chipset system clock generator. BSEL pins Intel® Pentium® processor with 512KB Cache open drain signals versus opens shorts found previous Intel® Pentium® processor FC-PGA package. Refer Table level specifications BSEL signals. BSEL signals rely 3.3V pull-up resistor signal logic high level. Similar signals described Section 2.6, VTT_PWRGD signal also informs platform that BSEL signals stable should sampled. During power-up, BSEL signals will indeterminate state small period time. chipset system clock generator should sample and/or latch BSEL signals until VTT_PWRGD signal asserted. assertion VTT_PWRGD signal indicates BSEL signals stable driven final state processor. Refer Figure power-up timing sequence VTT_PWRGD BSEL signals. Table defines possible combinations BSEL signals frequency associated with each combination. frequency selection determined processor(s) driven chipset system clock generator. system agents must operate same frequency determined processor. Intel® Pentium® processor with 512KB Cache operates 133MHz system frequency based system specified rating marked package. Over under-clocking system frequency outside specified rating marked package recommended.
Figure BSEL[1:0] Example System Design
Table
Frequency Select Truth Table BSEL[1:0]
BSEL1 BSEL0 Frequency Reserved Reserved Reserved
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Test Access Port (TAP) Connection
voltage levels supported other components Test Access Port (TAP) logic, recommended that processor first chain followed other components within system. translation buffer should used connect rest chain unless other components capable accepting input appropriate voltage. Similar considerations must made TCK, TMS, TRST#. copies each signal required with each driving different voltage level. Refer Chapter more detailed information.
2.10
Maximum Ratings
Table contains processor stress ratings only. Functional operation absolute maximum minimum implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions given timing level tables Section 2.11 through Section 2.13. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Table
Absolute Maximum Ratings
Symbol TSTORAGE VCCCORE VinAGTL VinCMOS1.5 VVID VBSEL Parameter Processor storage temperature Processor core voltage termination supply voltage with respect AGTL buffer input voltage CMOS buffer input voltage with respect BSEL current -0.3 -0.3 -0.3 1.75 1.78 2.08 Unit Notes
NOTES: Input voltage never exceed +1.78 volts. Input voltage never exceed 2.08 volts. Input voltage never below -0.3V Parameter applies CMOS, APIC, signal groups only.
2.11
Processor Voltage Level Specifications
processor voltage level specifications this section defined PGA370 socket pins (bottom side motherboard). Section processor signal descriptions Section signal listings. Most signals processor system AGTL signal group. These signals specified terminated 1.25V. voltage level specifications these signals listed Table page allow connection with other devices, clock, CMOS, APIC, signals designed interface non-AGTL levels. voltage level specifications these pins listed Table page
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table through Table list voltage level specifications Intel® Pentium® processor with 512KB Cache. Specifications valid only while meeting specifications junction temperature, clock frequency, input voltages. Care should taken read notes associated with each parameter. Table Voltage Current Specifications
Symbol VCCCORE Vcc_cmos1.5 Vcc_cmos1.8 Baseboard VCCCORE Tolerance, Static Baseboard VCCCORE Tolerance, Transient ICCCORE ICCCMOS1.5 ICCCMOS1.8 ICCCMOS3.3 IVTT ISGnt IDSLP dICCCORE/dt dIvTT/dt Processor core voltage static tolerance level PGA370 socket pins Processor core voltage transient tolerance level PGA370 socket pins processor core VccCMOS1.5 VccCMOS1.8 VccCMOS3.3 Termination voltage supply current Stop-Grant processor core Deep Sleep processor core Power supply current slew rate Termination current slew rate 1.13 1.26 1.13 1.26 Parameter processor core Static AGTL termination voltage Transient AGTL termination voltage Core Freq 1.13 1.26 1.45 1.45 1.25 1.25 Unit 1.25 ±3%, 1.25 ±9%, 10%, 10%, Notes
Please refer Figure Table Tolerance values
19.4 20.5 13.2 14.0 10.2 Please refer Table Slew Rate Table
Table
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. specifications this table apply only Intel® Pentium® processor with 512KB Cache. VccCORE IccCORE supply processor core on-die cache. must held 1.25V while AGTL active. required that held 1.25V while processor system static (idle condition). range required design target; will come from transient noise added. This measured PGA370 socket pins bottom side baseboard. These tolerance requirements, across frequency bandwidth, measured processor socket soldered-side motherboard. VCCCORE must return within static voltage specification within after transient event; DC-DC Converter Design Guidelines further details. Maximum measured typical voltage under maximum signal loading conditions. current specified also AutoHALT state. Maximum values specified design/characterization nominal VccCORE.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Based simulation averaged over duration change current. compute maximum inductance tolerable reaction time voltage regulator. This parameter tested. 10.dIcc/dt specifications measured specified PGA370 socket pins. Static voltage regulation includes: output initial voltage point adjust, Output ripple noise, Output load ranges specified tables above. DC-Dc Converter Design Guidelines. 12.Pull only.
Table
Power Supply Current Slew Rate (dIcccore/dt)
Slew Step
Slew (26A socket
socket
Slew
(uS) socket 26.23 0.15 23.18 20.03 21.10 21.88 22.29 22.30 22.07 21.78 21.58 21.51
Table contains typical slew rate data Intel® Pentium® processor with 512KB Cache. Actual slew rate values wave-shapes vary slightly depending type size decoupling capacitors used particular implementation.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table
Static Transient Tolerance
Voltage Deviation from Setting (mV) Static Tolerance Transient Tolerance
Figure Static Transient Tolerance
Droop from setting (mV) -100
Static Minimum Load Line Transient Minimum Load Line Transient Maximum Load Line Static Maximum Load Line
Load
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table AGTL Signal Group Levels Specifications
Symbol Parameter Input Voltage Input High Voltage Buffer Resistance Leakage Current inputs, outputs, VREF 0.200 16.67 ±100 VREF 0.200 Unit Notes
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. inputs, outputs, pins must comply with signal quality specifications Section 3.0. Minimum maximum given Table page 1.25 +3%) (0VOUT1.25V+3%). Refer processor Buffer Models characteristics. Steady state input voltage must above 1.65V below 1.65V. Does apply leakage current presence RTT.
Table Non-AGTL Signal Group Levels Specifications
Symbol VIL1.2 VIL1.5 VIL1.8 VIL2.0 VIH1.2 VIH1.5 VIH1.5PICD VIH1.8 VIH2.0 Output Voltage Output Current Input Leakage Current Output Leakage Current Parameter Input Voltage Input Voltage Input Voltage Input Voltage Input High Voltage Input High Voltage Input High Voltage PICD[1:0] Input High Voltage Input High Voltage -0.150 -0.36 -0.40 1.08 Vcmos_ref 0.250 Vcmos_ref 0.200 1.44 1.60 0.30 ±100 ±100 VCC_CMOS1.5 2.16 Vcmos_ref 0.300 0.36 0.40 Unit outputs open-drain Notes
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. Parameter measured (for with inputs). 1.8V +10%). VOUT 1.8V +10%). BCLK specifications, refer Table page 1.5V +10%). VOUT 1.5V +10%). Applies non-AGTL signal PWRGOOD. Applies non-AGTL signal PICCLK. 10.Applies non-AGTL signals except BCLK, PICCLK, PWRGOOD. Applies non-AGTL signal VTT_PWRGD. 12.Vcmos_ref Vcc_cmos1.5, refer Table page 13.Applies PICD[1:0].
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Volt CMOS Output Signal Group Specifications
Symbol Parameter Nominal Voltage Output High Voltage Output Leakage Current 3.45 Unit Notes
2.12
AGTL System Specifications
recommended that AGTL routed daisy-chain fashion with termination resistors VTT. These termination resistors placed electrically between ends signal traces voltage supply. valid high levels determined input buffers using reference voltage called VREF. Refer appropriate platform design guide more information Table below lists nominal specification AGTL termination voltage (VTT). AGTL reference voltage (VREF) generated system motherboard should processor other AGTL logic. important that baseboard impedance specified held ±15% tolerance, that intrinsic trace capacitance AGTL signal group traces known well-controlled. more details AGTL buffer specification, Intel® Pentium® Processor Developer's Manual AP-585, Intel® Pentium® Processor AGTL Guidelines.
Table Processor AGTL Specifications
Symbol On-die VREF Parameter Termination Voltage Termination Resistor Reference Voltage 1.1375 1.25 2/3VTT Units Notes
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. Intel® Pentium® processors with 512KB cache PGA370 socket contain AGTL termination resistors processor die, except RESET# input. must held 1.25V ±9%. required that held 1.25V while processor system idle (static condition). This measured PGA370 socket pins bottom side baseboard. Uni-processor platforms require resistor dual-processor platforms require resistor. Tolerance on-die +/-10% (56, resistors). +/-15% (100 resistors). VREF generated motherboard should nominally. Ensure that there adequate VREF decoupling motherboard.
2.13
System Timing Specifications
processor system timings specified this section defined socket pins bottom motherboard. Unless otherwise specified, timings tested processor pins during manufacturing. Timings processor pins specified design characterization. Section processor signal definitions.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table through Table list timing specifications associated with processor system bus. These specifications broken into following categories: Table contains system clock specifications single-ended clock mode operation Table contains system clock specifications differential clock mode operation. Table contains AGTL specifications, Table contains CMOS signal group specifications, Table contains timings reset conditions, Table covers APIC timing, Table covers timing. processor system timing specifications AGTL signal group relative rising edge BCLK input. AGTL timings referenced VREF both logic levels unless otherwise specified. timings specified this section should used conjunction with buffer models provided Intel. These buffer models, which include package information, available Intel® Pentium® processor with 512KB Cache FC-PGA2 package IBIS* model format. These buffer models available Intel's Developer Website (http:// developer.intel.com). AGTL layout guidelines also available appropriate platform design guide. Care should taken read notes associated with particular timing parameter.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table System Timing Specifications (Single-Ended Clock)1,4
Parameter BCLK Period average T1abs: BCLK Period Instantaneous minimum BCLK Period Stability BCLK Rise Time BCLK Fall Time BCLK High Time BCLK Time BCLK Input High BCLK Input 7.25 7.65 10.0 9.75 10.15 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. Period, jitter, offset skew measured 1.25V. Measured from 2.0V. CLKREF (BCLK#) 1.25V with tolerance. CLKREF must generated from stable source. tolerances must less than -40dB 1MHz. BCLK High Time measured above 2.0V. BCLK Time measured below 0.5V.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table System Timing Specifications (Differential Clock)1,
Parameter BCLK Period average T1abs: BCLK Period Instantaneous minimum BCLK Period Stability Vcross: Crossing point Swing BCLK Rise Time BCLK Fall Time Rise/Fall Time Matching BCLK Duty Cycle Input High Voltage Input Voltage Rising Edge Ring Back Falling Edge Ring Back 0.92 -0.2 0.35 -0.35 0.51 7.30 0.76 1.45 0.35 0.92 -0.2 0.35 -0.35 0.51 10.0 0.76 1.45 0.35 10.2 Unit Figure Notes
Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. timings AGTL signals referenced rising edge BCLK falling edge BCLK# processor pin. AGTL signal timings (address bus, data bus, etc.) referenced 1.00V processor pins. internal core clock frequency derived from processor system clock. system clock core clock ratio determined during initialization. Individual processors will only operate their specified system frequency, MHz. Table shows supported ratios each processor. difficulty accurately measuring clock jitter system, recommended that clock driver used that designed meet period stability specification into test load This should measured adjacent crossing points BCLK BCLK# which defined rising edge BCLK falling edge BCLK# processor pin. jitter present must accounted component BCLK timing skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. appropriate clock synthesizer/driver specification details Measurement taken from differential waveform, defined BCLK BCLK#. Rise time measured from -0.35 +0.35V fall time measured from 0.35V -0.35V. Measured socket pin.
Table System Timing Specifications (AGTL Signal Group)1,
Parameter AGTL Output Valid Delay AGTL Input Setup Time AGTL Input Hold Time T10: RESET# Pulse Width 0.40 0.95 1.00 1.00 3.25 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB Cache frequencies. These specifications tested during manufacturing. timings AGTL signals referenced rising edge BCLK falling edge BCLK# processor pin. AGTL signal timings (compatibility signals, etc.) referenced 0.80V processor pins.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Valid delay timings these signals specified into 1.25V, VREF with on-die RTT. minimum clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. Specification minimum 0.40 swing from VREF VREF This assumes edge rate 0.3V/ns. Specification maximum swing from 0.8V VTT. This assumes edge rate 3V/ns. This should measured after VCCCORE, VTT, VccCMOS, BCLK (and BCLK#) stable 10.BREQ signals observe 1.2nS minimum setup time.
Table System Timing Specifications (CMOS Signal Group)
Parameter T14: CMOS Input Pulse Width, except PWRGOOD T15: PWRGOOD Inactive Pulse Width Unit BCLKs BCLKs Figure Notes Active Inactive states
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies These specifications tested during manufacturing. These signals driven asynchronously. CMOS outputs shall asserted least system clocks. When driven inactive after VCCCORE, VTT, VCCCMOS, BCLK BCLK# stable.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table System Timing Specifications (Reset Conditions)
Parameter T16: Reset Configuration Signals (A[14:5]#, BR0#, INIT#) Setup Time T17: Reset Configuration Signals (A[14:5]#, BR0#, INIT#) Hold Time Unit BCLKs BCLKs Figure Notes Before deassertion RESET# After clock that deasserts RESET#
NOTE: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies.
Table System Timing Specifications (APIC Clock APIC I/O)1,
Parameter T21: PICCLK Frequency T22: PICCLK Period T23: PICCLK High Time T24: PICCLK Time T25: PICCLK Rise Time T26: PICCLK Fall Time T27: PICD[1:0] Setup Time T28: PICD[1:0] Hold Time T29a: PICD[1:0] Valid Delay (Rising Edge) T29b: PICD[1:0] Valid Delay (Falling Edge) 30.0 10.5 10.5 0.25 0.25 12.0 33.3 500.0 Unit 1.60V 0.40V (0.40V 1.60V) (1.60 0.40V) Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. These specifications tested during manufacturing. timings APIC signals referenced PICCLK rising edge processor pins. APIC signal timings referenced processor pins. Referenced PICCLK rising edge. open drain signals, valid delay synonymous with float delay. Valid delay timings these signals specified into load pulled
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table System Timing Specifications (TAP Connection)1,
Parameter T30: Frequency T31: Period T32: High Time T33: Time 60.0 25.0 25.0 16.667 Unit Vcmos_ref 0.200V, Vcmos_ref 0.200V,
Figure
Notes
T34: Rise Time
(Vcmos_ref 0.200V) (Vcmos_ref 0.200V),
T35: Fall Time
(Vcmos_ref 0.200V) (Vcmos_ref 0.200V),
T36: TRST# Pulse Width T37: TDI, Setup Time T38: TDI, Hold Time T39: Valid Delay T40: Float Delay T41: Non-Test Outputs Valid Delay T42: Non-Test Inputs Setup Time T43: Non-Test Inputs Setup Time T44: Non-Test Inputs Hold Time
40.0 14.0 10.0 25.0 25.0 25.0 13.0
Asynchronous,
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. timings signals referenced rising edge processor pins. signal timings (TMS, TDI, etc.) referenced processor pins. These specifications tested during manufacturing, unless otherwise noted. added maximum rise fall times every below 16.667 MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals operations. During Debug Port operation, normal specified timings rather than signal timings. 10.Not 100% tested. Specified design characterization.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Platform Power-On Timings2
Parameter T45: Valid Time Before VTT_PWRGD T46: Valid Time Before PWRGOOD T47: RESET# Inactive Valid Outputs T48: RESET# Inactive Drive Signals Unit BCLK BCLK Figure Notes
NOTES: signals, during their invalid states, must guarded against spurious levels from effecting platform during processor power-up sequence. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. timing these signals, please refer Table Figure
Notes: Figure through Figure following apply: Figure through Figure used conjunction with Table through Table timings AGTL signals processor pins referenced rising edge BCLK falling edge BCLK# crossing point differential clock mode rising edge BCLK BCLKVREF (1.25V) single-ended clock mode. AGTL signal timings (address bus, data bus, etc.) referenced processor pins. timings APIC signals processor pins referenced PICCLK rising edge APIC signal timings referenced processor pins. timings signals processor pins referenced rising edge signal timings (TMS, TDI, etc.) referenced processor pins.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Clock Waveform
BCLK#
Figure BCLK/BCLK#, PICCLK, Generic Clock Waveform
Vringback (rise) Vringback (fall)
diff
diff
T25, T34, (Rise T26, T35, (Fall T23, T32, (High T24, T33, (Low T22, TCK, Period) referenced 0.30V ifferential ode), 0.50V (Single-Ended ode) referenced Vref PICC referenced 0.4V. refernced 0.9V (Differental ode), 2.0V (Single-E nded ode) referenced Vref PICC refernced 1.6V BLCK crossing point rising edge BLCK falling edge BCLK# (Differential ode), BCLK refereced 1.25V (Single-Ended ode), reference 1.0V, referenced osref
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure System Valid Delay Timings
BCLK# BCLK Valid
T29a, T29b (Valid Delay) T14, (Pulse Width) NOTE: Single-Ended clock uses BCLK only, Differential clock uses BCLK BCLK#
Signal
Valid
Vref AGTL signal group; Vcmosref CMOS, APIC signal groups
Figure System Setup Hold Timings
BCLK# VCross BCLK Valid
VCross Crossing point BLCK BCLK# (Setup Time) NOTE: Single-Ended clock uses BCLK only, Differential clock uses BCLK BCLK# (Hold Time) Vref AGTL signal group; 0.75V APIC signal groups
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure System Reset Configuration Timings
BCLK# BCLK
RESET#
Configuration (A[14:5]#, BR0#, BR1#, FLUSH#, INT#)
Valid
(AGTL+ Input Hold Time) NOTE: Single-Ended clock uses BCLK only, (AGTL+ Input Setup Time) Differential clock uses BCLK BCLK# (RESET# Pulse Width) (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Setup (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Hold Time)
Figure Platform Power-On Sequence Timings
Vtt, Vref Vcmosref BSEL[1:0]
Valid
Valid
VTT_PWRGD VCC_Core BCLK# BCLK PICCLK VCC_PWRGD Configuration Inputs RESET# THERMTRIP# PICD[1:0] AGTL Outputs other CMOS Outputs other Inputs
Inactive Inactive
Valid Config
Active
Valid
Valid
Valid
Valid
Active
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Power-On Reset Configuration Timings
BCLK CORE, VTT, VREF
PWRGOOD RESET#
VIL,
VIH,
Configuration (A20M#, IGNNE#, INTR, NMI) Valid Ratio (PWRGOOD Inactive Pulse) (RESET# Pulse Width) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
765a
Figure Test Timings (TAP Connection)
TDI, Input Signal Output Signal
(All Non-Test Inputs Setup Time) (All Non-Test Inputs Hold Time) (TDO Float Delay) (TDI, Setup Time) (TDI, Hold TIme) (TDO Valid Delay) (All Non-Test Outputs Valid Delay) (All Non-Test Outputs Float Time)
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Test Reset Timings
TRST#
1.00V
TRST# Pulse Width
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Signal Quality Specifications
Signals driven processor system should meet signal quality specifications ensure that components read data properly ensure that incoming signals affect long term reliability component. Specifications provided simulation processor pins. Meeting specifications processor pins Table Table Table ensures that signal quality effects will adversely affect processor operation.
BCLK/BCLK# PICCLK Signal Quality Specifications Measurement Guidelines
Table describes signal quality specifications processor pins processor system clock (BCLK/BCLK#) APIC clock (PICCLK) signals. References made BCLK signal quality specifications also applies BCLK#. Figure describes signal quality waveform system clock processor pins.
Table BCLK (Single-Ended Clock Mode) Signal Quality Specifications Simulation Processor Pins1
Parameter BCLK BCLK BCLK Absolute Voltage Range BCLK Rising Edge Ringback BCLK Falling Edge Ringback -0.5 Unit Figure Notes
Table BCLK/BCLK# (Differential Clock Mode) PICCLK Signal Quality Specifications Simulation Processor Pins
Parameter BCLK PICCLK BCLK PICCLK BCLK Absolute Voltage Range PICCLK Absolute Voltage Range BCLK Rising Edge Ringback PICCLK Rising Edge Ringback BCLK Falling Edge Ringback PICCLK Falling Edge Ringback 0.92 1.60 -0.2 -0.4 0.35 1.60 -0.35 0.40 1.45 -0.2 0.35 0.40 1.45 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK/BCLK# PICCLK signals back after passing (rising) (falling) voltage limits. This specification absolute value.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure BCLK/BCLK#, PICCLK Generic Clock Waveform Processor Pins
AGTL Signal Quality Specifications Measurement Guidelines
Many scenarios have been simulated generate AGTL layout guidelines which available appropriate platform design guide. Refer Intel® Pentium® Processor Developer's Manual (Order Number 243502) AGTL buffer specification. Table provides AGTL signal quality specifications processor simulating signal quality processor pins. Intel® Pentium® processor with 512KB Cache maximum allowable overshoot undershoot specifications given duration time detailed Table through Table Figure shows AGTL ringback tolerance Figure shows overshoot/undershoot waveform.
Table AGTL Signal Groups Ringback Tolerance Specifications Processor Pins
Parameter Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Squarewave Ringback 0.50 ±200 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. Specifications edge rate 3V/ns. Figure generic waveform. values specified design characterization. Please Table maximum allowable overshoot. Ringback between VREF VREF VREF VREF requires flight time measurements adjusted described Intel AGTL Specifications. Ringback below VREF above VREF supported. Intel recommends simulations exceed ringback value VREF ±200 allow margin other sources system noise.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
negative value indicates that amplitude ringback above VREF. (i.e., -100 specifies signal cannot ringback below VREF mV). measured relative VREF. measured relative VREF
Figure High AGTL Receiver Ringback Tolerance
Vstart Clock
VREF VREF VREF
0.7V
Time Note: High case analogous
AGTL Signal Quality Specifications Measurement Guidelines
Overshoot/Undershoot Guidelines
Overshoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot guideline limits transitions beyond fast signal edge rates. processor damaged repeated overshoot events 1.25 tolerant buffers charge large enough (i.e., overshoot great enough). Determining impact overshoot/undershoot condition requires knowledge magnitude, pulse direction activity factor (AF). Permanent damage processor likely result excessive overshoot/undershoot. Violating overshoot/undershoot guideline will also make satisfying ringback specification difficult. When performing simulations determine impact overshoot undershoot, diodes must properly characterized. protection diodes voltage clamps will provide overshoot undershoot protection. diodes modeled within Intel buffer models clamp undershoot overshoot will yield correct simulation results. other buffer models being used characterize Intel® Pentium® processor with 512KB Cache performance, care must taken ensure that models clamp extreme voltage levels. Intel buffer models also contain capacitance characterization. Therefore, removing diodes from buffer model will impact results yield excessive overshoot/undershoot.
3.3.1
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes maximum potential difference between signal voltage reference level, (overshoot) (undershoot). While overshoot measured relative using probe (probe signal lead VSS), undershoot must measured relative VTT. This could accomplished simultaneously measuring plane while measuring signal undershoot. Today's oscilloscopes easily calculate true undershoot waveform. true undershoot waveform also obtained with following oscilloscope data file analysis: Converted Undershoot Waveform Signal_measured Note: Note: converted undershoot waveform appears positive (overshoot) signal. Overshoot (rising edge) undershoot (falling edge) conditions separate their impact must determined independently. After true waveform conversion, undershoot/overshoot specifications shown Table through Table applied converted undershoot waveform using same magnitude pulse duration specifications used with overshoot waveform. Overshoot/undershoot magnitude levels must observe Absolute Maximum Specifications listed Table through Table These specifications must violated time regardless activity system state. Within these specifications threshold levels that define different allowed pulse durations. Provided that magnitude overshoot/undershoot within Absolute Maximum Specifications (1.78V AGTL, 2.08V CMOS), pulse magnitude, duration activity factor must used determine overshoot/undershoot pulse within specifications.
3.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes total time overshoot/undershoot event exceeds overshoot/ undershoot reference voltage (Vos_ref 1.32V AGTL, 1.80V CMOS). total time could encompass several oscillations above reference voltage. Multiple overshoot/undershoot pulses within single overshoot/undershoot event need measured determine total pulse duration. Note: Note: Oscillations below reference voltage subtracted from total overshoot/undershoot pulse duration. Multiple Overshoot/Undershoot events occurring within same clock cycle must considered together event. Using worst case Overshoot/Undershoot Magnitude, together individual Pulse Durations determine total Overshoot/Undershoot Pulse Duration that total event.
3.3.4
Activity Factor
Activity Factor (AF) describes frequency overshoot undershoot) occurrence relative clock. Since highest frequency assertion AGTL CMOS signal every other clock, indicates that specific overshoot undershoot) waveform occurs EVERY OTHER clock cycle. Thus, 0.01 indicates that specific overshoot undershoot) waveform occurs time every clock cycles. specifications provided Table through Table show Maximum Pulse Duration allowed given Overshoot/Undershoot Magnitude specific Activity Factor. Each Table entry independent others, meaning that Pulse Duration reflects existence overshoot/undershoot events that magnitude ONLY. platform with overshoot/undershoot
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
that just meets pulse duration specific magnitude where means that there other overshoot/undershoot events, even lesser magnitude (note that then event occurs times other events occur). Note: Note: Activity factor AGTL signals referenced system clock frequency. Activity factor CMOS signals referenced PICCLK frequency.
3.3.5
Reading Overshoot/Undershoot Specification Tables
overshoot/undershoot specification Intel® Pentium® processor with 512KB cache simple single value. Instead, many factors needed determine what over/ undershoot specification addition magnitude overshoot, following parameters must also known: case temperature processor will operating width overshoot measured above 1.78 Activity Factor (AF). determine allowed overshoot particular overshoot event, following must done: Determine signal group that particular signal falls into. signal AGTL signal operating with 133MHz system bus, Table (133 AGTL signal group). signal CMOS signal, Table CMOS signal group). Determine maximum case temperature (Tcase) range processors that system will support. Determine Magnitude overshoot (relative VSS) Determine Activity Factor (how often this overshoot occurs?) From appropriate Specification table, read Maximum Pulse Duration allowed. Compare specified Maximum Pulse Duration signal being measured. Pulse Duration measured less than Pulse Duration shown table, then signal meets specifications. above procedure similar undershoots after undershoot waveform been converted look like overshoot. Undershoot events must analyzed separately from Overshoot events they mutually exclusive. Below example showing maximum pulse duration determined given waveform.
Table Example Platform Information
Required Information Signal Group Tcase Overshoot Magnitude Activity Factor (AF) Maximum Platform Support AGTL 1.78 Measured Value Measured overshoot occurs average every clocks Notes
Given above parameters, using Table (69oC/AF column) maximum allowed pulse duration Since measure pulse duration this particular overshoot event passes overshoot specifications, although this doesn't guarantee that combined overshoot/ undershoot events meet specifications.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
3.3.6
Determining System Meets Overshoot/Undershoot Specifications
overshoot/undershoot specifications listed following tables specify allowable overshoot/undershoot single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their parameters (duration, magnitude). While each overshoot meet overshoot specification, when total impact overshoot events, system fail. guideline ensure system passes overshoot undershoot specifications shown below. important meet these guidelines; otherwise, contact your Intel field representative. Ensure AGTL signal ever exceeds 1.78V CMOS signal ever exceeds 2.08V. only overshoot/undershoot event magnitude occurs, ensure meets over/undershoot specifications following tables multiple overshoots and/or multiple undershoots occur, measure worst case pulse duration each magnitude compare results against specifications. these worst case overshoot undershoot events meet specifications (measured time specifications) table (where AF=1), then system passes. following notes apply Table through Table
NOTES:
Overshoot/Undershoot Magnitude 1.78V(AGTL), 2.08V(CMOS) absolute value should never exceeded Overshoot measured relative VSS. Undershoot measured relative Overshoot/Undershoot Pulse Duration measured relative 1.32V AGTL 1.80V CMOS. Rinbacks below subtracted from Overshoots/Undershoots Lesser Undershoot does allocate longer larger Overshoot OEM's encouraged follow Intel provided layout guidelines. Consult layout guidelines provided specific platform design guide. values specified design characterization
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table AGTL Signal Group Overshoot/Undershoot Tolerance
Overshoot/Undershoot Magnitude 1.78 1.73 1.68 1.63 1.58 1.53 1.48 Maximum Pulse Duration Tcase (ns) 0.01 0.153 0.31 0.68 1.42 2.95 13.2 Maximum Pulse Duration Tcase (ns) 0.01 0.87 0.087 0.20 0.46
Notes: Measurements taken processor socket pins solder-side motherboard. Overshoot/Undershoot Magnitude 1.78V absolute value should never exceeded. BCLK Period 7.5nS. Figure Maximum Acceptable AGTL Overshoot/Undershoot Waveform
.1ns .3ns
Time dependent Overshoot
1.78V 1.62V 1.47V 1.32V
Vos_ref
-.15V -.30V -.46V
.1ns
.3ns
Time dependent Undershoot
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Non-AGTL Signal Quality Specifications Measurement Guidelines
There three signal quality parameters defined non-AGTL signals: overshoot/undershoot, ringback, settling limit. three signal quality parameters shown Figure nonAGTL signal group.
Figure Non-AGTL Overshoot/Undershoot, Settling Limit, Ringback
Overshoot Settling Limit
Rising-Edge Ringback
Falling-Edge Ringback
Settling Limit
Time
Undershoot
NOTE: 1.80 non-AGTL signals except BCLK, PICCLK, PWRGOOD. =2.0 PICCLK, =1.8 PWRGOOD. BCLK PICCLK signal quality detailed Section 3.1.
3.4.1
Overshoot/Undershoot Guidelines
Overshoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot guideline limits transitions beyond fast signal edge rates (see Figure non-AGTL signals). processor damaged repeated overshoot events 1.25 tolerant buffers charge large enough (i.e., overshoot great enough). Permanent damage processor likely result excessive overshoot/undershoot. Violating overshoot/undershoot guideline will also make satisfying ringback specification difficult. overshoot/undershoot guideline assumes absence diodes input. These guidelines should verified simulations without onchip protection diodes present because diodes will begin clamping 1.25 tolerant signals beginning approximately above appropriate supply below VSS. signals reaching clamping voltage, this will issue. system should rely diodes overshoot/undershoot protection this will negatively affect life components make meeting ringback specification very difficult.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table CMOS Signal Group Overshoot/Undershoot Tolerance
Maximum Pulse Duration Tcase (ns) 0.01 2.38 2.33 2.28 2.23 2.18 2.13 2.08 0.35
Overshoot/Undershoot Magnitude
Note:
undershoot guideline limits transitions exactly described AGTL signals. Figure
3.4.2
Ringback Specification
Ringback refers amount reflection seen after signal switched. ringback specification voltage that signal rings back after achieving maximum absolute value. Figure illustration ringback. Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input each receiving agent. Violations signal ringback specification allowed under circumstances non-AGTL signals. Ringback simulated with without input protection diodes that added input buffer model. However, signals that reach clamping voltage should evaluated further. Table signal ringback specifications non-AGTL signals simulations processor pins.
Table Signal Ringback Specifications Non-AGTL Signal Simulation Processor Pins
Input Signal Group Non-AGTL Signals
Transition
Maximum Ringback (with Input Diodes Present) Vcmos_ref 0.200 Vcmos_ref 0.300 1.44
Unit
Figure
Non-AGTL Signals PWRGOOD
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processors with 512KB cache frequencies. Non-AGTL signals except PWRGOOD.
3.4.3
Settling Limit Guideline
Settling limit defines maximum amount ringing receiving that signal must reach before next transition. amount allowed total signal swing (VHI -VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Signals that within their settling limit before transitioning risk unwanted oscillations which could jeopardize signal integrity. Simulations verify settling limit done either with without input protection diodes present. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Thermal Specifications Design Considerations
This chapter provides needed data designing thermal solution. However, correct thermal measuring processes, refer Intel® Pentium® processors FC-PGA2 Package Thermal Design Guide (Order Number 249660). Intel® Pentium® processor with 512KB Cache uses flip chip grid array packaging technology with Integrated Heat Spreader case temperature (Tcase) specified.
Thermal Specifications
Table provides thermal design power dissipation maximum temperatures Intel® Pentium® processor with 512KB Cache. Systems should design highest possible processor power, even processor with lower thermal dissipation planned. thermal solution should designed ensure case temperature never exceeds these specifications.
Table Intel® Pentium® processor with 512KB cache Thermal Design Power
Processor Processor Core Frequency (GHz) 1.13 1.26 Cache Size (Kbytes) Processor Power 27.9 29.5 Maximum TCASE (°C)
1.13 1.26
These values specified nominal VCCCORE processor pins. Processor power includes power dissipated processor core, cache, AGTL termination. maximum power each these components does occur simultaneously. Processor core power includes only power dissipated core die.
4.1.1
THERMTRIP# Requirement
event processor drives THERMTRIP# signal active during valid operation, both supplies processor must turned prevent thermal runaway processor. Valid operation refers operating conditions where THERMTRIP# signal guaranteed valid. time required from THERMTRIP# asserted rail nominal THERMTRIP# asserted rail nominal
Table THERMTRIP# Time Requirement
Power Rail Power Target Nominal Nominal Time required power drop seconds seconds
NOTE: Once supplies turned THERMTRIP# signal will deactivated. System logic should ensure "unsafe" power cycling occurs this deassertion.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
4.1.2
Thermal Diode
Intel® Pentium® processor with 512KB Cache incorporates on-die diode that used monitor temperature (junction temperature). thermal sensor located motherboard, stand-alone measurement kit, monitor temperature processor thermal management instrumentation purposes. Table Table provide diode parameter interface specifications. Intel® Pentium® processor with 512KB Cache uses Integrated Heat Spreader (IHS) case temperature requirement. Please Intel® Pentium® processors FCPGA2 Package Thermal Design Guide document details measuring case temperature. thermal diode should used system thermal management determining spec compliance.
Table Thermal Diode Parameters1
Symbol Parameter Forward Bias Current Diode Ideality Factor Forward Bias Current Diode Ideality Factor 1.001452 1.000807 1.007152 1.009528 1.012852 1.018249 Unit Notes
NOTES: Intel does support recommend operation thermal diode under reverse bias. Characterized with forward bias current Characterized with forward bias current ideality factor, represents deviation from ideal diode behavior exemplified diode equation: Ifw=Is(e^ ((Vd*q)/(nkT)) where saturation current, electronic charge, voltage across diode, Boltzmann Constant, absolute temperature (Kelvin). 100% tested. Specified design characterization.
Table Thermal Diode Interface
Name THERMDP THERMDN PGA370 Socket AL31 AL29 Description diode anode (p_junction) diode cathode (n_junction)
Thermal Metrology
thermal metrology Intel® Pentium® processor FC-PGA2 package should followed evaluate thermal performance proposed cooling solutions. thermal metrology contained Intel® Pentium® processors FC-PGA2 Package Thermal Design Guide.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Mechanical Specifications
Intel® Pentium® processor with 512KB Cache uses FC-PGA2 package technology. Mechanical specifications processor given this section. Section 1.1.1 complete terminology listing. processor utilizes PGA370 socket installation into motherboard. Details socket available 370-Pin Socket (PGA370) Design Guidelines.
Note:
Figure following apply: Unless otherwise specified, following drawings dimensioned inches. dimensions provided with tolerances guaranteed normal production product. Figures drawings labeled "Reference Dimensions" provided informational purposes only. Reference dimensions extracted from mechanical design database nominal dimensions with tolerance information applied. Reference dimensions checked part processor manufacturing. Unless noted such, dimensions parentheses without tolerances reference dimensions. Drawings scale.
FC-PGA2 Mechanical Specifications
following figure with package dimensions provided design heatsink clip solutions well demonstrate where pin-side capacitors will located processor. Table includes measurements these dimensions both inches millimeters.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Package Dimensions
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Intel® Pentium® processor with 512KB Cache Package Dimensions
Millimeters Symbol Minimum 3.048 0.431 2.266 0.980 30.800 30.800 Maximum 2.690 1.180 31.200 31.200 Notes Minimum 0.089 0.038 1.212 1.212 1.299 1.299 1.946 1.790 0.000 0.000 0.000 Nominal 3.302 0.483 0.120 0.017 0.100 0.130 0.019 1.954 1.810 0.700 0.700 0.035 Nominal Maximum 0.106 0.047 1.229 1.229 Notes Inches
33.000 33.000 49.428 45.466 0.000 0.000 0.000 2.540 49.632 45.974 17.780 17.780 0.889
0.508 Diametric True Position (Pin-to-Pin)
0.020 Diametric True Position (Pin-to-Pin)
NOTE: Capacitors will placed pin-side FC-PGA2 package area defined This area keepout zone motherboard designers.
Table following apply: recommended portion processor substrate mechanical reference load bearing surface thermal solutions. Parameters assume uniformly applied loads
Table Processor Case Loading Parameters
Parameter Surface Edge Corner Dynamic (max)1 Static (max)2,3 Unit
NOTES: This specification applies uniform non-uniform load. This maximum static force that applied heatsink clip maintain heatsink processor interface. Please socket manufacturer's force loading specification also ensure compliance. Maximum static loading listed here does account maximum reaction forces socket tabs pins.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure FC-PGA2 Flatness Specification
Note: Flatness specifications millimeters
Recommended Mechanical Keep-Out Zones
Figure Volumetric Keep-Out
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Component Keep-Out
Processor Markings
following figure exemplifies processor top-side markings provided identification Intel® Pentium® processor with 512KB Cache. Table lists measurements package dimensions.
Figure Side Processor Markings
GRP1LN1 GRP1LN2
GRP2LN1 GRP2LN2
Production GRP1LN1: Intel'01 (m)(c)_-_{COO} GRP1LN2: {FPO}-{S/N} GRP2LN1: {core freq}/{cache size}/{FSB}/{VID} GRP2LN2: {S-spec here}
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Processor Signal Listing
Table Table provide processor definitions. signal locations PGA370 socket used signal routing, simulation, component placement baseboard. Figure provides pin-side view Intel® Pentium® processor with 512KB Cache pin-out.
Figure Intel® Pentium® processor with 512KB Cache Pinout
DYN_OE BERR VREF1 VREF2 PICCLK VREF3 VREF4 VREF5 VREF6 REQ1 REQ4 REQ0 BPRI DEFER REQ3 LOCK HIAERR TRDY DBSY PWRGD DRDY TRST VID0 VID1
RESET2# RESET THRMDN THRMDP VID2 VttPWRGD CMOSREF VID25m VID3
BSEL1 INIT A20M
BSEL0
REQ2 THERM TRIP
STPCLK IGNNE DETECT FLUSH
IERR
FERR
BCLK#/ CLKREF PLL1
BCLK
Side View
PLL2
CTRL NCHCTRL LINT0 PICD1 PICD0 PREQ LINT1
SLEW DEP6 DEP4 VREF0 BPM1 CTRL DEP5 DEP7 DEP3 DEP1 DEP0 BPM0 DEP2 CPUPRES
BINIT
PRDY
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Signal Name
AK10 AK14 AE33 AH12 AL15 AH10 AN31 AK24 AL11 AN13 Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADS# AERR# AP0# AP1# BCLK
BCLK#/CLKREF
Table Signal Listing Order Signal Name (Continued)
AH14 AN17 AN29 AJ33 AJ31 Name BERR# BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BR1# BSEL0 BSEL1 CPUPRES# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# Signal Group AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL Input AGTL AGTL 3.3V Output 3.3V Output Power/Other AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL
Signal Group AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL CMOS Input AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL System Clock System Clock
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Signal Name (Continued)
AL27 AN19 Name D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DEP0# Signal Group AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL Input AGTL
Table Signal Listing Order Signal Name (Continued)
AF36 AN27 AC35 AE37 AL25 AL23 AE35 AG37 AG33 AK20 AK26 AK18 AH16 AH18 AL19 AL17 AK30 Name DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# DETECT DRDY# DYN_OE FERR# FLUSH# HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# NCHCTRL PICCLK PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Signal Group AGTL AGTL AGTL AGTL AGTL AGTL AGTL Power/Other AGTL Power/Other CMOS Output CMOS Input AGTL AGTL CMOS Output CMOS Input CMOS Input Power/Other CMOS Input CMOS Input AGTL Power/Other APIC Clock Input APIC APIC Power/Other Power/Other AGTL Output CMOS Input CMOS Input AGTL AGTL AGTL AGTL AGTL Reserved future Reserved future Reserved future Reserved future Reserved future
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Signal Name (Continued)
AN23 AH26 AH22 AK28 AC37 AH30 AJ35 AG35 AL33 AN35 AN37 AL29 AL31 AH28 AK32 AN25 AN33 AA37 AB34 AD32 AF34 AH24 AH32 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET# RESET2# RS0# RS1# RS2# RSP# RTTCTRL SLEWCTRL SLP# SMI# STPCLK# THERMDN THERMDP THERMTRIP# TRDY# TRST# VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE Signal Group Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future AGTL Input AGTL Input AGTL AGTL Input AGTL Input AGTL Input AGTL Input Power/Other Power/Other CMOS Input CMOS Input CMOS Input Input Input Output Power/Other Power/Other CMOS Output Input AGTL Input Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Signal Listing Order Signal Name (Continued)
AH36 AJ13 AJ17 AJ21 AJ25 AJ29 AK34 AM12 AM16 AM20 AM24 AM28 AM32 Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Signal Name (Continued)
AK22 AK36 AL35 AM36 AL37 AJ37 AK12 AB32 AC33 Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCMOS_REF 25mV VID0 VID1 VID2 VID3 VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 3.3V Output 3.3V Output 3.3V Output 3.3V Output 3.3V Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Signal Listing Order Signal Name (Continued)
AD34 AF32 AH34 AJ11 AJ15 AJ19 AJ23 AJ27 AM10 AM14 AM18 AM22 AM26 AM30 AM34 Name Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Signal Name (Continued)
AB36 AD36 AH20 AK16 AL13 AL21 AN11 AN15 Name Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Signal Listing Order Signal Name (Continued)
AA33 AA35 AN21 Name VTT_PWRGD Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Number
AA33 AA35 AA37 AB32 AB34 AB36 AC33 AC35 AC37 AD32 Name D29# D28# D43# D37# D44# D51# D47# D48# D57# D46# D53# D60# D61# DEP7# DEP3# DEP2# PRDY# A27# A30# VCCCORE VCCCORE VCCCORE A24# A23# VCCCORE A33# A20# FERR# RSP# A31# VREF5 VCCCORE Signal Group AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL Output Power/Other AGTL AGTL Power/Other Power/Other Power/Other Power/Other Power/Other AGTL AGTL Power/Other Power/Other Power/Other AGTL AGTL Power/Other Power/Other CMOS Output AGTL Input Power/Other AGTL Power/Other Power/Other
Table Signal Listing Order Number (Continued)
AD34 AD36 AE33 AE35 AE37 AF32 AF34 AF36 AG33 AG35 AG37 AH10 AH12 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AH32 AH34 AH36 Name A17# A22# VCCCORE A20M# IERR# FLUSH# VCCCORE A35# A25# VCCCORE DETECT A19# INIT# STPCLK# IGNNE# RESET# A10# BNR# REQ1# REQ2# RS1# VCCCORE RS0# THERMTRIP# SLP# VCCCORE VCCCORE A21# RESET2# Signal Group Power/Other Power/Other AGTL AGTL Power/Other CMOS Input CMOS Output CMOS Input Power/Other AGTL AGTL Power/Other Power/Other Power/Other Power/Other AGTL Power/Other CMOS Input CMOS Input CMOS Input Power/Other AGTL Input AGTL AGTL AGTL AGTL AGTL AGTL AGTL Power/Other AGTL Input Power/Other AGTL Input CMOS Output CMOS Input Power/Other Power/Other Power/Other AGTL AGTL Input
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Number (Continued)
AJ11 AJ13 AJ15 AJ17 AJ19 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AJ33 AJ35 AJ37 AK10 AK12 AK14 AK16 AK18 AK20 AK22 AK24 AK26 AK28 AK30 AK32 AK34 AK36 Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE BSEL1 BSEL0 SMI# VID3 VCCCORE VTT_PWRGD A28# A11# VREF6 A14# REQ0# LOCK# VCMOS_REF AERR# PWRGOOD RS2# Reserved VCCCORE 25mV Reserved A15# A13# Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 3.3V Output 3.3V Output CMOS Input 3.3V Output Power/Other Power/Other AGTL AGTL AGTL Power/Other AGTL Power/Other AGTL AGTL Power/Other AGTL CMOS Input AGTL Input Reserved future Input Power/Other 3.3V Output Reserved future Power/Other AGTL AGTL AGTL
Table Signal Listing Order Number (Continued)
AL11 AL13 AL15 AL17 AL19 AL21 AL23 AL25 AL27 AL29 AL31 AL33 AL35 AL37 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AM32 AM34 AM36 AN11 AN13 AN15 AN17 Name AP0# REQ4# REQ3# HITM# HIT# DBSY# THERMDN THERMDP VID0 VID2 VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VID1 DYN_OE A12# A16# AP1# BPRI# Signal Group AGTL Power/Other AGTL AGTL AGTL Power/Other AGTL AGTL AGTL Power/Other Power/Other Input 3.3V Output 3.3V Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 3.3V Output Power/Other AGTL AGTL AGTL Power/Other AGTL Power/Other AGTL Input
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Number (Continued)
AN19 AN21 AN23 AN25 AN27 AN29 AN31 AN33 AN35 AN37 Name DEFER# TRDY# DRDY# BR0# ADS# TRST# D35# VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE BINIT# D33# VCCCORE D31# D34# D36# D45# D49# D40# D59# D55# D54# D58# Signal Group AGTL Input Power/Other AGTL AGTL Input AGTL AGTL AGTL Input Input Output AGTL Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL AGTL Power/Other AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL AGTL
Table Signal Listing Order Number (Continued)
Name D50# D56# DEP5# DEP1# DEP0# BPM0# CPUPRES# VCCCORE D38# D39# D42# D41# D52# VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE D26# D25# VCCCORE VCCCORE VCCCORE VCCCORE Reserved D62# SLEWCTRL DEP6# Signal Group AGTL AGTL AGTL AGTL AGTL AGTL Power/Other Power/Other Power/Other Power/Other AGTL AGTL AGTL AGTL AGTL Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL AGTL Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved future Power/Other AGTL Power/Other AGTL
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Number (Continued)
Name DEP4# VREF0 BPM1# BP3# VCCCORE VCCCORE D32# D22# Reserved D27# VCCCORE D63# VREF1 VCCCORE VCCCORE VCCCORE VCCCORE D21# D23# BP2# D16# D19# VCCCORE VCCCORE D30# VCCCORE PICCLK PICD0 PREQ# Signal Group AGTL Power/Other AGTL AGTL Power/Other Power/Other AGTL AGTL Reserved future AGTL Power/Other AGTL Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL AGTL Power/Other AGTL Power/Other Power/Other Power/Other AGTL AGTL Power/Other Power/Other Power/Other AGTL AGTL Power/Other APIC Clock Input APIC CMOS Input
Table Signal Listing Order Number (Continued)
Name VCCCORE VREF2 D24# VCCCORE VCCCORE D13# D20# Reserved PICD1 LINT1/NMI D11# VCCCORE LINT0/INTR D14# VCCCORE Reserved Reserved NCHCTRL Reserved VCCCORE D18# VCCCORE D12# D10# Reserved Reserved Reserved D17# VREF3 VCCCORE Signal Group Power/Other Power/Other AGTL Power/Other Power/Other Power/Other AGTL AGTL Power/Other Reserved future APIC CMOS Input Power/Other AGTL AGTL Power/Other Power/Other CMOS Input AGTL AGTL Power/Other Reserved future Reserved future Power/Other Reserved future Power/Other AGTL AGTL Power/Other Power/Other Power/Other AGTL AGTL Power/Other Reserved future Reserved future Reserved future AGTL Power/Other Power/Other
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Table Signal Listing Order Number (Continued)
Name VCCCORE VCCCORE RTTCTRL VCCCORE VCCCORE D15# PLL2 BERR# VREF4 VCCCORE Signal Group Power/Other Power/Other AGTL AGTL Power/Other Power/Other Power/Other Power/Other Power/Other AGTL AGTL Power/Other Power/Other Power/Other AGTL AGTL Power/Other Power/Other Power/Other Power/Other Power/Other AGTL Power/Other Power/Other Power/Other
Table Signal Listing Order Number (Continued)
Name VCCCORE A34# VCCCORE PLL1 Reserved BCLK BR1# A32# Reserved A26#
BCLK#/CLKREF
Signal Group Power/Other AGTL AGTL Power/Other Power/Other Reserved future System Clock AGTL Power/Other AGTL Power/Other Power/Other Power/Other Reserved future AGTL Power/Other System Clock Power/Other Power/Other Power/Other AGTL AGTL Power/Other Power/Other Reserved future
VCCCORE A29# A18# VCCCORE Reserved
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Boxed Processor Specifications
Intel® Pentium® processor with 512KB Cache PGA370 socket also offered Intel® boxed processor. Intel® boxed processors intended system integrators build systems from motherboards standard components. boxed Intel® Pentium® processor with 512KB Cache will supplied with unattached heatsink. This section documents motherboard system requirements heatsink that will supplied with boxed Intel® Pentium® processor with 512KB Cache. This section particularly important OEMs that manufacture motherboards system integrators. Unless otherwise noted, figures this section dimensioned inches. Figure shows mechanical representation boxed Intel® Pentium® processor with 512KB Cache Flip Chip Grid Array (FC-PGA2) package.
Note:
Drawings this section reflect only specifications Intel® Boxed Processor product. These dimensions should used generic keep-out zone heatsinks. system designer's responsibility consider their proprietary solution when designing required keepout zone their system platform chassis. Refer Intel® Pentium® processor Thermal/ Mechanical Functional Specification further guidance. Contact your local Intel Sales Representative this document.
Figure Conceptual Boxed Intel® Pentium® processor with 512KB Cache PGA370 Socket
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
6.1.1
Mechanical Specifications
Mechanical Specifications FC-PGA2 Package
This section documents mechanical specifications boxed Intel® Pentium® processor with 512KB Cache heatsink FC-PGA2 Package. boxed processor FCPGA2 Package ships with un-attached heatsink. Figure shows mechanical representation boxed Intel® Pentium® processor with 512KB Cache PGA370 socket Flip Chip Grid Array (FC-PGA2) package. boxed processor heatsink also asymmetrical that mechanical step feature, Figure must over socket's cam. step allows heatsink securely interface with processor order meet processor's thermal requirements. dimensions boxed processor with integrated heatsink shown Figure dimensions inches. Intel® Pentium® processor with 512KB Cache uses technology termed FCPGA2. FC-PGA2 package leverages previous FC-PGA package technology used legacy Pentium® processors. FC-PGA2 package adds Integrated Heat Spreader (IHS) improve heat conduction from processor die. This solution prevent need exotic thermal solutions higher power density processors. section this document mechanical specifications PGA370 socket. Section this document also shows recommended mechanical keepout zones boxed processor heatsink assembly. Figure Figure show REQUIRED keepout dimensions boxed processor thermal solution. cooling orientation heatsink relative PGA370 socket subject change. Contact your local Intel Sales Representative documentation specific boxed heatsink orientation relative PGA370 socket. Figure shows changes package mechanicals between FC-PGA FC-PGA2 designs. Note that boxed heatsinks associated clips compatible with earlier boxed Intel® Pentium® processor heatsinks.
Figure Comparison between FC-PGA FC-PGA2 package
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Side View Space Requirements Boxed Processor
Table Boxed Processor Heatsink Spatial Dimensions
Dimensions (Inches) Heatsink Length Heatsink Height Heatsink Width Heatsink height above motherboard Keepout Zones from Heatsink 3.14 1.81 Units Inches Inches Inches Inches Inches
Figure Dimensions Mechanical Step Feature Heatsink Base
0.043
0.472
6.1.2
Boxed Processor Heatsink Weight
boxed processor thermal cooling solution will weigh more than grams.
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Thermal Specifications
This section describes cooling requirements thermal cooling solution utilized boxed processor.
6.2.1
Boxed Processor Cooling Requirements
boxed processor directly cooled with heatsink. However, meeting processor's temperature specification also function thermal design entire system ultimately responsibility system integrator. processor temperature specification found Section this document. boxed processor heatsink able keep processor temperature within specifications (see Table Section 4.1) chassis that provide good thermal management. boxed processor heatsink operate properly, critical that airflow provided heatsink unimpeded. Airflow heatsink into center sides heatsink. Airspace required around ensure that airflow through heatsink blocked. Blocking airflow heatsink reduces cooling efficiency decreases life. Figure illustrate acceptable airspace clearance heatsink. also recommended that temperature entering kept below degrees Again, meeting processor's temperature specification responsibility system integrator. processor temperature specification found Section this document.
Figure Thermal Airspace Requirement Boxed Intel® Pentium® processor with 512KB Cache Heatsinks PGA370 Socket
6.2.2
Boxed Processor Thermal Cooling Solution Clip
boxed processor thermal solution requires installation system integrator secure thermal cooling solution processor after installed 370-pin socket socket. Motherboards designed system integrators should take care consider implications clip installation potential scraping motherboard underneath 370-pin socket attach tabs. Motherboard components should placed close 370-pin socket attach
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
tabs that interferes with installation boxed processor thermal cooling solution Figure Figure show REQUIRED keepout dimensions boxed processor thermal solution.
Electrical Requirements Boxed Intel® Pentium® processor with 512KB Cache
Electrical Requirements
boxed processor's heatsink requires power supply. power cable attached will draw power from power header motherboard. power cable connector pinout shown Figure Motherboards must provide matched power header support boxed processor. Table contains specifications input output signals heatsink connector. heatsink outputs SENSE signal open-collector output) that pulses rate pulses revolution. motherboard pull-up resistor provides match motherboard-mounted speed monitor requirements, applicable. SENSE signal optional. SENSE signal used, connector should tied GND. power header baseboard must positioned allow heatsink power cable reach power header identification location should documented motherboard documentation motherboard. Figure shows recommended location power connector relative PGA370 socket. motherboard power header should positioned within 4.00 inches (lateral) power connector FC-PGA2 package.
6.3.1
Figure Boxed Processor Heatsink Power Cable Connector Description
Signal +12V SENSE Straight square pin, 3-pin terminal housing with polarizing ribs friction locking ramp. 0.100" pitch, 0.025" square width. Waldom/Molex 22-01-3037 equivalent. Match with straight pin, friction lock header motherboard Waldom/Molex 22-23-2031, 640456-3, equivalent.
Table Heatsink Power Signal Specifications
Description volt power supply current draw SENSE: SENSE frequency (motherboard should pull this appropriate with resistor) pulses revolution 10.8 13.2
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Figure Motherboard Power Header Placement Relative Boxed Intel® Pentium® processor with 512KB Cache
0.10"
4.00"
PGA370 Socket
0.10"
Pentium® Processor with 512KB Cache 1.13GHz 1.26GHz
Processor Signal Description
This section provides alphabetical listing Intel® Pentium® processor with Cache signals. tables this section summarize signals direction: output, input, I/O.
Alphabetical Signals Reference
Table Signal Description (Sheet
Name Type Description A20M# (Address-20 Mask) input signal asserted, processor masks physical address (A20#) before looking line internal cache before driving read/write transaction bus. Asserting A20M# emulates 8086 processor's address wrap-around boundary. Assertion A20M# only supported real mode. A20M# asynchronous signal. However, ensure recognition this signal following write instruction, must valid along with TRDY# assertion corresponding Write transaction. A[35:3]# (Address) signals define 236-byte physical memory address space. When ADS# active, these pins transmit address transaction; when ADS# inactive, these pins transmit transaction type information. These signals must connect appropriate pins agents processor system bus. A[35:24]# signals parity-protected AP1# parity signal, A[23:3]# signals parity-protected AP0# parity signal. active-to-inactive transition RESET#, processors sample A[35:3]# pins determine their power-on configuration. Intel® Pentium® Processor Developer's Manual details. ADS# (Address Strobe) signal asserted indicate validity transaction address A[35:3]# pins. agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop, deferred reply match operations associated with transaction. This signal must connect appropriate pins processor system agents. AERR# (Address Parity Error) signal observed driven processor system agents, used, must connect appropriate pins processor system agents. AERR# observation optionally enabled during power-on configuration; enabled, valid assertion AERR# aborts current transaction. AERR# observation disabled during power-on configuration, central agent handle assertion AERR# appropriate error handling architecture system. AP[1:0]# (Address Parity) signals driven request initiator along with ADS#, A[35:3]#, REQ[4:0]#, RP#. AP1# covers A[35:24]#, AP0# covers A[23:3]#. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high. AP[1:0]# should connect appropriate pins processor system agents. BCLK (Bus Clock) BCLK# (for differential clock) signals determines frequency. processor system agents must receive this signal drive their outputs latch their inputs rising edge BCLK. differential clocking, processor system agents must receive this signal drive their outputs latch their inputs BCLK BCLK# crossing point. external timin
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