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January 2001, this document replaces Level document known HDSL2 Evalua


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HDSL2 Evaluation System Applications LXDHDSL2-T1
January 2001, this document replaces Level document known HDSL2 Evaluation System Applications LXDHDSL2-T1.
Order Number: 249389-001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. LXDHDSL2-T1 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
HDSL2 Evaluation System Applications LXDHDSL2-T1
Contents
11.0
General Description
Features Reference Documents.9 Packing List Equipment Required Evaluation.9 Microcontroller Board 3.1.1 FPGA.12 3.1.2 Serial Interface 3.1.3 Transceiver Board Interface 3.1.4 Reset Switch 3.1.5 LEDs.13 Transceiver Board 3.2.1 HDSL2 Line Interface 3.2.2 T1/E1 Transceiver 3.2.3 Clock Oscillators.15 3.2.4 Power Supplies 3.2.5 Processor Interface 3.2.6 Digital Data Interface 3.2.7 FPGA.15 3.2.8 Pattern Display Interface Connectors Jumpers.17 Test Points Requirements Installation Operation.19 Hardware Setup Screen 4.4.1 Controls Main Screen 4.5.1 Control Buttons.21 4.5.2 Configuration 4.5.3 Status 4.5.4 Menu Selections Basic Setup Activation.26 Error Rate Testing.27 5.3.1 Mode 5.3.2 Mode 5.3.3 Mode
Overview
Hardware Description
Software Description
Test Procedures
HDSL2 Evaluation System Applications LXDHDSL2-T1
Pattern
Connector Jumper Description Cable Description Microcontroller Board Schematics Transceiver Board Schematics
Figures
LXDHDSL2-T1 Block Diagram. Evaluation System Boards Setup Screen Main Screen Load Setup Screen Save Setup Screen Typical Register Write Screen. Typical Register Read Screen Basic Test Set-up. Mode Set-Up (HDSL2 Framer Bypassed, Fireberd Digital Interface) Mode Set-Up (HDSL2 Framer Bypassed, Fireberds Digital Interfaces) Mode Set-Up (HDSL2 Framer Enabled, Fireberd Digital Interface) Mode Set-Up (HDSL2 Framer Enabled, Fireberd LIU). Pattern Set-Up 8051 Microcontroller RS232. Microcontroller FPGA. Miscellaneous HDSL2 Line Interface Circuit. DAC. SK70740 SK70741 Interface. SK70741, SK70742, LXT361 Microprocessor Interface SK70742 LXT361 Interfaces Power Transceiver FPGA. Connector
HDSL2 Evaluation System Applications LXDHDSL2-T1
Tables
Memory Mode Selection.16 MCLK Configurations Microcontroller Board Connectors.17 Transceiver Board Connectors.17 Jumpers Microcontroller Board Jumpers Transceiver Board Test Options.27 Mode Configuration.28 Fireberd Settings Mode Configuration.31 Fireberd Settings Mode Configuration.33 Fireberd Settings CON1 Microcontroller Board (CON10 Transceiver Board) Microcontroller RJ1- Serial Port Connector.37 Microcontroller Jumper.37 Microcontroller Jumper.37 T1/E1 Interface Connectors HDSL2 Line Connector.38 Pattern Display Connector Digital Data Interface.38 Power Supply Connector.38 CON1 JTAG Port SK70741 CON2 JTAG Port SK70740 CON3 JTAG Port SK70742 Jumper Configuration Jumper FPGA Port (5x2 Header).40 Jumper JP18 Line Driver Output Configuration Jumper JP22 SK70742 Configuration HDSL2 Line Cable (RJ48 plug RJ48 plug).42 Serial (COMM) Port Cable (RJ11 plug plug).42 Serial Port Cable Adapter (RJ11 socket socket) Serial Port Cable Adapter (RJ11 socket DB25 socket)
HDSL2 Evaluation System Applications LXDHDSL2-T1
HDSL2 Evaluation System Applications LXDHDSL2-T1
General Description
LXDHDSL2-T1 Evaluation system versatile tool evaluating performance Intel's HDSL2 transceiver chip applications. system includes four printed circuit boards: i8051 based Microcontroller boards Transceiver boards allowing evaluation both ends HDSL2 link. Either Transceiver/Microcontroller board configured either H2TU-C H2TU-R. Transceiver board provides data interfaces operates under software control Microcontroller board. Activation, mode selection other functions controlled monitored using HDSL2 software. This resident software operates under Windows features user-friendly graphical user interface (GUI). data interface source selectable between digital back-end line interface. Intel's LXT361 transceiver provides function. HDSL2 framer placed either framed mode unframed (framer bypass) mode. Internal registers HDSL2 chip transceiver read modified HDSL2 software. digital interface used connect Error Rate Tester (BERT). Microcontroller board draws power from Transceiver board connector.
Features
Provides end-to-end full duplex transmission evaluation Demonstrates functionality Intel's HDSL2 chip indicators show activation states digital data interface external BERT User friendly Windows based operate system pattern monitoring capability
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Figure LXDHDSL2-T1 Block Diagram
Microcontroller Board
Activation State LEDs Intel 8051
Comm Port
FPGA
Flash
RS232
Address, Data, Timing Control
MCLK
Line
LXT361
Transceiver Board
FPGA
Digital Back-End
TFSYSNC TXDATA TXCLK RFSYNC RXDATA RXCLK
DEMUX
SK70742 FEC/Framer
SK70741 Transceiver
SK70740 Analog Front
Line Driver Hybrid
RJ48
PATTERN
Telstar Chipset DGND
Power
HDSL2 Line
HDSL2 Evaluation System Applications LXDHDSL2-T1
Caution:
Overview
CMOS devices static (ESD) sensitive. Take industry standard precautions when handling Evaluation system boards, HDSL2 chip other sensitive electronic components.
Reference Documents
SK70740 Data Sheet SK70741 Data Sheet SK70742 Data Sheet Application Note AN110 (Revision 2.1) "HDSL2 System Design Chip Overview" HDSL2 White Paper Draft HDSL2 Standard (T1E1.4/99-006R4)
Packing List
Evaluation system contains following components:
Transceiver boards with Intel HDSL2 chip sets installed i8051 Microcontroller boards serial port (RJ11) cables RJ11 adapter RJ11 DB25 adapter LXDHDSL2-T1 Windows compatible software Category unshielded twisted pair cable with RJ48 connector both ends (HDSL2 line cable)
LXDHDSL2-T1 User Guide (this document) SK70740/SK70741/SK70742 chip data sheets Application Note AN110 "HDSL2 System Design Chip Overview"
Equipment Required Evaluation
Evaluation board includes circuit components needed successful evaluation. However, following additional equipment required operate Evaluation system:
Power Supplies (common both H2TU-C H2TU-R systems):
+3.3V. current +5V. current current 500mA
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Telecom cable cable simulator pattern generator/analyzer (such Fireberd 6000A with module module) Tektronics series equivalent) oscilloscope observe pattern Compatible with serial ports, Windows least memory Banana cables power supply connections interface connections coaxial cables with connectors digital interface
HDSL2 Evaluation System Applications LXDHDSL2-T1
Figure Evaluation System Boards
Microcontroller Board
NOTE: boards shown with default jumpers shipped from factory.
Transceiver Board
EYEOUT TP11 TEST8 DGND TP20 TP21 RESYNC TP16 TP14 TP12 TP13 RXCLK (BNCK) TEST6 DGND RDATA CON3 TP41 MOTO INTEL TEST3 AGND A_RRING A_RTIP A_TTIP TP38 TP31 TP30 JP22
TP15 TP18 TP17 TP19
CON1
SK70742
SK70741
TP27 TP28 TP25 TP26 TP23 TP24
BN12
TEST7 DGND
Telstar Chipset Voltage
SK70740
CON2
DGND
TFSYNC
PORT 360QE TXCLK TDATA
AGND TEST4 JP21 TTIP DRVGND JP18
LXT361
A_TRING JP12 JP20 JP13 TRING
TEST1 DRVGND
TEST2
TRIN
TTIP
RTIP
RRING
DGND
T1/E1 LINE
HDSL2 LINE
TEST5
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Hardware Description
LXDHDSL2-T1 Evaluation system consists Microcontroller boards, Transceiver boards various cables. shown Figure Microcontroller board connected Transceiver board form HDSL2 terminal (H2TU-C H2TU-R). terminals required provide complete HDSL2 Evaluation system. following paragraphs provide description Evaluation system hardware.
Microcontroller Board
Microcontroller board contains i8051 class microprocessor operating 11.0592MHz. serial interface connector (RJ11 type) provided connection Eight LEDs provided display various internal states. microprocessor executes HDSL2 chip controller code interprets commands from Microcontroller program storage consists bytes external FLASH bytes internal FLASH. board includes external byte SRAM. Switch resets microprocessor. When jumper removed, execution from internal FLASH enabled. "Microcontroller Board Schematics" page details board circuitry.
3.1.1
FPGA
FPGA generates chip selects following Transceiver board hardware: SK70741 Transceiver, SK70742 FEC/Framer, LXT361 T1/E1 LIU. Interrupts from these three devices combined FPGA drive INT1 microprocessor. FLASH EPROM read write strobes also generated FPGA. Table provides memory Evaluation system.
3.1.2
Serial Interface
serial interface connects host compatible COMM port Microcontroller board RJ11 connector (RJ1). RJ11 DB9/DB25 adapters provided with Evaluation system. Table page provides details serial interface connector RJ1.
3.1.3
Transceiver Board Interface
Microcontroller board connects Transceiver board type-C connector (CON1). microprocessor buses various FPGA signals brought this connector. Table page provides detailed description CON1. Note that CON1 Microcontroller board connects CON10 Transceiver board. Transceiver board provides 3.3V power Microprocessor board CON1. Note: must connected between select 3.3V from connector CON1.
3.1.4
Reset Switch
This momentary push-button switch (S1) resets i8051 microprocessor when pressed released.
HDSL2 Evaluation System Applications LXDHDSL2-T1
3.1.5
LEDs
Eight LEDs, labeled through display binary value current HDSL2 activation state. H2TU-C, active state. H2TU-R, active state.
Table
Memory
Device (D7-D0) Internal FLASH
Address Range (hex) 8003 through 3FFF through FFFF through 7FFF 8100 through 81FF 8200 through 82FF 8300 8400
Board Microcontroller Microcontroller Microcontroller Microcontroller Transceiver Transceiver Microcontroller Transceiver
External FLASH External SRAM SK70741 Transceiver SK70742 Framer FPGA MODE LXT361 T1/E1 Transceiver NOTE: Disabled when installed.
Transceiver Board
HDSL2 Transceiver board contains Intel's HDSL2 chipset following associated circuits components which described following paragraphs:
3.2.1
HDSL2 line interface T1/E1 transceiver Clock oscillators/crystals Power supply interface Processor interface Digital data interface FPGA pattern display interface
HDSL2 Line Interface
HDSL2 line interface includes line driver, hybrid, transformer.
3.2.1.1
Line Driver
line driver circuit uses Analog Devices AD8016 power, high output current line driver. This line driver provides excellent overall distortion performance.
LXDHDSL2-T1 HDSL2 Evaluation System Applications
first order passive filter used between SK70740 line driver minimize out-ofband noise transmit spectrum. cut-off frequency this filter nominally KHz. first-order passive filter also used RTIP/RRING inputs. cut-off frequency this filter nominally MHz. Note that optimum performance usually requires adjustment based empirical data. Also, protection circuitry should inserted line side transformer. Refer Intel application note AN79, MDSL/HDSL Line Protection Circuit.
3.2.1.2
Hybrid
Because upstream downstream spectrums overlap, input receiver consists both spectrums. hybrid network receiver input provides first order echo cancellation reduce dynamic range converter SK70740. hybrid network designed deliver received signal, scaled amplitude. This passive cancellation network also removes 20dB transmitted signal echo from receive input properly terminated line. Subsequent echo cancellation digital transceiver used fully separate upstream downstream signals.
3.2.1.3
Transformer
HDSL2 uses single 1:2.3 step-up transformer interface twisted pair line. line driver this transformer deliver over power line. TTIP/TRING outputs, 12.7 resistors used series with transformer properly match twisted pair line. Transformer specifications provided SK70740 data sheet.
3.2.2
T1/E1 Transceiver
HDSL2 Transceiver board includes Intel's LXT361 T1/E1 transceiver provide end-to-end connectivity interface. This interface used perform tests using standard test equipment such Fireberd 6000A.
3.2.2.1
LXT361
LXT361 full featured, fully integrated transceiver ISDN Primary Rate Interface long short haul applications. parallel port allows microprocessor control. LXT361 incorporates crystal-less digital jitter attenuation both transmit receive path. B8ZS/ HDB3 encoding/decoding unipolar bipolar data available. Loss signal monitoring variety diagnostic loopback modes also provided. Transmit clock data come from SK70742 Framer FPGA. MCLK switched between 1.544 2.048 through HDSL2 software. Refer Table Table configuration details.
3.2.2.2
T1/E1 Line Interface
step-up transformer used transmit path with series resistors. This configuration provides 17dB transmit return loss applications. receive side uses transformer with termination resistor. Refer LXT361 data sheet transformer specifications. Four banana jacks provided connect RTIP, RRING, TTIP, TRING signals.
HDSL2 Evaluation System Applications LXDHDSL2-T1
3.2.3
Clock Oscillators
oscillators provided source LXT361 MCLK; 1.544 2.048MHz MCLK source selected through HDSL2 software. HDSL2-T1 Evaluation system factory configured 1.544 MCLK. single 21.5 crystal oscillator provides timing reference HDSL2 chip set.
3.2.4
Power Supplies
+3.3 power supplies required. Maximum current consumption Microcontroller Transceiver board follows:
750mA +3.3 250mA 75mA 3.2.5 Processor Interface
Transceiver board communicates with Microcontroller board type-C connector (CON10). microprocessor buses various FPGA signals brought this connector. Transceiver board provides 3.3V Microcontroller board through this connector. Note that CON1 Microcontroller board connects CON10 Transceiver board.
3.2.6
Digital Data Interface
digital data interface available BNC2 through BNC7. These connectors connecting external framer test equipment, such Fireberd 6000A with "Lab Module". lines have source termination impedance
3.2.7
FPGA
FPGA functions multiplexer select MCLK source LXT361 transceiver, data source SK70742 FEC/Framer chip. Selection made through HDSL2 software. Once selected, Microcontroller board configures IO13, IO14, IO15 pins FPGA mode. Table describes various modes. Table describes IO12 which used select MCLK source. Mode selection done automatically microcontroller code depends upon system configuration described "Bit Error Rate Testing" page Note that non-standard microcontroller board used, reconfiguration necessary. Table Table FPGA also outputs data generate pattern display.
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Table
Mode Selection
IO13 IO14 IO15 Configuration Mode external T1/E1 framer mode. Connects SK70742 TSER, TFSYNC, TCLK, RSER RFSYNC RCLK pins TXDATA, TFSYNC, TXCLK, RXDATA RFSYNC RXCLK BNCs. (without re-latching data) Mode FEC-only mode. Connects SK70742 TSER, RSER HBCLK pins TXDATA, RXDATA RXCLK(BNCLK) BNCs. Mode Framed mode. Connects SK70742 TSER, TCLK, RSER RCLK pins TXDATA, TXCLK, RXDATA RXCLK BNCs. SK70742 TFSYNC input grounded. Mode Framed analog T1/E1 interface mode. Connects SK70742 TSER LXT361 RDATA pin; SK70742 TCLK LXT361 RCLK pin; SK70742 RSER LXT361 TDATA pin; SK70742 RCLK LXT361 TCLK pin. SK70742 TFSYNC input grounded. reserved future reserved future reserved future reserved future
Table
MCLK Configurations
IO12 Configuration MCLK output taken from 1.544 output (FPGA MCLK output taken from 2.048 output (FPGA
3.2.8
Pattern Display Interface
useful method monitoring activation process view pattern received signal. FEC_RX, equalized representation receive signal level generated SK70741 (pin 15), processed FPGA digital analog converter. FPGA converts this serial data into parallel data that used drive Analog Devices AD9752 TxDAC. pattern signal available BNC1 (EYEOUT). initial stages activation, level should observed. These levels correspond with signals. When third stage Tomlinson convergence reached, active state, full level signal should observed. channel oscilloscope required observe pattern. Figure shows necessary connections display pattern.
Connectors
Table summarizes connectors Microcontroller board. Table lists connectors Transceiver board. detailed descriptions, "Connector Jumper Description" page
HDSL2 Evaluation System Applications LXDHDSL2-T1
Jumpers
Table summarizes jumpers Microcontroller board. Table describes jumpers Transceiver board. detailed descriptions, "Connector Jumper Description" page
Test Points
There total test points Transceiver board. location each test point shown Figure page signal available each test point shown "Transceiver Board Schematics" page Microcontroller board test points.
Table
Microcontroller Board Connectors
Label CON1 Type Type socket RJ11 socket Description Connects Microcontroller board Transceiver board. Table page details. Connects serial communication port using RJ11 cable included with Evaluation system. Table page details.
Table
Transceiver Board Connectors
Label CON10 BN5, BN6, BN8, BN9, BN12 BNC1 BNC2 BNC7 CON1 CON3 Type Type Plug RJ48 socket Banana socket Banana socket socket socket Berg pins Description Connects Transceiver board Microcontroller board. Table describes details this connector. Connects HDSL2 line between Transceiver boards using RJ48 cable included with Evaluation system. T1/E1 interface. Table page details. Power supply interface. Table page details. Pattern Output. Table page details. Digital interface. Table page details. JTAG ports. Table page details.
Table
Jumpers Microcontroller Board
Label Type Description Selects internal external FLASH ROM. Table page details. Select operation. Table page details.
NOTE: Factory (default) jumper settings shown Figure page
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Table
Jumpers Transceiver Board
Label Type Description Intel/Motorola configuration. Table details. Enables voltage regulator from single power supply. install this jumper. Feed power supplies banana jacks shown Figure page Port FPGA programming. Table page details. VCC/2 receiver bias voltage. install this jumper. VCC/2 line driver bias voltage. install this jumper. Configures line driver output voltage. Table page details. Connects PWDN0 driver GND. install this jumper. Connects PWDN1 driver GND. install this jumper. Configures SK70742 interface Intel Motorola Table page details.
JP12 JP13 JP18 JP20 JP21 JP22
NOTE: Factory (default) jumper settings shown Figure page
HDSL2 Evaluation System Applications LXDHDSL2-T1
Software Description
Requirements
serial (COM) ports port Microcontroller board Mbytes main (RAM) memory Windows operating system Mbyte hard disk space
Installation
Insert HDSL2 software CD-ROM execute setup.exe program. Follow on-screen prompts complete installation.
Operation
Once installed, HDSL2 software clicking "HDSL2" icon.
Hardware Setup Screen
Each time HDSL2 software run, Hardware setup screen appears shown Figure This screen allows user select operating mode port associated Microcontroller/Transceiver board set. Note: Normally, Basic Test Setup shown Figure page connected before using Hardware setup screen.
4.4.1
4.4.1.1
Controls
Serial Ports
Click port that Microcontroller/Transceiver board connected
4.4.1.2
Online Button
Clicking this button, establishes communication between associated Microcontroller/Transceiver board set. After clicking Online button, Main screen appears.
LXDHDSL2-T1 HDSL2 Evaluation System Applications
4.4.1.3
Offline Button
Clicking this button, disables communication between associated Microcontroller/ Transceiver board set. Offline allows demonstration HDSL2 software without Microcontroller/Transceiver board set. After clicking Offline button, Main screen appears.
4.4.1.4
Flash
Clicking this button invokes firmware download programming utility that allows updating Flash ROM. Contact Intel availability firmware updates.
4.4.1.5
Exit Button
Clicking this button terminates operation HDSL2 software.
Figure Setup Screen
Main Screen
Main screen shown Figure From this screen, associated HDSL2 terminal (H2TU-C H2TU-R) configured, activated monitored. Main screen controls status indicators described following paragraphs.
HDSL2 Evaluation System Applications LXDHDSL2-T1
Figure Main Screen
4.5.1
4.5.1.1
Control Buttons
Configure Button
Clicking Configure button downloads parameters, shown configuration box, Microcontroller board.
4.5.1.2
Activate Button
Clicking Activate button sends command start HDSL2 activation state machine.
4.5.1.3
Deactivate Button
Clicking Deactivate button sends command deactivate HDSL2 state machine.
4.5.2
4.5.2.1
Configuration
Terminal Type
Select HTU-C HTU-R. Each HDSL2 link must different.
LXDHDSL2-T1 HDSL2 Evaluation System Applications
4.5.2.2
HDSL2 Framer
Select Enabled mode enable 1.544 Mbps signal within 1.552 Mbps HDSL2 stream. Select Disable bypass HDSL2 framer (FEC-only mode) transfer data transparently full HDSL2 line rate 1.552 Mbps. this revision software, Enabled option available.
4.5.2.3
Time Slots
this revision software, only time slots available (default).
4.5.2.4
Line Rate
this revision software, only 1.552 Mbps line rate available (default).
4.5.2.5
SK70740 Clock
this revision software, only 21.5 clock available (default).
4.5.2.6
Data Interface
Select T1/E1 Line LXT361 LIU. Select Connectors digital interface.
Note:
Unframed mode only digital data interface (BNC connectors) available.
4.5.2.7
Config
this revision software, configured operation only (default).
4.5.3
4.5.3.1
Status
Activation
Displays status data pumps. Values Inactive, Activating, Active.
4.5.3.2
Microcontroller software calculates approximate value signal noise ratio HDSL2 line updates this field. short loop should read approximately 40dB.
4.5.3.3
Pulse Attenuation
attenuation HDSL2 pulse displayed here should short loop.
4.5.3.4
TIP/RING Reversal
there TIP/RING reversal HDSL2 link, this indicator will yellow.
HDSL2 Evaluation System Applications LXDHDSL2-T1
4.5.3.5
HDSL2 Frame Sync
Framer bypass mode, HDSL2 Frame Sync indicator stays dark. HDSL2 Framed mode, indicator will turn green when HDSL2 frame sync word detected.
4.5.3.6
Serial Link
This indicator blinks indicate that serial communication between Evaluation system board functional.
4.5.3.7
T1/E1
This indicator active only when T1/E1 Line interface selected. When loss signal condition detected, indicator red.
4.5.4
4.5.4.1
Menu Selections
File Pull Down Menu Exit
Allows user exit from program.
Open
Allows user retrieve (load) previously saved configuration. Figure
Save
Allows user save current configuration. Figure
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Figure Load Setup Screen
Figure Save Setup Screen
4.5.4.2
Register Read Write Screens
registers SK70741, SK70742, LXT361 read written from pull-down menus. typical register write register read screen shown Figure Figure Refer applicable device data sheet register definitions.
HDSL2 Evaluation System Applications LXDHDSL2-T1
Figure Typical Register Write Screen
Figure Typical Register Read Screen
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Test Procedures
Basic Setup
Basic setup prepares Evaluation system Activation testing, testing, pattern observation. Figure shows connections needed complete Basic setup. Note that both Microcontroller boards identical, thus connected either Transceiver board. following step-by-step procedure complete Basic setup: Connect Microcontroller Boards Transceiver Boards create Microcontroller/ Transceiver board sets. Connect ports Microcontroller boards RJ1) using RJ11 cable appropriate adapters. Connect Transceiver boards using RJ48 cable. loop emulator real loop between HDSL2 sides shown Figure Connect power cables shown Figure Turn power supplies. sequence acceptable. Press Reset button both Microcontroller boards. Install HDSL2 software described page Select desired port click ONLINE button. Typically COM1 selected. Repeat previous steps again load software, this time select different port. Typically COM2 selected. each Main screens, select configuration H2TU-C other H2TU-R. Load previous configuration From File menu choose desired configuration. "Main Screen" page typical configuration described Table Configure each board clicking Configure button. Observe that both Microcontroller boards blinking. This indicates that serial link between Evaluation boards operating properly. Several tests performed with Evaluation system. following paragraphs provide procedures perform typical tests.
Activation
This test establishes verifies basic communication between H2TU-C H2TU-R: Complete Basic Setup procedure. "Basic Setup" page Activate H2TU-R clicking "Activate" button from Main screen. Activate H2TU-C clicking "Activate" button from Main screen. When both sides have been successfully activated, each status display will show "Active" LEDs Microcontroller board will display H2TU-C side H2TU-R side.
HDSL2 Evaluation System Applications LXDHDSL2-T1
Error Rate Testing
Evaluation system used perform testing under various loop setups. After completion Basic setup, configure activate system described above. There several options available testing shown Table described following paragraphs.
Table
Test Options
HDSL2 Framer Disabled Enabled Enabled Interface Digital using connectors Digital using connectors using banana jacks Mode1 Mode Mode Mode
NOTE: Refer Table details regarding Modes
Figure Basic Test Set-up
Microcontroller Board
Microcontroller Board
COM1
Activation State LEDs
CON1 CON10
COM2
Activation State LEDs
CON1 CON10
Supply Chipset DGND Chipset DGND
Transceiver Board
Transceiver Board
H2TU-C
H2TU-R
Supply
Supply
Loop Emulator (optional)
LXDHDSL2-T1 HDSL2 Evaluation System Applications
5.3.1
Mode
Mode HDSL2 Framer bypassed (FEC only) data passed transparently through HDSL2 chip 1.552 Mbps. wiring diagram Mode shown Figure Power supply port connections shown Figure Table shows HDSL2 software configuration Mode Fireberd settings specified Table SK70742 framer provides reference clock Fireberd's connector from Transceiver board RXCLK. shown Figure digital data sent into board shown right received board left. TDATA also sent board left order maintain link with data transmitted both directions. Figure shows another Fireberd could added test both directions.
Table
Mode Configuration
Parameter Terminal Type Framer Mode Data Interface Configuration H2TU-C side; H2TU-R other side Unframed Connectors
Table Fireberd Settings
Parameter Interface Adapter GENCLK TIMING Mode RXCLK Polarity GENCLK Polarity Setting INTF SYNC AUTO NORMAL
HDSL2 Evaluation System Applications LXDHDSL2-T1
Figure Mode Set-Up (HDSL2 Framer Bypassed, Fireberd Digital Interface)
Micrcontroller Board Micrcontroller Board
EYEOUT
Transceiver Board
EYEOUT
Transceiver Board
RESYNC
RESYNC
RXCLK (BNCK)
RXCLK (BNCK)
RDATA
RDATA
TFSYNC
TFSYNC
TXCLK
TXCLK
TDATA
TDATA
TRING
T1/E1 LINE TTIP RTIP
RRING
TRING
T1/E1 LINE TTIP RTIP
RRING
HDSL2 LINE
HDSL2 LINE
Ohms
UNIPOLAR UNBAL
DATA
DATA
Fireberd 6000A BERT with Module Data Interface
Micrcontroller Board Micrcontroller Board Transceiver Board
EYEOUT
EYEOUT
Transceiver Board
RESYNC
RESYNC
RXCLK (BNCK)
RXCLK (BNCK)
RDATA
RDATA
TFSYNC
TFSYNC
TXCLK
TXCLK
LXDHDSL2-T1 HDSL2 Evaluation System Applications
TDATA
TDATA
TRING
T1/E1 LINE TTIP RTIP RRING
TRING
T1/E1 LINE TTIP RTIP
RRING
Figure Mode Set-Up (HDSL2 Framer Bypassed, Fireberds Digital Interfaces)
HDSL2 LINE
HDSL2 LINE
Ohms UNBAL
UNIPOLAR
Ohms
UNIPOLAR UNBAL
DATA
DATA
DATA
DATA
Fireberd 6000A BERT with Module Data Interface
Fireberd 6000A BERT with Module Data Interface
HDSL2 Evaluation System Applications LXDHDSL2-T1
5.3.2
Mode
Figure shows connections Fireberd 6000A HDSL2-Framed mode using digital interface. Power supply port connections shown Figure Table shows HDSL2 software configuration Mode Fireberd settings specified Table Data transmitted from Fireberd Module Transceiver board digital interface, into HDSL2 chip then over line second Transceiver board where looped back digital interface. alternate configuration uses Fireberd 6000As, each link.
Table Mode Configuration
Parameter Terminal Type Framer Mode Data Interface Configuration H2TU-C side; H2TU-R other side Framed Connectors
Table Fireberd Settings
Parameter Interface Adapter GENCLK TIMING Mode RXCLK Polarity GENCLK Polarity SYNTH Frequency Setting SYNTH SYNC AUTO NORMAL 1544kHz
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Figure Mode Set-Up (HDSL2 Framer Enabled, Fireberd Digital Interface)
Micrcontroller Board Micrcontroller Board
EYEOUT
Transceiver Board
EYEOUT
Transceiver Board
RESYNC
RESYNC
RXCLK (BNCK)
RXCLK (BNCK)
RDATA
RDATA
TFSYNC
TFSYNC
TXCLK
TXCLK
TDATA
TDATA
TRING
T1/E1 LINE TTIP RTIP
RRING
TRING
T1/E1 LINE TTIP RTIP
RRING
HDSL2 LINE
HDSL2 LINE
Fireberd 6000A BERT with Module Data Interface
Ohms UNIPOLAR UNBAL
DATA
DATA
5.3.3
Mode
Figure shows test configuration using Fireberd 6000A using line interface unit. Power supply port connections shown Figure Table shows HDSL2 software configuration Mode Fireberd settings specified Table Data transmitted from Fireberd LXT361 LIU, into HDSL2 chip over line second Transceiver board, where looped back line. alternate configuration uses Fireberd 6000As, each link.
HDSL2 Evaluation System Applications LXDHDSL2-T1
Table Mode Configuration
Parameter Terminal Type Framer Mode Data Interface Configuration H2TU-C side; H2TU-R other side Framed Line
Table Fireberd Settings
Parameter Interface Adapter T1/FT1 Configuration Frame Code Input Result MODE GENCLK Auxiliary Parameters RXCLK Polarity GENCLK Polarity SYNTH Frequency T1/FT1 B8ZS TERM FULL SYNTH AUTO NORMAL 1544 Setting
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Figure Mode Set-Up (HDSL2 Framer Enabled, Fireberd LIU)
Micrcontroller Board Micrcontroller Board
EYEOUT
Transceiver Board
EYEOUT
Transceiver Board
RESYNC
RESYNC
RXCLK (BNCK)
RXCLK (BNCK)
RDATA
RDATA
TFSYNC
TFSYNC
TXCLK
TXCLK
TDATA
TDATA
TRING
T1/E1 LINE TTIP RTIP
RRING
TRING
T1/E1 LINE TTIP RTIP
RRING
HDSL2 LINE
HDSL2 LINE
Fireberd 6000A BERT with Module Data Interface
DATA LINK/DS0
INPUT
OUTPUT INPUT
HANDSET
T1/FT1 INTERFACE ADAPTOR
Model 41440A
Pattern
Setup connect oscilloscope Transceiver board shown Figure Activate system described "BER Mode page observe pattern oscilloscope. initial stages activation, level should observed. These levels correspond with signals. When third stage Tomlinson convergence reached, while active state, full level signal should observed.
HDSL2 Evaluation System Applications LXDHDSL2-T1
Figure Pattern Set-Up
Microcontroller Board
Transceiver Board EYEOUT BNC1 TP12
Tektronics Series
Channel
Channel
NOTES: Trigger Channel display "infinite variable persistence". Data pump must Active state.
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Connector Jumper Description
This section provides detailed information connectors jumpers used LXDHDSL2-T1 Evaluation system. Table through Table describe Microcontroller board connectors jumpers. Table through Table describe Transceiver board connectors jumpers.
Table CON1 Microcontroller Board (CON10 Transceiver Board)
CON1 (CON10) PINS 1(32) 2(31) 3(30) 4(29) 5(28) 6(27) 7(26) 8(25) 9(24) 10(23) 11(22) 12(21) 13(20) 14(19) 15(18) 16(17) 17(16) 18(15) 19(14) 20(13) 21(12) 22(11) 23(10) 24(9) 25(8) 26(7) 27(6) COLUMN CAD1 (AD1) CAD3 (AD3) CAD5 (AD5) CAD7 (AD7) (A1) (A3) (A5) (A7) (A9) CA11 (A11) CA13 (A13) CA15 (A15) CRESET (RESET) CALE (ALE) CPSEN (PSEN) IO10 (/AS) IO13 (IO13) IO16 (IO16) IO19 (IO19) IO22 (IO22) IO25 (IO25) P1.3 (nc) VCC_IN (VCC_3.3) VCC_IN (VCC_3.3) VCC_IN (VCC_3.3) VCC_IN (VCC_3.3) VCC_IN (VCC_3.3) COLUMN (GND) (GND) (GND) (GND) (GND) (GND) BOPCS (I/M) (ROM_CS) (ROM_INT) (TI_CS) (TI_INT) (QE_CS) (QE_INT) (IO8) (IO9) IO11 (IO11) IO14 (IO14) IO17 (IO17) IO20 (IO20) IO23 (IO23) IO26 (IO26) CINT (IO29) (GND) (GND) I_GCLK (nc) (GND) (GND) COLUMN CAD0 (AD0) CAD2 (AD2) CAD4 (AD4) CAD6 (AD6) (A0) (A2) (A4) (A6) (A8) CA10 (A10) CA12 (A12) CA14 (A14) C/RESET (/RESET) CWRITE (WRITE) CREAD (READ) IO12 (IO12) IO15 (IO15) IO18 (IO18) IO21 (IO21) IO24 (IO24) P1.4 (nc) (GND) VCC_IN (VCC_3.3) VCC_IN (VCC_3.3) VCC_IN (VCC_3.3) VCC_IN (VCC_3.3) VCC_IN (VCC_3.3)
NOTES: Information parenthesis applies CON10 Transceiver board. (nc) connect. ROM_INT ROM_CS interrupt chip select SK70741; TI_INT TI_CS interrupt chip select SK70742; QE_INT QE_CS interrupt chip select LXT361.
HDSL2 Evaluation System Applications LXDHDSL2-T1
Table CON1 Microcontroller Board (CON10 Transceiver Board) (Continued)
CON1 (CON10) PINS 28(5) COLUMN VCC_IN (VCC_3.3) COLUMN (GND) COLUMN VCC_IN (VCC_3.3)
29(4) 30(3) 31(2) 32(1)
VCC_IN (VCC_3.3) ALE_SCLK (nc) MOT_INT (nc) (nc)
(GND) (GND) (GND) (GND)
MODE (nc) CLKE (nc) CSDO (nc) WR_SDI (nc)
NOTES: Information parenthesis applies CON10 Transceiver board. (nc) connect. ROM_INT ROM_CS interrupt chip select SK70741; TI_INT TI_CS interrupt chip select SK70742; QE_INT QE_CS interrupt chip select LXT361.
Table Microcontroller RJ1- Serial Port Connector
Signal (data board) (data into board)
Table Microcontroller Jumper
Jumper Function Executes from external FLASH Enables execution from internal FLASH
NOTE: Factory (default) setting
Table Microcontroller Jumper
Jumper Description 3.3V selected. Connects CON1. used
NOTE: Factory (default) setting
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Table T1/E1 Interface Connectors
Label Yellow Blue TRING T1/E1 interface. RRING T1/E1 interface. TTIP T1/E1 interface. Color Signal RTIP T1/E1 interface.
Table HDSL2 Line Connector
Signal connect RING
Table Pattern Display Connector
Connector EYEOUT (BNC1) Type socket Signal EYEOUT from
Table Digital Data Interface
Connector BNC2 BNC3 BNC4 BNC5 BNC6 BNC7 Type socket socket socket socket socket socket Description TXDATA. Input TXCLK. Input TFSYNC. Input RXDATA. Output RXCLK. Output RFSYNC. Output
Table Power Supply Connector
Connector Telstar Chipset Voltage (BN5) (BN6) Description Connect +3.3 power supply. Connect power supply. Supplies power digital section Transceiver board.
HDSL2 Evaluation System Applications LXDHDSL2-T1
Table Power Supply Connector
Connector (BN8) (BN9) (BN12) Description Connect power supply. Supplies power Line driver. Connect ground power supplies. Provides ground return path digital section Connect +3.3 power supply.
Table CON1 JTAG Port SK70741
Signal TCLK TRST
Table CON2 JTAG Port SK70740
Signal TCLK TRST
Table CON3 JTAG Port SK70742
Signal TCLK TRST
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Table Jumper Configuration
OUT* OUT* OUT* Intel microprocessor NOTE: Factory (default) setting Intel microprocessor Motorola microprocessor (R/W) Intel microprocessor Motorola microprocessor (DS) Motorola microprocessor Motorola microprocessor (AS) Motorola microprocessor Intel microprocessor (WR) Motorola microprocessor Intel microprocessor (RD) Jumper Description Intel microprocessor (ALE)
Table Jumper FPGA Port (5x2 Header)
pull-up) connect pull-up) pull-up) pull-up) Signal
Table Jumper JP18 Line Driver Output Configuration
Jumper Description Connects line driver Analog applications. Note that board modifications required. Connects line driver single supply operation.
NOTE: Factory (default) setting
HDSL2 Evaluation System Applications LXDHDSL2-T1
Table Jumper JP22 SK70742 Configuration
OUT* Intel microprocessor NOTES: Factory (default) setting Motorola remove R123 R124. Figure page circuit schematic. Jumper
Description Motorola microprocessor2 Intel microprocessor Motorola microprocessor1
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Cable Description
Table HDSL2 Line Cable (RJ48 plug RJ48 plug)
RJ48 RJ48 Signal RING
Table Serial (COMM) Port Cable (RJ11 plug plug)
RJ11 RJ11 Signal
Table Serial Port Cable Adapter (RJ11 socket socket)
Signal (data board) (data into board)
Table Serial Port Cable Adapter (RJ11 socket DB25 socket)
RJ11 DB25 Signal (data board) (data into board)
AD[7.0] AD[7.0] A[7.0] A[15.8] A[7.0] AD[7.0] A[15.8] 0.1uF READ WRITE PRGFLASH EA/VP PSEN PRGFLASH PSEN PRGFLASH RESET BOPCS1 A[7.0] 74LVX373 INT0 INT1 SCLK 8051CLK A[15.8] RDFLASH WRFLASH AT29LV512-15 R-SIP_10(4.7K) BOPCS1 8051CLK RESET RESET READ WRITE 0.1uF 0.1uF 0.1uF 4.7K JUMPER 4.7K 4.7K
49.9
PROGRAM FLASH
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 PSEN ALE/P 0.1uF READ WRITE PSEN
0.1uF
C2VR8 0.1uF R-SIP_10(330) 0.1uF
0.1uF
Rin_1 Rin_2 RJ11 74LVX373 .01uF
Microcontroller Board Schematics
Rout_1 Rout_2
LTC1386CS
RESET INT0 INT1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 SCLK 8051CLK P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 MODE MODE P1.3 P1.4 BOPCS1 SCLK AT89LV52-12JC P1.3 P1.4 P1.3 P1.4
OSC(11.0592 MHz)
22uF
RESET
OSC(11.0592 MHz)
4.7K
INT0
INT0
INT1
INT1
MODE
MODE
RDFLASH
RDFLASH
Figure 8051 Microcontroller RS232
WRFLASH
WRFLASH
READ WRITE
0.1uF
Tin_1 Tin_2
RS232 Tout_1 Tout_2
CY62256V-70SNC
HDSL2 Evaluation System Applications LXDHDSL2-T1
READ WRITE VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
READ WRITE
.022uF
0.22uF
0.22uF .022uF 0.22uF
DCLK
DATA0 4.7K DATA0 DCLK
EPF10K10ATC144-2
EPC1PC8
.022uF 0.22uF .022uF .022uF 0.22uF .022uF 0.22uF 0.22uF 0.22uF .022uF .022uF 0.22uF
AD[7.0]
AD[7.0]
A[15.8]
A[15.8]
.022uF
.022uF 0.22uF
RESET
RESET
PSEN
PSEN
PRGFLASH
ALE_SCLK WR_SDI PSEN PRGFLASH
PRGFLASH READ WRITE INT1 INT0 49.9 RESET RESET SCLK INPUT3 CLK_IN1 INPUT2 8051CLK P1.3 P1.4 49.9
ALE_SCLK WR_SDI
BOPCS MOT_INT CLKE
BOPCS1
BOPCS1
BOPCS MOT_INT CLKE
Figure Microcontroller FPGA
SCLK
SCLK
8051CLK
8051CLK
BOPCS1
INT0 INT1
INT0 INT1
I_GCLK
I_GCLK
BOPCS 49.9 49.9 49.9 49.9
49.9 49.9 49.9
CINT
CINT
RDFLASH WRFLASH 49.9 49.9 49.9 C/RESET RDFLASH 49.9 BUS_EN WRFLASH
IO[26.2]
IO[26.2]
P1.3
P1.3
P1.4
P1.4
C/RESET 49.9 49.9 IO10 IO11 49.9 IO12 IO13 49.9 INPUT0 CLK_IN0 INPUT1 IO14 IO15 IO16 IO17 IO18 I_GCLK IO19 IO20 IO21 IO22 IO23 IO24 CONF_DONE nSTATUS IO25 IO26
49.9 49.9 49.9 49.9
C/RESET
RDFLASH WRFLASH
LXDHDSL2-T1 HDSL2 Evaluation System Applications
BUS_EN
BUS_EN
4.7K
4.7K
.01uF
MSEL0 MSEL1
49.9 49.9
CLKE WR_SDI 49.9 ALE_SCLK MOT_INT 49.9
DATA
DCLK
nSTATUS CONF_DONE nCONFIG
nSTATUS CONF_DONE nCONFIG DATA0 DCLK
CINT
49.9
nCASC
CINT MODE I_GCLK CINT MODE I_GCLK 0.1uF 0.1uF
A[15.8]
A[15.8]
A[7.0]
A[7.0]
AD[7.0]
AD[7.0]
PSEN 74LVX245 74LVX244 CON1B
Figure Miscellaneous
PSEN
MOT_INT CSDO
MOT_INT
CLKE
CLKE
IO[26.2] 74LVX244 74LVX244
IO[26.2]
RESET PSEN WRITE READ
CRESET CPSEN CALE CWRITE CREAD CA10 CA11 CA12 CA13 CA14 CA15
JUMPER 47uF 10uF 10uF
BUS_EN READ CAD0 CAD1 CAD2 CAD3 CAD4 CAD5 CAD6 CAD7 0.1uF 0.1uF BOPCS IO11 IO14 IO17 IO20 IO23 IO26 CINT I_GCLK CON1A CON1C CONNECTOR FEMALE VCC_IN 10uF LT1086-3.3V .01uF 0.1uF 47uF VCC_IN 0.1uF CAD1 CAD3 CAD5 CAD7 CA11 CA13 CA15 CRESET CALE CPSEN IO10 IO13 IO16 IO19 IO22 IO25 P1.3 VCC_IN CAD0 CAD2 CAD4 CAD6 CA10 CA12 CA14 C/RESET CWRITE CREAD IO12 IO15 IO18 IO21 IO24 P1.4 ALE_SCLK MOT_INT CONNECTOR FEMALE MODE CLKE CSDO WR_SDI CONNECTOR FEMALE
READ
READ
WRITE
WRITE
RESET
RESET
ALE_SCLK WR_SDI
ALE_SCLK WR_SDI
BOPCS
BOPCS
C/RESET
C/RESET
BUS_EN
BUS_EN
P1.3
P1.3
P1.4
P1.4
.01uF
VCC_IN
HDSL2 Evaluation System Applications LXDHDSL2-T1
R104 C191 AD8016 R131 TXTIP 0.01uF R106
R107
C174 270pF NVCC R108 TXRING Pulse Fascia
R109 R110 AD8016 12.7 H27650-A R111 C192 0.01uF PVCC C195 100nF C196 10nF R113 JP20 JP21 BIAS PWDN0 PWDN1 AD8016 R112
A_TRING
LXDHDSL2-T1 HDSL2 Evaluation System Applications
Transceiver Board Schematics
PVCC
C193 10uF
C194 100nF
MIDCOM 50730
C211 1800pF RTIP A_RTIP A_RRING RRING C201 1800pF AVCC_5 RTIP JP18 JP12 VCCby2 JUMPER R117 JP13 VCCby2 R118 JUMPER C202 1800pF C215 1800pF PVCC R105 12.7 AVCC_12 C181 .01uF C182 0.1uF C180 C190 0.01uF RRING C214 C178 .01uF C179 0.1uF C177 R115 HEADER 82pF C213 0.01uF C212
PVCC
4.7V ZENER
R114
R116
4.7V ZENER
NVCC
Figure HDSL2 Line Interface Circuit
A_TTIP
1:2.3
RJ48
AVDD DVDD
IOUTA IOUTB ICOMP SLEEP C209 0.1uF R128 C207 20pF R129
C208 20pF
DAC_DAT11 DAC_DAT10 DAC_DAT9 DAC_DAT8 DAC_DAT7 DAC_DAT6 DAC_DAT5 DAC_DAT4 DAC_DAT3 DAC_DAT2 DAC_DAT1 DAC_DAT0 DB11 DB10 R136 CLOCK REFLO REFIO FS_ADJ ACOM DCOM 0.1uF R125 AD9752
TLE2141A
DAC_SEL
Developer Manual Figure
VCC_5 VCC_5 10uF R135 R126 R127 49.9 0.1uF 0.1uF 10uF C206 0.1uF 10uF TP11
DAC_DAT[11.0]
HDSL2 Evaluation System Applications LXDHDSL2-T1
0.1uF 0.1uF 0.1uF TP16 AVCC_5 0.1uF REF_CLK TP22 24.83 APOLLO_OSC 56pF R134 AVCC_5 VCC_2.5 R121 R122 VCC_2.5 RSDI RSDO 56pF TP20 TP21 49.9 .01uF 0.1uF .01uF TP14 .01uF
TP15 TP17 TP18 TP19 DAC0 DAC1 DAC2 DAC3 RBIAS 15.0K DAC0 DAC1 DAC2 DAC3
TCLK DVCC TDVCC RDVCC IOVCC1 IOVCC2 AVCC1 AVCC2
SK70740
R_TDO R_TDI R_TMS R_TCLK R_TRST DGND TDGND RDGND IOGND1 IOGND2 AGND1 AGND2
CON2
LXDHDSL2-T1 HDSL2 Evaluation System Applications
10uF 10uF .01uF 0.1uF 0.1uF DAC0 DAC1 DAC2 DAC3 A_RTIP A_RRING .01uF 0.1uF
A_TDO A_TDI A_TMS A_TCLK A_TRST
0.1uF 0.1uF 0.1uF VCC1 VCC2 VCC_PLL IOVCC1 IOVCC2 IOVCC3 0.1uF
0.1uF
DAC0 DAC1 DAC2 DAC3 RTIP
BVCC RVCC4 RVCC3 RVCC2 RVCC1 TVCC1 TVCC2 TVCC3 TVCC4
BGND RGND4 RGND3 RGND2 RGND1 TGND1 TGND2 TGND3 TGND4
GND1 GND2 GND_PLL
4.7K SK70741 4.7K
4.7K
IOGND1 IOGND2 GNDIO3 GND,
VCC_5 VCC_2.5 VCC_2.5 FCLK FEC_RX FCLK FEC_RX 10uF 10uF A_TTIP A_TRING TP12 TP13 A_TTIP A_TRING
FEC_TX
FEC_TX
A_RTIP
A_RTIP
A_RRING
A_RRING
AVCC_5
.01uF .01uF 0.1uF .01uF 0.1uF .01uF 0.1uF FCLK FEC_TX FEC_RX FCLK FEC_TX FEC_RX HSYM BCLK REF_CLK EXT_CLK ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 SK70741
10uF
A_TDI A_TDO A_TMS A_TCLK
Figure SK70740 SK70741 Interface
JTAG PORT
A_TRST TRST
CON1 TP23 TP24 TP25 TP26 TP27 TP28
HEADER 10uF
HEADER
.01uF 0.1uF .01uF 0.1uF
0.1uF .01uF 0.1uF
.01uF
TRST TCLK IO_CTL SCEN
REFCLK ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 TTIP RRING TRING VREF RBAS SK70740
REF_CLK ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 A_TTIP A_TRING
TP29
R_TRST R_TDI R_TDO R_TMS R_TCLK
IO_CTL
C210 0.1uF 24.9K
0.47uF
AD[7.0]
AD[7.0]
A[6.0] VCC_3.3
TI_CS TI_INT
4.7K 4.7K 4.7K ROM_INT TI_INT QE_INT QE_INT ROM_INT TI_INT ROM_INT SK70741 VCC_3.3 4.7K /WR, /RD, /INT /RST SK70742 JP22 HEADER TST0 TST1 R124 R123 4.7K TST0 TST1 VCC_3.3 HEADER
A[6.0]
WRITE READ ROM_CS
/RESET
TP30
TP31
Figure SK70741, SK70742, LXT361 Microprocessor Interface
4.7K
4.7K
QE_CS QE_INT
ALE,
LXT361QE
HDSL2 Evaluation System Applications LXDHDSL2-T1
0.1uF
0.1uF 0.1uF
0.1uF 0.1uF
0.1uF
FCLK FEC_TX FEC_RX /FCE FCLK FEC_TX FEC_RX HRSYNC RCLK RFSYNC RSER
VCC_CK
VCC1 VCC2 VCC3 VCC4 VCC5
MCTL
GND_CK
GND1 GND2 GND3 GND4 GND5 GND,TST0 GND,TST1
Figure SK70742 LXT361 Interfaces
R133
TP36 TP37 TP38 TP39 TP40 TP41
F_RCLK T_RCLK MCLK YELLOW PE-64936 LXT361QE F_RSER T_RSER INSBPV RTIP YELLOW MCLK TCLK TDATA INSBPV
TVCC
TGND
FEC_TX VCC_2.5 10uF TP32 TP33 TP34 TP35 FEC_TX HRSYNC T_RCLK T_RFSYNC T_RSER T_TDI T_TMS 49.9 VCC_PLL GND_PLLA SK70742 2.2uF HSCLK HBCLK VCC_2.5 /TRST GND_PLLP T_TDO TTCLK T_TRST 0.1uF 10nF T_TDO T_TDI T_TMS TTCLK T_TRST HTSYNC TFSYNC TCLK TSER HTSYNC T_TFSYNC T_TCLK T_TSER HSCLK HBCLK SK70742 R132 VCC_5 QE_RCLK RDATA 0.1uF 0.1uF RCLK RDATA TTIP RRING TRING 470pF BLUE PE-65351 68uF QE_RCLK RDATA QE_RCLK RDATA BLUE
FCLK FEC_RX
FCLK FEC_RX
CON3
HEADER
LXDHDSL2-T1 HDSL2 Evaluation System Applications
F_RCLK F_RSER MCLK INSBPV
F_RCLK F_RSER MCLK INSBPV
VCC_5
Developer Manual Figure Power
+3.3V (1.5A)
LT1086CT
10uF
100uF
10uF 100uF
+2.5V (1.5A)
LT1086CT
HEADER
VCC_3.3
VCC_2.5
VCC_5
FERRITE BEAD
AVCC_5
AVCC_12
BN12
SMBJ3.3
C203 100uF
C204 0.1uF
C205 .01uF
SMBJ5.0
C101 100uF
C105 0.1uF
C106 .01uF
SMBJ6.5
C102 100uF
C107 0.1uF
C108 .01uF
C103 100uF
C109 0.1uF
C110 .01uF
SMBJ12 FERRITE BEAD
C104 100uF
C111 0.1uF
C112 .01uF
BLACK
INSTALL
HDSL2 Evaluation System Applications LXDHDSL2-T1
HBCLK HSCLK HTSYNC HRSYNC T_RCLK T_RSER T_RFSYNC C119 .022uF VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO MCLK INSBPV F_RCLK F_RSER FEC_RX T_RCLK QE_RCLK FCLK MCLK INSBPV F_RCLK F_RSER C120 0.22uF C121 .022uF C122 0.22uF C123 .022uF C124 0.22uF C125 .022uF C126 0.22uF C127 .022uF C128 0.22uF C129 0.22uF C130 .022uF C131 0.22uF C132 .022uF VCCINT VCCINT TXDATA TXCLK F_TFSYNC RXDATA RXCLK F_RFSYNC 109G 107G 49.9 49.9 49.9 144I 141I 139I OE2/GCLK2 INPUT/GCLKRn INPUT/OE1 INPUT/GCLK1
BNC5
BNC6
TXDATA
TXCLK
F_TFSYNC
BNC7
BNC5 BNC6 BNC7
EPM7256ATC100-7
RXDATA RXCLK F_RFSYNC BNC2 49.9 49.9 49.9 BNC3 BNC4 BNC5 49.9 BNC6 49.9 BNC7
49.9
74HC244
INPUTS
OUTPUTS
DAC_SEL DAC_SEL DAC_DAT[11.0] VCC_3.3 DAC_DAT[11.0] VCC_3.3 T_TSER T_TCLK T_TFSYNC T_TSER T_TCLK T_TFSYNC
FCLK FEC_RX
FCLK FEC_RX
HBCLK HSCLK HTSYNC HRSYNC T_RCLK T_RSER T_RFSYNC
Figure Transceiver FPGA
RDATA QE_RCLK
RDATA QE_RCLK
IO11 IO12 IO13 IO14 IO15
IO11 IO12 IO13 IO14 IO15
DAC_SEL DAC_DAT0 DAC_DAT1 VCC_5 C116 0.1uF 49.9 1MHz R103 49.9 2MHz HBCLK HSCLK HTSYNC HRSYNC 1MHz 2MHz VCC_5 C117 0.1uF 118H 115H 113H 184L 185L 187L DAC_DAT9 49.9 DAC_DAT10 49.9 DAC_DAT11 49.9
105G 104G 131I 129I 208M 206M 203M 201M 195M
IO11 IO12 IO13 IO14 IO15
VCC_5
DAC_DAT2 DAC_DAT3 DAC_DAT4 DAC_DAT5 DAC_DAT6 DAC_DAT7 DAC_DAT8 128H 125H
49.9 49.9 49.9 49.9 49.9 49.9 49.9
PORT
221N 219N 216N 211N 160J 155J
149J 147J 145J 173K 171K
RDATA 49.9 R100 49.9 49.9 49.9 49.9 49.9 49.9 256P MCLK INSBPV F_RCLK F_RSER
LXDHDSL2-T1 HDSL2 Evaluation System Applications
HEADER
189L 192L 241P 243P 245P 246P
168K 163K 240O 237O 235O 233O 232O
R101 R102 T_RFSYNC T_RSER
T_TFSYNC T_TCLK T_TSER
VCC_5
C118 0.1uF
CON10B AD[7.0] A[6.0] TEST1 TEST3 TEST2 TEST4 /RESET AD[7.0]
Figure Connector
VCC_3.3
A[6.0] /RESET TEST5 TEST6 TEST7 TEST8 CON10C READ WRITE READ WRITE ROM_CS TI_CS QE_CS ROM_CS TI_CS QE_CS IO29 IO26 IO23 IO20 IO17 IO14 IO11 QE_INT QE_CS TI_INT TI_CS ROM_INT ROM_CSB25 Male DINN IO11 IO12 IO13 IO14 IO15 CON10A VCC_3.3 IO24 IO21 IO18 IO15 IO12 READ WRITE /RESET Male DINN IO11 IO12 IO13 IO14 IO15 IO25 IO22 IO19 IO16 IO13 PSEN RESET Male DINN
ROM_INT
ROM_INT
TI_INT
TI_INT
QE_INT
QE_INT
HDSL2 Evaluation System Applications LXDHDSL2-T1

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