SST37VF512 SST37VF010 SST37VF020 SST37VF040 SST37VF512 0402.7V-Re
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Kbit Mbit Mbit Mbit (x8) Many-Time Programmable Flash
SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF512 0402.7V-Read 512Kb (x8) flash memories
FEATURES:
Organized 128K 256K 512K 2.7-3.6V Read Operation Superior Reliability Endurance: least 1000 Cycles Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Fast Read Access Time: Latched Address Data Fast Byte-Program Operation: Byte-Program Time: (typical) Chip Program Time: seconds (typical) SST37VF512 seconds (typical) SST37VF010 seconds (typical) SST37VF020 seconds (typical) SST37VF040 Electrical Erase Using Programmer Does require source Chip-Erase Time: (typical) CMOS Compatibility JEDEC Standard Byte-wide Flash EEPROM Pinouts Packages Available 32-pin PLCC 32-pin TSOP (8mm 14mm) 32-pin PDIP
PRODUCT DESCRIPTION
SST37VF512/010/020/040 devices 128K 256K 512K CMOS, Many-Time Programmable (MTP), cost flash, manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST37VF512/010/020/040 electrically erased programmed least 1000 times using external programmer, e.g., change contents devices inventory. SST37VF512/010/020/040 have erased prior programming. These devices conform JEDEC standard pinouts byte-wide flash memories. Featuring high performance Byte-Program, SST37VF512/010/020/040 provide typical Byte-Program time Designed, manufactured, tested wide spectrum applications, these devices offered with endurance least 1000 cycles. Data retention rated greater than years. SST37VF512/010/020/040 suited applications that require infrequent writes power nonvolatile storage. These devices will improve flexibility, efficiency, performance while matching cost nonvolatile applications that currently UV-EPROMs, OTPs, mask ROMs. meet surface mount conventional through hole requirements, SST37VF512/010/020/040 offered 32-pin PLCC, TSOP PDIP packages. Figures pinouts.
Device Operation
SST37VF512/010/020/040 devices nonvolatile memory solutions that used instead standard flash devices in-system programmability required. functionally (Read) compatible with industry standard flash products.The device supports electrical Erase operation external programmer.
Read
Read operation SST37VF512/010/020/040 controlled OE#. Both have system obtain data from outputs. Once address stable, address access time equal delay from output (TCE). Data available output after delay from falling edge OE#, assuming been addresses have been stable least TOE. When high, chip deselected standby current only (typical) consumed. output control used gate data from output pins. data high impedance state when either VIH. Refer Figure timing diagram.
©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Byte-Program Operation
SST37VF512/010/020/040 programmed using external programmer. programming mode activated asserting (±5%) pin. device programmed using single pulse (WE# low) byte. Using programming algorithm, Byte-Program process continues byte-bybyte until entire chip been programmed. Refer Figure flowchart Figure timing diagram.
Product Identification Mode
Product Identification mode identifies devices SST37VF512, SST37VF010, SST37VF020, SST37VF040 manufacturer SST. This mode accessed hardware method. activate this mode, programming equipment must force (12V±5%) address identifier bytes then sequenced from device outputs toggling address line details, Table hardware operation. TABLE PRODUCT IDENTIFICATION
Chip-Erase Operation
only change data from electrical erase that changes every device "1". SST37VF512/010/020/040 electrical Chip-Erase operation. entire chip erased (WE# low). order activate erase mode, (±5%) applied pins while low. other address data pins "don't care". falling edge will start Chip-Erase operation. Once chip been erased, bytes must verified FFH. Refer Figure flowchart Figure timing diagram.
Manufacturer's Device SST37VF512 SST37VF010 SST37VF020 SST37VF040
Address 0000H 0001H 0001H 0001H 0001H
Data
T1.2
Design Considerations
SST37VF512/010/020/040 should have 0.1µF ceramic high frequency, inductance capacitor connected between GND. This capacitor should placed close package terminals possible. must remain stable entire duration Erase operation. must remain stable entire duration Program operation.
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer Y-Decoder
Control Logic
Buffers
B1.1
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF040 SST37VF020 SST37VF010 SST37VF512
SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF040 SST37VF020 SST37VF010 SST37VF512
32-pin PLCC View
F02a.2
FIGURE ASSIGNMENTS 32-PIN PLCC
SST37VF040 SST37VF020 SST37VF010 SST37VF512
SST37VF512 SST37VF010 SST37VF020 SST37VF040
F01.0
Standard Pinout View
FIGURE ASSIGNMENTS 32-PIN TSOP (8MM
©2001 Silicon Storage Technology, Inc.
14MM)
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF040 SST37VF020 SST37VF010 SST37VF512 32-pin PDIP View
SST37VF512 SST37VF010 SST37VF020 SST37VF040
F02b.1
FIGURE ASSIGNMENTS 32-PIN PDIP TABLE DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Name Address Inputs Data Input/output Chip Enable Write Enable Output Enable Power Supply Ground Connection Unconnected pins.
T2.1
Functions provide memory addresses. output data during Read cycles receive input data during Program cycles. outputs tri-state when high. activate device when low. program erase (WE# pulse during Program Erase) gate data output buffers during Read operation when provide 3.0V supply (2.7-3.6V)
Most significant address SST37VF512, SST37VF010, SST37VF020, SST37VF040
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet TABLE OPERATION MODES SELECTION
Mode Read Output Disable Standby Chip-Erase Byte-Program Program/Erase Inhibit Product Identification DOUT High High High High High DOUT Manufacturer's (BFH) Device Address AMS2 VIL, AMS2 VIL,
T3.1
Device SST37VF512, SST37VF020, SST37VF020, SST37VF040 Most significant address SST37VF512, SST37VF010, SST37VF020, SST37VF040 Note: case 12V±5%
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V 0.5V Transient Voltage (<20 Ground Potential -1.0V 1.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Through Hold Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Ambient Temp +70°C 2.7-3.6V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet TABLE READ MODE OPERATING CHARACTERISTICS VDD=2.7-3.6V +70°C (Commercial))
Limits Symbol Parameter Read Current VIHC Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage Supervoltage Current Read-ID VDD-0.3 VDD-0.3 Units Test Conditions Address input=VIL/VIH, f=1/TRC VDD=VDD CE#=OE#=VIL, I/Os open CE#=VIHC, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD CE#=OE#=VIL, A9=VH
T4.3
TABLE PROGRAM/ERASE OPERATING CHARACTERISTICS VDD=2.7-3.6V
Limits Symbol Parameter Erase Program Current Input Leakage Current Output Leakage Current Supervoltage Supervoltage Current Units Test Conditions 11.4 12.6
25°C±5°C)
CE#=VIL, OE#=VH, VDD=VDD Max, WE#=VIL VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD OE#=VH Max, A9=VH Max, VDD=VDD Max,
T5.1
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T6.1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T7.0
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 10,000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T8.3
This parameter measured only initial qualification after design process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 2.7-3.6V
+70°C (Commercial))
SST37VF512-70 SST37VF010-70 SST37VF020-70 SST37VF040-70 Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
SST37VF512-90 SST37VF010-90 SST37VF020-90 SST37VF040-90 Units
T9.2
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS 2.7-3.6V 25°C±5°C)
Symbol TCES TCEH TPRT TVPS TVPH TART TA9S TA9H Parameter Byte-Program Time Setup Time Hold Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Rise Time Program Erase Setup Time Program Erase Hold Time Program Erase Program Pulse Width Erase Pulse Width OE#/A9 Recovery Time Erase Rise Time during Erase Setup Time during Erase Hold Time during Erase Units
T10.0
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
ADDRESS
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TCLZ
DATA VALID
F03.0
FIGURE READ CYCLE TIMING DIAGRAM
ADDRESS (EXCEPT
TCEH
DQ7-0 TART TA9H TCES
F04.0
TVPS TVPH TPRT TA9S
FIGURE CHIP-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
ADDRESS
ADDRESS VALID
TCEH
DQ7-0
HIGH-Z
DATA VALID
TVPS TPRT
TVPH
TCES
F05.0
FIGURE BYTE-PROGRAM TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F06.1
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
F07.1
FIGURE TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Start
Erase 100ms pulse (WE# VIL)
OE#/A9
Wait Recovery Time
Read Device
Compare bytes
Device Passed
Device Failed
F08.0
FIGURE CHIP-ERASE ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Start
Erase*
Address First Location; Load Data
Program 10µs pulse (WE# VIL)
Increment Address
Last Address?
Wait
Read Device
Compare bytes original data
Device Passed
Device Failed
F09.1
*See Figure
FIGURE BYTE-PROGRAM ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet Device SST37VFxxx Speed Suffix1 Suffix2 Package Modifier pins Numeric modifier Package Type PLCC TSOP (die (8mm 14mm) PDIP Operating Temperature Commercial +70°C Minimum Endurance 1000 cycles Read Access Speed Device Density Kilobit Megabit Megabit Megabit
SST37VF512 Valid combinations SST37VF512-70-3C-NH SST37VF512-90-3C-NH SST37VF512-70-3C-WH SST37VF512-90-3C-WH SST37VF512-90-3C-PH
SST37VF010 Valid combinations SST37VF010-70-3C-NH SST37VF010-90-3C-NH SST37VF010-70-3C-WH SST37VF010-90-3C-WH SST37VF010-90-3C-PH
SST37VF020 Valid combinations SST37VF020-70-3C-NH SST37VF020-90-3C-NH SST37VF020-70-3C-WH SST37VF020-90-3C-WH SST37VF020-90-3C-PH
SST37VF040 Valid combinations SST37VF040-70-3C-NH SST37VF040-90-3C-NH
Example:
SST37VF040-70-3C-WH SST37VF040-90-3C-WH
SST37VF040-90-3C-PH
Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
PACKAGING DIAGRAMS
VIEW
.485 .495 .447 .453 .042 .048
SIDE VIEW
.106 .112 .020 MAX. .023 .029 .030 .040
BOTTOM VIEW
Optional Identifier
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400
.490 .530
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
Note:
Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches. 32.PLCC.NH-ILL.2 Coplanarity: mils.
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
Identifier
1.05 0.95
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
32.TSOP-WH-ILL.4
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05) Maximum allowable mold flash 0.15mm package ends, 0.25mm between leads.
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
14MM
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
.600 .625
Identifier
.065 .075
1.645 1.655 PLCS.
.530 .550
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600
.070 .080
.045 .065
.016 .022
.100
Note:
Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .010 inches.
32.pdipPH-ILL.2
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) PACKAGE CODE:
©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com
©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01
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