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LXD332 Evaluation Board T1/E1 Applications
January 2001, this document replaces Level document known LXD332 Evaluation Board T1/E1 Applications.
Order Number: 249220-001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. LXD332 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
LXD332 Evaluation Board T1/E1 Applications
Contents
General Description
Features Design Evaluation 1.2.1 Equipment Requirements Typical Connections Typical Setup 1.4.1 Additional Setup Configurations Typical Setup 1.5.1 Additional Setup
Figures
LXD332 Evaluation Board Basic Test Setup Demo Board Schematic Diagrams (Sheet Demo Board Schematic Diagrams (Sheet Demo Board Schematic Diagrams (Sheet Demo Board Schematic Diagrams (Sheet Demo Board Schematic Diagrams (Sheet
Tables
On-Board Jumper Settings.9 Switch Settings. Setting LENxn Bits Needed Receive Cable Length Settings Targeted Return Loss Cable On-Board Jumper Settings.11 Switch Settings.11 Output Combinations
LXD332 Evaluation Board T1/E1 Applications
Evaluation Board T1/E1 Applications LXD332
General Description
LXD332 Evalution Board versatile evaluation tool engineers involved designing short-haul applcations.It LXT332 Dual Line Interface Unit incorporates supporting circuitry either E1applications. Evaluation Board provides banana jacks line interface connectors framer interface. error tester (bert) framer/mux used provide external signal needed evaluation. This document describes typical Evaluation Board setup procedures both (North American) (European) environments. Before using Evaluation Board, review current LXT332 data sheet complete information about this transceiver. Evaluation Board schematic also available.
Features
Board design permits quick setup, ease clear visibility application settings
Local dual testing Complete system evaluation Individual circuit isolation
Exploits crystal-less jitter attenuation dual Jitter attenuation switchable into transmit, receive, data bypass path twisted-pair line interfaces related digital signals available analysis testing Banana jacks twisted-pair line interface connectors clock framer interface LEDs indicators Design supports both evaluation Switches emulate stand-alone Hardware Mode
LXD332 Evaluation Board T1/E1 Applications
Figure LXD332 Evaluation Board
Design Evaluation
LXT332 Demo Board supports design evaluation LXT332 Dual Line Interface Unit. Using Demo Board, variety front circuit options tested evaluated. Demo Board also provides convenient pre-tested front circuit which allows design engineers verify back circuit designs. However, setup descriptions this document focus dual front-end. Figure shows typical test setup basic front testing. Additional test setups framer interface accomplished using connectors Demo Board. Follow operations described here become familiar with basic test configuration. Once setup complete, wide variety tests performed evaluate system designs.
Evaluation Board T1/E1 Applications LXD332
Figure Basic Test Setup
1.2.1
Equipment Requirements
LXD332 Demo Board includes circuit components needed successful evaluation. However, following additional equipment required:
Power Supply VDC) Twisted-Pair Cable Cable Length Simulator Coax Cables WBNC Terminators Signal Source. Error Rate Tester (BERT) Clock Source (1.544 2.048
LXD332 Evaluation Board T1/E1 Applications
Typical Connections
Before proceeding, with Demo Board operations, review specifications LXT332 transceiver. Refer Figure cable configuration.
Caution:
CMOS devices static (ESD) sensitive. Take industry standard precautions when handling Demo Board, chip other electronic components. Power Supply VDC). Connect volts banana jack. Connect ground lead banana jack. This provides both safety (earth) signal (reference) ground functions. Ammeter. Ficure shows ammeter connected JPI3. This optional test point. Several jumpers (JP5, JP6, JP7, JPI3) built into Demo Board which allow test engineer isolate sections circuit measure current voltage values. circuit board shipped with power supply circuit traces intact. isolate section, associated circuit trace. Once cut, jumper shorting plugs must installed normal board operation. Framer Interface. simplest framer interface coax loop between RPOS/RNEG/ RCLK jacks TPOS/TNEG/TCLK jacks. This loops recovered data clock signals back into transmitter, allows front design tested without framer. loop framer signals, connect following points: RTIP TTIP RRING TRING RCLK TCLK
Note:
dual framer interface ports must allowed float. terminators jack which otherwise connected. example, only channel dual being tested, connect terminators other channel jacks. Clock Source (1.544 2.048 El). Connect suitable clock source MCLK port Demo Board. connector MCLK input located center framer interface. Line Interface. simplest line interface twisted-pair loop between TTIP/TRING jacks RTIP/RRING jacks. This loop sufficient transmit data supplied through framer interface. However, shown Figure this document assumes that framer interface simple loop, uses BERT twisted-pair line signal source. BERT provides known signal (all ones example) dual receiver. recovered data looped through framer interface, back dual transmit inputs, driven TTIP/TRING jacks onto line back BERT. BERT performs comparison registers error when zero appears input. line interface, make following connections: Demo Board TTIP/TRING outputs BERT input. BERT output Demo Board RTIP/RRING inputs. usina cable length simulator, insert simulator between BERT output Demo Board input.
Note:
using cable length simulator, must simulate correct cable type applications applications). Typical Setup procedures assume cable length zero although additional settings listed Table simulator allows engineer more easily evaluate system operating characteristics over various cable lengths.
Evaluation Board T1/E1 Applications LXD332
Typical Setup
This Demo Board setup envirom-nent. transmit pulse shape settings (LENxn) cable length 0~133ft. This simulates both laboratory environment local installation. other cable lengths, Table Install LXT332 transceiver center socket. on-board jumpers follows:
Table
On-Board Jumper Settings
Jumper Description Short transformer open "FULL" Setting
JP9, JP10 JP11 JP12 JP13
Dual MCLK input this float
RVCC measurement TVCC measurement RGND measurement TVCC0 measurement Short R13, transformer JASEL enable VCC-DVCC
MCLK center (center- MCLK signal)
short short short short open "FULL" short short measure voltage currrent dual circuits
switches follows: Table Switch Settings
Switch S1,1 S1,2 S1,3 S1,4 S1,5 S1,6 S1,7 S1,8 S2,1 S2,2 S2,3 S2,4 S2,5 S2,6 Name RLOOP1 LLOOP1 LEN01 LEN11 LEN12 TAOS1 used used RLOOP0 LLOOP0 LEN00 LEN10 LEN20 TAOS0 "Off" "Off" "On" "On" "Off" "Off" Settinh "Off" "Off" "On" "Off" "Off" "Off" Setting cable length 0~133 Table
LXD332 Evaluation Board T1/E1 Applications
Table
Switch Settings (Continued)
Switch S2,7 S2,8 Name TRSTE SOFT/UNP JA-position Settinh "Off Either JA-T JA-R desired
Install transformers follows: PE65351 (full tap)-JP3 T'2: PE65351 PE65351 PE65351 (full tap)-JP Install resistors follows: R13: R14:
setup complete. After supplyinc, power around, applydata signals appropriate connectors. Transceiver signals available analysis connectors banana jacks.
1.4.1
Additional Setup Configurations
Other Configurations suitable variety design needs result from changing LENxn settings, resistors values, transformer ratio jumper settings. Table shows LENxn settings required receive-side cable lengths environments. Table identifies return loss values available with various resistor/transformer combinations.
Table
Setting LENxn Bits Needed Receive Cable Length
ABAM Cable Length (ft) 0~133 133~266 266~399 399~533 533~655 LEN2n LEN1n LEN0n Cable Loss 1/.8
Table
Settings Targeted Return Loss Cable
Return Loss Suggested Transformer Ratio (T2, 1:2.3 Suggested Resistor Value (R4,
Evaluation Board T1/E1 Applications LXD332
Typical Setup
This example shows Demo Board 120-inch, twisted-pair cable environment. Table shows modify settings coaxial cable. Install LXT332 transceiver center socket. on-board jumpers follows:
Table
On-Board Jumper Settings
Jumper JP1, JP9, JP10 JP11 JP12 JP13 Description Short transformer Dual MCLK input this float RVCC measurement TVCC1 mesaurement RGND measurement TVCC0 measurement Short R13, transformer JASEL enable VCC-DVCC isolation open "FULL" MCLK center (center-gnd MCLK signal) short short short short open "FULL" sort short measure voltage current dual circuits Setting
switches follows: Table Switch Settings
Switch S1,1 S1,2 S1,3 S1,4 S1,5 S1,6 S1,7 S1,8 S2,1 S2,2 S1,3 S1,4 S1,5 S2,6 Name RLOOP1 LLOOP1 LEN01 LEN11 LEN21 TAOS1 used used RLOOP0 LLOOP0 LEN00 LEN10 LEN20 TAOS0 "Off" "Off" "Off" "Off" "Off" "Off" Setting CCITT Recommendation G.7036120 Setting "Off" "Off" "Off" "Off" "Off" "Off" Setting CCITT Recommendation G.7036120
LXD332 Evaluation Board T1/E1 Applications
Table
Switch Settings (Continued)
Switch S2,7 S2,8 Name TRSTE SOFT/UNP JA-position Either JA-T JA-R desired Setting "Off"
Install transformers follows: PE65351 (fall tap) -JP3 PE65351 PE65351 PE65351 (full tap) -JPI Install resistors follows: R13: R14: setup complete. After supplying power ground, apply data signals appropriate connectors. Transceiver signals available analysis connectors banana jacks.
1.5.1
Additional Setup
Other configurations suitable variety design needs result from changing LENnx bits setting, resistors values, transformer ratio jumper settings. Table shows return losses which result from using various settings, resistor values transformer ratios with either coax twisted-pair cables.
Table
Output Combinations
Return Loss Value Cable Type Coax Coax Transformer Ratio (T2, Resistor Value (R4, 14.3
JUMPER DECOUPLING CAPS TGND0 TGND1 {Schematic} MAD1108P SIPP7 SIPP7 MAD1108P MAD1108P MAD1108P TGND1 TGND0
MCLK
MAD1108P MAD1108P MAD1108P DIP-8 RLOOP_0/PS_0 LLOOP_0/CLKE LEN00/INT_0 LEN10/INT_1 LEN20/VCQ_0 TAOS_0/SCLK RLOOP0 LLOOP0 LEN00 LEN10 LEN20 TAOS0 TRSTE SOFT TCLK0 TPOS0 TNEG0 TCLK1 TPOS1 TNEG1 MCLK MCLK TCLK_0 TPOS/TDATA_0 TNEG/ECE_0 TCLK_1 TPOS/TDATA_1 TNEG/ECE_1 MAD1108P MAD1108P DIP-8 MAD1108P MAD1108P TRSTE SOFT LINE INTERFACE {Schematic} MAD1108P MAD1108P RCLK0 RPOS0 RNEG0 RCLK1 RPOS1 RNEG1 RCLK_0 RPOS/RDATA_0 RNEG/BVP_0 RCLK_1 RPOS/RDATA_1 RNEG/BVP_1 JASEL LOS_0 LOS_1 TRSTE RTIP_0 RRING_0 RTIP_1 RRING_1 RTIP0 RRING0 RTIP1 RRING1 TTIP_0 TRING_0 TTIP_1 TRING_1 TTIP0 TRING0 TTIP1 TRING1 JASEL LOS_0 LOS_1 TRSTE RLOOP_1/SD_0 LLOOP_1/SDI LEN01/VCQ_1 LEN11/SPE LEN21/VCQ_E TAOS_1/PS1 RLOOP1 LLOOP1 LEN01 LEN11 LEN21 TAOS1
TCLK0
TPOS0
TNEG0
TCLK1
TPOS1
TNEG1
RCLK0
PLCC SOCKET SWITCHES MCLK TRSTE JASEL SOFT
Figure Demo Board Schematic Diagrams (Sheet
RPOS0
RNEG0
LEDS LOS0 LOS1 {Schematic}
TTIP0 TRING0 TTIP1 TRING1 RTIP0 RRING0 RTIP1 RRING1 {Schematic}
RC05
RCLK1
TVCC0 TVCC1 RVCC TGND0 TGND1
1000pf
RPOS1
JP13 RGND JUMPER
RNEG1
Evaluation Board T1/E1 Applications LXD332
LXD332 Evaluation Board T1/E1 Applications
Figure Demo Board Schematic Diagrams (Sheet
JUMPER .1uF JUMPER JUMPER 10uF .1uF .1uF .1uF .1uF .1uF .1uF 10uF .1uF 68uF TGND1 TGND1 68uF TGND0 TGND0
Banana
Banana JUMPER
DIODE
74HC04
74HC04
74HC125
DIODE
74HC04
DIODE
74HC125 74HC04 74HC04 74HC125
Evaluation Board T1/E1 Applications LXD332
Figure Demo Board Schematic Diagrams (Sheet
LOSS SIGNAL LEDS
RC05 LOS0 LOS0
74HC04
RC05 LOS1 LOS1
74HC04
RC05
74HC04
JP10 JUMPER TTIP0 CK05 RC05 JP11 JUMPER Banana JUMPER Socket Strips TRING0 RC05 Banana TRING0 Banana RC05 Banana TTIP0 RC05 Socket Strips
RRING0
RRING0
65388 65351 64936 65389 (CEPT 75/120
1:1.15 1:1.266 OHMS)
RTIP0
RTIP0
LXD332 Evaluation Board T1/E1 Applications
65351
JUMPER TTIP1 CK05 RC05 Banana TTIP1 RCO5 Banana
Figure Demo Board Schematic Diagrams (Sheet
RRING1
RRING1
JUMPER Socket Strips JUMPER
Socket Strips TRING1 Banana RC05
65388 65351 64936 65389 (CEPT 75/120
1:1.15 1:1.266 OHMS)
Banana TRING1
RTIP1
RTIP1
RC05
65351
RC05
TRSTE TRSTE RC05 74HC125
MCLK 74HC04 74HC04
MCLK
TRISTATE SWITCH WHEN OPEN, BIPOLAR ENABLED B8ZS/HDB3 DISABLED.
WHEN CLOSED, OUTPUT PINS FORCED HIGH MODE.
SOFT
SOFT
CIRCUITS PLACED TRANSMIT PATHS.
74HC04 74HC04 4.75K RC05 ON-OFF-ON
Figure Demo Board Schematic Diagrams (Sheet
WHEN SWITCH LEFT OPEN CIRCUIT DISABLED. CIRCUITS PLACED RECIEVE PATHS.
JP12 JASEL JUMPER JASEL
Evaluation Board T1/E1 Applications LXD332
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