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LXD332 - Evaluation Board for T1 / E1 Applications

As of January 15, 2001, this document replaces the Level One document known as LXD332 - Evaluation Board for T1 / E1 Applications.

LXD332 - Evaluation Board for T1 / E1 Applications
Developer Manual
January 2001
As of January 15, 2001, this document replaces the Level One document known as LXD332 - Evaluation Board for T1 / E1 Applications.
Order Number: 249220-001
LXD332 - Evaluation Board for T1 / E1 Applications Developer Manual
Contents
1.0 General Description ................................................. 5
1.1 1.2 1.3 1.4 1.5 Features ........................................................ 5 Design Evaluation .................................................6 1.2.1 Equipment Requirements ................................... 7 Typical Connections ............................................... 8 Typical T1 Setup .................................................. 9 1.4.1 Additional Tl Setup Configurations ...........................10 Typical E1 Setup .................................................11 1.5.1 Additional E1 Setup ......................................12
Figures
1 2 3 4 5 6 7 LXD332 Evaluation Board ........................................... 6 Basic Test Setup .................................................. 7 Demo Board Schematic Diagrams (Sheet 1 of 5) ........................13 Demo Board Schematic Diagrams (Sheet 2 of 5) ........................14 Demo Board Schematic Diagrams (Sheet 3 of 5) ........................15 Demo Board Schematic Diagrams (Sheet 4 of 5) ........................16 Demo Board Schematic Diagrams (Sheet 5 of 5) ........................17
Tables
1 2 3 4 5 6 7 On-Board Jumper Settings..........................................9 Switch Settings................................................... 9 Setting LENxn Bits for Needed Receive Cable Length ....................10 Settings for Targeted Return Loss - 100 Cable ........................10 On-Board Jumper Settings.........................................11 Switch Settings..................................................11 E1 Output Combinations ...........................................12
LXD332 - Evaluation Board for T1 / E1 Applications Developer Manual
Evaluation Board for T1 / E1 Applications - LXD332
General Description
The LXD332 Evalution Board is a versatile evaluation tool for engineers involved in designing T1 / E1 short-haul applcations.It use s an LXT332 Dual Line Interface Unit and incorporates all supporting circuitry for either Tl or E1applications. The Evaluation Board provides banana jacks for the line interface and BNC connectors for the framer interface. A bit error tester (bert) or framer / mux may be used to provide the external signal needed for evaluation. This document describes typical Evaluation Board setup procedures for both T1 (North American) and E1 (European) environments. Before using the Evaluation Board, review the current LXT332 data sheet for complete information about this transceiver. An Evaluation Board schematic is also available.
Features
· Board design permits quick setup, ease of use and clear visibility of application settings
- Local dual LIU testing - Complete system evaluation - Individual circuit isolation
Exploits crystal-less jitter attenuation of the dual LIU Jitter attenuation switchable into transmit, receive, or data bypass path Two twisted-pair line interfaces and all related digital signals available for analysis and testing Banana jacks for twisted-pair line interface BNC connectors for clock and framer interface LEDs indicators for DFM and LOS Design supports both E1 and T1 evaluation Switches emulate stand-alone Hardware Mode
Developer Manual
LXD332 - Evaluation Board for T1 / E1 Applications
Figure 1. LXD332 Evaluation Board
Design Evaluation
The LXT332 Demo Board supports design evaluation of the LXT332 Dual Line Interface Unit. Using the Demo Board, a variety of front end circuit options may be tested and evaluated. The Demo Board also provides a convenient pre-tested front end circuit which allows design engineers to verify back end circuit designs. However, the setup descriptions in this document focus on the dual LIU front-end. Figure 2 shows a typical test setup for basic front end testing. Additional test setups for the framer interface can be accomplished using the BNC connectors on the Demo Board. Follow the operations described here to become familiar with the basic test configuration. Once the setup is complete, a wide variety of tests can be performed to evaluate system designs.
Developer Manual
Evaluation Board for T1 / E1 Applications - LXD332
Figure 2. Basic Test Setup
Equipment Requirements
The LXD332 Demo Board includes all the circuit components needed for a successful evaluation. However, the following additional equipment is required:
Power Supply (+5 VDC) Twisted-Pair Cable or Cable Length Simulator Coax Cables or 5 WBNC Terminators Signal Source. A Bit Error Rate Tester (BERT) Clock Source (1.544 MHz for T1, 2.048 MHz for E1)
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LXD332 - Evaluation Board for T1 / E1 Applications
Typical Connections
Before proceeding, with any Demo Board operations, review the specifications for the LXT332 transceiver. Refer to Figure 2 for cable configuration.
Caution:
CMOS devices are static (ESD) sensitive. Take all industry standard precautions when handling the Demo Board, chip and other electronic components. 1. Power Supply (+5 VDC). Connect +5 volts to the VCC banana jack. Connect the ground lead to the GND banana jack. This provides both safety (earth) and signal (reference) ground functions. 2. Ammeter. Ficure 2 shows an ammeter connected at JPI3. This is an optional test point. Several jumpers (JP5, JP6, JP7, JP8 and JPI3) are built into the Demo Board which allow the test engineer to isolate sections of the circuit and measure current and voltage values. The circuit board is shipped with all power supply circuit traces intact. To isolate a section, cut the associated circuit trace. Once cut, jumper shorting plugs must be installed for normal board operation. 3. Framer Interface. The simplest framer interface is a coax loop between the RPOS / RNEG / RCLK jacks and the TPOS / TNEG / TCLK jacks. This loops the recovered data and clock signals back into the transmitter, and allows the front end design to be tested in the lab without a framer. To loop the framer I / 0 signals, connect the following points: - RTIP to TTIP - RRING to TRING - RCLK to TCLK
Note:
The dual LIU framer interface ports must not be allowed to float. Use 5 W terminators on any BNC jack which is not otherwise connected. For example, if only one channel of the dual LIU is being tested, connect 5 W terminators to the other channel BNC jacks. 4. Clock Source (1.544 MHz for T1, 2.048 MHz for El). Connect a suitable clock source to the MCLK port of the Demo Board. The BNC connector for the MCLK input is located in the center of the framer interface. 5. Line Interface. The simplest line interface is a twisted-pair loop between the TTIP / TRING jacks and the RTIP / RRING jacks. This loop is sufficient if the transmit data is supplied through the framer interface. However, as shown in Figure 2, this document assumes that the framer interface is a simple loop, and uses a BERT in the twisted-pair line as the signal source. The BERT provides a known signal (all ones for example) to the dual LIU receiver. The recovered data is looped out through the framer interface, back to the dual LIU transmit inputs, driven out the TTIP / TRING jacks onto the line and back to the BERT. The BERT performs an 1 / 0 comparison and registers an error when a zero appears on its input. To set up the line interface, make the following connections: - Demo Board TTIP / TRING outputs to the BERT input. - BERT output to the Demo Board RTIP / RRING inputs. If usina a cable length simulator, insert the simulator between the BERT output and the Demo Board input.
Note:
If using a cable length simulator, it must simulate the correct cable type (22 AWG for T1 applications or 0.6 mm for El applications). The Typical T1 Setup procedures assume a cable length of zero to 133 ft although additional settings are listed in Table 3. The simulator allows the engineer to more easily evaluate system operating characteristics over various cable lengths.
Developer Manual
Evaluation Board for T1 / E1 Applications - LXD332
Typical T1 Setup
This Demo Board setup is for the T1 envirom-nent. The transmit pulse shape settings (LENxn) are for a cable length of 0~133ft. This simulates both a laboratory environment and a local installation. For other cable lengths, see Table 1. 1. Install an LXT332 transceiver in the center socket. 2. Set the on-board jumpers as follows:
Table 1.
On-Board Jumper Settings
Jumper JP I, JP2 JP3 Description Short R2, R3 RX1 transformer tap open "FULL" Setting
JP5 JP6 JP7 JP8 JP9, JP10 JP11 JP12 JP13
Dual LIU MCLK input do not let this pin float
RVCC measurement TVCC measurement RGND measurement TVCC0 measurement Short R13, R14 RX0 transformer tap JASEL enable VCC-DVCC
MCLK to center pin (center- GND for no MCLK signal)
short short short short open "FULL" short short measure voltage or currrent in dual LIU circuits
3. Set switches as follows: Table 2. Switch Settings
Developer Manual
LXD332 - Evaluation Board for T1 / E1 Applications
Table 2.
Switch Settings (Continued)
The setup is now complete. After supplyinc, + 5 VDC power and around, applydata signals to the appropriate connectors. Transceiver signals are available for analysis at the BNC connectors and banana jacks.
Additional Tl Setup Configurations
Other Configurations suitable to a variety of design needs result from changing LENxn bit settings, the resistors values, transformer ratio and jumper settings. Table 3 shows LENxn bit settings required for receive-side cable lengths in T1 environments. Table 4 identifies return loss values available with various resistor / transformer combinations.
Table 3.
Setting LENxn Bits for Needed Receive Cable Length
ABAM Cable (22 awg 100 ) Length (ft) 0~133 133~266 266~399 399~533 533~655 LEN2n 0 1 1 1 1 LEN1n 1 0 0 1 1 LEN0n 1 0 1 0 1 Cable Loss 0.6 dB 1.2 dB 1 / .8 dB 2.4 dB 3.0 dB
Table 4.
Settings for Targeted Return Loss - 100 Cable
Return Loss 14 dB 18 dB Suggested Transformer Ratio (T2, T3) 1:2 1:2.3 Suggested Resistor Value (R4, R5, R8, R9) 9.1 9.1
Developer Manual
Evaluation Board for T1 / E1 Applications - LXD332
Typical E1 Setup
This example shows how to use the Demo Board in the El, 120-inch, twisted-pair cable environment. Table 7 shows how to modify the settings for 75 coaxial cable. 1. Install an LXT332 transceiver in the center socket. 2. Set the on-board jumpers as follows:
Table 5.
On-Board Jumper Settings
Jumper JP1, JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9, JP10 JP11 JP12 JP13 Description Short R2, R3 RX1 transformer tap Dual LIU MCLK input do not let this pin float RVCC measurement TVCC1 mesaurement RGND measurement TVCC0 measurement Short R13, R14 RX0 transformer tap JASEL enable VCC-DVCC isolation open "FULL" MCLK to center pin (center-gnd for no MCLK signal) short short short short open "FULL" sort short measure voltage or current in dual LIU circuits Setting
3. Set switches as follows: Table 6. Switch Settings
Developer Manual
LXD332 - Evaluation Board for T1 / E1 Applications
Table 6.
Switch Settings (Continued)
4. Install transformers as follows: T1: PE65351 (fall tap) -JP3 T2: PE65351 T3: PE65351 T4: PE65351 (full tap) -JPI 1 5. Install resistors as follows: R1: 9.1 R2: 9.1 R4: 240 R5: 240 R8: 240 R9: 240 R13: 9.1 R14: 9.1 The setup is now complete. After supplying +5 Vcc power and ground, apply data signals to the appropriate connectors. Transceiver signals are available for analysis at the bnc connectors and banana jacks.
Additional E1 Setup
Other configurations suitable to a variety of design needs result from changing LENnx bits setting, the resistors values, transformer ratio and jumper settings. Table 7 shows the return losses which result from using various LEN settings, resistor values and transformer ratios with either coax or twisted-pair cables.
Table 7.
E1 Output Combinations
Return Loss 18 dB 10 dB 10 dB 18 dB LEN Value 001 001 000 000 Cable Type T-P Coax TP Coax Transformer Ratio (T2, T3) 1:2 1:2 1:2 1:2 Resistor Value (R4, R5, R8, R9) 15 14.3 8.7 9.1
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J7 BNC
Developer Manual
J8 BNC
TCLK0
J10 BNC
TPOS0
J12 BNC
TNEG0
J5 BNC
TCLK1
J3 BNC
TPOS1
J1 BNC
TNEG1
J13 BNC
RCLK0
44 PIN PLCC SOCKET SWITCHES MCLK TRSTE JASEL SOFT
Figure 3. Demo Board Schematic Diagrams (Sheet 1 of 5)
J11 BNC
RPOS0
J9 BNC
RNEG0
J2 BNC
R1 22K RC05
RCLK1
TVCC0 TVCC1 VCC RVCC TGND0 TGND1
J4 BNC
C3 1000pf
RPOS1
J6 BNC
JP13 VCC GND RGND JUMPER VCC
RNEG1
Evaluation Board for T1 / E1 Applications - LXD332
LXD332 - Evaluation Board for T1 / E1 Applications
Figure 4. Demo Board Schematic Diagrams (Sheet 2 of 5)
VCC JP8 JUMPER + C11 .1uF JP6 JUMPER + JP5 JUMPER + C1 10uF C5 .1uF C13 .1uF C2 .1uF C14 .1uF C8 .1uF C9 .1uF + C6 10uF C10 .1uF C7 68uF TGND1 TGND1 C12 68uF TGND0 TGND0
B1 Banana 1 VCC
B2 Banana 1 GND JP7 JUMPER
D14 3 DIODE
74HC04
U2A 74HC125 4
D15 DIODE
U5C 5 6 5 74HC04
D16 6 DIODE
U2B 74HC125 10 9 74HC04 74HC04 U2C 74HC125 U5D 9 8 11 U5E 10
Developer Manual
Evaluation Board for T1 / E1 Applications - LXD332
Figure 5. Demo Board Schematic Diagrams (Sheet 3 of 5)
LOSS OF SIGNAL LEDS
VCC U6A D4 LED R11 2 221 RC05 1 LOS0 LOS0
74HC04 U6B
D5 LED
R12 4 221 RC05 3 LOS1 LOS1
74HC04
DFM LED
VCC U5F D3 LED R10 12 221 RC05 13 DFM DFM
74HC04
Developer Manual
JP10 JUMPER B4 B7 C15 1 TTIP0 .47 uF CK05 1 R8 200 RC05 3 4 4 3 JP11 1 2 1 2 3 JUMPER Banana 1 JP9 JUMPER 2 Socket Strips R13 1 TRING0 9.1 RC05 Banana TRING0 T3 2 6 5 Banana T4 9.1 RC05 Banana TTIP0 1 R14 5 R9 200 RC05 2 Socket Strips B3 6
RRING0
PE 65388 FOR PE 65351 FOR PE 64936 FOR PE 65389 FOR (CEPT 75 / 120
1:1.15 CT 1:2 CT 1:1 CT 1:1.266 OHMS)
RTIP0
LXD332 - Evaluation Board for T1 / E1 Applications
PE 65351 FOR 1:2 CT
JP2 JUMPER B6 C4 1 TTIP1 .47 uF CK05 1 R5 200 RC05 3 4 T2 2 Banana TTIP1 9.1 RCO5 6 T1 5 Banana R3 1 B8
Figure 6. Demo Board Schematic Diagrams (Sheet 4 of 5)
RRING1
3 JP3 1 JP1 JUMPER R2 2 1 2 Socket Strips 2 3 JUMPER 1
5 2 Socket Strips B5 1 TRING1 Banana R4 200 RC05
PE 65388 FOR PE 65351 FOR PE 64936 FOR PE 65389 FOR (CEPT 75 / 120
1:1.15 CT 1:2 CT 1:1 CT 1:1.266 OHMS)
Banana TRING1
RTIP1
9.1 RC05
Developer Manual
PE 65351 FOR 1:2 CT
VCC R6 10K RC05
U6F R7 13 TRSTE TRSTE 1K RC05 U2D 74HC125 12 11 10 12 11
MCLK 74HC04 74HC04
TRISTATE SWITCH WHEN OPEN, BIPOLAR I / O IS ENABLED AND THE B8ZS / HDB3 ARE DISABLED.
Developer Manual
WHEN CLOSED, ALL OUTPUT PINS ARE FORCED TO A HIGH Z MODE.
JA CIRCUITS PLACED IN THE TRANSMIT PATHS.
U6C R15 5 3 74HC04 U6D 74HC04 4.75K RC05 SW ON-OFF-ON 6 2 1 S3
Figure 7. Demo Board Schematic Diagrams (Sheet 5 of 5)
WHEN SWITCH IS LEFT OPEN THE JA CIRCUIT IS DISABLED. JA CIRCUITS PLACED IN THE RECIEVE PATHS.
JP12 JASEL JUMPER JASEL
Evaluation Board for T1 / E1 Applications - LXD332