relimin EM73A88A advanced single chip CMOS 4-bit micro-controller
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
EM73A88A advanced single chip CMOS 4-bit micro-controller. contains 16K-byte ROM, 500-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, 12-bit timer/counters kernel function. EM73A88A also equipped with interrupt sources, ports (including input port bidirection ports), display (64x16), built-in sound generator speech synthesizer direct drive speaker. It's power consumption high speed feature further strengten with DUAL, SLOW, IDLE STOP operation mode optimized power saving.
FEATURES
Operation voltage Clock source 2.2V 4.8V. Dual clock system. Low-frequency oscillator Crystal oscillator high-frequency oscillator built-in internal oscillator (4.6 MHz). Instruction powerful instructions. Instruction cycle time 1.7µs 4.6M (high speed clock). 244µs 32768 (low speed clock). capacity bits. capacity bits. Input port port (P0.0-P0.3), IDLE/STOP releasing function available mask option. (each input pull-up pull-down resistor available mask option). Bidrection port ports (P4, P8). IDLE/STOP release function P8(0.3) available mask option. Built-in watch-dog-timer counter available mask option. 12-bit timer/counter 12-bit timer/counters programmable timer, event counter pulse width measurement mode. Built-in time base counter stages. Subroutine nesting levels. Interrupt External interrupt input interrupt sources. Internal interrupt timer overflow interrupts, time base interrupt. speech interrupt. driver 64x16 dots, 1/16 duty, bias with voltage multiplier. Sound effect Tone generator random generator. Speech synthesizer 448K speech data (use 448K nibbles data ROM). current Output selection mask option. Power saving function SLOW, IDLE, STOP operation modes. Package type Chip form pins.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
FUNCTION BLOCK DIAGRAM
RESET
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Timing Generator Clock Mode Control
LXIN LXOUT
Reset Control
Clock Generator
System Control Data pointer Interrupt Control Time Base Instruction Decoder Instruction Register Stack pointer Stack P0.0/WAKEUP0 P0.1/WAKEUP1 P0.2/WAKEUP2 P0.3/WAKEUP3
Data
Flag
Timer/Counter (TA,TB)
Control V1~V5 VA,VB Driver Speech synthesizer Sound Generator
COM0~COM15
SEG0~SEG63
DESCRIPTIONS
Symbol RESET Function Power supply Power supply RESET-A System reset input signal, active mask option none pull-up OSC-G Capacitor connecting internal high frequency oscillator. LXIN OSC-B/OSC-H Crystal connecting speed clock source. LXOUT OSC-B Crystal connecting speed clock source. P0(0.3)/WAKEUP0.3 INPUT-B 4-bit input port with IDLE/STOP releasing function mask option wakeup enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none P4(0.3) I/O-O 4-bit bidirection port with high current source. mask option open-drain push-pull, high current PMOS push-pull, current PMOS P8.0(INT1)/WAKEUPA I/O-L 2-bit bidirection port with external interrupt sources input IDLE P8.2(INT0)/WAKEUPC /STOP releasing function mask option wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain P8.1(TRGB)/WAKEUPB I/O-L 2-bit bidirection port with time/counter external input IDLE P8.3(TRGA)/WAKEUPD /STOP releasing function
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Pin-type
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P4.0 P4.1 P4.2 P4.3 P8.0(INT1)/WAKEUPA P8.1(TRGB)/WAKEUPB P8.2(INT0)/WAKEUPC P8.3(TRGA)/WAKEUPD
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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Symbol Pin-type Function wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain Tone Speech output Tone Speech output bias pins mask option common output pins segment output pins package type, connecting type
COM0~COM15 SEG0~SEG63 TEST
FUNCTION DESCRIPTIONS
PROGRAM bits bits program contains user's program some fixed data. basic structure program categorized into partitions. Address 0000h: Reset start address. Address 0002h 000Ch kinds interrupt service routine entry addresses. Address 000Eh-0086h SCALL subroutine entry address, only available 000Eh, 0016h, 001Eh, 0026h, 002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh,0086h. Address 0000h 07FFh LCALL subroutine entry address. Address 0000h 1FFFh Except used above function, other region used user's program data region. address Bank
0000h 0002h 0004h 0006h 0008h 000Ah 000Ch 000Eh 0086h Reset start address INT0 interrupt service routine entry address TRGA TRGB INT1 SCALL, subroutine call entry address
Subroutine call entry address designated [LCALL instruction
07FFh 0800h 0FFFh 1000h
1FFFh
Bank Bank Bank
Data table [LDAX],[LDAXI] instruction
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
User's program fixed data stored program ROM. User's program executed using value fetch instruction code. 16Kx8 bits program divided into banks. There 4Kx8 bits bank. program bank selected P3(1.0). program counter 13-bit binary counter. initialized during reset. When P3(1.0)=00B, bank0 bank1 program will selected. P3(1.0)=01B, bank0 bank2 will selected. Address 0000h 0FFFh 1000h 1FFFh P3=xx00B P3=xx01B P3=xx10B
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Bank0
Bank0
Bank0
Bank1
Bank2
Bank3
PROGRAM EXAMPLE
BANK LDIA #00H program bank1 OUTA LDIA #01H program bank2 OUTA LDIA #02H program bank3 OUTA -BANK START:
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
-BANK -BANK
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Fixed data read table-look-up instruction. Table-look-up instruction requires Data point (DP) indicate address obtaining code data (Except bank LDAX LDAXI ROM[DP]L ROM[DP]H,DP+1
12-bit data register that stores program address pointer code data. User initially load address into with instructions "STADPL", "STADPM, STADPH", then obtain lower nibble code data instruction "LDAX" higher nibble instruction "LDAXI" PROGRAM EXAMPLE: Read code address 1777h table-look-up instruction.
LDIA #07h; STADPL STADPM STADPH #00h; #03h; LDAX STAMI LDAXI STAM 1777h DATA 56h; [DP]L [DP]M [DP]H 07h, Load DP=777h
RAM[30] RAM[31]
DATA 500-nibble total nibble data available from address 1FFh Data includes zero page region, stacks data areas.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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Increment Address Bank 000h 00Fh 010h 01Fh 020h 02Fh
Zero-page
Increment
0C0h 0CFh 0D0h 0DFh 0E0h 0EFh 0F0h 0F3h
Level Level Level Level
Level Level Level
Level Level Level
Level Level Level
Bank
100h 10Fh 110h 11Fh
1E0h 1EFh 1F0h 1FFh
ZERO- PAGE: From 000h 00Fh zero-page location. used zero-page address mode pointer instruction "STD #k,y; #k,y; y,b; k,y". PROGRAM EXAMPLE: write immediate data "07h" [03] clear [0Eh].
#07h, RAM[03] 0Eh,2 RAM[0Eh]2
STACK: There level (maximum) stack levels that user subroutine (including interrupt CALL). User assign level starting stack providing level number stack pointer (SP). When instruction (CALL interrupt) invoked, before enter subroutine, previous address saved into stack until returned from those subroutines, value restored data saved stack. DATA AREA: Except area used user's application, whole used data area storing loading general data. ADDRESSING MODE nibble data memory consists banks (bank bank There 244x4 bits (address 000h~0F3h) bank 256x4 bits (address 100h~1FFh) bank
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin bank selected P9.3. When P9.3 cleared "0", bank selected. When P9.3 "1", bank
selected. Data Memory consists three Address mode, namely Indirect addressing mode: address bank specified registers.
P9.3
address
PROGRAM EXAMPLE: Load data address "143h" address "032h".
P9,3 LDAM P9,3 STAM P9.3 RAM[134h] P9.3 RAM[023h]
Direct addressing mode: address bank directly specified bits code second byte instruction field.
instruction field xxxxxxxx P9.3
address
P9,3 P9,3 P9.3 RAM[143h] P9.3 RAM[023h]
xxxxxxxx
PROGRAM EXAMPLE: Load data address "143h" address "023h".
Zero-page addressing mode: zero-page bank (address 000h~00Fh). address lower bits code second byte instruction field.
instruction field yyyy
address
0000 yyyy
PROGRAM EXAMPLE: Write immediate "0Fh" address "005h".
#0Fh, RAM[05h]
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin PROGRAM COUNTER (16K ROM)
Program counter composed 13-bit counter, which indicates next executed address instruction program instruction. BRANCH CALL instructions, changed instruction indicating. only indicate address from 0000h-1FFFh. bank number decided Branch instruction: Object code: 00aa aaaa Condition: SF=1; 12-6.a branch condition satisified Hold original value+1
SF=0; branch condition satisified) Original value
Object code: 1100 aaaa aaaa aaaa Condition: SF=1; 12.a branch condition satisified
Hold
SF=0; branch condition satisified) Original value
SLBR Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh) 0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh) Condition: SF=1; branch condition satisified)
SF=0 branch condition satisified Original value
Subroutine instruction: SCALL Object code: 1110 nnnn Condition a=8n+6 n=1.Fh a=86h,
LCALL Object code: 0100 0aaa aaaa aaaa Condition: This specification subject changed without notice.
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Object code: 0100 1111 Condition: STACK[SP]; return address stored stack
Object code: 0100 1101 Condition FLAG. STACK[SP]; return address stored stack
Interrupt acceptance operation: When interrupt accepted, original pushed into stack interrupt vector will loaded into interrupt vectors follows INT0 (External interrupt from P8.2)
(speech interrupt)
TRGA (Timer overflow interrupt)
TRGB (Time overflow interrupt)
(Time base interrupt)
INT1 (External interrupt from P8.0) Reset operation:
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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Other operations: 1-byte instruction execution: 2-byte instruction execution: 3-byte instruction execution: ACCUMULATOR Accumulator(ACC) 4-bit data register temporary data storage. arithematic, logic comparative opertion., plays role which holds source data result. FLAGS There three kinds flag, (Carry flag), (Zero flag) (Status flag), these three 1-bit flags included arithematic, logic comparative operation. flags will into stack when interrupt subroutine served, flags will restored after instruction executed. Carry Flag carry flag affected following operations: Addition carry indicator, under addition operation, when carry-out occures, "1", likewise, operation carry-out, "0". Subtraction borrow-in indicator, under subtraction operation, when borrow occures, "0", likewise, there borrow-in, "1". Comparision: borrow-in indicator Comparision operation subtraction operation. Rotation: shifts into empty accumulator rotation holds shift data after rotation. test instruction Under TFCFC instruction, content sent into then clear itself "0". Under TTSFC instruction, content sent into then itself "1". Zero Flag affected result ALU, operation generates result, "1", likewise, "0". Status Flag affected instruction operation system status. initiated reset condition. Branch instruction decided when SF=1, branch condition satisified, likewise, when branch condition unsatisified.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
PROGRAM EXAMPLE: Check following arithematic operation
LDIA #00h; LDIA #03h; ADDA #05h; ADDA #0Dh; ADDA #0Eh;
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arithematic operation data performed unit There flags that affected result operation, operation affected only. STRUCTURE supported user arithematic operation functions, including Addition, Subtraction Rotaion.
DATA
FUNCTION Addition: supports addition function with instructions ADDAM, ADCAM, ADDM #k,y addition operation affects Under addition operation, result "0", will "1", otherwise, will "0", When addition operation carry-out. will "1", otherwise, will "0". EXAMPLE:
Operation 3+4=7 7+F=6 0+0=0 8+8=0 Carry Zero
Subtraction: supports subtraction function with instructions SUBM SUBA SBCAM, DECM. subtraction operation affects Under subtraction operation, result negative, will "0", borrow out, otherwise, result positive, will "1". result subtraction operation "0", "1", likewise, "1".
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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EXAMPLE:
Operation 8-4=4 7-F= -8(1000) 9-9=0 Carry Zero
Rotation: types rotation operation available, rotation left, other rotation right. RLCA instruction rotates value counter-clockwise, shift value into hold shift data
RRCA instruction operation rotates value clockwise, shift value into hold shift data
PROGRAM EXAMPLE: rotate clockwise (right) shift into Acc.
TTCFS; RRCA; rotate right shift CF=1 into MSB.
REGISTER register 4-bit registers, they used pair pointer memoryaddress. They used also independent temporary 4-bit data registers. certain instructions, register pointer indicate number Port4 only REGISTER STRUCTURE
REGISTER REGISTER
REGISTER FUNCTION register used temporary register instructions THA, THL, INCL, DECL, EXAL, EXAH. PROGRAM EXAMPLE: Load immediate data "5h" into register, "0Dh" into register.
#05h; #0Dh;
register used pointer address memory instructions LDAM, STAM, STAMI PROGRAM EXAMPLE: Store immediate data "#0Ah" into address 35h.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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#5h; #3h; STDMI #0Ah; RAM[35]
register used pointer indicate port instructions SELP, CLPL, TFPL, (When indicate P4.0) PROGRAM EXAMPLE: Port4
#00h; SEPL P4.0
STACK POINTER (SP) Stack pointer 4-bit register that stores present stack level number. Before using stack, user must value first, will initiate value after reset condition. When subroutine received, decreased automatically, likewise, returning from subroutine, increased one. data transfer between done with instructions "LDASP" "STASP". DATA POINTER (DP) Data pointer 12-bit register that stores address indicating code data specified user (refer data ROM). CLOCK TIMING GENERATOR clock generator supported dual clock system. high-frequency oscillator internal oscillator, working frequency MHz. low-frequency oscillator sourced from crystal osc, working frequency KHz. CLOCK GENERATOR STRUCTURE There clock generator system clock control unit, status register that hold status. P16, command register system clock mode control.
High-frequency generator Low-frequency generator
LXIN
System clock mode control
LXOUT
System control
LXIN LXIN LXOUT open LXOUT
Crystal connection
oscillator connection R=1M
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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SYSTEM CLOCK MODE CONTROL system clock mode controller start stop high-frequency low-frequency clock oscillator switch between basic clocks. EM73A88A four operation modes (DUAL, SLOW, IDLE STOP operation modes).
STOP operation mode High stopped stopped
wakeup Reset
Command (P16)
Reset
NORMAL operation mode
High oscillating oscillating Command (P22) Command (P22)
Command (P16)
Reset release
RESET operation
Reset
SLOW operation mode
High stopped oscillating
Reset
Command (P19)
internal timer wakeup
IDLE (CPU stops)
High stopped oscillating
Operation Mode NORMAL SLOW IDLE STOP
Oscillator System Clock Available function instruction cycle High, frequency High frequency clock LCD, speech, sound gen. frequency frequency clock frequency stops None stops disable
DUAL OPERATION MODE 4-bit DUAL operation mode when reseted. This mode dual clock system (high-frequency low-frequency clocks oscillating). changed SLOW STOP operation mode with command register (P22 P16). display, speech synthesizer sound generator available DUAL operation mode. SLOW OPERATION MODE SLOW operation mode single clock system (low-frequency clock oscillating). changed DUAL operation mode with command register (P22), STOP operation mode with IDEL operation mode with P19. display available SLOW operation mode. Speech synthesizer sound generator disabled this mode.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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Initial value 0000
Select operation mode DUAL operation mode SLOW operation mode
CPUS
Initial value *000
Low-frequency status LXIN source stable LXIN source stable Wakeup status Wakeup internal timer Wakeup internal timer
CPUS
status DUAL operation mode SLOW operation mode
Port14 status register CPU. P14.0 (CPU status) P14.1 (Low-frequency status) read-only bits. P14.2 (wakeup status) will when waked internal timer. P14.2 will cleared when user data P14. IDLE OPERATION MODE IDLE operation mode suspends functions except low-frequency clock oscillation driver. keeps internal status with power consumption without stopping slow clock oscillator display. display available IDLE operation mode. Sound generator disabled this mode. IDLE operation mode will wakeup return SLOW operation mode internal timing generator pins (P0(0.3)/WAKEUP P8(0.3)/WAKEUPA.D).
IDME SIDR
Initial value 0000
IDME
Enable IDLE mode Enable IDLE mode function
SIDR
Select IDLE releasing condition P0(0.3), P8(0.3) input P0(0.3), P8(0.3) input signal P0(0.3), P8(0.3) input signal P0(0.3), P8(0.3) input 15.625 signal
STOP OPERATION MODE STOP operation mode suspends system operation holds internal status immediately before suspension with power consumption. This mode will released reset pins (P0(0.3)/ WAKEUP P8(0.3)/WAKEUP A.D). display sound generator disabled STOP operation mode.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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SPME SWWT
Initial value 0000
SPME
Enable STOP mode Enable STOP mode function
SWWT
wake-up warm-up time 214/LXIN 210/LXIN 212/LXIN function
TIME BASE INTERRUPT (TBI time base used generate single fixed frequency interrupt. Eight types frequencies selected with "P25" setting.
initial value 0000
DUAL operation mode Interrupt disable Interrupt frequency LXIN Interrupt frequency LXIN Interrupt frequency LXIN Interrupt frequency LXIN Interrupt frequency LXIN Interrupt frequency LXIN Interrupt frequency LXIN Interrupt frequency LXIN Reserved
SLOW operation mode Interrupt disable Reserved Reserved Reserved Interrupt frequency LXIN Reserved Interrupt frequency LXIN Interrupt frequency LXIN Interrupt frequency LXIN Reserved
TIMER COUNTER TIMERA, TIMERB) Timer/counters support three special functions: Even counter Timer. Pulse-width measurement. These three functions executed timer/counter independently. With timerA, counter data saved timer register TAH, TAM, TAL. User counter initial value read counter value instruction "LDATAH(M,L)" "STATAH(M,L)". With timer register TBH, TBM, instruction "LDATBH (M,L)" "STATBH (M,L)". basic structure timer/counter composed identical counter module, these modules initial timer counter value timer registers, command registers timerA timer user choose different operation modes internal clock rates setting these registers. When timer/counter overflows, will generate TRGA(B) interrupt request interrupt control unit.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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INTERRUPT CONTROL TRGA request DATA
COUNTER COUNTER
TRGB request
P8.3/ TRGA internal clock
EVENT COUNTER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL
EVENT COUNTER CONTROL TIMER CONTROL PULSE-WIDTH MEASUREMENT CONTROL
P8.1/ TRGB
internal clock
TMSA
IPSA
TMSB
IPSB
TIMER/COUNTER CONTROL P8.1/TRGB, P8.3/TRGA external timer inputs timerB timerA, they used event counter pulse-width measurement mode. Timer/counter command port: command port timer/counterA timer/ counterB.
Port IPSA TIMER/COUNTER MODE SELECTION TMSA Port IPSB Stop Event counter mode Timer mode Pulse width measurement mode Function description
TMSA
Initial state: 0000
TMSB
Initial state: 0000
INTERNAL PULSE-RATE SELECTION IPSA(B) DUAL mode LXIN/23 LXIN/2 LXIN/2 11Hz LXIN/2 SLOW mode Reserved LXIN/2 LXIN/2 LXIN/215Hz
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
TIMER/COUNTER FUNCTION
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Timer/counterA,B programmable timer, event counter pulse width measurement mode. Each timer/counter execute these functions independently. EVENT COUNTER MODE under event counter mode, timer/counter increased rising edge P8.1/TRGB timerB (P8.3/TRGA timer When timerB (timerA) counts overflow, will provide interrupt request TRGB (TRGA) interrupt control unit.
P8.1/TRGB (P8.3/TRGA)
TimerB (TimerA) value
PROGRAM EXAMPLE: Enable timerA with
LDIA #0100b; OUTA P28; Enable timerA with event counter mode
TIMER MODE Under timer mode ,the timer/counter increased rising edge internal pulse. User choose types internal pulse rate setting IPSB timerB (IPSA timerA). When timer/counter counts overflow, interrupt request will sent interrupt control unit.
Internal pulse
TimerB (TimerA )value
PROGRAM EXAMPLE: generate TRGA interrupt request after with system clock LXlN=32KHz
LDIA #0100B; EXAE; enable mask EICIL 110111b; interrupt latch enable LDIA #0Ah; STATAL; LDIA #00h; STATAM; LDIA #0Fh; STATAH; LDIA #1000B; OUTA P28; enable timerA with internal pulse rate: LXIN/23
NOTE:
preset value timer/counter register calculated following procedure. Internal pulse rate: LXIN/23 LXIN 32KHz time timer counter count /LXIN 8/32768=0.244ms number internal pulse timer overflow 0.244ms 245.901= 0F6h preset value timer/counter register 1000h 0F6h F0Ah
PULSE WIDTH MEASUREMENT MODE
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin Under pulse width measurement mode, counter incresed rising edge internal pulse during
external timer/counter input (P8.1/TRGB, P8.3/TRGA high level, interrupt request generated soon timer/counter count overflow.
P8.1/TRGB(P8.3/TRGA)
Internal pulse
TimerB(TimerA) value
PROGRAM EXAMPLE: Enable timerA pulse width measurement mode.
LDIA #1100b; OUTA P28; Enable timerA with pulse width measurement mode.
INTERRUPT FUNCTION interrupt sources available, from external interrupt sources from internal interrupt sources. Multiple interrupts admitted according their priority.
Type Interrupt source Priority Interrupt Latch Interrupt Enable condition EI=1 EI=1, MASK3=1 EI=1, MASK2=1 EI=1, MASK1=1 EI=1,MASK0=1 ProgramROM entry address 002h 004h 006h 008h 00Ah 00Ch
External Internal Internal Internal Internal External
External interrupt(INT0) speech interrupt (SPI) TimerA overflow interrupt (TRGA) TimerB overflow interrupt (TRGB) Time base interrupt(TBI) External interrupt(INT1)
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3 INT1 Reset system reset program instruction TRGB TRGA
INT0
Priority checker Reset system reset program instruction program instruction
Entry address generator
Interrupt request
Interrupt entry address
Interrupt controller: IL0-IL5 Interrupt latch. Hold interrupt requests from interrupt sources. IL's program, reset program system reset, only decide which interrupt source accepted. Except INT0, MASK register permit inhibit interrupt sources.
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MASK0-MASK3
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
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Enable interrupt Flip-Flop promit inhibit interrupt sources, when interrupt occurs, auto cleared "0", after instruction executed, auto again.
Priority checker Check interrupt priority when multiple interrupts occur. INTERRUPT OPERATION procedure interrupt operation Push flags stack. interrupt entry address into Clear inhibit other interrupts occur. Clear with which interrupt source already been accepted. Excute interrupt subroutine from interrupt entry address. accept RTI, restore flags from stack. accept other interrupt requests. PROGRAM EXAMPLE: enable interrupt "INT0, TRGA"
LDIA #0100B; EXAE; mask register "1100b" EICIL 010111B enable interrupt F.F. clear
DRIVER directly drive liquid crystal display segments, commons output pins. There total 64x16 dots display. V1~V5 bias voltage input pins. driver control command register: Port27 Initial value: 0000 DISPLAY CONTROL Function description display disable Blanking function display enable Don't care. driver control command register. initial value 0000. When bit2 bit3 "00", display disabled. When "01", blanking, pins inactive pins output display data continuously. When "11", display enabled. display data area: display data stored display data area data memory (RAM). display data area illustrated below
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin display data from display data area automatically read send driver directly
hardware. Therefore, display patterns changed only overwritting contents display data area through software. dispaly memory area that used store display data could used ordinary data memory. display data area Bank1 P9.3=1
100-10Fh 110-11Fh 120-12Fh 130-13Fh 140-14Fh 150-15Fh 160-16Fh 170-17Fh 180-18Fh 190-19Fh 1A0-1AFh 1B0-1BFh 1C0-1CFh 1D0-1DFh 1E0-1EFh 1F0-1FFh COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63
start address register common pin. Port26 Initial value: 0000
Common start address register
100109h 110119h
COM1
120129h
COM2 COM1
130139h
COM3 COM2 COM1
140149h
COM4 COM3 COM2 COM1
150159h
COM5 COM4 COM3 COM2 COM1
160169h
COM6 COM5 COM4 COM3 COM2 COM1
170179h
COM7 COM6 COM5 COM4 COM3 COM2 COM1
180189h
COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
190199h
COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
1A01A9h
COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
1B01B9h
1C01C9h
1D01D9h
1E01F01EF9h 1F9h
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
COM0
COM10 COM11 COM12 COM13 COM14 COM15 COM10 COM11 COM12 COM13 COM14 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM10 COM11 COM12 COM13 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM10 COM11 COM12 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM10 COM11 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
COM15 COM0
COM14 COM15 COM0
COM13 COM14 COM15 COM0
COM12 COM13 COM14 COM15 COM0
COM11 COM12 COM13 COM14 COM15 COM0
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9 COM8 COM7 COM6 COM5 COM4 COM3
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9 COM8 COM7 COM6 COM5 COM4
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9 COM8 COM7 COM6 COM5
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9 COM8 COM7 COM6
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9 COM8 COM7
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9 COM8
COM10 COM11 COM12 COM13 COM14 COM15 COM0 COM9
COM10 COM11 COM12 COM13 COM14 COM15 COM0
PROGRAM EXAMPLE:
LDIA OUTA LDIA OUTA LDIA #0000B #1100B display enable #1010B store 1010B RAM[101h] P9,3 10.8.2001
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
waveform (1/5 bias)
TYPE
COM0
TYPE
COM0
COM0
COM1 COM15
COM1
SEG0
SEG0
SEG0-COM0
SEG0-COM0
SEG0-COM1
SEG0-COM1
Frame freq.=64Hz
Frame freq.=64Hz
drive voltage bias voltage supplied voltage multiplier. application circuit illustated below
0.1µF
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
SPEECH SYNTHESIZER
sound freq. P23,24 Write sound mode Write sound effect amplitude Write
Sound effect generator
speech
speech decoder
interrupt
Write data address (write times)
Read Read data
Write Write speech address (write times) sample rate
P5.3 read Speech active
Block diagram speech sound effect
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
EM73A88A speech synthesizer operates following Send speech start address address latch writing four times. Choose sampling rate, enable speech synthesizer writing address counters send address speech ROM. speech acknowledge signal. When speech synthesizer voice output. high When changed from high low, speech synthesizer generate speech ending interrupt SPI. signal read from P5.3. SPEECH SYNTHESIZER CONTROL Speech sample rate control register write) Initial value *111 Sample rate selection CLK/64/1/3 CLK/64/1/4 CLK/64/2/3 CLK/64/2/4 CLK/64/3/3 CLK/64/3/4 Sample rate
relimin
port initialization "*111". port initialization pointed lownibble start address latch. CLK=4.6
Speech active flag read)
Initial value 0***
speech acknowledge signal. When speech synthesizer voice output, high. When high low, speech synthesizer generate speech ending interrupt SPI. Speech start address register write) Port Initial value 1111
P6L1
P6L2
P6L3
P6L4
Send speech start address speech synthesizer writing four times. There pointer counter point address latch (P6L1, P6L2, P6L3, P6L4). will increase when write first time writing P6L1, second time P6L2, third time P6L3, fourth time P6L4 fifth time P6L1 latch again, etc. pointer counter point P6L1 when reset writen. NORMAL operation mode, speech synthesizer available. other operation modes, disable.
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10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
PROGRAM EXAMPLE:
LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA sample rate start speech LDIA OUTA wait speech WAIT SP_ADR1
relimin
1234H start address speech section #SP_ADR1 #SP_ADR1/10H #SP_ADR1/100H #SP_ADR1/1000H #0010B P5,3 WAIT speech active flag
USING SPEECH DATA speech used speech synthesizer data simutaneously. First, write initial address (five times), after four cycles, read data, address counter increases automatically.The following read operations must internval instruction cycles which more than read operation should done before leave normal mode change slow mode. speech data read) Port speech address write) Port P7L1 P7L2 P7L3 P7L4 P7L5
PROGRAM EXAMPLE:
D_ADR1 LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA 12345H start address speech #D_ADR1 #D_ADR1/10H #D_ADR1/100H #D_ADR1/1000H #D_ADR1/10000H
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
READ DATA
relimin
cycles
TEMP
read D_ADR1
cycles
read D_ADR1+1
MELODY (SOUND EFFECT) CONTROL channel melody/sound effect output, controlled port There built-in sound effect. includes tone generator random generator. tone generator binary down counter random generator 9-bit liner feedback shift register.
P23,P24 CLK/8
Tone kinds generator divider
Output control ckt.
f2x2
Random generator
Sound effect command register (P30) There kinds basic frequency sound generator which selected P30. output sound effect tone random combination. Port30
BFREQ SMODE Initial value 0000
BFREQ Basic frequency (f1) select CLK/16 CLK/32 CLK/64 Reserved (CLK=4.6MKz) Tone frequency register (P23, P24)
SMODE
Sound generator mode Disable Tone output Random output Tone+random output
8-bit tone frequency register P23. tone frequency will changed when user output different data P23. Thus, data must output before when users want change 8bit tone frequency (TF). Port24 Port23
Initial value 1111 1111 Higher nibble register Lower nibble register
f1=CLK/2X, f2=f1/(TF+1)/2, TF=1~255, TF-0 Example CLK=4.6 MHz, BFREQ=10, TF=00110001B. f1=143.75K f2=143.75K Hz/50/2=1430
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
Random generator f(x)=x9+x4+1
Volume control register (P17) levels volume sound generator. volume control register. Port17 Initial value 1111 ts/tp 15/16 14/16 CLK/64 (CLK=4.6MHz) 1/16 0/16 PROGRAM EXAMPLE:
LDIA OUTA LDIA OUTA LDIA OUTA LDIA OUTA #1001B #0111B #0011B #0001B basic frequency CLK/32, tone output volume control 1430 tone output
WATCH-DOG-TIMER (WDT) Watch-dog-timer help user detect malfunction (runaway) give system timeup signal every certain time User time signal give system reset signal when system fail. This function available mask option. mask option enabled, will stop counting when reseted STOP operation mode. basic structure Watch-Dog-Timer control composed 4-stage binary counter control unit counter counts certain time check status, there malfunction happened, counter will cleared continue counting Otherwise, there malfunction happened, control will send signal active reset CPU. checking period assign command port
counter LXIN/213 RESET counter clear request mask option control
command port
This specification subject changed without notice.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
control port watch-dog-timer, time signal connected RESET. Port
Initial value :0000
Clear watchdog timer counter Clear counter then return Nothing watch-dog-timer detect time 213/LXIN 213/32K 0.75 213/LXIN 213/32K 1.75
PROGRAM EXAMPLE enable with 213/LXIN detection time.
LDIA #0001B OUTA P21; detection time clear counter
RESETTING FUNCTION When normal working condition RESET held level three instruction cycles least, then begins initialize whole internal states, when RESET changes high level, begins work normal condition. internal state during reset condition following table Hardware condition RESET state Program counter Status flag Interrupt enable flip-flop MASK0 Interrupt latch CLK, LXIN Initial value 0000h Start oscillation
RESET hysteresis input pull-up resistor available mask option. simplest RESET circuit connect RESET with capacitor diode VDD.
RESET
This specification subject changed without notice.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
EM73A88A PORT DESCRIPTION
Port Input function Input port wakeup function -Input port P5.3 Speech active signal (ACT) -DATA data Input port, wakeup function, external interrupt input -CPU status register -Output function -P3(1.0) bank selection Output port Speech sample rate register Speech start address register Data start address register Output port P9.3 bank selection -STOP mode control register Sound effect volume control register -IDLE mode control register -WDT control register DUAL/SLOW mode control register Sound effect frequency register Sound effect frequency register Timebase control register common start address register control register Timer/counter control register Timer/counter control register Sound effect command register -Note
nibble high nibble
This specification subject changed without notice.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
APPLICATION CIRCUIT
VBAT
0.1µF
VBAT
0.1µF
VDD2
P0.0 P0.1 P0.2 LXOUT LXIN
SEG0~ SEG63 COM0~ COM15
PANNEL
0.1µF
0.1µF
RESET
0.1µF RESET
32.768KHz
0.022µF
EM73A88A
This specification subject changed without notice.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
ABSOLUTE MAXIMUM RATINGS
Items Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Sym. TSTG Ratings -0.5V -0.5V VDD+0.5V -0.5V VDD+0.5V 300mW 50oC -55oC 125oC Conditions
TOPR=50
RECOMMANDED OPERATING CONDITIONS
Items Supply Voltage Input Voltage Operating Frequency Sym. Ratings 2.2V 4.8V 0.90xVDD 0.10xVDD 4.6MHz 32KHz Condition
LXIN,LXOUT
ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, TOPR=25oC) Parameters
Supply current
Sym.
Min.
Typ.
-250 0.15
Max. Unit
0.75VDD 0.40VDD
Conditions
VDD=3.3V,no load,DUAL mode,Fs=32KHz, Fc=4.6MHz VDD=3.3V,SLOW mode,LCD VDD=3.3V,IDLE mode,LCD VDD=3.3V,IDLE mode,LCD VDD=3.3V, STOP mode RESET, RESET, VDD=3.3V,VIH=3.3/0V Open-drain, VDD=3.3V,VIH=3.3/0V Normal current push-pull,VDD=3.3V,P4(low), Push-pull, P4(high current PMOS), SOUND, VDD=2.7V, IOH=-0.9mA Push-pull, P4(low current PMOS), VDD=2.7V, IOH=-40µA VDD=2.7V,IOL=0.9mA, Open-drain, VDD=3.3V, VO=3.3V RESET
Hysteresis voltage Input current
VHYS+ VHYSIIH
0.50VDD 0.20VDD
-500
Output voltage
Leakage current Input resistor
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, TOPR=25oC) Parameters
Output current BZ1, Output current bias voltage
Sym.
Min.
Typ.
Max. Unit
Conditions
VDD=3V,VBZ=1.5V, VDD=3V,VO=0.7V VDD=3V, load
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
RESET TYPE
TYPE RESET-A
RESET
mask option
OSCILLATION TYPE
TYPE OSC-B
LXIN
TYPE OSC-G
Crystal Osc.
LXOUT
Internal Osc.
TYPE OSC-H
Osc.
LXIN
INPUT TYPE
TYPE INPUT-A TYPE INPUT-B
WAKEUP function mask option
mask option
P0/WAKEUP
TYPE INPUT-A
This specification subject changed without notice.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
TYPE TYPE
relimin
TYPE I/O-L
path path
mask option Output data latch
Special function control input Input data Output data
TYPE
WAKEUP function mask option
TYPE I/O-N
TYPE I/O-O
path path Input data
TYPE I/O-N
Output data latch
Output data Special function output
mask option
mask option
Path Path
clear port instructions, data goes through path from output data latch CPU. input test instructions, data from output through path output data latch will high.
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
DIAGRAM
SEG36 SEG40 SEG34 SEG35 SEG37 SEG38 SEG39 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53
SEG33 SEG32 P8.0 P8.1 P8.2 P8.3 P4.0 P4.1 P4.2 P4.3 P0.0 P0.1 P0.2 P0.3 VDD2 /RESET TEST LXIN LXOUT SEG31 SEG30
SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8
(0,0)
EM73A88A
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
This specification subject changed without notice.
SEG9
SEG54
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
Symbol
SEG33 SEG32 P8.0 P8.1 P8.2 P8.3 P4.0 P4.1 P4.2 P4.3 P0.0 P0.1 P0.2 P0.3 VDD2 /RESET TEST LXIN LXOUT SEG31 SEG30
-1104.7 -1104.7 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1099.8 -1104.7 -1104.7 -1104.7 -1104.7 -1104.7 -1104.7 -1104.7 -1104.7 -1104.7
1829.1 1708.6 1593.1 1482.6 1372.2 1261.7 1151.2 1040.8 930.3 819.9 709.4 598.9 488.5 378.0 257.5 133.7 23.3 -92.8 -223.6 -334.0 -444.5 -555.0 -665.4 -785.9 -915.2 -1025.7 -1136.1 -1246.6 -1359.6 -1475.1 -1590.6 -1708.6 -1829.1
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
Symbol
SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
-1113.7 -993.1 -875.1 -759.6 -646.6 -536.2 -425.7 -317.8 -212.3 -106.9 -1.5 103.9 209.3 314.8 422.7 533.2 643.6 756.6 872.1 993.1 1113.7
-1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7 -1949.7
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
Symbol
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55
1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7 1104.7
-1829.1 -1708.6 -1588.0 -1470.0 -1354.5 -1241.5 -1131.1 -1020.6 -910.2 -799.7 -689.2 -581.3 -474.4 -369.0 -263.6 -158.2 -52.7 52.7 158.1 263.5 368.9 474.4 581.3 689.2 799.7 910.2 1020.6 1131.1 1241.5 1354.5 1470.0 1588.0 1708.6 1829.1
This specification subject changed without notice.
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EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
Symbol
SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34
1113.7 993.1 872.1 756.6 643.6 533.2 422.7 314.8 209.3 103.9 -1.5 -106.9 -212.3 -317.8 -425.7 -536.2 -646.6 -759.6 -875.1 -993.1 -1113.7
1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7 1949.7
Unit Chip Size 2520 4210 Note layout, substrate must floated connected Vss.
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
INSTRUCTION TABLE
Data Transfer Mnemonic LDAM LDAX LDAXI LDHL LDIA STAM STAMD STAMI #k,y STDMI Rotate Mnemonic RLCA RRCA Object code binary 0101 0000 0101 0001 Object code binary 0110 1010 xxxx xxxx 0101 1010 0110 0101 0110 0111 1001 kkkk 0100 1110 xxxx xx00 1101 kkkk 1000 kkkk 0110 1001 xxxx xxxx 0101 1001 0111 1101 0111 1111 0100 1000 kkkk yyyy 1010 kkkk 0111 0110 0111 0100
relimin
Operation description AccRAM[x] RAM[HL] AccROM[DP]L AccROM[DP]H,DP+1 LRRAM[x],HRRAM[x+1] Acck RAM[x]Acc RAM[HL]Acc RAM[HL]Acc, LR-1 RAM[HL]Acc, LR+1 RAM[y]k RAM[HL]k, LR+1 AccHR AccLR
Byte
Cycle
Flag
Operation description CFAcc CFAcc
Byte
Cycle
Flag
Arithmetic operation Mnemonic ADCAM #k,y ADDA ADDAM ADDH ADDL ADDM DECA DECL DECM INCA Object code binary 0111 0100 0110 0111 0110 0110 0110 0101 0111 0101 0101 0000 1001 kkkk yyyy 1110 0101 kkkk 0001 1110 1001 kkkk 1110 0001 kkkk 1110 1101 kkkk 1100 1100 1101 1110 Operation description AccAcc RAM[HL] RAM[y]RAM[y] AccAcc+k AccAcc RAM[HL] HRHR+k LRLR+k RAM[HL]RAM[HL] AccAcc-1 LRLR-1 RAM[HL]RAM[HL] AccAcc Byte Cycle Flag
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
INCL INCM SUBA SBCAM SUBM 0111 1110 0101 1111 0110 1110 0111 kkkk 0111 0010 0110 1110 1111 kkkk LRLR RAM[HL]RAM[HL]+1 Acck-Acc AccRAM[HLl RAM[HL]k RAM[HL]
Logical operation
Mnemonic ANDA ANDAM ANDM ORAM XORAM Exchange Mnemonic Object code binary Operation description Byte Cycle Flag Object code binary 0110 0111 0110 0110 0111 0110 0111 1110 0110 kkkk 1011 1110 1110 kkkk 1110 0100 kkkk 1000 1110 1100 kkkk 1001 Operation description AccAcc&k AccAcc RAM[HL] RAM[HL]RAM[HL]&k AccAcc RAM[HL] RAM[HL]RAM[HL] AccAcc^RAM[HL]
Byte
Cycle
Flag
EXAH EXAL EXAM EXHL
0110 1000 xxxx xxxx 0110 0110 0110 0100 0101 1000 0100 1100 xxxx xx00
AccRAM[x] AccHR AccLR AccRAM[HL] LRRAM[x], HRRAM[x+1]
Branch
Mnemonic Object code binary Operation description Byte Cycle Flag
SLBR
00aa aaaa 1100 aaaa aaaa aaaa 0101 0101 1100 aaaa
aaaa aaaa (a:1000~1FFFh)
SF=1 then PCPC12-6.a5-0 else null then else null SF=1 then else null
0101 0111 1100 aaaa
aaaa aaaa (a:0000~0FFFh)
Compare
Mnemonic Object code binary Operation description Byte Cycle Flag
#k,y 0100 1011 kkkk yyyy CMPA 0110 1011 xxxx xxxx
k-RAM[y] RAM[x]-Acc
10.8.2001
This specification subject changed without notice.
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
relimin
Mnemonic Object code binary Operation description Byte Cycle Flag
CMPAM CMPH CMPIA CMPL
0111 0011 0110 1110 1011 kkkk 1011 kkkk 0110 1110 0011 kkkk
RAM[HL] k-LR
manipulation Mnemonic CLPL SEPL TFPL Object code binary 1111 00bb 0110 1101 11bb pppp 0110 0000 0110 1100 11bb yyyy 1111 01bb 0110 1101 01bb pppp 0110 0010 0110 1100 01bb yyyy 0110 1100 00bb yyyy 1111 10bb 1111 11bb 0110 1101 00bb pppp 0110 0001 0110 1100 10bb yyyy 0110 1101 10bb pppp Operation description RAM[HL]b0 PORT[p]b0 PORT[LR3-2+4]LR1-00 RAM[y]b0 RAM[HL]b1 PORT[p]b1 PORT[LR3-2+4]LRl-01 RAM[y]b1 SFRAM[y]b' SFAccb' SFRAM[HL]b' SFPORT[p]b' SFPORT[LR +4]LR1-0' SFRAM[y]b SFPORT[p]b Byte Cycle Flag
Subroutine Mnemonic LCALL SCALL Object code binary 0100 0aaa aaaa aaaa 1110 nnnn Operation description STACK[SP]PC, SPSP STACK[SP]PC, SPSP PCa, =115),0086h SPSP PCSTACK[SP] Byte Cycle Flag
(10) Input/output Mnemonic OUTA #k,p
0100 1111
Object code binary 0110 1111 0100 pppp 0110 1111 1100 pppp 0100 1010 kkkk pppp 0110 1111 000p pppp 0110 1111 100p pppp
Operation description AccPORT[p] RAM[HL]PORT[p] PORT[p]k PORT[p]Acc PORT[p]RAM[HL]
Byte
Cycle
Flag
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT (11) Flag manipulation Mnemonic TFCFC TTCFS
relimin
Operation description SFCF', SFCF, SFZF Byte Cycle Flag
Object code binary 0101 0011 0101 0010 0101 1011
(12) Interrupt control Mnemonic DICIL EICIL EXAE Object code binary 0110 0011 11rr rrrr 0110 0011 10rr rrrr 0110 0011 01rr rrrr 0111 0101 0100 1101 Operation description ILIL EIF0,ILIL&r EIF1,ILIL&r MASKAcc SPSP+1,FLAG.PC STACK[SP],EIF Byte Cycle Flag
(13) control Mnemonic Object code binary 0101 0110 Operation description operation Byte Cycle Flag
(14) Timer/Counter Data pointer Stack pointer control Mnemonic LDADPL LDADPM LDADPH LDASP LDATAL LDATAM LDATAH LDATBL LDATBM LDATBH STADPL STADPM STADPH STASP STATAL STATAM STATAH STATBL STATBM STATBH Object code binary 0110 1010 1111 1100 0110 1010 1111 1101 0110 1010 1111 1110 0110 1010 1111 1111 0110 1010 1111 0100 0110 1010 1111 0101 0110 1010 1111 0110 0110 1010 1111 1000 0110 1010 1111 1001 0110 1010 1111 1010 0110 1001 1111 1100 0110 1001 1111 1101 0110 1001 1111 1110 0110 1001 1111 1111 0110 1001 1111 0100 0110 1001 1111 0101 0110 1001 1111 0110 0110 1001 1111 1000 0110 1001 1111 1001 0110 1001 1111 1010 Operation description Acc[DP]L Acc[DP]M Acc[DP]H AccSP Acc[TA]L Acc[TA]M Acc[TA]H Acc[TB]L Acc[TB]M Acc[TB]H [DP]LAcc [DP]MAcc [DP]HAcc SPAcc [TA]LAcc [TA]MAcc [TA]HAcc TB]LAcc [TB]MAcc [TB]HAcc Byte Cycle Flag
This specification subject changed without notice.
10.8.2001
EM73A88A 4-BIT MICRO-CONTROLLER PRODUCT
**** SYMBOL DESCRIPTION
Symbol PORT[p] RAM[x] ROM[DP]H [DP]M [TA]L([TB]L) [TA]H([TB]H) LR3-2 PC12-6
relimin
Symbol STACK[SP] FLAG MASK RAM[HL] ROM[DP]L [DP]L [DP]H [TA]M([TB]M) a5-0 Description register Data pointer Stack specified flags Zero flag Enable interrupt register Interrupt mask Timer/counter Data memory (address 4-bit program memory 4-bit data pointer register High 4-bit data pointer register Middle 4-bit timer/counter (timer/counter register Contents assigned destination address branch instruction Transfer Addition Logic Logic Concatenation 8-bit address 4-bit 5-bit port address 6-bit interrupt latch
Description register Program counter Stack pointer Accumulator Carry flag Status flag Interrupt latch Port address Timer/counter Data memory (address High 4-bit program memory Middle 4-bit data pointer register 4-bit timer/counter (timer/counter register High 4-bit timer/counter (timer/counter register program counter Exchange Substraction Logic Inverse operation 4-bit immediate data 4-bit zero-page address address
This specification subject changed without notice.
10.8.2001
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