1.3GHz Phase Noise Frequency Synthesiser Preliminary Information
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SP5730
1.3GHz Phase Noise Frequency Synthesiser Preliminary Information
DS4877 issue July 1999
Complete 1.3GHz single chip system
Digital Terrestrial Television applications Selectable reference division ratio, compatible with (DTT) requirements Optimised phase noise, with comparison frequencies 4MHz prescaler Selectable reference/comparison frequency output Four selectable address fast mode compliant compatible with logic levels Four switching ports protection, (Normal Handling procedures should observed)
Ordering Information
SP5730A/KG/MP1S Sticks SP5730A/KG/MP1T Tape Reel SP5730A/KG/QP1S Sticks SP5730A/KG/QP1T Tape Reel
Description
SP5730 single chip frequency synthesiser designed tuning systems 1.3GHz optimised digital terrestrial applications. preamplifier interfaces direct with programmable divider, which MN+A construction giving step size equal loop comparison frequency prescaler phase noise degradation over operating range. comparison frequency obtained either from on-chip crystal controlled oscillator, from external source. oscillator frequency, Fref, phase comparator frequency, Fcomp, switched REF/COMP output providing reference frequency second frequency synthesiser. synthesiser controlled fast mode compliant. hard wired respond four addresses enable more synthesisers used common bus. device contains four switching ports P0-P3.
Applications
Digital Satellite ,Cable Terrestrial tuning systems Communications systems
SP5730
Preliminary Information
RF/COMP enable/select COUNT INPUT COUNT Lock fpd/2 LATCH PUMP mode disable CHARGE PUMP CRYSTAL CRYSTAL
DIVIDER
DRIVE
ADDRESS TRANSCEIVER
LATCH PORT INTERFACE
fpd/2 select
PORT PORT PORT P1PORT
Figure Block diagram
CHARGE PUMP CRYSTALIOUT CRYSTAL VEEA IFINB IFIN PORT P3/LOGLEV IVCCA PORT QOUT PORT
DRIVE VCCB VCODIS VCOINPUT VCOINPUT VEEB REF/COMP PSCAL ADDRESS PSCALB PORT VCCC
VEEC
SL1711B
MP16 Figure connections view
MP16 QP16
Preliminary Information
Electrical Characteristics
SP5730
Tamb= VCC= 5.5V These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage unless otherwise stated.
Characteristic Supply current input voltage input voltage input impedance SDA, Input high voltage Input voltage Input high voltage Input voltage Input high current Input current Leakage current Hysteresis output voltage
Value
Units mVrms mVrms
Conditions
13,14 13,14 13,14
12.5
1.3GHz, Figure. 50MHz 100MHz, Figure Figure.
logic selected logic selected logic selected logic selected Input voltage =Vcc Input voltage
Isink Isink
clock rate Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency Recommended crystal series resistance External reference input Frequency External reference drive level
Table Vpin1
Vpin1 +25°C
Vpin16 0.7V
Figure application "parallel resonant" crystal. Sinewave coupled through blocking capacitor Sinewave coupled through blocking capacitor
SP5730
Electrical Characteristics (continued)
Tamb= Vcc= 5.5V
Preliminary Information
These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage unless otherwise stated. Characteristic Buffered REF/COMP output output amplitude output impedance Phase detector Comparison frequency Equivalent phase noise phase detector division ratio Reference division ratio Output ports sink current Leakage current Address Select Input high current Input current Logic level select Input high level Input level Input current -0.5 0.35 Value Units coupled 0.5-20MHz Enabled note Conditions
dBc/Hz -152 -158
SSB, within loop bandwidth Fcomp 2MHz Fcomp 125kHz
32767 Table Note Vport Vport Figure Table note logic selected, open circuit logic selected
Notes: Output ports high impedance power with data, clock, enable logic REF/COMP output used, output should left open circuit connected Vcc, disabled setting Bi-directional port. When used output, input logic state ignored. When used input port should switched high impedance (off) state.
Preliminary Information
Absolute Maximum Ratings
voltages referred Characteristic Supply voltage, -0.3 input voltage port offsets -0.3 offset -0.3 Storage temperature Junction temperature QP16 thermal resistance, chip ambient chip case Power consumption 5.5V protection Vcc+0.3 +150 Units °C/W °C/W Conditions Transient Differential
SP5730
ports latest revision method 3015 class
Functional Description
SP5730 contains elements necessary, with exception frequency reference, loop filter external high voltage transistor, control varicap tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic, which enables generation loop with good phase noise performance. also operated with comparison frequencies appropriate frequency offsets required digital terrestrial (DTT) receivers block diagram shown Figure input signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier interfaces direct with 15-bit fully programmable divider, which MN+A architecture, where dual modulus prescaler 8/9, counter 3-bits, counter bits. output programmable divider phase comparator where compared both phase frequency domain with comparison frequency. This frequency derived either from on-board crystal controlled oscillator from external reference source. both cases reference frequency divided down comparison frequency reference divider which programmable into ratios detailed Table output phase detector feeds charge pump loop amplifier section, which when used with external high voltage transistor loop filter, integrates current pulses into varactor line voltage. programmable divider output divided switched port programming device into test mode. test modes described Table
Programming
SP5730 controlled data compatible with both standard fast mode formats with data generated from nominal 3.3V sources. logic level selected bi-directional port P3/LOGLEV. logic levels selected connecting P3/LOGLEV leaving open circuit 3.3V connecting ground. this port used input data should programmed high impedance. used output logic only levels used this case logic state imposed port input ignored. Data Clock lines respectively defined format. synthesiser either accept data (write mode), send data (read mode). address byte (R/W) sets device into write mode low, read mode high. Table illustrates format data. device programmed respond several addresses, which enables more than synthesiser system. Table shows address selected applying voltage `address' input.
SP5730
When device receives valid address byte, pulls line during acknowledge period, during following acknowledge periods after further data bytes received. When device programmed into read mode, controller accepting data must pull line during status byte acknowledge periods read another status byte. controller fails pull line during this period, device generates internal STOP condition, which inhibits further reading. Write mode With reference Table bytes contain frequency information bits 214-20 inclusive. Byte byte control reference divider ratio, Table charge pump setting, Table REF/COMP output, seeTable output ports test modes, Table After reception acknowledgement correct address (byte first following byte determines whether byte interpreted byte logic indicating byte logic indicating byte Having interpreted this byte either byte following data byte will interpreted byte respectively. Having received complete data bytes, additional data bytes entered, where byte interpretation follows same procedure, without readdressing device. This procedure continues until STOP condition received. STOP condition generated after data byte, however occurs during byte transmission, previous byte data retained. facilitate smooth fine tuning, frequency data bytes only accepted device after bits frequency data have been received, after generation STOP condition. Read mode When device read mode, status byte read from device takes form shown Table (POR) power-on reset indicator, this logic supply device dropped below 25°C), e.g. when device initially turned reset when read sequence terminated STOP command. When high this indicates that programmed information have been corrupted device reset power condition. (FL) indicates whether device phase locked, logic present device locked, logic device unlocked.
Preliminary Information
Programmable features
programmable divider Function described above Reference programmable divider Function described above. Charge pump current charge pump current grammed bits C1-C0 within data byte defined Table Test mode test modes invoked bits REB. described Table Reference/Comparison frequency output reference frequency Fref comparison frequency Fcomp switched REF/COMP output, function defined Table default logic during device power thus enabling comparison frequency Fcomp REF/COMP output.
Preliminary Information
don't care Table Reference division ratio Ratio Illegal state Illegal state Illegal State
SP5730
Address Programmable divider Programmable divider Control Data Control Data
Byte Byte Byte Byte Byte
Table Write data format (MSB transmitted first)
SP5730
Preliminary Information
Address Status byte
Byte Byte
Table Read data format (MSB transmitted first) MA1,MA0 R4-R0 T1-T0 P3-P0 Acknowledge Variable address bits (see Table Programmable division ratio control bits Reference division ratio select (see Figure Charge pump current select (see Figure REF/COMP output enable REF/COMP output select when RE=1 (see Figure Test mode control bits port output states Power reset indicator Phase lock flag
Address input voltage level 0.1Vcc Open circuit 0.4Vcc 0.6Vcc 0.9Vcc
Programmed connecting resistor between Table Address selection
RE.RS
Test mode description Normal operation Normal operation Port Fpd/2 Charge pump sink.* Status byte logic Charge pump source Status byte logic Charge pump disabled Status byte logic
*clocks need present crystal inputs enable charge pump test modes toggle Status byte Dont Care Table Test modes
Preliminary Information
SP5730
byte
byte 1087
Current 1450 1812
Table Charge pump current
68pF 150pF
SP5730
Figure XTAL oscillator application
don't care
REF/COMP OUTPUT High impedance High impedance Test mode enabled, Figure Fref selected Fcomp selected
Table REF/COMP output
SP5730
Preliminary Information
37.5
12.5
1000 Frequency (MHz)
1300
1500
Figure Typical input sensitivity
+j0.5
+j0.2
-j0.2
-j0.5
FREQUENCY MARKERS 1.3GHz, 1.8GHz, 2.3GHz, 2.8GHz 50MHz, 500Mhz, 1GHz 1.3GHz
Figure input impedance
100pF 100nF 100pF 100pF100nF 100nF 4u7F
0.1" HEADER
Synth
+30V Synth
100nF 100pF 4u7F 100nF
Preliminary Information
68pF 15nF
Varactor Line
2.2nF
Varactor Line
Charge Pump Drive Output Phase Comparator Xtal Xtal Input Programmable Divider PSOUTB
150pF
BCW31
82pF
Synth Input Interface Synth
4MHz
SCL5 SDA5
PSOUT
Synth Ref/Comp
P3/LL
Address
100pF 100pF
SP5769
LOSEL
SP5730
Figure evaluation board schematic
SP5730
Preliminary Information
Figure Evaluation board (top view)
Figure Evaluation board (bottom view)
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