1.3GHz Bidirectional Controlled Synthesiser Supersedes version Ap

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1.3GHz Bidirectional Controlled Synthesiser Supersedes version Ap

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SP5510
1.3GHz Bidirectional Controlled Synthesiser
Supersedes version April 1994 Consumer Handbook, HB3120 DS2184 Janaury 1997
SP5510 single-chip frequency synthesiser designed tuning systems. Control data entered standard format. device four addressable currentlimited output ports (P0-P3) four bi-directional opencollector ports (P4-P7), which (P6) also 3-bit 5-level input. information these ports read BUS. SP5510S variant 16-lead miniature plastic package, without P0-P2 functionally identical other respects. Both variants have fixed address three programmable addresses, allowing more synthesisers used system.
FEATURES Complete Single Chip System
Programmable Power Consumption (215mW Typ.) Radiation Phase Lock Detector Varactor Drive Disable Controllable Outputs, Bi-directional(SP5510) Controllable Outputs, Bi-directional (SP5510S) 5-Level Variable Address Picture Picture Protection
Normal handling precautions should observed.
APPLICATIONS Cable Tuning Systems VCRs ORDERING INFORMATION
SP5510 (18-lead plastic package) SP5510S (16-lead miniature plastic package) Fig. connections view
SP5510
ELECTRICAL CHARACTERISTICS
TAMB 10°C 80°C, references SP5510 (DP18 package). These Characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Value Characteristic Supply current Prescaler input voltage Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, Input high voltage Input voltage Input high current Input current Leakage current Output voltage Charge pump current Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance Output Ports P0-P3 sink current (see note P0-P3 leakage current (see note P4-P7 sink current P4-P7 leakage current Input Ports input current high input current input voltage input voltage high input current high input current Min. 15,16 15,16 Typ. 6400 10-13 10-13 6,8,9 6,8,9 Parallel resonant crystal (note VOUT VOUT VOUT VOUT Max. mVrms 50MHz 1GHz mVrms Fig. Units Conditions
Input voltage Input voltage When Sink current Byte Byte Byte
Table levels
NOTES Ports P0-P2 present SP5510S. maximum resistance quoted refers conditions, including start-up.
SP5510
ABSOLUTE MAXIMUM RATINGS
voltages referred references SP5510 (DP18 package) Parameter Supply voltage input voltage Port voltage Min. 15,16 6-13 10-13 6-13 15-16 Value Max. °C/W °C/W °C/W °C/W With applied applied Port state Port state Port state Units Conditions
Total port output current input offset Charge pump offset Drive output offset Crystal oscillator offset SDA, input voltage
Storage temperature Junction temperature DP18 thermal resistance, chip-to-ambient DP18 thermal resistance, chip-to-case MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case Power consumption
Fig. Block diagram. (Ports P0-P2 present SP5510S)
SP5510
FUNCTIONAL DESCRIPTION
SP5510 programmed from BUS. Data Clock lines respectively defined format. synthesiser either accept data (write mode) send data (read mode). Tables Fig. illustrate format data. device programmed respond several addresses, which enables more than synthesiser system. Table shows address selected applying voltage address Byte (R/W) sets device into read mode high write mode low. When SP5510 receives correct address Byte pulls line during acknowledge period during following acknowledge periods after further data Bytes programmed. When SP5510 programmed into read mode controlling device accepting data must pull down line during following acknowledge period read another status Byte. local oscillator control voltage until output programmable divider frequency phase locked comparison frequency. reference frequency generated external source capacitively coupled into provided onchip 4MHz crystal controlled oscillator. Note that comparison frequency when 4MHz reference used. Byte programming data (CP) controls current charge pump circuit, logic 170µA logic 50µA, allowing compensation variable tuning slope tuner also enable fast channel changes over full band. Byte (T0) disables charge pump logic Byte (OS) switches charge pump drive amplifier's output when logic Byte (T1) selects test mode where phase comparator inputs available logic connects FCOMP FDIV Byte programs output ports P0-P7, logic high impedance output, logic impedance (on).
WRITE MODE (FREQUENCY SYNTHESIS)
When device write mode Bytes select synthesised frequency while Bytes select output port states charge pump information. Once correct address received acknowledged, first next Byte determines whether that Byte interpreted Byte logic frequency information logic charge pump output port information. Additional data Bytes entered without need readdress device until stop condition recognised. This allows smooth frequency sweep fine tuning purposes. transmission data stopped mid-byte (i.e., another device bus) then previously programmed byte maintained. Frequency data from Bytes stored 15-bit shift register used control division ratio 15-bit programmable divider which preceded divide-by-8 prescaler amplifier give excellent sensitivity local oscillator input; input impedance shown Figs. programmed frequency calculated multiplying programmed division ratio times comparison frequency FCOMP When frequency data entered, phase comparator, charge pump varactor drive amplifier, adjusts
READ MODE
When device read mode status data read from device line takes form shown Table (POR) power reset indicator logic power supply device dropped below nominal programmed information lost (e.g., when device initially turned on). when read sequence terminated stop command. outputs high impedance when device initially powered (FL) indicates whether device phase locked, logic present device locked logic device unlocked. Bits (I2, show status Ports respectively. logic indicates level logic high level. ports used inputs they should programmed high impedance state (logic1). These inputs will then respond data complying with standard voltage levels. Bits (A2,A1,A0) combine give output 5-level ADC. 5-level used feed information microprocessor from section television, illustrated Fig.
SP5510
Address Programmable divider Programmable divider Charge pump test bits port control bits
Byte Byte Byte Byte Byte
Table Write data format (MSB transmitted first)
Address Status byte
Byte Byte
Table Read data format
Voltage input Voltage input Always valid
Table levels MA1, P2*,
Table Address selection Acknowledge Variable address bits (see Table Charge Pump current select Test mode selection Charge pump disable Varactor drive Output disable Switch Control output port states Power Reset indicator Phase lock detect flag Digital information from ports respectively 5-level data from (see Table
NOTE Don't care condition SP5510S.
Fig. Data formats
SP5510
APPLICATION
typical application shown Fig. input/output interface circuits shown Fig.
Fig. Typical application
Fig. Typical input sensitivity
SP5510
Fig. SP5510 input/output interface circuits
SP5510
Fig. Typical input impedance, SP5510
Fig. Typical input impedance, SP5510S
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1.3GHz Bidirectional Controlled Synthesiser Supersedes version Ap

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