State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

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State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

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SN54ABT125, SN74ABT125 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Protection Exceeds 2000 MIL-STD-883, Method 3015; Exceeds Using Machine Model Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C High-Impedance State During Power Power Down High-Drive Outputs (-32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat Package, Plastic Ceramic DIPs
SN54ABT125 PACKAGE SN74ABT125 PACKAGE (TOP VIEW)
SN54ABT125 PACKAGE (TOP VIEW)
description
'ABT125 quadruple buffer gates feature independent line drivers with 3-state outputs. Each output disabled when associated output-enable (OE) input high. When between device high-impedance state during power power down. However, ensure high-impedance state above should tied through pullup resistor; minimum value resistor determined current-sinking capability driver.
internal connection
SN54ABT125 characterized operation over full military temperature range -55°C 125°C. SN74ABT125 characterized operation from -40°C 85°C.
FUNCTION TABLE (each buffer) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC-B trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1997, Texas Instruments Incorporated
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SN54ABT125, SN74ABT125 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
logic symbol
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages.
logic diagram (positive logic)
numbers shown packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, SN54ABT125 SN74ABT125 Input clamp current, Output clamp current, Package thermal impedance, (see Note package 127°C/W package 158°C/W package 78°C/W package 170°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stressratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with EIA/JEDEC JESD51, except through-hole packages, which trace length zero.
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SN54ABT125, SN74ABT125 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54ABT125 t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Power-up ramp rate Operating free-air temperature SN74ABT125 UNIT ns/V µs/V
NOTE Unused inputs must held high prevent them from floating.
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SN54ABT125, SN74ABT125 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER Vhys IOZPU IOZPD IOZH IOZL Ioff ICEX TEST CONDITIONS Data inputs Control inputs input Other inputs Outputs high Outputs high Outputs Outputs disabled Outputs enabled Outputs disabled -100 ±100 0.05 0.05 ±100 0.05 0.55 0.55* 0.55 0.55 25°C -1.2 SN54ABT125 -1.2 SN74ABT125 -1.2 UNIT
ICC#
input Other inputs
products compliant MIL-PRF-38535, this parameter does apply. typical values This parameter characterized, production tested. more than output should tested time, duration test should exceed second. This limit vary among suppliers. This increase supply current each input that specified voltage level rather than GND.
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SN54ABT125, SN74ABT125 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
switching characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) 25°C SN54ABT125 SN74ABT125 UNIT
This limit vary among suppliers.
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SN54ABT125, SN74ABT125 QUADRUPLE BUFFER GATES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
From Output Under Test (see Note
LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING tPLZ tPHZ
Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated

State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

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