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55°C 125°C Operating Temperature Range, Processing Processed MIL-PRF-3


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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
55°C 125°C Operating Temperature Range, Processing Processed MIL-PRF-38535 (QML) Approval 50-MHz Versions High-Performance Floating-Point Digital Signal Processor (DSP): SMJ320C31-50 40-ns Instruction Cycle Time Million Operations Second (MOPS), Million Floating-Point Operations Second (MFLOPS), Million Instructions Second (MIPS) SMJ320C31-40 50-ns Instruction Cycle Time MOPS, MFLOPS, MIPS SMJ320LC31-40 (3.3 50-ns Instruction Cycle Time MOPS, MFLOPS, MIPS SMQ320LC31-40 (3.3 50-ns Instruction Cycle Time MOPS, MFLOPS, MIPS 32-Bit High-Performance 32-Bit Integer 40-Bit Floating-Point Operations 32-Bit Instruction Data Words, 24-Bit Addresses Word 32-Bit Single-Cycle Dual-Access On-Chip Blocks Boot-Program Loader 64-Word 32-Bit Instruction Cache Eight Extended-Precision Registers Address Generators With Eight Auxiliary Registers Auxiliary Register Arithmetic Units (ARAUs) Low-Power Modes
On-Chip Memory-Mapped Peripherals: Serial Port Supporting 32-Bit Transfers 32-Bit Timers One-Channel Direct Memory Access (DMA) Coprocessor Concurrent Operation Fabricated Using Enhanced Performance Implanted CMOS (EPICTM) Technology Texas Instruments (TITM) Two- Three-Operand Instructions 32-Bit Floating-Point Integer Multiplier Arithmetic Logic Unit (ALU) Parallel Multiplier Execution Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls Returns Interlocked Instructions Multiprocessing Support Bus-Control Registers Configure Strobe-Control Wait-State Generation Validated Compiler Integer, Floating-Point, Logical Operations 32-Bit Barrel Shifter 32-Bit Data (24-Bit Address) Packaging 132-Lead Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) 141-Pin Ceramic Staggered Grid- Array Package (GFA Suffix) 132-Lead Frame 132-Lead Plastic Quad Flatpack Suffix)
description
SMJ320C31, SMJ320LC31, SMQ320LC31 digital signal processors (DSPs) 32-bit, floating-point processors manufactured 0.72-µm triple-level-metal CMOS technology. devices part SMJ320C3x generation DSPs from Texas Instruments.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC trademarks Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1999, Texas Instruments Incorporated
products compliant MIL-PRF-38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
description (continued)
SMJ320C3x internal busing special digital-signal-processing instruction have speed flexibility execute MFLOPS. SMJ320C3x optimizes speed implementing functions hardware that other processors implement through software microcode. This hardware-intensive approach provides performance previously unavailable single chip. SMJ320C3x perform parallel multiply operations integer floating-point data single cycle. Each processor also possesses general-purpose register file, program cache, dedicated ARAUs, internal dual-access memories, channel supporting concurrent I/O, short machine-cycle time. High performance ease results these features. General-purpose applications greatly enhanced large address space, multiprocessor interface, internally externally generated wait states, external interface port, timers, serial port, multiple-interrupt structure. SMJ320C3x supports wide variety system applications from host processor dedicated coprocessor. High-level-language support easily implemented through register-based architecture, large address space, powerful addressing modes, flexible instruction set, well-supported floating-point arithmetic.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
141-PIN STAGGERED GRID ARRAY PACKAGE BOTTOM VIEW
PACKAGE VIEW
Face Leads
132-PIN QUAD FLATPACK VIEW
PACKAGE VIEW
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Leads
Face
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
SMQ320LC31 pinout (top view)
SMQ320LC31 device also packaged a132-pin plastic quad flatpack Suffix). full part numbers SMQ320LC31PQM40 5962-9760601NXB.
PACKAGE (TOP VIEW)
MCBL/MP EMU2 EMU1 EMU0 EMU3 TCLK1 TCLK0
FSX0 CLKX0 CLKR0 FSR0 INT3 INT2 INT1 INT0 IACK RESET STRB HOLD HOLDA X2/CLKIN
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
Terminal Assignments
NUMBER NAME CLKR0 CLKX0 NUMBER NAME EMU0 EMU1 EMU2 EMU3 FSR0 FSX0 HOLD HOLDA IACK INT0
CVSS, VSSL, IVSS same plane. AVDD, DVDD, CVDD, PVDD same plane. VSUBS connects metallization. this clean ground.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
Terminal Assignments (Continued)
NUMBER NAME INT1 INT2 INT3 MCBL/MP RESET STRB TCLK0 TCLK1 AVDD AVDD AVDD VDDL VDDL DVDD DVDD DVDD VDDL VDDL DVDD DVDD CVDD CVDD VDDL VDDL PVDD PVDD VDDL VDDL VSSL DVSS CVSS DVSS CVSS NUMBER NAME VSSL VSSL DVSS IVSS DVSS CVSS IVSS DVSS VSSL VSSL DVSS CVSS IVSS DVSS VSSL CVSS IVSS DVSS CVSS X2/CLKIN Connect DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
CVSS, VSSL, IVSS same plane. AVDD, DVDD, CVDD, PVDD same plane. VSUBS connects metallization. this clean ground.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
Terminal Functions
TERMINAL NAME PRIMARY-BUS INTERFACE STRB I/O/Z 32-bit data port 24-bit address port Read write. high when read performed when write performed over parallel interface. External-access strobe Ready. indicates that external device prepared transaction completion. Hold. When HOLD logic low, ongoing transaction completed. STRB, placed high-impedance state transactions over primary-bus interface held until HOLD becomes logic high until NOHOLD primary-bus-control register set. Hold acknowledge. HOLDA generated response logic HOLD. HOLDA indicates that STRB, high-impedance state that transactions over held. HOLDA high response logic high HOLD NOHOLD primary-bus-control register set. CONTROL SIGNALS RESET INT3 INT0 IACK MCBL Reset. When RESET logic low, device reset condition. When RESET becomes logic high, execution begins from location specified reset vector. External interrupts Interrupt acknowledge. IACK generated IACK instruction. IACK used indicate beginning interrupt-service routine. Microcomputer boot-loader microprocessor mode-select Shutdown high impedance. When active, shuts down device places pins high-impedance state. used board-level testing ensure that dual-drive conditions occur. CAUTION: corrupts device memory register contents. Reset device with high restore known operating condition. External flags. used general-purpose support interlocked processor instruction. SERIAL PORT SIGNALS CLKR0 CLKX0 FSR0 FSX0 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Serial port receive clock. CLKR0 serial shift clock serial port receiver. Serial port transmit clock. CLKX0 serial shift clock serial port transmitter. Data-receive. Serial port receives serial data DR0. Data-transmit output. Serial port transmits serial data DX0. Frame-synchronization pulse receive. FSR0 pulse initiates data-receive process using DR0. Frame-synchronization pulse transmit. FSX0 pulse initiates data-transmit process using DX0. TIMER SIGNALS TCLK0 TCLK1 I/O/Z I/O/Z Timer clock input, TCLK0 used timer count external pulses. output, TCLK0 outputs pulses generated timer Timer clock input, TCLK0 used timer count external pulses. output, TCLK1 outputs pulses generated timer TYPE DESCRIPTION CONDITIONS WHEN SIGNAL TYPE
HOLD
HOLDA
XF1,
I/O/Z
input, output, high-impedance state active, HOLD active, RESET active
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
Terminal Functions (Continued)
TERMINAL NAME SUPPLY OSCILLATOR SIGNALS CLKIN EMU2 EMU0 External clock. period equal twice CLKIN. External clock. period equal twice CLKIN. supply 'C31 devices 3.3-V supply 'LC31 devices. must connected common supply Ground. grounds must connected common ground plane. Output from internal-crystal oscillator. crystal used, should left unconnected. Internal-oscillator input from crystal clock TYPE DESCRIPTION CONDITIONS WHEN SIGNAL TYPE
Reserved emulation. pullup resistors EMU3 Reserved emulation input, output, high-impedance state active, HOLD active, RESET active Recommended decoupling capacitor value Follow connections specified reserved pins. 22-k pullup resistors best results. supply pins must connected common supply plane, ground pins must connected common ground plane.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
functional block diagram
Cache Block Block
PDATA PADDR HOLD HOLDA STRB D31- DDATA DADDR1 DADDR2 DMADATA DMAADDR
Controller Serial Port Global-Control Register Serial-Port-Control Register Receive/Transmit Timer Register Data-Transmit Register Data-Receive Register FSX0 CLKX0 FSR0 CLKR0
RESET INT(3 IACK MCBL XF(1,0) VDD(19 VSS(24 CPU1 CPU2 REG1 REG2 Controller CPU1 REG1 REG2 Multiplier 32-Bit Barrel Shifter ExtendedPrecision Registers (R7-R0) Source-Address Register DestinationAddress Register TransferCounter Register Peripheral Address
Peripheral Data
CLKIN EMU(3
DISP0, IR0, Global-Control Register ARAU0 ARAU1 Timer-Period Register Auxiliary Registers (AR0 AR7) Port Control Other Registers (12) STRB-Control Register Timer-Counter Register TCLK1
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Boot Loader Timer Global-Control Register Timer-Period Register Timer-Counter Register Timer TCLK0
SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
memory
Reset, Interrupt, Trap Vector, Reserved Locations (64) (External STRB Active)
03Fh 040h
Reserved Boot-Loader Operations
External STRB Active Words Words)
FFFh 1000h
Boot External STRB Active Words Words)
400000h 7FFFFFh 800000h Reserved (32K Words) 807FFFh 808000h Peripheral Memory-Mapped Registers Words Internal) 807FFFh 808000h 7FFFFFh 800000h
Boot
Reserved (32K Words) Peripheral Memory-Mapped Registers Words Internal)
8097FFh 809800h Block Words Internal) 809BFFh 809C00h
8097FFh 809800h Block Words Internal) 809BFFh 809C00h Block Words Words Internal) Block Words Internal) 809FC0h 809FC1h User-Program Interrupt Trap Branches Words Internal) External STRB Active Words Words)
809FFFh 80A000h
External STRB Active Words Words)
809FFFh 80A000h FFF000h FFFFFFh Boot
FFFFFFh Microprocessor Mode
Microcomputer/Boot-Loader Mode
Figure depicts memory SMJ320C31. TMS320C3x Users Guide (literature number SPRU031) detailed description this memory mapping.
Figure SMJ320C31 Memory
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
memory (continued)
Reset INT0 INT1 INT2 809FC4h INT3 809FC5h XINT0 RINT0 Reserved TINT0 TINT1 DINT Reserved TRAP 809FC6h 809FC7h 809FC8h 809FC9h 809FCAh 809FCBh 809FCCh 809FDFh 809FE0h TINT0 TINT1 DINT Reserved TRAP RINT0 Reserved XINT0 INT3 809FC1h 809FC2h 809FC3h INT0 INT1 INT2
TRAP Reserved Microprocessor Mode
809FFBh 809FFCh 809FFFh
TRAP Reserved
Microcomputer Boot-Loader Mode
Figure Reset, Interrupt, Trap Vector/Branches Memory-Map Locations
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
memory (continued)
808000h 808004h 808006h 808008h 808020h 808024h 808028h 808030h 808034h 808038h 808040h 808042h 808043h 808044h 808045h 808046h 808048h 80804Ch 808064h Global Control Source Address Destination Address Transfer Counter Timer Global Control Timer Counter Timer Period Register Timer Global Control Timer Counter Timer Period Register Serial Global Control FSX/DX/CLKX Serial Port Control FSR/DR/CLKR Serial Port Control Serial Timer Control Serial Timer Counter Serial Timer Period Register Data-Transmit Data-Receive Primary-Bus Control
Shading denotes reserved address locations
Figure Peripheral Memory-Mapped Registers
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
absolute maximum ratings over specified temperature range (unless otherwise noted)
'C31 Supply voltage, (see Note 'LC31
(for SMJ320LC31-33)
Input voltage, Output voltage, Continuous power dissipation (worst case) (see Note (for SMJ320C31-33) Operating free-air temperature, -55°C 125°C Storage temperature, Tstg 65°C 150°C
-55°C 125°C 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: voltage values with respect VSS. Actual operating power less. This value obtained under specially produced worst-case test conditions TMS320C31-33 TMS320LC31-33, which sustained during normal device operation. These conditions consist continuous parallel writes checkerboard pattern both primary extension buses maximum rate possible. normal (ICC) current specification electrical characteristics table also read Calculation TMS320C30 Power Dissipation Application Report (literature number SPRA020).
recommended operating conditions (see Note
'C31 Supply voltage (DVDD, etc.) Supply voltage (CVSS, etc.) High-level input voltage (except RESET) High-level input voltage (RESET) Low-level input voltage High-level output current Low-level output current Operating free-air temperature 0.3* '320C31-40 '320C31-50 '320LC31-40 4.75 4.75 0.3* 0.3* 0.3* 5.25 5.25 3.13 0.3* 0.3* 3.47 'LC31 UNIT
High-level input voltage CLKIN 0.3* 0.3* This parameter production tested. NOTE voltage values with respect VSS. input output voltage levels TTL-compatible. CLKIN driven CMOS clock.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
electrical characteristics over recommended ranges supply voltage (unless otherwise noted) (see Note
PARAMETER High-level output voltage Low-level output voltage High-impedance current Input current Input current (with internal pullup) Supply Supply current Input capacitance CLKIN TEST CONDITIONS MIN, MIN, Inputs with internal 25°C, Standby, inputs except CLKIN 'C31-40 'LC31-40 'C31 'LC31 UNIT
'C31-50 IDLE2 Clocks shut
Output capacitance input output voltage levels compatible. 'C31, typical values 25°C. 'LC31, typical values 25°C. Pins with internal pullup devices: INT3 INT0, MCBL Actual operating current less than this maximum value. This value obtained under specially produced worst-case test conditions, which sustained during normal device operation. These conditions consist continuous parallel writes checkerboard pattern both primary expansion buses maximum rate possible. Calculation TMS320C30 Power Dissipation Application Report (literature number SPRA020). input clock frequency. This parameter production tested. NOTE voltage values with respect VSS. input output voltage levels TTL-compatible. CLKIN driven CMOS clock.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
PARAMETER MEASUREMENT INFORMATION
Tester Electronics
VLoad
Output Under Test
Where:
VLOAD
(all outputs) (all outputs) Selected emulate termination (typical value 1.54 80-pF typical load-circuit capacitance
Figure SMJ320C31 Test Load Circuit
signal transition levels 'C31 (see Figure Figure
TTL-level outputs driven minimum logic-high level maximum logic-low level Output transition times specified follows:
high-to-low transition TTL-compatible output signal, level which output said longer high level which output said low-to-high transition, level which output said longer level which output said high
Figure TTL-Level Outputs Transition times TTL-compatible inputs specified follows:
high-to-low transition input signal, level which input said longer high level which input said low-to-high transition input signal, level which input said longer level which input said high
Figure TTL-Level Inputs
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
PARAMETER MEASUREMENT INFORMATION
Tester Electronics
VLoad
Output Under Test
Where:
VLOAD
(all outputs) (all outputs) 2.15 80-pF typical load-circuit capacitance
Figure SMJ320LC31 Test Load Circuit
signal transition levels 'LC31 (see Figure Figure
Outputs driven minimum logic-high level maximum logic-low level Output transition times specified follows:
high-to-low transition output signal, level which output said longer high level which output said low-to-high transition, level which output said longer level which output said high
Figure 'LC31 Output Levels Transition times inputs specified follows:
high-to-low transition input signal, level which input said longer high level which input said low-to-high transition input signal, level which input said longer level which input said high
Figure 'LC31 Input Levels
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
PARAMETER MEASUREMENT INFORMATION timing parameter symbology
Timing parameter symbols used herein were created accordance with JEDEC Standard 100-A. order shorten symbols, some names other related terminology have been abbreviated follows, unless otherwise noted:
ASYNCH CLKR CONTROL GPIO Asynchronous reset signals CLKX0 CLKIN CLKR0 Control signals FSX/R FSX0 FSR0 General-purpose input General-purpose input/output; peripheral General-purpose output HOLD HOLDA IACK RESET TCLK XFIO HOLD HOLDA IACK INT3 INT0 RESET STRB CLKX/R TCLK0, TCLK1, TCLKx XF0, XF1, switching from input output
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
timing
Timing specifications apply SMJ320C31 SMJ320LC31. X2/CLKIN, timing following table defines timing parameters X2/CLKIN, interface signals.
timing parameters X2/CLKIN, (see Figure Figure Figure Figure
tf(CI) tw(CIL) tw(CIH) tr(CI) tc(CI) tf(H) tw(HL) tw(HH) tr(H) td(HL-HH) Fall time, CLKIN Pulse duration, CLKIN tc(CI) Pulse duration, CLKIN high tc(CI) Rise time, CLKIN Cycle time, CLKIN Fall time, Pulse duration, Pulse duration, high Rise time, Delay time. from high from high 'C31-40 'LC31-40 'C31-50 UNIT
tc(H) Cycle time, tc(CI) This parameter production tested. X2/CLKIN
Figure Timing X2/CLKIN
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
X2/CLKIN, timing (continued)
Figure Timing
8.00 7.00 6.00 CLKIN H1/H3 5.00 4.00 3.00 2.00 1.00 0.00 -60.00 Band 0.00 Band
-40.00
-20.00
20.00
40.00 Temperature
60.00
80.00
100.00
120.00
140.00
Figure SMJ320C31 CLKIN Function Temperature (Typical)
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
X2/CLKIN, timing (continued)
12.00
10.00 CLKIN H1/H3
Band
8.00
6.00
4.00
Band
2.00
0.00 -60.00
-40.00 -20.00 0.00 20.00 40.00 Temperature 60.00 80.00 100.00 120.00 140.00
Figure SMJ320LC31 CLKIN Function Temperature (Typical)
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
memory read/write timing following table defines memory read/write timing parameters STRB.
timing parameters memory (STRB read/write (see Figure Figure
td(H1L-SL) td(H1L-SH) td(H1H-RWL)R td(H1L-A) tsu(D-H1L)R th(H1L-D)R tsu(RDY-H1H) th(H1H-RDY) td(H1H-RWH)W tv(H1L-D)W th(H1H-D)W td(H1H-A)W Delay time, STRB Delay time, STRB high Delay time, high (read) Delay time, valid Setup time, before (read) Hold time, after (read) Setup time, before high Hold time, after high Delay time, high high (write) Valid time, after (write) Hold time, after high (write) Delay time, high valid back-to-back write cycles (write) 'C31-40 'LC31-40 'C31-50 UNIT
td(A-RDY) Delay time, from valid Figure address timing variation with load capacitance greater than typical load-circuit capacitance pF). This parameter production tested. STRB
NOTE STRB remains during back-to-back read operations.
Figure Timing Memory (STRB Read
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
memory read write timing (continued)
STRB
Figure Timing Memory (STRB Write
Address-Bus Timing Variation Load Capacitance
Change Address-Bus Timing, 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50
Change Load Capacitance, NOTE pF/ns slope
Figure Address-Bus Timing Variation With Load Capacitance (see Note
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
timing when executing LDFI LDII following table defines timing parameters during execution LDFI LDII.
timing when executing LDFI LDII SMJ320C31 (see Figure
td(H3H-XF0L) tsu(XF1-H1L) th(H1L-XF1) Delay time, high Setup time, before Hold time, after 'C31-40 'LC31-40 'C31-50 UNIT
Fetch LDFI LDII
Decode
Read
Execute
STRB
Figure Timing When Executing LDFI LDII
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
timing when executing STFI STII following table defines timing parameters during execution STFI STII.
timing when executing STFI STII (see Figure
'C31-40 'LC31-40 'C31-50 UNIT
td(H3H-XF0H) Delay time, high high always high beginning execute phase interlock-store instruction. When pipeline conflicts occur, address store also driven beginning execute phase interlock-store instruction. However, pipeline conflict prevents store from executing, address store will driven until store execute. Fetch STFI STII Decode Read Execute
STRB
Figure Timing When Executing STFI STII
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
timing when executing SIGI following table defines timing parameters pins during execution SIGI.
timing when executing SIGI SMJ320C31 (see Figure
td(H3H-XF0L) td(H3H-XF0H) tsu(XF1-H1L) th(H1L-XF1) Delay time, high Delay time, high high Setup time, before Hold time, after 'C31-40 'LC31-40 'C31-50 UNIT
Fetch SIGI
Decode
Read
Execute
Figure Timing When Executing SIGI
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
loading when configured output following table defines timing parameter loading register when configured output.
timing loading register when configured output (see Figure
tv(H3H-XF) Valid time, high 'C31-40 'LC31-40 'C31-50 UNIT
Fetch Load Instruction
Decode
Read
Execute
OUTXFx (see Note
NOTE OUTXFx represents either register.
Figure Timing Loading Register When Configured Output
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
changing from output input following table defines timing parameters changing from output input pin.
timing changing from output input mode SMJ320C31 (see Figure
th(H3H-XF) tsu(XF-H1L) Hold time, after high Setup time, before 'C31-40 'LC31-40 'C31-50 UNIT
th(H1L-XF) Hold time, after This parameter production tested.
Execute Load
Buffers From Output Output
Synchronizer Value Seen Delay
OxFx (see Note Output
INXFx (see Note
Data Sampled Data Seen
NOTE OxFx represents either register, INXFx represents either register.
Figure Timing Change From Output Input Mode
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
changing from input output following table defines timing parameter changing from input output pin.
timing changing from input output mode (see Figure
td(H3H-XFIO) Delay time, high switching from input output 'C31-40 'LC31-40 'C31-50 UNIT
Execution Load
OxFx (see Note
NOTE OxFx represents either register.
Figure Timing Change From Input Output Mode reset timing RESET asynchronous input that asserted time during clock cycle. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle possible. asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, TCLK0/1. Resetting device initializes primary- expansion-bus control registers seven software wait states therefore results slow external accesses until these registers initialized. HOLD asynchronous input asserted during reset.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
RESET timing (see Figure
tsu(RESET-CIL) td(CLKINH-H1H) td(CLKINH-H1L) tsu(RESETH-H1L) td(CLKINH-H3L) td(CLKINH-H3H) tdis(H1H-DZ) tdis(H3H-AZ) td(H3H-CONTROLH) td(H1H-RWH) td(H1H-IACKH) tdis(RESETL-ASYNCH) Setup time, RESET before CLKIN Delay time, CLKIN high high (see Note Delay time, CLKIN high (see Note Setup time, RESET high before after clock cycles Delay time, CLKIN high (see Note Delay time, CLKIN high high (see Note Disable time, high (high impedance) Disable time, high (high impedance) Delay time, high control signals high Delay time, high high Delay time, high IACK high Disable time, RESET asynchronous reset signals disabled (high impedance) 'C31-40 'LC31-40 'C31-50 UNIT
tc(CI) This parameter production tested. NOTE Figure Figure typical temperature dependence.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
RESET timing (continued)
CLKIN RESET (see Notes Clock Cycles (see Note (see Note Control Signals (see Note SMJ320C31 (see Note IACK Asynchronous Reset Signals (see Note
NOTES: Asynchronous reset signals include CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, TCLK0/1. RESET asynchronous input asserted point during clock cycle. specified timings met, exact sequence shown occurs; otherwise, additional delay clock cycle possible. microprocessor mode, reset vector fetched twice, with seven software wait states each time. microcomputer mode, reset vector fetched twice, with software wait states. Control signals include STRB. outputs placed high-impedance state during reset provided with resistive pullup, nominally 18-22 undesirable spurious writes caused when these outputs low.
Figure Timing RESET
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
interrupt response timing following table defines timing parameters signals.
timing INT3-INT0 response (see Figure
tsu(INT-H1L) tw(INT) Setup time, INT3-INT0 before 'C31-40 'LC31-40 'C31-50 UNIT
Pulse duration, interrupt ensure only interrupt tc(H) This parameter production tested.
interrupt (INT) pins asynchronous inputs that asserted time during clock cycle. SMJ320C3x interrupts level-sensitive, edge-sensitive. Interrupts detected falling edge Therefore, interrupts must held falling edge proper detection. respond detected interrupts instruction-fetch boundaries only. processor recognize only interrupt given input, interrupt pulse must held
minimum falling edge more than falling edges
SMJ320C3x accept interrupt from same source every clock cycles. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle possible.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
timing parameters INT3-INT0 response (continued)
Reset Interrupt Vector Read Fetch First Instruction Service Routine
INT3 INT0 INT3 INT0 Flag
ADDR Vector Address Data First Instruction Address
Figure Timing INT3-INT0 Response
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
interrupt-acknowledge timing IACK output goes active first half-cycle rising) decode phase IACK instruction goes inactive first half-cycle rising) read phase IACK instruction.
timing IACK (see Note Figure
td(H1H-IACKL) td(H1H-IACKH) Delay time, high IACK Delay time, high IACK high 'C31-40 'LC31-40 'C31-50 UNIT
NOTE IACK goes active first half-cycle rising) decode phase IACK instruction goes inactive first half-cycle rising) read phase IACK instruction. Because pipeline conflicts, IACK remains cycle even decode phase IACK instruction extended.
Fetch IACK Instruction
Decode IACK Instruction
IACK Data Read
IACK
ADDR
Data
Figure Timing IACK
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
serial-port timing SMJ320C31-40 SMJ320LC31-40 (see Figure Figure
td(H1H-SCK) tc(SCK) (SCK) tw(SCK) (SCK) tr(SCK) tf(SCK) td(C d(C-DX) tsu(DR-CLKRL) CLKRL) th(CLKRL h(CLKRL-DR) td(C FSX) d(C-FSX) tsu(FSR-CLKRL) (FSR CLKRL) th(SCKL h(SCKL-FS) tsu(FSX-C) (FSX td(CH DX)V d(CH-DX)V td(FSX-DX)V td(CH-DXZ) Delay time, high internal CLKX/R Cycle time CLKX/R time, Pulse duration CLKX/R high/low duration, Rise time, CLKX/R Fall time, CLKX/R Delay time, CLKX valid time Setup time before CLKR time, Hold time from CLKR time, Delay time CLKX internal high/low time, Setup time before CLKR time, Hold time, FSX/R input from CLKX/R time Setup time external before CLKX time, Delay time, CLKX first bit, precedes CLKX high CLKX CLKX CLKR CLKR CLKR CLKR CLKX CLKX CLKR CLKR CLKX/R CLKX/R CLKX CLKX CLKX CLKX -[tc(H)-8]* [tc(H)-21]* [tc(SCK)/2]-10* tc(SCK)/2* CLKX/R CLKX/R CLKX/R CLKX/R tc(H)x2.6 tc(H)x2 tc(H)+10 [tc(SCK)/2]-5 'C31-40 'LC31-40 tc(H)x232 [tc(SCK)/2]+5 UNIT
Delay time, first bit, CLKX precedes Delay time, CLKX high high impedance following last data
This parameter production tested.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
serial-port timing SMJ320C31-50 (see Figure Figure
td(H1H-SCK) tc(SCK) (SCK) tw(SCK) (SCK) tr(SCK) tf(SCK) td(C d(C-DX) tsu(DR-CLKRL) CLKRL) th(CLKRL h(CLKRL-DR) td(C FSX) d(C-FSX) tsu(FSR-CLKRL) (FSR CLKRL) th(SCKL h(SCKL-FS) tsu(FSX-C) (FSX td(CH DX)V d(CH-DX)V td(FSX-DX)V td(CH-DXZ) Delay time, high internal CLKX/R Cycle time CLKX/R time, Pulse duration CLKX/R high/low duration, Rise time, CLKX/R Fall time, CLKX/R Delay time, CLKX valid time Setup time before CLKR time, Hold time from CLKR time, Delay time CLKX internal high/low time, Setup time before CLKR time, Hold time FSX/R input from CLKX/R time, Setup time external before CLKX time, Delay time, CLKX first bit, precedes CLKX high CLKX CLKX CLKR CLKR CLKR CLKR CLKX CLKX CLKR CLKR CLKX/R CLKX/R CLKX CLKX CLKX CLKX [tc(H) [tc(H) 21]* [tc(SCK)/2] tc(SCK)/2* CLKX/R CLKX/R CLKX/R CLKX/R tc(H)x2.6 tc(H)x2 tc(H)+10 [tc(SCK)/2]-5 'C31-50 tc(H)x232 [tc(SCK)/2]+5 UNIT
Delay time, first bit, CLKX precedes Delay time, CLKX high high impedance following last data
This parameter production tested.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
data-rate timing modes Unless otherwise indicated, data-rate timings shown Figure Figure valid serial-port modes, including handshake. functional description serial-port operation, subsection 8.2.12 TMS320C3x User's Guide (literature number SPRU031).
CLKX/R FSX(INT) FSX(EXT) NOTES: Timing diagrams show operations with CLKXP CLKRP FSXP FSRP Timing diagrams depend length serial-port word, where bits, respectively.
Figure Timing Fixed Data-Rate Mode
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
data-rate timing modes (continued)
CLKX/R FSX(INT) FSX(EXT)
NOTES: Timing diagrams show operation with CLKXP CLKRP FSXP FSRP Timing diagrams depend length serial-port word, where bits, respectively. timings that specified expressly variable data-rate mode same those that specified fixed data-rate mode.
Figure Timing Variable Data-Rate Mode
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
HOLD timing HOLD asynchronous input that asserted time during clock cycle. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle possible. NOHOLD primary-bus control register overrides HOLD signal. When this set, device comes hold prevents future hold cycles. Asserting HOLD prevents processor from accessing primary bus. Program execution continues until read from write primary requested. certain circumstances, first write pending, thus allowing processor continue until second write encountered.
timing HOLD/HOLDA (see Figure
tsu(HOLD-H1L) tv(H1L-HOLDA) tw(HOLD) tw(HOLDA) td(H1L-SH)H tdis(H1L-S) ten(H1L-S) tdis(H1L-RW) ten(H1L-RW) tdis(H1L-A) ten(H1L-A) tdis(H1H-D) Setup time, HOLD before Valid time, HOLDA after Pulse duration, HOLD Pulse duration, HOLDA Delay time, STRB high HOLD Disable time, STRB high-impedance state Enable time, STRB enabled (active) Disable time, high-impedance state Enable time, enabled (active) Disable time, address high-impedance state Enable time, address enabled (valid) Disable time, high data high-impedance state 'C31-40 2tc(H) tcH-5* 'LC31-40 2tc(H) tcH-5* 'C31-50 2tc(H) UNIT
HOLD asynchronous input asserted point during clock cycle. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle possible. This parameter production tested.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
HOLD timing (continued)
HOLD HOLDA STRB Write Data
NOTE HOLDA goes response HOLD going continues remain until cycle after HOLD goes back high.
Figure Timing HOLD/HOLDA
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
general-purpose timing Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0 contents internal control registers associated with each peripheral define modes these pins.
peripheral timing
table, timing parameters peripheral general-purpose I/O, defines peripheral general-purpose timing parameters.
timing requirements peripheral general-purpose (see Note Figure
tsu(GPIO-H1L) th(H1L-GPIO) Setup time, general-purpose input before Hold time, general-purpose input after 'C31-33 'C31-40 'LC31-40 'C31-50 UNIT
td(H1H-GPIO) Delay time, general-purpose output after high NOTE Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0 modes these pins defined contents internal-control registers associated with each peripheral.
Peripheral (see Note NOTE Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0/1.
Figure Timing Peripheral General-Purpose
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
changing peripheral modes
following tables show timing parameters changing peripheral from general-purpose output general-purpose input vice versa.
timing requirements peripheral changing from general-purpose output input mode (see Note Figure
th(H1H) tsu(GPIO-H1L) Hold time, peripheral after high Setup time, peripheral before 'C31-40 'LC31-40 'C31-50 UNIT
th(H1L-GPIO) Hold time, peripheral after NOTE Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0 modes these pins defined contents internal-control registers associated with each peripheral.
Execution Store PeripheralControl Register Control Peripheral (see Note Data Output
Buffers From Output Input
Synchronizer Delay
Value Seen PeripheralControl Register
Data Sampled
Data Seen
NOTE Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0/1.
Figure Timing Change Peripheral From General-Purpose Output Input Mode
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
timing peripheral changing from general-purpose input output mode (see Note Figure
'C31-40 'LC31-40 'C31-50 UNIT
td(H1H-GPIO) Delay time, high peripheral switching from input output NOTE Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0 modes these pins defined contents internal-control registers associated with each peripheral. Execution Store PeripheralControl Register
Control Peripheral (see Note NOTE Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0/1.
Figure Timing Change Peripheral From General-Purpose Input Output Mode
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
timer timing Valid logic-level periods polarity specified contents internal control registers. following tables define timing requirements timer pin.
timing timer (see Figure Note
tsu(TCLK-H1L) th(H1L-TCLK) td(H1H-TCLK) tc(TCLK) (TCLK) tw(TCLK) (TCLK) Setup time, TCLK external before Hold time, TCLK external after Delay time, high TCLK internal valid Cycle time TCLK time, Pulse duration TCLK high/low duration, TCLK TCLK TCLK TCLK 'C31-40, 'LC31-40 'C31-50 UNIT
tc(H)+10 [tc(TCLK)/2]-15 [tc(TCLK)/2]+5 NOTE Numbers applicable synchronous input clock. Timing parameters applicable asynchronous input clock. This parameter production tested. Peripheral (see Note NOTE HOLDA goes response HOLD going continues remain until cycle after HOLD goes back high.
Figure Timing Timer
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
timing following table defines timing parameter pin.
timing parameters (see Figure
tdis(SHZ) Disable time, pins disabled (high impedance) tc(CI) This parameter production tested. 'C31 'LC31 UNIT
Pins NOTE Enabling destroys SMJ320C3x register memory contents. Assert reset SMJ320C3x restore known condition.
Figure Timing
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
part order information
DEVICE 5962-9205803MXA SMJ320C31GFAM40 SM320C31GFAM40 5962-9205803MYA SMJ320C31HFGM40 SM320C31HFGM40 5962-9205803Q9A SMJ320C31KGDM40B 5962-9205804MXA SMJ320C31GFAM50 SM320C31GFAM50 5962-9205804MYA SMJ320C31HFGM50 SM320C31HFGM50 5962-9760601NXB SMQ320LC31PQM40 5962-9760601Q9A SMJ320LC31KGDM40B TECHNOLOGY 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS 0.72-µm CMOS POWER SUPPLY OPERATING FREQUENCY PACKAGE TYPE Ceramic 141-pin staggered Ceramic 141-pin staggered Ceramic 141-pin staggered Ceramic 132-pin quad flatpack with nonconductive bar. Ceramic 132-lead quad flatpack with nonconductive Ceramic 132-lead quad flatpack with nonconductive C31-40 (known good die) C31-40 (known good die) Ceramic 141-pin staggered Ceramic 141-pin staggered Ceramic 141-pin staggered Ceramic 132-pin quad flatpack with nonconductive bar. Ceramic 132-lead quad flatpack with nonconductive Ceramic 132-lead quad flatpack with nonconductive Plastic 132-lead good flatpack Plastic 132-lead good flatpack LC31-40 (known good die) LC31-40 (known good die) PROCESSING LEVEL DSCC DSCC DSCC DSCC DSCC DSCC DSCC
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
part order information (continued)
PREFIX
MIL-PRF-38535 (QML) Standard Processing Plastic (QML)
SPEED RANGE TEMPERATURE RANGE 55°C 125°C 70°C PACKAGE TYPE 141-Pin Ceramic Staggered Grid Array Ceramic Package 132-Pin Ceramic Quad Flatpack with nonconductive 132-lead Plastic Quad Flatpack 132-lead frame with polyimide encapsulant 132-lead frame, bare-die option Known Good
DEVICE FAMILY SMJ320 Family TECHNOLOGY Voltage (3.3-V option) TECHNOLOGY CMOS DEVICE '320C31 '320LC31
Figure Device Nomenclature
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
SMJ320C31 (Rev. Inner Lead Bond Information
Designator Number (Origin) Side Number
Side Number XXXX 8051.8 (317 mils)
Side Number
Side Number 7518.4 (296 mils)
Figure Numbering Format (See Table inner lead bond (ILB) pitch leadframe same bond pitch. Table provides reference following: lead numbers. lead numbers same bond numbers. 'C31 signal identities relation numbers Signal functions that more than test location. (There bond locations, leads, test locations.) 'C31 X-,Y-coordinates, where bond serves origin, (0,0) pitch leadframe
addition, following notes significant: X-,Y-coordinate data microns. Coordinate origin (0,0) (center bond Average pitch (7.95 mils). active silicon dimensions 7889,00 7353,25 (311.00 mils 289.00 mils). size approximately 7518,40 8051,80 (317.00 mils 296.00 mils). Distance from diced silicon polyimide support ring approximately 635.00 mils).
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
Table Pad/TAB Lead Information (0,72
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY DVSS AVDD CVSS VDDL VDDL VSSL VSSL DVSS DVDD IVSS DVDD X-COORDINATE BOND (mm) Y-COORDINATE BOND (mm) 0.00 224.46 426.24 650.70 875.16 1099.62 1302.48 1504.26 1728.72 1953.18 2177.64 2402.10 2604.96 2828.34 3100.32 3262.68 3463.20 3670.38 3832.74 4011.66 4256.64 4481.10 4669.56 4950.54 5153.40 5333.58 5536.44 5739.30 5942.16 6145.02 6347.88 6522.48 6695.46 PITCH LEAD (#,# REFERENCES WHICH BONDS) (mm) 224.46 201.78 224.46 224.46 224.46 202.86 201.78 224.46 224.46 224.46 (10, 224.46 (11, 202.86 (12, 223.38 (13, 271.98 (14, 162.36 (15, 200.52 (16, 207.18 (17, 162.36 (18, 178.92 (19, 244.98 (20, 224.46 (21, 188.46 (22, 280.98 (23, 202.86 (24, 180.18 (25, 202.86 (26, 202.86 (27, 202.86 (28, 202.86 (29, 202.86 (30, 174.60 (31, 172.98 (32,
0.00
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
Table Pad/TAB Lead Information (0,72 (continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY DVSS CVSS DVDD IVSS VDDL VDDL DVSS VSSL VSSL DVDD DVDD X-COORDINATE BOND (mm) 396.72 577.44 780.30 990.36 1200.42 1410.48 1598.94 1786.32 1974.78 2162.16 2350.62 2538.00 2748.06 2958.12 3150.90 3313.26 3499.38 3709.44 3897.90 4068.00 4230.36 4416.48 4626.54 4815.00 5002.38 5212.44 5422.50 5632.56 5842.62 6052.68 6262.74 6472.80 6646.86 Y-COORDINATE BOND (mm) PITCH LEAD (#,# REFERENCES WHICH BONDS) (mm) 180.72 (34, 202.86 (35, 210.06 (36, 210.06 (37, 210.06 (38, 188.46 (39, 187.38 (40, 188.46 (41, 187.38 (42, 188.46 (43, 187.38 (44, 210.06 (45, 210.06 (46, 192.78 (47, 162.36 (48, 186.12 (49, 210.06 (50, 188.46 (51, 170.10 (52, 162.36 (53, 186.12 (54, 210.06 (55, 188.46 (56, 187.38 (57, 210.06 (58, 210.06 (59, 210.06 (60, 210.06 (61, 210.06 (62, 210.06 (63, 210.06 (64, 174.06 (65,
-7219.80
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
Table Pad/TAB Lead Information (0,72 (continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY DVSS CVSS IVSS HOLDA HOLD CVDD STRB RESET CVDD IACK INT0 DVSS VSSL INT1 VDDL VDDL INT2 INT3 CVSS FSR0 CLKR0 CLKX0 IVSS FSX0 PVDD X-COORDINATE BOND (mm) Y-COORDINATE BOND (mm) -6714.54 -6555.96 6402.42 6241.86 6072.30 5780.16 5574.60 5392.62 5116.14 4898.16 4673.70 4453.74 4235.76 4032.90 3809.52 3585.06 3365.10 3168.72 2988.54 2791.26 2590.56 2428.20 -2232.18 -2018.70 -1750.32 -1547.46 -1345.68 -1121.22 -896.76 -693.90 -492.12 -289.26 -15.48 PITCH LEAD (#,# REFERENCES WHICH BONDS) (mm) 158.58 (67, 153.54 (68, 160.56 (69, 169.56 (70, 292.14 (71, 205.56 (72, 181.98 (73, 276.48 (74, 217.98 (75, 224.46 (76, 219.96 (77, 217.98 (78, 202.86 (79, 223.38 (80, 224.46 (81, 219.96 (82, 196.38 (83, 180.18 (84, 197.28 (85, 200.70 (86, 162.36 (87, 196.02 (88, 213.48 (89, 268.38 (90, 202.86 (91, 201.78 (92, 224.46 (93, 224.46 (94, 202.86 (95, 201.78 (96, 202.86 (97, 273.78 (98,
7136.64
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
Table Pad/TAB Lead Information (0,72 (continued)
SIDE BOND LOCATIONS DIE/TAB BOND IDENTITY VSUBS DVSS TCLK0 PVDD TCLK1 EMU3 EMU0 EMU1 EMU2 MCMP CVSS VDDL VDDL VSSL DVSS AVDD AVDD CVSS X-COORDINATE BOND (mm) 6705.00 6480.90 6298.92 6125.94 5951.88 5721.30 5439.24 5248.08 5063.40 4878.72 4694.04 4526.46 4324.68 4129.02 3862.62 3700.26 3421.98 3226.50 3052.44 2901.06 2728.08 2554.02 2381.04 2185.38 1989.72 1794.06 1598.40 1316.34 1120.68 925.02 750.96 577.98 403.92 Y-COORDINATE BOND (mm) PITCH LEAD (#,# REFERENCES WHICH BONDS) (mm) 224.10 (100, 101) 181.98 (101, 102) 172.98 (102, 103) 174.06 (103, 104) 230.58 (104, 105) 282.06 (105, 106) 191.16 (106, 107) 184.68 (107, 108) 184.68 (108, 109) 184.68 (109, 110) 167.58 (110, 111) 201.78 (111, 112) 195.66 (112, 113) 266.40 (113, 114) 162.36 (114, 115) 278.28 (115, 116) 195.48 (116, 117) 174,06 (117, 118) 151.38 (118, 119) 172.98 (119, 120) 174.06 (120, 121) 172.98 (121, 122) 195.66 (122, 123) 195.66 (123, 124) 195.66 (124, 125) 195.66 (125, 126) 282.06 (126, 127) 195.66 (127, 128) 195.66 (128, 129) 174.06 (129, 130) 172.98 (130, 131) 174.06 (131, 132)
452.52
VSUBS connects metallization. this clean ground.
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
(S-CPGA-P141)
1.080 (27,43) 1.040 (26,42)
CERAMIC GRID ARRAY PACKAGE
0.900 (22,86) 0.100 (2,54) 0.050 (1,27)
0.026 (0,66) 0.006 (0,15) 0.145 (3,68) 0.105 (2,67)
0.034 (0,86) 0.022 (0,56) 0.016 (0,41) 0.048 (1,22) Places 4040133/D 04/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MO-128 Thermal Resistance Characteristics PARAMETER °C/W 39.0 0.140 (3,56) 0.120 (3,05)
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
(S-CQFP-F132) CERAMIC QUAD FLATPACK WITH TIE-BAR
0.960 (24,38) 0.945 (24,00) 0.800 (20,32) 0.225 (5,72) Width 0.175 (4,45)
1.210 (30,73) 2.015 (51,18) 1.990 (50,55)
2.025 (51,44)
0.061 (1,55) 0.059 (1,50)
0.013 (0,33) 0.006 (0,15)
Braze 0.014 (0,36) 0.002 (0,05)
0.040 (1,02) 0.030 (0,76) 0.025 (0,64) DETAIL 0.020 (0,51) DETAIL
0.010 (0,25) 0.005 (0,12)
0.116 (2,95) DETAIL 4040231-8 04/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Ceramic quad flatpack with flat leads brazed non-conductive carrier. This package hermetically sealed with metal lid. terminals will gold plated. Thermal Resistance Characteristics PARAMETER °C/W
44.3 Falls within MIL-STD-1835 CMGA7-PN CMGA19-PN JEDEC MO-067AG MO-066AG, respectively
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
(S-PQFP-G***)
LEAD SHOWN
PLASTIC QUAD FLATPACK
0.012 (0,30) 0.008 (0,20)
0.006 (0,15)
"D3"
0.025 (0,635) 0.006 (0,16) 0.150 (3,81) 0.130 (3,30) "D1" "D2" 0.020 (0,51) 0.046 (1,17) 0.036 (0,91) Seating Plane 0.180 (4,57) LEADS 0.890 (22,61) 0.870 (22,10) 0.766 (19,46) 0.734 (18,64) 0.912 (23,16) 0.888 (22,56) 0.600 (15,24) 0.004 (0,10) 0.010 (0,25) Gage Plane
1.090 (27,69) 1.070 (27,18) 0.966 (24,54) 0.934 (23,72) 1.112 (28,25) 1.088 (27,64) 0.800 (20,32) 4040045 11/95
"D1"
"D2" "D3"
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MO-069
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SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
WITH PROTECTIVE FILM) SMJ320C31 244-PIN FRAME (PG6) SOCKET, OLB/ILB 0,30-mm PITCH
0,31 9,62 0,29 9,58
Leads 0,31 9,62 0,29 9,58
Face
2,25 Places)
0,31 9,62 0,29 9,58 14,00 Places)
4081548/A 11/95
NOTES:
linear dimensions millimeters. This drawing subject change without notice. lead width 0,120 0,03 lead width 0,0832 0,015 tape width encapsulated with polyimide overcoat.
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0,31 9,62 0,29 9,58
SMJ320C31, SMJ320LC31, SMQ320LC31 DIGITAL SIGNAL PROCESSORS
MECHANICAL DATA
WITHOUT PROTECTIVE FILM) SMJ320C31 244-PIN FRAME (PG6) SOCKET, OLB/ILB 0,30-mm PITCH
0,31 9,62 0,29 9,58
Leads 0,31 9,62 0,29 9,58
Face
2,25 Places)
0,31 9,62 0,29 9,58 14,00 Places) 4081549/A 11/95
NOTES:
linear dimensions millimeters. This drawing subject change without notice. lead width 0,120 0,03 lead width 0,0832 0,015 tape width bare die.
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0,31 9,62 0,29 9,58
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated

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