CMOS Programmable Rate Generator HD-4702/883 Rate Generator provi

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CMOS Programmable Rate Generator HD-4702/883 Rate Generator provi

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HD-4702/883
CMOS Programmable Rate Generator
HD-4702/883 Rate Generator provides necessary clock signals digital data transmission systems, such UART. generates commonly used rates using on-chip crystal oscillator external input. conventional operation generating output clock pulses period, input clock frequency must 2.4576MHz (i.e., 9600 Baud since there internal prescaler). lower input frequency will result proportionally lower output frequency. HD-4702/883 provide multi-channel operation with minimum external logic having clock frequency prescaler outputs available externally. signals have duty cycle except 1800 Baud, which less than 0.39% distortion. four rate select inputs (S0-S3) select which rate output (Z). Truth Table Rate Select Inputs select code output rate. select codes HD-4702/883 select internally generated frequency, select input into which user feed either different frequency, static level (High Low) generate "ZERO BAUD". rates most commonly used modern data terminals (110,150, 300,1200, 2400 Baud) require that more than input grounded HD-4702/883, which easily achieved with single 5-position switch. HD-4702/883 initialization circuit which generates master reset scan counter. This signal derived from digital differentiator that senses first high level input after input goes low. When high, selecting crystal input, must low. high level would apply continuous reset. Clock Modes Initialization below.
Features
This Circuit Processed Accordance MIL-STD-883 Fully Conformant Under Provisions Paragraph HD-4702/883 Provides Commonly Used Rates Uses 2.4576MHz Crystal/Input Standard Frequency Output Times Rate) Power Dissipation Conforms RS-404 HD-4702/883 Controls Eight Transmission Channels Initialization Circuit Facilitates Diagnostic Fault Isolation On-Chip Input Pull-Up Circuit
Ordering Information
PART NUMBER HD1-4702/883 TEMPERATURE RANGE (oC) PACKAGE CERDIP PKG. F16.3
Pinout
HD-4702/883 (CERDIP) VIEW
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
File Number
2955.2
HD-4702/883 Truth Table
TRUTH TABLE RATE SELECT INPUTS (Using 2.4576MHz Crystal) NOTE: 19200 Baud connecting OUTPUT RATE Input (lM) Input (lM) Baud Baud 134.5 Baud Baud Baud 2400 Baud 9600 Baud 4800 Baud 1800 Baud 1200 Baud 2400 Baud Baud Baud Baud NOTE: Actual output frequency times indicated output rate, assuming clock frequency 2.4576MHz. HIGH Level Level Don't Care Clock Pulse First HIGH Level Clock Pulse after goes Clocked from Continuous Reset Reset During First High Time Clocked from CLOCK MODES INITIALIZATION OPERATION
HD-4702/883
Absolute Maximum Ratings
Supply Voltage +8.0V Input, Output Voltage -0.5V +0.5V Classification Class Typical Derating Factor 1mA/MHz Increase ICCOP
Thermal Information
Thermal Resistance, (Typical, Note (oC/W) (oC/W) CERDIP Package Maximum Storage Temperature Range .-65oC 150oC Maximum Junction Temperature 175oC Maximum Lead Temperature (Soldering, 10s) 300oC
Operating Conditions
Operating Voltage Range +4.5V +5.5V Operating Temperature Range -55oC 125oC
Characteristics
Gate Count Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air. TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed 100% Tested GROUP SUBGROUPS
PARAMETER Input High Voltage Input Voltage Output High Voltage
SYMBOL VOH1 VOL1 IILX IOHX
CONDITIONS 4.5V 4.5V -1µA, 4.5V, (Note +1µA, (Note VCC. Other Pins 5.5V Other Pins VCC, 5.5V Other Pins VCC, 5.5V (Note VOUT -0.5, 4.5V Input Logic Function Truth Table VOUT 2.5V, 4.5V Input Logic Function Truth Table VOUT -0.5, 4.5V Input Logic Function Truth Table VOUT 0.4V, 4.5V Input Logic Function Truth Table VOUT 0.4V, 4.5V Input Logic Function Truth Table
TEMPERATURE (oC)
-0.1
UNITS
Output Voltage
Input High Current
Input Current Input) Input Current (All Other Inputs) Output High Current (OX)
-100
-0.1
Output High Current (All Other Outputs)
IOH1
-1.0
Output High Current (All Other Outputs)
IOH2
-0.3
Output Current (OX)
IOLX
Output Current (All Other Outputs)
HD-4702/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed 100% Tested GROUP SUBGROUPS
PARAMETER Supply Current (Static)
SYMBOL
CONDITIONS 5.5V Other Inputs GND, (Note 5.5V Other Inputs (Note
TEMPERATURE (oC)
1500
UNITS
1000
NOTES: Interchanging force sense conditions permitted. Input Current Quiescent Power Supply Current relatively higher this device because active pull-up circuits inputs except TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed 100% Tested. PARAMETER Propagation Delay, Propagation Delay, Propagation Delay, Propagation Delay, Propagation Delay, Propagation Delay, Propagation Delay, Propagation Delay, Output Transition Time (Except Output Transition Time (Except Set-UpTime Select Hold Time, Select Set-UpTime, Hold Time, Minimum Clock Pulse Width, (Notes Minimum Clock Pulse Width, High (Notes Minimum Pulse Width, (Note Minimum Pulse Width, High (Note NOTES: Propagation Delays (tPLH tPHL) Output Transition Times (tTLH tTHL) will change with Output Load Capacitance (CL). Set-Up Times (tS), Hold Times (tH), Minimum Pulse Widths (tW) vary with load capacitance. multichannel operation, Propagation Delay Qn), plus Set-Up Time, Select guaranteed 367ns. first High Level Clock Pulse alter goes must least 350ns long guarantee reset Counters. recommended that input rise fall times clock inputs less than 15ns. SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tWCP(L) tWCP(H) tWCP(L) tWCP(H) 4.5V 50pF (Note CONDITIONS GROUP SUBGROUPS TEMPERATURE (oC) (Note (Note UNITS
HD-4702/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER Input Capacitance Output Capacitance SYMBOL CONDITIONS Measurements referenced device ground, 1MHz. NOTES TEMPERATURE (oC) 15.0 UNITS
Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Output Transition Time (Except Output Transition Time (Except NOTES:
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL 4.5V 15pF
(Note (Note
parameters listed Table controlled design process parameters directly tested. These parameters characterized upon initial design after major process and/or design changes. multichannel operation, Propagation Delay plus Set-Up Time, Select guaranteed 367ns. Propagation Delays (tPLH tPHL) Output Transition Times (tTLH tTHL) will change with Output Load Capacitance (CL). Set-Up Times (tS), Hold Times (tH), Minimum Pulse Widths (tW) vary with load capacitance.
TABLE APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test Final Test Group Groups METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS
HD-4702/883 Burn-In Circuit
HD-4702/883 CERDIP
VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
NOTES: 100kHz ±10%, F0/2, F1/2., 10k, 1/4W, ±10%. 5.5V ±0.5V, 0.01µF Min.
HD-4702/883 Characteristics
DIMENSIONS: mils mils mils METALLIZATION: Type: Thickness: GLASSIVATION: Type: SiO2 Thickness: WORST CASE CURRENT DENSITY: 104A/cm2
Metallization Mask Layout
HD-4702/883
HD-4702/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
-A-DBASE METAL -Bbbb BASE PLANE SEATING PLANE SECTION LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION
LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL 0.014 0.014 0.045 0.023 0.008 0.008 0.220 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS 0.36 0.36 1.14 0.58 0.20 0.20 5.59 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES Rev. 4/94
eA/2
eA/2
0.100 0.300 0.150 0.125 0.015 0.005 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 7.62 3.81 3.18 0.38 0.13 5.08 1.52 105o 0.38 0.76 0.25 0.038
NOTES: Index area: notch identification mark shall located adjacent shall located within shaded area shown. manufacturer's identification shall used identification mark. maximum limits lead dimensions shall measured centroid finished lead surfaces, when solder plate lead finish applied. Dimensions apply lead base metal only. Dimension applies lead plating finish thickness. Corner leads N/2, N/2+1) configured with partial lead paddle. this configuration dimension replaces dimension This dimension allows off-center lid, meniscus, glass overrun. Dimension shall measured from seating plane base plane. Measure dimension four corners. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH.
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation 883, Mail Stop 53-204 Melbourne, 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil Mercure Center 100, Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, Hsing North Road Taipei, Taiwan Republic China TEL: (886) 2716 9310 FAX: (886) 2715 3029

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