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SAN3010 APPLICATION NOTE
SINGLE CHIP TELEPHONE INTERFACE KEYBOARD ENTRY
Scope
This application note describes simple interface keyboard entry SA253x family Microcontroller. also includes hardware description flowchart software example based 80Cxx family Microcontrollers.
Features
only outputs input required from handshake access keys SA253x keyboard matrix universal interface, restricted specific Microcontrollers supports both same hardware single chip telephones SA2531/2 same software single chip telephones, only labels must replaced
Table Contents
SCOPE.1 FEATURES OTHER APPLICABLE DOCUMENTS PAPERS REVISION STATUS GENERAL DESCRIPTION HARDWARE CONFIGURATION APPLICATION SCHEMATIC:.2 SCANNING TABLE/FLOWCHART.3 SAMPLE SOFTWARE.3 ENTRY SIGNAL TABLE: APPENDIX APPLICATION SCHEMATIC APPENDIX FLOWCHART: APPENDIX SAMPLE SOFTWARE LISTING LIABILITY COPYRIGHT STATEMENT
Other applicable documents papers
Data Sheet SA2531, SA2532 Pin-out Comparison SA2531/2 Product Presentation Single Chip Telephone Evolution (Apr. 1996)
SAN3010
PDS038-SA2531/2-003
Rev.
21-03-00
SAN3010
Revision status
SAN3010 Application Note (this document): AN3010 Schematic: AN3010 Sample Software Rev.: Rev.:
General Description
interface must capable forcing keyboard rows (hereafter indicated R1.R4) both (Vss) high (VDD) forcing keyboard columns (hereafter indicated C1.C4) high (VDD). Only column forced same time while remaining rows/columns must high ohmic (hereafter indicated Since only row/column must driven same time, decoder (IC5 74138) implemented save count output ports were used row/column selection, output port disable rows/columns output port 3-state buffer inputs select forcing high must configured input handshake. output input pins available from row/column selectors, force hi/lo selector handshake input) 74138 omitted. (=74HC125) separately addressable 3-state buffers. simple discrete gate (Q1,D2,D3,R9.11) used synchronization.
Hardware configuration
SA253x Single Chip Telephone connected entry when following conditions met: Supply voltage: SA253x works VDD, high/low input levels 30/70% VDD. supplied with current limiter (serial resistor) must added row/column pins SA253x. supply must provide adequate high level 70%VDD SA253x >2.8V) driver Tristate output pins, each separately adjustable either output (Hi/Lo) tristate Only driven same time, other rows/columns high ohmic. Column driver: Tristate output pins, each separately adjustable either output (Hi) tristate. Only column driven same time, other rows/columns high ohmic. Synchronization: SA253x intentionally designed standby power, oscillator running long pressed. external row/column driving done asynchronously. scanning sequence synchronized triggering rising edge specific columns (see table Therefore 1-bit input must provided synchronization.
Application schematic:
also: Appendix solution which only requires output pins input shown attached schematic. common (80C51-family) used. This controller widely known, both hardware software description this application note should easily understood which simplifies adaption other controller. rows/columns driven separately selectable tristate buffers (e.g. 74HC125). Power supply therefore resistors R2.R8 necessary provide adaption 4V-logic SA253x. always connected 5kOhms resistor prevent collision outputs when initiates entry unsynchronous state.
2/13
SAN3010 Since only row/column forced high same time number output port pins limited using 1-of-8 decoder (74HC138). bits (A,B,C, respectively Port1 pins 0.2) select appropriate row/column, Port disables outputs. selected row/column forced high depending state Port1.5 Port used input detect acknowledge SA253x during scanning phase. Acknowledge done rising edge either C1,C2,C3 detection logic simplified just monitoring because both always used detection (see table ColY). Diode necessary prevent collision outputs when Port1 output mode. Since Port1 80C31 open-drain output diode used. other controllers, using standard I/O, resistor must used place diode.
Scanning table/flowchart
also: Appendix interfacing procedure shown attached flowchart, additional information given below: entry only occur, when SA253x been off-hook >20ms. Internal scanning SA253x started when case: been forced low, then acknowledge SA253x done moving specific col-pins high. When this Lo/Hi transition detected asynchronous timing must started. SCAN1 SCAN time slots which certain must forced high (SCAN1) forced (SCAN time slot SCAN3 certain column must forced high. entry corresponding Column shown table Between SCAN1.3 time slots rows columns must high ohmic (see flowchart). valid entry accepted, when SCAN1.3 procedure been repeated times. certain constant delay must added between entries. only exception when memory keys cascaded. this special case, entering subsequent memory only accepted, when previous memory been fully dialed out.
Sample software
also: Appendix Attached sample software program, written 8051 Assembler language which incorporates necessary timing correct row/column selection. only entry load accumulator with code then make subroutine call. Table appropriate codes when using either SA2531-2 assembler command lines well described, should easily understood. Again, adaption other controllers based upon this software should problem. Care must taken when using different system clock speed. this case delay blocks must recalculated based number machine cycles used.
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SAN3010
entry signal table:
Keycode example
SA2531 Mute Pause Enter
SA2532 Mute Pause
SCAN SCAN force force
SCAN force
Synchronization
none none none none none none none none none none none none none none none none
C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3 C2,3,4 C1,3,4 C1,2,4 C1,2,3
Table entry lookup table
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SAN3010
Appendix Application Schematic
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SAN3010
Appendix Flowchart:
Flowchart Microcontroller interface AS253x single-chip-telephone Notes: RowX,ColX,ColY: table1 tclk= 256/3.58MHz 71.5µs timings: Tol.:+-30µs
Start
delay5
wait >20ms after AS253x off-hook ensure correct start-up wait tclk= 321µs force ColX high other rows/cols= =SCAN3
Key_in delay6
Loop=0 wait tclk=107.25µs disable rows/cols=
Row1 force other rows/cols=Hi
sync
Loop= Loop+1
Y=high
Loop
delay1
wait tclk=71.5µs force RowX high other rows/cols= =SCAN1
delay7
wait 24*9 tclk=15.5ms
delay2
wait tclk=107.25µs disable rows/cols= another entry?
delay3
wait tclk=321µs force RowY other rows/cols= =SCAN2
delay4
wait tclk=321µs disable rows/cols=
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SAN3010
Appendix Sample Software listing
MCS-51 MACRO ASSEMBLER 09/09/96 PAGE LINE 0000 0001 0002 0003 0004 0005 0006 0007 0090 0080 SOURCE Austria Mikro Systeme International J.Janisch telecom applications Program name: KEY.ASM Version: Date: 1996-09-09 Author: J.Janisch Telecom Applications User program 8051 interface SA253x entry microcontroller Application Note AN3010 Program code Address 4000 Reference calculations: Clock Frequency Microcontroller (80C31) 11.0592 machine cycle clock cycles 1.085 Decoder Logic: Port1: P1.7 active input; detects rising edge should high output command port P1.6 used P1.5 used P1.4 forces selected row/column high P1.3 when high, disables rows/columns (high P1.2 column selector P1.1 column selector P1.0 column selector P1.2 P1.1 P1.0 select: column column column column
Row1 Row2 Row3 Row4 Col1 Col2 Col3 Col4 ForceHi ForceLo
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SAN3010
PAGE 0088
4000 4000 758160 4003
4004 740A 4006 12400B 4009 80FE
400B 12405C
400E 4010 4012 4014 4017
7B00 7480 F590 3097FD 2097FD
401A 791F 401C D9FE 401E 7490 4020 4021 F590
4023 7930 4025 D9FE 4027 7488
LINE
SOURCE Disable
Main program: load Accumulator with code (see below) call subroutine "Key_In" start address program stack pointer HS_OK: make sure that this point SA253x been off-hook >20ms Ld_Key: a,#10 load keycode, here Call Key_in execute keystroke main program, exit this point continue with next entry rem.: additional delay when cascading memories Delay7:) Subroutine Key_in this subroutine executes entry SA253x corresponding code(0.31) must loaded accu table label:"scantbl" codes affected Registers: A,B,R1,R2,R3,R5,R6,R7,DPTR 04000H SP,#060H
Key_in: call
getScTb
preload Reg5.7 with variable variable variable clear loop counter force
scan table Reg5 Reg6 Reg7
Exe_Key:mov sync:
R3,#0 a,#ForceLO P1,A P1.7, P1.7,
make sure, wait rising edge trigger asynch. timing
Delay 1:wait 71.5 machine cycles force RowX high delay1: R1,#31 cycle djnz R1,$ cycles; #Loops=(66-4)/2 SCAN1: A,#ForceHi A,R5 P1,A cycle cycle cycle
;-;Delay2:wait 107.25us= machine cycles +disable rows/cols delay2: R1,#48 cycle djnz R1,$ cycles; #Loops =(99-3)/2 A,#Disable cycle
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SAN3010
PAGE 4029 F590
402B 7991 402D D9FE 402F 4030 4032 4033 7480 F590
4035 4037 4039 403B
7992 D9FE 7488 F590
403D 7991 403F D9FE 4041 4042 4044 4045 7490 F590
4047 4049 404B 404D
7930 D9FE 7488 F590
404F 4050 BB09C1
4053 7900 4055 7A1C
LINE
SOURCE P1,A cycle
;-;- Delay 3:wait machine cycles force RowY delay3: R1,#145 cycle djnz R1,$ cycles;#Loops=(295-5)/2=145 SCAN2: cycle cycle cycle cycle
A,#ForceLO A,R6 P1,A
;-;Delay wait 321us= machine cycles +disable rows/cols delay4: R1,#146 cycle djnz R1,$ cycles;#Loops=(295-3)/2=146 A,#Disable cycle P1,A cycle ;-;- Delay 5:wait machine cycles force ColX high delay5: R1,#145 cycle djnz R1,$ cycles;#Loops=(295-5)/2=145 SCAN3: cycle A,#ForceHi cycle A,R7 cycle P1,A cycle ;-;Delay 6:wait 107.25us=99 machine cycles +disable rows/cols delay6: R1,#48 cycle djnz R1,$ cycles;#Loops=(99-3)/2 A,#Disable cycle P1,A cycle ;-inc increment loop counter cjne R3,#9,Sync repeat loop times
Delay wait >15444 14233 machine cycles before ;-next entry Remark: when cascading memory keys (M1.M10, Mem) dialling subsequent stored number only accepted when previous number been fully dialled out. Example1: entry "M1","M2" ;-M2 only detected when completed dialing ;-its stored number, delay added between ;-key entries Example2: entry "M1","0" ;-numbers stored FIFO they entered ;-immediately after Memory entry, additional ;-delay necessary delay7: R1,#0 R2,#28
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SAN3010
PAGE 4057 D9FE 4059 DAFC
405B
405C 405F 4062 4063
904074 75F003 F5F0
4065 4066 4067 4069 406A 406C 406D 406E 4070 4071 4072 E5F0 F5F0 E5F0
4073
4074 4075 4076 4077 4078 4079 407A 407B 407C 407D 407E 407F 4080 4081 4082 4083
LINE
SOURCE Del7a:
djnz djnz
R1,$ R2,Del7a
=256*2 machine cycles machine cycles 28*(256*2+2)=14392mc's=15.6ms return from subroutine
Subroutine GetScTb this subroutine loads Reg5.Reg7 registers according keycode passed accumulator contents. valid keycodes 0.31 (dec) 0.1F (Hex)
GetScTb:mov movc movc movc
dptr,#Scantbl B,#3 A,@A+DPTR R5,A A,@A+DPTR R6,A A,@A+DPTR R7,A
calculate offset Address: scantable startaddress (keycode save offset address scan table: RowX
next code save scan table: RowY
next code scan table: ColX
Scan table: three constants indicate rows/columns driven SCAN1.SCAN3 phase Scantbl:db Row1,Row1,Col1 "Pgm/Mt, keycode=
Row1,Row1,Col2
keycode=
Row1,Row1,Col3
keycode=
Row1,Row1,Col4
keycode=
Row2,Row2,Col1
keycode=
Row2,Row2,Col2
keycode=
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SAN3010
PAGE 4084 4085 4086 4087 4088 4089 408A 408B 408C 408D 408E 408F 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 409A 409B 409C 409D 409E 409F 40A0 40A1 40A2 40A3 40A4 40A5 40A6 40A7 40A8 40A9 40AA 40AB 40AC 40AD 40AE 40AF 40B0 40B1 40B2 40B3 40B4 40B5 40B6 40B7 40B8 40B9 40BA
LINE
SOURCE
Row2,Row2,Col3
keycode=
Row2,Row2,Col4
keycode=
Row3,Row3,Col1
keycode=
Row3,Row3,Col2
keycode=
Row3,Row3,Col3
keycode=
Row3,Row3,Col4
keycode=
Row4,Row4,Col1
keycode=
Row4,Row4,Col2
"PS,R1", keycode=
Row4,Row4,Col3
"R,R2" keycode=
Row4,Row4,Col4
"R2,R3 keycode=
disable,Row1,Col1
"LNR"
keycode=
disable,Row1,Col2
"Vol"
keycode=
disable,Row1,Col3
"Vol+" keycode=
disable,Row1,Col4
"Vol-" keycode=
disable,Row2,Col1
keycode=
disable,Row2,Col2
keycode=
disable,Row2,Col3
keycode=
disable,Row2,Col4
keycode=
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SAN3010
PAGE 40BB 40BC 40BD 40BE 40BF 40C0 40C1 40C2 40C3 40C4 40C5 40C6 40C7 40C8 40C9 40CA 40CB 40CC 40CD 40CE 40CF 40D0 40D1 40D2 40D3
LINE
SOURCE disable,Row3,Col1 keycode=
disable,Row3,Col2
keycode=
disable,Row3,Col3
keycode=
disable,Row3,Col4
keycode=
disable,Row4,Col1
keycode=
disable,Row4,Col2
keycode=
disable,Row4,Col3
keycode=
disable,Row4,Col4
keycode=
REGISTER BANK(S) USED:
ASSEMBLY COMPLETE, ERRORS FOUND
12/13
SAN3010
Liability Copyright Statement
Disclaimer: information contained this document confidential proprietary South African Micro-Electronic Systems (Pty) ("SAMES") copied disclosed third party, whole part, without express written consent SAMES. information contained herein current date publication; however, delivery this document shall under circumstances create implication that information contained herein correct time subsequent such date. SAMES does undertake inform recipient this document changes information contained herein, SAMES expressly reserves right make changes such information, without notification,even such changes would render information contained herein inaccurate incomplete. SAMES makes representation warranty that circuit designed reference information contained herein, will function without errors intended designer.
South African Micro-Electronic Systems (Pty)
15888, Lynn East, 0039 Republic South Africa, Eland Street, Koedoespoort Industrial Area, Pretoria, Republic South Africa
Tel: Fax:
333-6021 333-3158
Tel: Fax:
333-6021 333-3158
Site http://www.sames.co.za
13/13
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