SAA7348GP Compact Disc Engine (ACE) Preliminary specification Fil

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SAA7348GP Compact Disc Engine (ACE)
Preliminary specification File under Integrated Circuits, IC22 1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
CONTENTS 7.1.1 7.1.2 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.5.1 7.7.1 7.8.1 7.10 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog front-end Decoder front-end Servo front Decoder functions Servo functions Signal conditioning Focus control Radial control Off-track counting Off-track detection Shock detection Defect detection Driver interface Laser interface Subcode interface Digital output Format interface Audio support Serial audio data interface CD-ROM support Serial CD-ROM data interface Reset External support MICROCONTROLLER INTERFACE Microcontroller applications registers generate register (CLKgen) Port Servo Register (PSR) Servo Control Register (SCR) Servo Status Register (STR) Motor Output QCLV Register (MOQ; address 0XF2H 0XF3H) Register Decoder Status Register (DSR) Motor Setpoint Register (MSR; address 0XF9H) Motor Gain QCLV Register (address 0XFAH) Data Direction Registers (DDR0, DDR2 DDR3) Configuration Control Register (CCR) second serial interface 8.1.13 8.1.14 8.1.15 8.4.1 10.1 10.2 10.3 12.1 12.2 12.3 12.4
SAA7348GP
Memory access servo Registers DIV17 Register (address 0X9FH) Memory Summary functions controlled decoder registers Summary servo commands Summary servo command parameters LIMITING VALUES CHARACTERISTICS General characteristics Subcode interface timing characteristics timing characteristics PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
FEATURES
SAA7348GP
Improved playability ABEX TCD-721R, TCD-725 TCD-714 discs Automatic closed loop gain control available focus radial loops chip clock multiplier allows 8.4672 crystal serial interface with host controller Double speed servo Integrated engine controller (high speed embedded 80C51) External program support. GENERAL DESCRIPTION
Focus servo loop Radial servo loop Built-in access procedure with fast track count possibilities Sledge motor servo loop with pulsed sledge support High speed error correction, sixteen times over-speed Supports three different over-speed ranges with only external crystal Lock-to-disc mode Full turntable motor control Full error correction strategy, standard decoder functions implemented digitally Adaptive digital equalizer FIFO overflow concealment rotational shock resistance Digital audio interface (EBU), audio data times oversampling integrated digital filter, including mode Audio data peak level detection Kill interface deactivation during digital silence TDA1301 (DSIC2) digital servo functions focus noise ORDERING INFORMATION
SAA7348 Compact Disc Engine (ACE) combines functionality decoder (LO9585), digital servo (OQ8868) microcontroller core (80C51 based) single chip. developed high speed CD-ROM applications but, large scale integration, also used other applications. internal microcontroller makes possible develop other applications quickly. microcontroller operate with internal external ROM. Additional features include: High level integration Improved communication speed.
PACKAG0E TYPE NUMBER NAME SAA7348GP DESCRIPTION VERSION SOT407-1 LQFP100 plastic profile quad flat package; leads; body
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
QUICK REFERENCE DATA SYMBOL VDDD(pads) VDDD(core) VDDA fxtal Tamb Tstg Note PARAMETER digital supply voltage cells digital supply voltage core analog supply voltage supply current crystal frequency operating ambient temperature storage temperature note note mode CONDITIONS MIN.
SAA7348GP
TYP. 8.4672
MAX. +125
UNIT
analog digital core supply pins (VDDA VDDD(core)) must connected same external supply. core pads operate different voltages should never connected together directly.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
BLOCK DIAGRAM
VSSA VDDA
SAA7348GP
handbook, full pagewidth
VSSD
SBSY
VALID
DATA
SCLK
KILL DEEM DOBM SUBQW MOTOV MOTOS C2FAIL CFLG
VDDD(core) VDDD(pads)
SFSY
WCLK
DACCLK
MIDLAD REFLCA HFIN REFHCA Iref
FRONT-END DECODER
SAA7348GP
IrefT FTCH FTCL FRONT-END DIGITAL SERVO DSDEN DEFI DEFO LDON
XTALI XTALO SELPLL
CLOCK 80C51
TPWM
TEST
Pins Pins Pins Pins Pins
RXD0
INT0 INT1
RXD1 TXD1
TXD0
PSEN
MGK498
Fig.1 Block diagram.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
PINNING SYMBOL TPWM MIDLAD REFLCA HFIN REFHCA Iref VSSA1 VDDA1 VSSA2 VDDA2 IrefT FTCH FTCL SELPLL XTALO XTALI VSSD1 RXD0 TXD0 INT0 INT1 RXD1 TXD1 VSSD2 VDDD1(core) 1997 TYPE(1) DESCRIPTION test control input; this should tied test control input; this should tied test control input; this should tied power-on reset input tray output tray enable output ladder middle decoupling High Frequency (HF) ladder decoupling input ladder high decoupling reference current input analog ground front-end analog supply voltage front-end (3.3 calibrated reference voltage output from unipolar current input (central diode signal input) unipolar current input (central diode signal input) unipolar current input (central diode signal input) analog ground front-end analog supply voltage front-end (3.3 unipolar current input (central diode signal input) unipolar current input (satellite diode signal input) unipolar current input (satellite diode signal input) current reference, input range front-end ADCs fast track counter comparator input fast track counter comparator input enables internal clock multiplier crystal output crystal input digital ground P3.0 P3.1 P3.2 (interrupt P3.3 (interrupt P3.4 P3.5 P3.6; active P3.7; active digital ground digital supply voltage core (3.3 P2.0 (address I/O)
SAA7348GP
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
SYMBOL PSEN VSSD3 VDDD1(pads) VSSD4 DACCLK VSSD5 VDDD2(pads) VALID DATA WCLK SCLK VSSD6 SUBQW MOTOS MOTOV DSDEN VSSD7 VDDD3(pads) VSSD8 1997
TYPE(1) P2.1 (address I/O) P2.2 (address I/O) P2.3 (address I/O) P2.4 (address I/O) P2.5 (address I/O) P2.6 (address I/O) P2.7 (address I/O)
DESCRIPTION
program store enable (pull-up; active LOW) address latch enable (pull-up) external select (active LOW); enhanced hooks digital ground digital supply voltage pads pins P0.0 (data, address I/O) P0.1 (data, address I/O) P0.2 (data, address I/O) P0.3 (data, address I/O) P0.4 (data, address I/O) P0.5 (data, address I/O) P0.6 (data, address I/O) P0.7 (data, address I/O) digital ground BCC-DAC clock output digital ground digital supply voltage (level shifter) pads data validity flag; error flag; (3-state) serial audio data output (3-state) serial data output block decoder (3-state) word clock output (3-state) serial clock output (3-state) digital ground subcode output; subcode bits motor output, sign motor output, value enable output (active LOW) clock output digital ground digital supply voltage pads pins radial actuator output focus actuator output sledge control output digital ground
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
SYMBOL CFLG C2FAIL VSSD9 VDDD2(core) DOBM SBSY SFSY DEEM KILL DEFI DEFO LDON Note
TYPE(1) track loss signal (open drain)
DESCRIPTION radial polarity signal (open drain) focus signal decoder measurement signal (open drain) correction flag output (open drain) indication correction failure (open drain) digital ground digital supply voltage core (3.3 bi-phase mark output (externally buffered) (3-state) off-track detect FIFO boundary, motor overflow (open drain) subcode block sync (3-state) subcode frame sync (3-state) subcode clock input subcode bits (3-state) deemphasis active output kill output (open drain) defect detector input defect detector output laser drive output (open drain)
type abbreviations: Output, Input, power Supply, Analog function, Open Drain, Bidirectional, 3-state output. supply pins must connected directly their respective external power supply voltages.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
VDDD3(pads)
VDDD2(core) VSSD9
LDON
TPWM MIDLAD REFLCA HFIN
VSSD7 DSDEN MOTOV MOTOS SUBQW VSSD6 SCLK WCLK DATA VALID VDDD2(pads) VSSD5 DACCLK VSSD4 VDDD1(pads) VSSD3
C2FAIL
VSSD8
DOBM
DEEM
DEFO
SBSY
CFLG
SFSY
DEFI
KILL
REFHCA Iref VSSA1 VDDA1 VSSA2 VDDA2 IrefT FTCH FTCL SELPLL XTALO XTALI VSSD1 RXD0 TXD0 INT0 INT1 RXD1 TXD1 VSSD2 VDDD1(core) PSEN
SAA7348GP
MGK497
Fig.2 configuration.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
FUNCTIONAL DESCRIPTION
SAA7348GP
data incorrect. off-track input connected internally servo section.
combines functionality DSICS (OQ8868), CD65 (LO9585) 80C51-based microcontroller (83C654). addition, large part glue logic been integrated help minimize number external components required CD-ROM applications. Analog front-end
handbook, halfpage
+3.3
VDDA1
front-end circuit split into parts: decoder input front-end) servo input front-end). Each powered separate power supply pair.
MIDLAD VSSA1
MGK500
7.1.1
DECODER FRONT-END
signal decoder through ADC, which preceded stage. order make full digital front-end resolution, gain control amplifier should deliver constant output signal. gain range controlled steps gain variable gain amplifier controlled on-chip digital gain control block. This block allows both automatic microcontroller gain control. internal detector sensitive disturbance signal; clean (good signal-to-noise ratio) signal necessary since high frequency components disturb detector. input range front-end varies from down 0.35 p-p. lower range signal level between range, detector will signal this range translates into half range equals total offset equal LSBs, signal range would reduced this case signal less than would signal HF). ensure offset minimized when gain high, necessary connect resistor divider MIDLAD, shown Fig.3. SAA7348 contains on-chip digital equalizer data slicer. equalizer adaptive; actual equalization depends disc speed. data slicer microcontroller programmable bandwidth. fully digital internal used regenerate clock. bandwidth equalization programmed microcontroller. off-track input necessary certain applications. off-track input flag HIGH, SAA7348 will assume that servo following wrong track, will flag incoming
Fig.3 Front-end offset compensation.
7.1.2
SERVO FRONT
servo front contains current-input ADCs (four focus radial signals). ADCs require external capacitors, unlike OQ8868 (SAA7370). high performance radial access, comparator input available (Fast Track Count) signal. dynamic range input currents adjusted over range dependent value external resistor connected IrefT. maximum input current central satellite diodes, respectively, given below: i(central) IrefT satellite
IrefT
generated internally. value dependent upon spread internal capacitors value reference current generated external resistor IrefT. Typical input currents range resistance values given Table
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Table Typical input currents range values RIrefT TYPICAL CURRENT INPUT RANGE RIrefT fsys (µA) 12.000 10.909 10.000 8.889 8.000 7.273 6.667 6.154 5.581 5.106 4.706 4.286 3.871 3.529 3.200
SAA7348GP
4.2336 (µA) 6.000 5.455 5.000 4.444 4.000 3.636 3.333 3.077 2.791 2.553 2.353 2.143 1.935 1.765 1.600 1.891 1.719 1.576 1.396 1.261 1.146 1.051 0.970 0.880 0.805 0.742 0.675 0.610 0.556 0.504
fsys(1) 8.4672 (µA) 12.000 10.909 10.000 8.889 8.000 7.273 6.667 6.350 (µA) 6.000 5.455 5.000 4.444 4.000 3.636 3.333 3.175 0.946 0.860 0.788 0.698 0.631 0.573 0.526 0.500
Note
servo clock fsys always equal Table preset latch command used select this method automatic adjustment. Alternatively, dynamic range input currents made dependent reference voltage, VRH. this case, maximum input current central satellite diodes, respectively, i(central) 1.10
playback speeds selected, depending crystal frequency internal clock settings; Table following functions performed decoder block: Demodulation (includes sync protection circuit); converts 14-bit data subcode words into 8-bit symbols. Subcode data processing. Error correction; type used both symbol) symbol) frames. error corrector correct errors level errors level. error corrector also contains flag processor. Flags assigned symbols when error corrector cannot ascertain symbols definitely good. generates output flags that used output flags used interpolator conceal uncorrectable errors audio output; they also output signal (DOBM) VALID output with CD-ROM applications.
i(satellite) 0.55 where fsys 4.2336 MHz.
pre-defined levels, selectable under software control. initially using preset latch command, then incremented decremented level time repeatedly resending same commend. Decoder functions
SAA7348 multi-speed decoding device with internal phase locked loop clock multiplier. Several 1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Motor control; spindle motor controlled fully integrated digital servo. Address information from internal frame FIFO disc speed information used calculate motor control output signals. Several output modes supported: Pulse density, 2-line (true complement output), sample frequency Table Decoder playback speeds; note INTERNAL FREQUENCY (MHz) REGISTER 00XX 00XX 01XX 01XX 10XX 10XX 11XX Notes don't care. REGISTER 0XXX 1XXX 0XXX 1XXX 0XXX 1XXX 0XXX 67.7376(2) 50.8032(2) 33.8688(2)(3)
SAA7348GP
PWM-output, 2-line, 22.05 modulation frequency motor mode Brushless motor control mode. simplified illustration data flow through decoder shown Fig.4.
16.9344(4)
With 8.4672 crystal, only SELPLL (i.e. clock multiplier enabled; also Section 8.1.1). external 33.8688 crystal. external 16.9344 crystal.
1997
1997
handbook, full pagewidth
SUBQW xx0x GRAPHICS INTERFACE SUBCODE INTERFACE INTERFACE DOBM MICROCONTROLLER INTERFACE SBSY SFSY
Philips Semiconductors
xx10 xx11
SUBCODE PROCESSOR
xx0x xx1x xx10 (1fs mode)
Compact Disc Engine (ACE)
DIGITAL DEMODULATOR
FIFO
pre-emphasis detected 0xxx pre-emphasis detected 1xxx registers
FADE/MUTE/ INTERPOLATE DIGITAL FILTER PHASE COMPENSATION DE-EMPHASIS FILTER KILL KILL x000/reg 101x/reg 00xx/reg x0xx
MGK499
ERROR CORRECTOR
I2S-BUS INTERFACE DATA SCLK WCLK 101x (CD-ROM modes)
MONO FUNCTION
11xx 00xx
VALID DEEM
pre-emphasis detected 0xxx 11xx
Preliminary specification
SAA7348GP
Fig.4 SAA7348 decoder function: simplified data flow.
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
7.3.1 Servo functions SIGNAL CONDITIONING
SAA7348GP
radial tracking error signal generated satellite detector signals radial error signal formulated follows: re_gain re_offset where index indicates automatic scaling operation performed radial error signal. This scaling necessary avoid non-optimal dynamic range usage digital representation reduce radial bandwidth spread. Furthermore, radial error signal will free offset during disc start-up. four signals from central aperture detectors, together with satellite detector signals, generate track position signal (TPI), which formulated follows: sign [(D1 sum_gain] where weighting factor sum_gain generated internally SAA7348 during initialization.
digital codes retrieved from ADCs applied logic circuitry obtain various control signals. signals from central aperture diodes processed obtain normalised focus error signal: where detector set-up illustrated Fig.5 assumed. single Foucault focusing, signal conditioning switched under software control such that: error signal, FEn, further processed Proportional Integral Differential (PID) filter section. Focus (FOK) flag generated means central aperture signal adjustable reference level. This signal used provide extra protection Track-Loss (TL) generation, drop detection focus start-up procedure.
handbook, full pagewidth
SATELLITE DIODE
SATELLITE DIODE
SATELLITE DIODE
SATELLITE DIODE
SATELLITE DIODE
SATELLITE DIODE
single Foucault
astigmatic focus
double Foucault
MBG422
Fig.5 Detector arrangement.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
7.3.2 Focus control
SAA7348GP
switched off, applied only focus control, applied both focus radial controls under software control. actions circuit monitored DEFO (active HIGH). external defect detector added removing connection between DEFO DEFI (normal operation) inserting necessary circuitry. 7.3.8 DRIVER INTERFACE
SAA7348 performs following focus servo function: Focus start-up Focus position control loop Drop-out detection Focus loss detection fast restart Focus loop gain switching Focus automatic gain control loop. 7.3.3 RADIAL CONTROL
SAA7348 performs following radial servo functions: Level initialization Radial position control loop Sledge control Tracking control Access with without track loss information Radial automatic gain control loop. 7.3.4 OFF-TRACK COUNTING
control signals (pins mechanism actuators pulse density modulated. modulating frequency either servo clock servo clock MHz. analog representation output signals generated connecting first order low-pass filter outputs. During reset (i.e. held HIGH) pins high impedance. 7.3.9 LASER INTERFACE
track position signal (TPI) flag used indicate whether radial spot positioned track with margin ±0.25 track pitch. following three counting states selected: Protected state Slow counting state Fast counting state. 7.3.5 OFF-TRACK DETECTION
LDON (open-drain output) used turn laser off. When laser output high impedance. action LDON controlled xtra_preset parameter; automatically driven focus control loop active. Subcode interface
There subcode interfaces: which conforms "EIAJ CP-2401" (using SBSY, SFSY, SUB) configured either 4-wire interface. interface formats illustrated Fig.6. RS232 like format SUBQW illustrated Fig.7. subcode sync word formed pause minimum. Each subcode byte starts with followed bits between bytes vary 11.3 between Note that SUBQW valid lock-to-disc mode (includes QLLV). subcode data also available output (DOBM).
Off-Track Detection (OTD) signal flags off-track conditions; polarity this signal programmable. 7.3.6 SHOCK DETECTION
shock detector switched during normal track following. Within adjustable frequency range, detects whether disturbances radial spot relative track exceed programmable level. Every time Radial tracking Error (RE) exceeds this level, radial control bandwidth switched twice original bandwidth loop gain increased factor 7.3.7 DEFECT DETECTION
defect detection circuit incorporated into SAA7348. defect detected, circuit hold radial focus controls. defect detector 1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
SF97
SBSY SFSY EIAJ 4-wire subcode interface
SFSY
SF97
EIAJ 3-wire subcode interface
SFSY
MBG410
Fig.6 EIAJ subcode graphics) interface format.
200/n
11.3/n
11.3/n 90/n
MGK501
disc speed.
Fig.7 Subcode format timing SUBQW pin.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Digital output
SAA7348GP
Data taken after concealment, mute fade (can only used audio modes). 7.5.1 FORMAT
AES/EBU signal DOBM accordance with format defined "IEC 958". This signal only available decoder's modes audio features enabled (not QCLV modes). Three different modes selected: DOBM held Data taken before concealment, mute fade (must always used CD-ROM modes) Table 32-bit digital audio output format BITS note used; normally zero
digital audio output consists 32-bit words (`subframes') transmitted bi-phasemark code (two transitions logic transition logic Words transmitted blocks 384.
FUNCTION Sync Auxiliary Error flags Audio sample(2) Validity User flag(3) data(4)
DESCRIPTION
CFLG error interpolation flags when selected register first bits used (always zero); two's complement; valid logic used subcode data control bits category code even parity bits
Channel status(5) Parity Notes
sync word formed violation bi-phase rule and, therefore, does contain data. length equivalent data bits. different sync patterns indicate following situations: Sync word contains left sample (start block, words). Sync word contains left sample block start). Sync word contains right sample. Left right samples transmitted alternately. Audio samples flagged (bit error detected could corrected. This flag remains same even data taken after concealment. Subcode bits from subcode section transmitted user data bit. This data asynchronous with block rate. channel status same both left right words. Therefore, block words contains channel status bits. category code always assignment shown Table
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Table Channel status assignment DESCRIPTION
SAA7348GP
FUNCTION Control Reserved mode Category code Clock accuracy
copy checked Q-channel control bits logic when copy permitted; logic when recording pre-emphasis always zero logic other bits logic register class crystal (<50 ppm) class crystal (<1000 ppm) class crystal (>1000 ppm)
Remaining interface
always zero peak detector (measures highest audio level; absolute level left right channels; MSBs each output Q-channel data). Mono output selection. Either channel selected output over both left right channels. 7.7.1 SERIAL AUDIO DATA INTERFACE
This interface accordance with "S2B Interface Description". It's serial interface with high level command controlling CD-ROM engine. Audio support
Audio support consists several parts: Serial data interface. Deemphasis control (DEEM). This signal HIGH subcode info track defines recorded with deemphasis. Kill control (KILL). This signal tests digital silence right left channel before digital filter. output switched active silence been detected least mute active, CD-ROM modes. Output clock BCC-DAC applications (DACCLK). Oversampled output. SAA7348 contains times oversampling (Infinite Impulse-Response) filter, selectable deemphasis filter de-emphasis signal selected come DEEM then filter bypassed; Table 31). Concealment, mute, attenuation fade. audio modes 1-sample linear interpolator becomes active single sample flagged erroneous; left right channels have independent interpolators. digital level converter performs following functions: soft mute (signal reduced maximum steps) full-scale (signal ramped back level) attenuation (signal scaled fade (activates stage counter which allows signal scaled down 0.07 steps) serial data interface switched between modes: Philips EIAJ format. each case, serial data transferred through 3-wire interface. signal contains three components: WCLK (word select), SCLK (serial clock) (serial data). polarity WCLK data inverted. oversampling frequency format selected shown Table serial data output separate from CD-ROM output. CD-ROM mode serial data output will muted. Table Oversampling frequency select NUMBER BITS EIAJ SAMPLE FREQUENCY
MODE
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
CD-ROM support
SAA7348GP
supply pins. ensure that SAA7348 resets fully necessary following: Connect SELPLL DSDEN (rather than VDD). This allows internal clock multiplier start immediately after reset. Note that internal clocks guaranteed operate correct frequencies first after reset. Note also that operating speed microcontroller reduced Idle mode (and that baud rates change with processor clock). Connect SELPLL inverted reset signal. internal clock multiplier starts after reset, during Idle mode microcontroller speed normal. 7.10 External support
principle difference between predecessors with regard CD-ROM support provision separate serial data pin, which removes need external components. format EIAJ. 7.8.1 SERIAL CD-ROM DATA INTERFACE
serial data signal contains three components: WCLK (word select), SCLK (serial clock) DATA (serial data). polarity WCLK data inverted. WCLK SCLK common with audio serial data output. VALID signal used flag errors either 16-bit data word. Reset
SAA7348 active HIGH Schmitt trigger. valid reset, signal should HIGH period XTALI clock cycles, during which time power supply must within specification power
Since incorporates 80C51 core can, like microcontroller, program from external ROM. should tied this case. security reasons, this only sampled during reset, program cannot partly from external ROM. Signal relationships external program execution shown Fig.8. Timing specification found Table
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Table Timing specifications external program memory search PARAMETER pulse width address valid address hold after PSEN PSEN pulse width PSEN valid instruction input instruction hold after PSEN input instruction float after PSEN address valid instruction PSEN address float read pulse width write pulse width valid data data hold after data float after valid data address valid data address valid data valid transition data hold address float HIGH HIGH MIN.
SAA7348GP
SYMBOL tLHLL tAVLL tLLAX tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH
MAX.
UNIT
addition external program memory, external accessed. Timing relationships external data read shown Fig.9, external data write Fig.10.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
tLHLL tAVLL tLLPL tPLPH tPLIV PSEN tLLAX tPXIZ tPXIX
tPLAZ tAVIV
MGK502
Fig.8 Timing external program memory fetch.
handbook, full pagewidth
tWHLH PSEN tLLDV tRLRH tLLWL tAVLL tLLAX tRHDZ
tAVWL tAVDV
MGK503
Fig.9 Timing external data read.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
tWHLH PSEN tLLWL tAVLL tLLAX tQVWX tAVWL
MGK504
tWLWH
tWHQX
Fig.10 Timing external data write.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
MICROCONTROLLER INTERFACE
SAA7348GP
generates single internal master clock from which other clock signals derived. Note that both microcontroller servo designed duty factor input clock. decoder speed, internal master clock must 67.7376 (i.e. clock multiplier 16.9344 signal generated setting clock divider resulting standard duty factor clock. decoder speed, internal master clock must 50.8032 (i.e. clock multiplier divide factor will generate 16.9344 signal, resulting duty factor clock. clock divider values means CLKgen register shown Table
This section describes microcontroller application registers, memory map, decoder registers servo commands. 8.1.1 Microcontroller applications registers GENERATE REGISTER (CLKgen)
generate register used select clock multiplier frequencies dividers switch servo clock between single double frequency. register byte addressable; R/W. on-chip clock multiplier (programmable: allows external 8.4672 crystal used. This Table generate register (address 0X9EH) CLKgen.5 clock_servohi
clock_seldiv2
clock_seldiv1
clock_selpll2
clock_selpll1
CLKgen.7 CLKgen.6 Table
Description CLKgen bits SYMBOL CLKgen.7 CLKgen.6 CLKgen.5 clock_servohi clock_seldiv2 clock_seldiv1 clock_selpll2 clock_selpll1 these bits select clock multiplier frequency; Table selects single servo clock these bits select clock divider 80C51 core servo; Table used DESCRIPTION
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Table Divider selection REGISTER CLKgen 1(1) 1(1) 0(1) 1(1) SERVO CLOCK (MHz) 8.4672 16.9344 8.4672 16.9344 8.4672 16.9344 8.4672 16.9344
SAA7348GP
MASTER CLOCK CLOCK (MHz) (MHz) 33.8688 50.8032 67.7376 33.8688 16.9344 16.9344 16.9344 16.9344
DIVIDE FACTOR
OVER-SPEED SERVO
Note internal clock multiplier operates same frequency both these options.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.2 PORT SERVO REGISTER (PSR)
SAA7348GP
Port Servo Register internal used communicate with servo. register addressable; R/W. operation handshake bits used serial communications with servo outlined Table Table Port servo register (address 0XD8H 0XDFH) Tray_en Tray_pwm Srv_rdy Srv_dacc Srv_sild Srv_sicl Srv_sida Srv_intreqn
Table Description bits SYMBOL Tray_en Tray_pwm Srv_rdy Srv_dacc Srv_sild Srv_sicl Srv_sida Srv_intreqn ADDRESS 0XDFH 0XDEH 0XDDH 0XDCH 0XDBH 0XDAH 0XD9H 0XD8H signal enable tray driver signal tray driver RDY; Table DAC; Table SILD SICL SIDA INTREQN DESCRIPTION
Table Servo serial communication handshake signals DESCRIPTION transmit register full; microcontroller read byte send command idle state, transmit register empty; microcontroller transmit parameter relating command received byte, waiting receive register full
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.3 SERVO CONTROL REGISTER (SCR)
SAA7348GP
Servo Control Register used reading writing internal control signals. register byte addressable; R/W. Table Servo control register (address 0XD9H) Srv_frc_flock Srv_frc_lock Srv_otd Srv_da Srv_cl Srv_rab Srv_startup Serv_halt
Table Description bits SYMBOL Srv_frc_lock Srv_otd Srv_da Srv_cl Srv_rab Srv_startup Serv_halt DESCRIPTION force_lock; HIGH indicates frequency lock controller: off-track signal generated controller input multiplexer; HIGH indicates laser track (used only with direct decoder communication) (used only with direct decoder communication) (used only with direct decoder communication) pulse (start servo processor execution sequence); pulse latched; latch cleared write operation servo halt; halts servo processor execution Srv_frc_flock force_flock: coarse lock indicator control; HIGH indicates disc speed
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.4 SERVO STATUS REGISTER (STR)
SAA7348GP
Servo Status Register holds high level status information servo system. information latched into register cleared whenever register read. This information could trigger initiate recovery. register byte addressable; read only. Table Servo status register (address 0XE9H) Srv_tl1 Srv_tl0 Srv_shock Srv_hf_present Srv_FIFO_ov Srv_fock Srv_otd_inp Srv_subc
Table Description bits SYMBOL Srv_tl1 Srv_tl0 Srv_shock internal servo signal; Table internal servo signal; Table shock: decoder status signal; Motstart2 PLL_phase_lock Motor-ov FOCOK FIFO_OV: decoder status signal; FIFO overflow occurred FOCOK: servo output signal; focus OK/OK OTD: servo output signal; laser spot on/off track subcode found: decoder status signal; subcode present servo buffer DESCRIPTION
Srv_hf_present HF_present: internal decoder signal; indicates laser spot recorded area Srv_FIFO_ov Srv_fock Srv_otd_inp Srv_subc
Srv_tl0 Srv_tl1 signals used determine which direction servo counting during jump execution. Table Servo jump modes Srv_tl1 Srv_tl0 protected mode fast jump_1 slow jump fast jump_2 DESCRIPTION
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.5 MOTOR OUTPUT QCLV REGISTER (MOQ; address 0XF2H 0XF3H)
SAA7348GP
Motor Output QCLV register holds sixteen bits filtered motor error signal. This signal updated frequency 16.537 kHz. Address 0XF3H holds eight most significant bits, address 0XF2H eight least significant bits. Refreshing rule: byte read, high byte locked avoid mixing successive samples. high byte been read, byte will refreshed. register byte addressable; read only. 8.1.6 REGISTER
register used same standard 80C51. contains second UART, however, whose input output pins RXD1 TXD1 respectively. Direction control DDROUT3 (SFR address 0XFD; Table Section 8.1.12). register addressable; R/W. Table register (address 0XB0H 0XB7H) TXD1 RXD1 INT1 INT0 TXD0 RXD0
Table Description register bits SYMBOL TXD1 RXD1 INT1 INT0 TXD0 RXD0 ADDRESS 0XB7H 0XB6H 0XB5H 0XB4H 0XB3H 0XB2H 0XB1H 0XB0H TXD1: serial buffer transmit RXD1: serial buffer receive INT1: external Interrupt INT0: external Interrupt TXD0: serial buffer transmit RXD0: serial buffer receive DESCRIPTION
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.7 DECODER STATUS REGISTER (DSR)
SAA7348GP
decoder status register provides decoder status information. register byte addressable; read only. Table Decoder status register (address 0XEBH)
Decoder_stat.7 TX_full Dec_motov Dec_pll_flock Dec_pll_lock Dec_motstop Dec_motstart_2 Dec_motstart_1 Table Description bits SYMBOL Decoder_stat.7 TX_full Dec_motov Dec_pll_flock Dec_pll_lock Dec_motstop Dec_motstart_2 Dec_motstart_1 communication buffer decoder full motor-overflow: decoder status signal; motor output saturates PLL_flock: decoder internal signal; forced PLL_lock: decoder internal signal; forced motstop: decoder status signal; speed <12% motstart decoder status signal; speed >50% motstart decoder status signal; speed >75% DESCRIPTION
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.8 MOTOR SETPOINT REGISTER (MSR; address 0XF9H)
SAA7348GP
setpoint/speed values. Note that these measured values. They were measured using motor control bread board. This bread board hooked onto 65000 loader 12.66 application. filter config control (Cnf_filter) switched off. motor gain used. register byte addressable; R/W.
motor setpoint register used speed motor Quasi mode. QCLV motor control switched making setpoint equal 00100000. Table Table Speed measurements SETPOINT 00100000 00100010 00100011 00100101 00100111 00101000 00101010 00101100 00101101 00101111 00110000 00110010 00110011 00110101 00110111 00111000 00101010 00111100 00111110 00111111 01000000 01000010 01000011 01000101 01000111 01001001 01001011 01001100 01001110 01001111 01010001 01010010 MEASURED SPEED
SETPOINT 01010100 01010110 01010111 01011001 01011011 01011100 01011110 01011111 01100001 01100010 01100100 01100110 01100111 01101001 01101011 01101100 01101110 01101111 01110001 01110010 01110100 01110110 01110111 01111001 01111011 01111100 01111110 10000000 01111111 10000001 10000011 10000100
MEASURED SPEED
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.9 MOTOR GAIN QCLV REGISTER (address 0XFAH)
SAA7348GP
Table values). actual gain depends filter config register (Cnf_filter). filtering switched gain reduced factor register byte addressable; R/W.
motor_gain_QCLV register used gain motor control signal. used quasi well mode. Only least significant bits used (see Table Loop gain GAIN SETTING FILTER 00000000 00111111 00111110 00111101 00111100 00111011 00111010 00111001 00111000 00110111 00110110 00110101 00110100 00110011 00110010 00110001 00110000 00101111 00101110 00101101 00101100 00101011 00101010 00101001 00101000 00100111 00100110 00100101 00100100 00100011 00100010 00100001 FILTER 0.125 0.25 0.375 0.625 0.75 0.875 1.125 1.25 1.375 1.625 1.75 1.875 2.125 2.25 2.375 2.625 2.75 2.875 3.125 3.25 3.375 3.625 3.75 3.875
GAIN SETTING FILTER 00100000 00011111 00011110 00011101 00011100 00011011 00011010 00011001 00011000 00010111 00010110 00010101 00010100 00010011 00010010 00010001 00010000 00001111 00001110 00001101 00001100 00001011 00001010 00001001 00001000 00000111 00000110 00000101 00000100 00000011 00000010 FILTER 4.125 4.25 4.375 4.625 4.75 4.875 5.125 5.25 5.375 5.625 5.75 5.875 6.125 6.25 6.375 6.625 6.75 6.875 7.125 7.25 7.375 7.625 7.75 7.875
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.10 DATA DIRECTION REGISTERS (DDR0, DDR2 DDR3)
SAA7348GP
data direction registers used control direction data flow port pins (P0, P3). DDR0 controls DDR2 controls DDR3 controls logic written makes relevant port input port. logic makes output port. register byte addressable; R/W. Table Data direction registers (address DDR0: 0XFBH; DDR2: 0XFCH; DDR3: 0XFDH); note Srv_otd Srv_da Srv_cl Srv_rab Srv_startup Serv_halt
Srv_frc_flock Srv_frc_lock
Table Description bits SYMBOL DDROUTX7 controls direction PX.7 DDROUTX6 controls direction PX.6 DDROUTX5 controls direction PX.5 DDROUTX4 controls direction PX.4 DDROUTX3 controls direction PX.3 DDROUTX2 controls direction PX.2 DDROUTX1 controls direction PX.1 DDROUTX0 controls direction PX.0 DESCRIPTION(1)
Note Tables depending register selected (DDR0, DDR2 DDR3).
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.11 CONFIGURATION CONTROL REGISTER (CCR)
SAA7348GP
Config_cntrl register used control internal multiplexers. Note that motor output configuration register decoder used choose between decoder motor control QCLV motor control. register byte addressable; R/W. Table Description bits (address 0XFEH) POSITION(1) READ WRITE Config_cntrl.7 Cnf_dac_clk_sel used master clock selects clock DAC; Cnf_dac_clk_sel master clock Cnf_dac_clk_sel Note Note that function positions depends whether register being written read from. Cnf_AGC_bypass decoder bypass; Cnf_AGC_bypass bypass; Cnf_AGC_bypass Cnf_lock_over Cnf_uPotd Cnf_sign_mag Cnf_filter Cnf_dircom Lock_over_rule; Cnf_lock_over overrules decoder signals force_lock, force_flock selects input; Cnf_uPotd controller; Cnf_uPotd DSICS selects output mode; Cnf_sign_mag sign magnitude; Cnf_sign_mag two's complement selects filter QCLV motor control; Cnf_filter enable; Cnf_filter disable selects decoder communication mode; Cnf_dircom direct; Cnf_dircom indirect (via servo)
SYMBOL
FUNCTION
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.12 SECOND SERIAL INTERFACE
SAA7348GP
priority level. vector address interrupt could 0033H. 8.1.13 MEMORY ACCESS SERVO
second serial interface implemented using following registers: SCON2: 0XC0 SBUF2: 0XC1. This course interrupt function. register used enable this function. register used define this interrupt highest
Since performance basic engine largely determined subcode retrieval speed, fast access subcode buffer desirable. servo mapped onto microcontroller. this possible directly access servo registers; Table
Table Servo memory ADDRESS (HEX) 0X100 0X101 0X102 0X103 0X104 0X105 0X106 0X107 0X108 0X109 0X10A 0X10B 0X10C 0X10D 0X10E 0X10F 0X110 0X111 0X112 0X113 0X114 0X115 0X116 0X117 0X118 0X119 0X11A 0X11B 0X11C 0X11D 1997 focus_stat rad_stat mem_sledge1_hi offtrack_hi_rb offtrack_lo_rb mem_sledge1_lo rad_int_hi rad_int_lo rad_offset_hi rad_error_gain_mem_hi tpi_gain_hi focus_error_mem rad_error_mem speed_hi speed_lo focus_int_hi focus_int_lo drop_out_code foc_prop_mem FOCUS_PROP_MULT FOCUS_INT_GAIN RAMP_MEAN_VALUE slee_mult_mem RAMP_HEIGTH FE_LEVEL timer1 acc_stat_mem rad_prop_mult_mem rad_error_acc_mem CONTENTS time_keeper ADDRESS (HEX) 0X11E 0X11F 0X120 0X121 0X122 0X123 0X124 0X125 0X126 0X127 0X128 0X129 0X12A 0X12B 0X12C 0X12D 0X12E 0X12F 0X130 0X131 0X132 0X133 0X134 0X135 0X136 0X137 0X138 0X139 0x13A 0x13B CONTENTS rad_int_gain_mem speed_mult_mem rad_offset_lo rad_error_gain_mem_lo tpi_gain_lo sp_mem_lo sp_mem_hi speed_setpoint tpi_signal_mem rad_ctrl_1_mem2 rad_ctrl_1_mem rad_ctrl_2_mem rad_gain_mem stack stack stack stack stack stack oldcom state_mult_mem mem_sledge2_lo mem_sledge2_h RAMP_GAIN slede_mult_mem2 FAST_SPEED mem_sledge2_lo_lo gain_filter2_mem_lo gain_filter2_mem_hi gain_filter1_mem
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
ADDRESS (HEX) 0x13C 0x13D 0x13E 0x13F 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14A 0x14B 0x14C 0x14D 0x14E 0x14F 0x150 0x151 0x152 0x153 0x154 0x155 0x156 0x157 0x158 0x159 0x15A 0x15B 0x15C 0x15D
CONTENTS low_gain_mem gain_drempel_mem rad_ctrl_1_mem3 focus_int_mem1 interruptreg cd6statmem HiState MotorStatTime mem_sledge1_drempel_lo mem_sledge1_drempel_hi sledge_pulse_mem sledge_time_ou speed_drempel_mem hold_mult_mem xtra_preset cd6subadr cd6cmd1 cd6cmd2 asec asecold aframe aframemeold playwatchtimer interruptmask playwatchtimer trackcount1 timer2 jumpwatchtime sledge_long_brake radwatchstat sledge_power_mem rad_mem_part1 StateTimerHi StateTimerLo
ADDRESS (HEX) 0x15E 0x15F 0x160 0x161 0x162 0x163 0x164 0x165 0x166 0x167 0x168 0x169 0x16A 0x16B 0x16C 0x16D 0x16E 0x16F 0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177 0x178 0x179 0x17A 0x17B 0x17C 0x17D 0x17E 0x17F
CONTENTS FocusStartTime MotorStartTime1 MotorStartTime2 RadInitTime BrakeTime RadialStartStat sledge_pulse_height focus_inject radial_inject detphase oscinc injectlevel1 injectlevel2 agcgainmem agcgainlo focus_offset inject_lo offtrack_hi oftrack_lo used used subcode byte subcode byte subcode byte subcode byte subcode byte subcode byte subcode byte subcode byte subcode byte subcode byte peak level left peak level right
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.14 DIGITAL REGISTERS
SAA7348GP
behaviour digital monitored controlled using following registers: Frequency Register (address 0XECH): This register holds MSBs frequency. register byte addressable; read only. Offset Register (address 0XEDH): This register holds 8-bit asymmetry signal two's complement form. register byte addressable; read only. Jitter Register (address 0XEE): This register holds MSBs jitter bits. register byte addressable; read only. Register (address 0XFF): Presets MSBs frequency certain value. register byte addressable; R/W.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.1.15 DIV17 REGISTER (address 0X9FH)
SAA7348GP
This register used generate serial communication baud rate. this method chosen, baud rate will 62259 LSBs DIV17 hold value MSBs connect this baud rate generator UART UART (see Table 28). register byte addressable; R/W. Table Baud rate UART connection baud rate generator selected select baud rate generator only UART1 select baud rate generator only UART2 select baud rate generator UART1 UART2 DESCRIPTION
course still possible timers generate baud rate. Table provides overview various baud rates generated using timer timer DIV17. Table Baud rate selection, timer based; note BAUD RATE kBAUD 1411.20 996.14 529.20 498.07 373.55 264.60 249.04 186.78 124.52 88.20 66.15 62.26 44.10 33.08 9.80 Note don't care. µPCLK (MHz) 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 16.9344 MODE SMOD RELOAD TIMER 0XFF 0XFF 0XF7 RELOAD TIMER 0XFFF0 0XFFE8 DIV17 (ACE)
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Memory
SAA7348GP
Table Memory ADDRESS(1) LOWER Note example, address PCON TCON TMOD CLKgen DIV17 SCON1 SBUF T2CON T2MOD RCAP2L RCAP2H PLLFREQ PLLOFS PLLJITT MOTSETP MOTGAIN DDR0 DDR2 DDR3 CONFIG PLLINT UPPER SCON2 SBUF2 MOTQCLVL MOTQCLVH
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Summary functions controlled decoder registers
SAA7348GP
decoder uses programmable registers, accessible under internal microcontroller control. addresses these registers given Table along with summary functions performed. INITIAL column shows power-on reset state. Table Decoder Registers REGISTER (Fade attenuation) ADDRESS 0000 DATA X000 X01X X001 X100 X101 0XXX 1XXX (Motor mode) 0001 X000 X001 X010 X011 X100 X101 X111 X110 1XXX 0XXX (Status control) 0010 0000 0001 0010 0011 010X 011X 1X00 1X01 1X10 1X11 mute attenuate full scale step down step DACCLK operating DACCLK 3-stated motor mode motor brake mode motor brake mode motor start mode motor start mode motor jump mode motor play mode motor jump mode anti-windup active anti-windup status SUBQREADY-I status MOTSTART1 status MOTSTART2 status MOTSTOP status lock status MOTOR-OV status FIFO overflow status shock detect status latched shock detect status latched shock detect reset FUNCTION INITIAL(1) reset reset reset reset reset
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
REGISTER (DAC output)
ADDRESS 0011
DATA 1010 1011 110X 1111 1110 000X 0011 0010 010X 0111 0110
FUNCTION I2S-bus; CD-ROM mode EIAJ; CD-ROM mode I2S-bus; 18-bit; mode I2S-bus; 18-bit; mode I2S-bus; 16-bit; mode EIAJ; 16-bit; EAIJ; 16-bit; EIAJ; 16-bit; EIAJ; 18-bit; EIAJ; 18-bit; EIAJ; 18-bit; motor gain motor gain motor gain motor gain motor gain 12.8 motor gain 16.0 motor gain 25.6 motor gain 32.0 motor control standard motor control motor motor motor motor motor 0.85 motor 1.71 motor 3.42 motor power maximum motor power maximum motor power maximum motor power maximum 100% MOTOS, MOTOV pins 3-state motor mode motor mode motor mode
INITIAL(1) reset reset reset reset reset reset reset
(Motor gain)
0100
X000 X001 X010 X011 X100 X101 X110 X111 0XXX 1XXX
(Motor bandwidth)
0101
XX00 XX01 XX10 XX11 00XX 01XX 10XX
(Motor output configuration)
0110
XX00 XX01 XX10 XX11 00XX 01XX 10XX 11XX
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
REGISTER (DAC output control)
ADDRESS 0111
DATA xxx0 xxx1 xx0x xx1x 11xx 10xx 01xx 00xx
FUNCTION data normal value data inverted value left channel first (WCLK normal) right channel first (WCLK inverted) stereo output left mono right mono both channels killed Table
INITIAL(1) reset reset reset
(PLL loop filter bandwidth) (PLL equalization) 1001 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 (EBU output) 1010 xx0x xx1x x1x1 x0x1 x0x0 x1x0 0xxx 1xxx
equalization equalization equalization equalization equalization equalization equalization equalization equalization equalization equalization equalization equalization equalization equalization equalization DOBM data before concealment DOBM data after concealment fade DOBM off; output class crystal (<50 ppm) class crystal (<1000 ppm) class crystal (>1000 ppm) flags DOBM flags DOBM
reset reset reset reset
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
REGISTER (Speed control)
ADDRESS 1011
DATA x0xx x1xx 0xxx 1xxx xx00 xx10 xx11
FUNCTION 33.8688 crystal present, 8.4672 crystal with SELPLL HIGH 16.9344 crystal present single speed mode register 0xxx) four times speed mode register 1xxx); note double speed mode register 0xxx) eight times speed mode register 1xxx); note standby `CD-STOP' mode standby `CD-PAUSE' mode operating mode slicer bandwidth slicer bandwidth slicer bandwidth digital equalizer enabled digital equalizer disabled active inactive hold) subcode channels SUBQW SUBQW SUBQW de-emphasis signal DEEM, internal de-emphasis filter DEEM DEEM controls operating speed mode, register audio features disabled audio features enabled lock-to-disc mode disabled lock-to-disc mode enabled low-stop motor brakes low-stop motor brakes
INITIAL(1) reset reset reset reset reset reset reset reset reset reset reset reset
(Data slicer control)
1100
1xxx 01xx 00xx xx0x xx1x xxx0 xxx1
(Versatile pins interface)
1101
xx01 xx10 xx11 01xx 10xx 11xx
1110
0xxx x0xx x1xx xx0x xx1x xxx0 xxx1
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
REGISTER (Subcode interface)
ADDRESS 1111
DATA x0xx x1xx 0xxx 1xxx xx10 xx10 subcode interface subcode interface 4-wire subcode 3-wire subcode
FUNCTION
INITIAL(1) reset reset
decrease gain step, when (register increase gain step, when (register
Notes initial column shows power-on reset state. Speed microcontroller application register CLKgen. Table Loop filter bandwidth FUNCTION REGISTER ADDRESS DATA LOOP BANDWIDTH (Hz) 1640 3279 6560 1640 3279 6560 1640 3279 6560 1640 3279 6560 INTERNAL BANDWIDTH (Hz) 1050 2101 1050 4200 2101 1050 LOW-PASS BANDWIDTH (Hz) 8400 16800 33600 8400 16800 33600 8400 16800 33600 8400 16800 33600 INITIAL(1)
(PLL loop filter bandwidth)
1000
0000 0001 0010 0100 0101 0110 1000 1001 1010 1100 1101 1110
reset
Note initial column shows power-on reset state.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
Summary servo commands
SAA7348GP
servo commands listed Table Table Servo commands COMMANDS Write commands Preset_Latch Write_focus_coefs1 Write_focus_coefs2 Write_focus_command Focus_gain_up Focus_gain_down Write_radial coefs Preset_init Radial_off Radial_init Short_jump Long_jump Steer_sledge Write_decoder_reg Write_parameter Read commands Read_status Read_aux_status Read_Q_subcode Read_hilevel_status <foc_stat> <rad_stat> <rad_int_lpf> <offtrack_hi> <offtrack_lo> <RE_offset> <RE_gain> <sum_gain> <foc_error> <rad_error> <intreq> <decstat> <seqstat> <motorstarttime> <chip_init> <foc_parm_3> <foc_int> <ramp_incr> <ramp_height> <ramp_offset> <FE_start> <foc_gain> <defect_parm> <rad_parm_jump> <vel_parm2> <vel_parm1> <foc_parm_1> <foc_parm_2> <CA_drop> <foc_mask> <foc_stat> <shock_level> <foc_gain> <foc_parm_1> <foc_gain> <foc_parm_1> <rad_length_lead> <rad_int> <rad_parm_play> <rad_pole_noise> <rad_gain> <sledge_parm_2> <sledge_parm_1> <RE_offset> <RE_gain> <sum_gain> <offtrack_hi> <offtrack_lo> <rad_stat> <brake_dist_max> <sledge_U_max> <offtrack_hi> <offtrack_lo> <rad_stat> <sledge_Uout> <deccmd> <param_ram_addr> <param_data> CODE BYTES PARAMETERS
<Q_sub1 <peak_l> <peak_r>
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
8.4.1 SUMMARY SERVO COMMAND PARAMETERS
SAA7348GP
Table Servo command parameters PARAMETER foc_parm_1 ADDRESS AFFECTS focus VALUE DETERMINES focus lead defect detector enabling polarity focus low-pass focus error normalising focus lead length minimum light level focus integrator crossover frequency focus loop gain sensitivity drop-out detector asymmetry focus ramp value ramp voltage slope ramp voltage minimum value focus error initial value RE_offset initial value RE_gain initial value sum_gain radial lead radial low-pass length radial lead radial integrator crossover frequency radial loop gain filter during jump controller crossover frequencies jump pre-defined profile maximum speed fast track mode electronic damping radial actuator sledge bandwidth during jump sledge distance allowed fast actuator steered mode brake distance sledge two's complement number tracks jump two's complement number tracks jump radial sledge control voltage sledge during long jump voltage sledge when steered
foc_parm_2 foc_parm_3 foc_int foc_gain CA_drop ramp_offset ramp_height ramp_incr FE_start RE_offset RE_gain sum_gain rad_parm_play rad_pole_noise rad_length_lead rad_int rad_gain rad_parm_jump vel_parm1 vel_parm2 speed_thres act_sled brake_dist_max sledge_brake_dist offtrack_hi offtrack_lo rad_stat sledge_Umax sledge_Uout
focus focus focus focus focus focus ramp focus ramp focus ramp focus ramp radial initialization radial initialization radial initialization radial radial radial radial radial radial jump radial jump radial jump radial jump radial jump radial jump radial jump radial jump radial jump radial/sledge sledge sledge
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
PARAMETER sledge_parm_1 sledge_parm_2
ADDRESS
AFFECTS sledge sledge
VALUE
DETERMINES sledge integrator crossover frequency shock filter sledge low-pass frequencies sledge gain sledge operation mode control pulse width control pulse height defect detector setting shock detector operation radial on-track watchdog time radial jump watchdog time-out enable/disable automatic radial feature level setting enable/disable decoder interface decoder interface speed interrupt request polarity fast radial brake laser on/off modulating frequency enable/disable fast brake fast jumping circuit on/off send commands decoder enabled interrupts autosequencer control focus start time motorstart1 time motorstart2 time radial initialisation time brake time radial command byte control frequency injected signal phase shift injected signal amplitude signal injected amplitude signal injected focus/radial gain
pulse_time pulse_height defect_parm shock_level playwatchtime jumpwatchtime wradcontrol chip_init
pulsed sledge pulsed sledge defect detector shock detector watchdog watchdog watchdog set-up
xtra_preset
set-up
deccmd interruptmask seq_state FocusStartTime MotorStartTime1 MotorStartTime2 RadialInitTime BrakeTime RadCmdByte osc_frequency detect_phase injectlevel1 injectlevel2 agc_gain
decoder interface STATUS autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer focus/radial focus/radial focus/radial focus/radial focus/radial
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
LIMITING VALUES accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VDDD(pads) VDDD(core) VDDA PARAMETER digital supply voltage cells digital supply voltage core analog supply voltage input voltage (any input) output voltage (any output) between analog digital (core) supply voltages II(d) Tamb Tstg output current (continuous) diode input current (continuous) operating ambient temperature storage temperature electrostatic handling note note Notes supply pins (VDDDn(pads)) must connected externally same power supply. pins must connected same external voltage. CONDITIONS notes notes notes MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -2000 -200
SAA7348GP
MAX. +6.5 +4.0 +4.0 +6.5 ±0.25 +125 +2000 +200
UNITS
VDDA-DDD(core) supply voltage difference
analog digital core supply pins (VDDA VDDDn(core)) must connected externally same power supply. Equivalent discharging capacitor series resistor with rise time Equivalent discharging capacitor series inductor.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
CHARACTERISTICS
SAA7348GP
10.1 General characteristics VDDD(pads) VDDD(core) VDDA Tamb unless otherwise specified. SYMBOL Supply VDDD(pads) VDDD(core) VDDA digital supply voltage cells digital supply voltage core analog supply voltage supply current mode PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Servo analog section (VDDD(pads) VDDD(core) VDDA Tamb PINS: VRH, IrefT, FTCL FTCH Cint IIrefT RIrefT IS(max) IIrefT RIrefT VIrefT VD1-D4, VGAP tch(VRH) (THD+N)/S internal capacitor input current IrefT external resistor IrefT input current central diode input signal maximum input current satellite diode input signal input current IrefT external resistor IrefT input current central diode input signal input current satellite diode input signal voltage current input IrefT voltage current inputs band voltage HIGH level reference voltage charge time buffer total harmonic distortion-plus-noise signal ratio note note fsys 4.2336 MHz; notes fsys 4.2336 MHz; notes fsys 4.2336 MHz; notes fsys 4.2336 MHz; notes fsys 8.4672 MHz; notes fsys 8.4672 MHz; notes fsys 8.4672 MHz; notes fsys 8.4672 MHz; notes 1.99 3.97 1.99 3.97 7.94 3.97 virtual VGAP virtual VSSA 5.95 11.91 5.95 11.91 23.81 11.91
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
SYMBOL PSRR Gtol Voffset(FTC)
PARAMETER signal-to-noise ratio
CONDITIONS
MIN.
TYP.
MAX.
UNIT
power supply ripple rejection note VDDA gain tolerance variation gain between channels channel separation comparator offset notes
Decoder analog front-end (VDDD(pads) VDDD(core) VDDA Tamb PINS: MIDLAD, REFLCA, HFIN, REFHCA Iref fclk BAGC Voffset Gv(AGC) clock frequency bandwidth total offset voltage gain: range step Vi(AGC)(p-p)) Vi(ADC) input signal range; peak-to-peak value input range plus buffer total harmonic distortion Digital inputs INPUT: DEFI; CMOS INPUT WITH PULL-DOWN Rpd(int) Vth(r) Vth(f) Vhys 1997 LOW-level input voltage HIGH-level input voltage internal pull-down resistance input capacitance switching threshold rising switching threshold falling hysteresis voltage input capacitance -0.3 -0.3 0.33 signal-to-noise ratio input impedance HFIN -4.4 +12.1 12/16 18/24
Input: RST; CMOS input with hysteresis
INPUTS: SELPLL; CMOS INPUTS LOW-level input voltage HIGH-level input voltage input leakage current input capacitance
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
SYMBOL Digital output
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
OUTPUTS: TPWM, TEN, SUBQW, DSDEN, CLO, DEEM, DEFO to(r) to(f) LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time levels; levels;
Open drain outputs OUTPUTS: FOK, CFLG, C2FAIL, KILL LDON; OPEN DRAIN OUTPUTS to(f) LOW-level output voltage LOW-level output current load capacitance output fall time levels;
3-state outputs OUTPUTS: DACCLK, VALID, DAC, DATA, WCLK, SCLK, MOTOS, MOTOV, DOBM, SBSY, SFSY to(r) to(f) LOW-level output voltage HIGH-level output voltage load capacitance output rise time output fall time 3-state leakage current level; levels;
Digital Input/Output INPUTS/OUTPUTS: PSEN, CMOS INPUT/OUTPUT WITH PULL-UP to(r) to(f) LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage output rise time output fall time load capacitance input capacitance input pull-up resistance levels; levels; -0.3
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
SYMBOL
PARAMETER
CONDITIONS
MIN. -0.3
TYP.
MAX.
UNIT
INPUTS/OUTPUTS: AD7, A15, RXD0, TXD0, INT0, INT1, RXD1, TXD1, to(r) to(f) fxtal gm(mutual) Notes servo clock fsys always equivalent Section 10.2. Current input range (resistor range) extended (minimum maximum) gain tolerance this region 25%. unipolar converter. Cref CDAC. Cref CDAC Internal reference source with different output voltages. Selection made during calibration period serial interface. values given unloaded VRH. output voltage measuring bandwidth: kHz, fi(ADC) kHz. fripple kHz, Vripple peak-to-peak. Gain tolerance determined accuracy external resistor Rext. recommended that series resistance crystal ceramic resonator 1997
-44.4
LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage 3-state leakage current output rise time output fall time load capacitance input capacitance levels; levels;
-0.3 -2.0
INPUT: XTALI (EXTERNAL CLOCK) LOW-level input voltage HIGH-level input voltage input HIGH time input leakage current input capacitance relative period +0.5
OUTPUT: XTALO crystal frequency mutual transconductance small signal voltage gain feedback capacitance output capacitance note 8.4672 mA/V
where
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
10.2 Subcode interface timing characteristics VDDD(pads) VDDD(core) VDDA Tamb unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Subcode interface timing (single speed note Fig.11 INPUT: tclkH tclkL td(SFSY-RCK) input clock HIGH time input clock time input clock rise time input clock fall time delay time SFSY
OUTPUTS: SBSY, SFSY Tcy(block) tW(SBSY) Tcy(frame) tW(SFSY) tSFSYH tSFSYL td(SFSY-SUB) td(RCK-SUB) th(RCK-SUB) block cycle time SBSY pulse width frame cycle time SFSY pulse width (3-wire mode only) SFSY HIGH time SFSY time delay time SFSY data) valid delay time falling hold time 12.0 13.3 14.7
Note subcode timing directly related over-speed factor, normal operating mode; replaced disc speed factor, lock-to-disc mode.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
handbook, full pagewidth
tW(SBSY)
Tcy(block)
SBSY tSFSYH SFSY (4-wire mode) tW(SFSY) SFSY (3-wire mode) tSFSYL tcy(frame)
SFSY td(SFSY-RCK) td(SFSY-SUB) th(RCK-SUB) td(RCK-SUB)
MBG414
Fig.11 Subcode interface timing.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SAA7348GP
10.3 timing characteristics VDDD(pads) VDDD(core) VDDA Tamb unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Timing (single speed note Fig.12 CLOCK OUTPUT: SCLK Tcy(clk) output clock period sample rate sample rate sample rate tclkH clock HIGH time sample rate sample rate sample rate tclkL clock time sample rate sample rate sample rate OUTPUTS: WCLK, DATA, VALID set-up time sample rate sample rate sample rate hold time sample rate sample rate sample rate Note timing directly related over-speed factor, normal operating mode; replaced disc speed factor, lock-to-disc mode. 95/n 48/n 24/n 95/n 48/n 24/n 166/n 83/n 42/n 166/n 83/n 42/n 472.4/n 236.2/n 118.1/n
clock period Tcy(clk) tCLKL tCLKH SCLK WCLK DATA VALID
MGK505
Fig.12 Timing.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
PACKAGE OUTLINE LQFP100: plastic profile quad flat package; leads; body
SAA7348GP
SOT407-1
index detail
scale
DIMENSIONS original dimensions) UNIT Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT407-1 REFERENCES JEDEC EIAJ EUROPEAN PROJECTION max. 0.20 0.05 0.25 0.28 0.16 0.18 0.12 14.1 13.9 14.1 13.9 0.75 0.45 0.70 0.57 0.12 1.15 0.85 1.15 0.85
16.25 16.25 15.75 15.75
ISSUE DATE 95-12-19
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
SOLDERING 12.1 Introduction
SAA7348GP
double-wave turbulent wave with high upward pressure followed smooth laminar wave) soldering technique should used. footprint must angle board direction must incorporate solder thieves downstream side corners. Even with these conditions, consider wave soldering following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) QFP160 (SOT322-1). During placement before soldering, package must fixed with droplet adhesive. adhesive applied screen printing, transfer syringe dispensing. package soldered after adhesive cured. Maximum permissible solder temperature maximum duration package immersion solder seconds, cooled less than within seconds. Typical dwell time seconds mildly-activated flux will eliminate need removal corrosive residues most applications. 12.4 Repairing soldered joints
There soldering method that ideal packages. Wave soldering often preferred when through-hole surface mounted components mixed printed-circuit board. However, wave soldering always suitable surface mounted ICs, printed-circuits with high population densities. these situations reflow soldering often used. This text gives very brief insight complex technology. more in-depth account soldering found Package Databook" (order code 9398 90011). 12.2 Reflow soldering
Reflow soldering techniques suitable packages. choice heating method influenced larger plastic packages leads, more). infrared vapour phase heating used large packages absolutely (less than 0.1% moisture content weight), vaporization small amount moisture them cause cracking plastic body. more information, refer Drypack chapter "Quality Reference Handbook" (order code 9397 00192). Reflow soldering requires solder paste suspension fine solder particles, flux binding agent) applied printed-circuit board screen printing, stencilling pressure-syringe dispensing before package placement. Several techniques exist reflowing; example, thermal conduction heated belt. Dwell times vary between seconds depending heating method. Typical reflow temperatures range from Preheating necessary paste evaporate binding agent. Preheating duration: minutes 12.3 Wave soldering
component first soldering diagonallyopposite leads. only voltage soldering iron (less than applied flat part lead. Contact time must limited seconds When using dedicated tool, other leads soldered operation within seconds between
Wave soldering recommended packages. This because likelihood solder bridging closely-spaced leads possibility incomplete solder penetration multi-lead devices. wave soldering cannot avoided, following conditions must observed:
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7348GP
This data sheet contains target goal specifications product development. This data sheet contains preliminary data; supplementary data published later. This data sheet contains final product specifications.
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Where application information given, advisory does form part specification. LIFE SUPPORT APPLICATIONS These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips customers using selling these products such applications their risk agree fully indemnify Philips damages resulting from such improper sale.
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
NOTES
SAA7348GP
1997
Philips Semiconductors
Preliminary specification
Compact Disc Engine (ACE)
NOTES
SAA7348GP
1997
Philips Semiconductors worldwide company
Argentina: South America Australia: Waterloo Road, NORTH RYDE, 2113, Tel. 9805 4455, Fax. 9805 4466 Austria: Computerstr. A-1101 WIEN, P.O. 213, Tel. 1010, Fax. 1210 Belarus: Hotel Minsk Business Center, Bld. 1211, Volodarski Str. 220050 MINSK, Tel. +375 733, Fax. +375 Belgium: Netherlands Brazil: South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, James Bourchier Blvd., 1407 SOFIA, Tel. +359 211, Fax. +359 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. 7381 China/Hong Kong: Hong Kong Industrial Technology Centre, Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: South America Czech Republic: Austria Denmark: Prags Boulevard 1919, DK-2300 COPENHAGEN Tel. 2636, Fax. 0044 Finland: Sinikalliontie FIN-02630 ESPOO, Tel. +358 615800, Fax. +358 61580920 France: Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. 6161, Fax. 6427 Germany: D-20097 HAMBURG, Tel. Fax. Greece: 25th March Street, 17778 TAVROS/ATHENS, Tel. 4894 339/239, Fax. 4814 Hungary: Austria India: Philips INDIA Ltd, Band Building, floor, 254-D, Annie Besant Road, Worli, MUMBAI 025, Tel. 8541, Fax. 0966 Indonesia: Singapore Ireland: Newstead, Clonskeagh, DUBLIN Tel. +353 7640 000, Fax. +353 7640 Israel: RAPAC Electronics, Kehilat Saloniki 18053, AVIV 61180, Tel. +972 0444, Fax. +972 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza Novembre 20124 MILANO, Tel. 6752 2531, Fax. 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. 3740 5130, Fax. 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. 1412, Fax. 1415 Malaysia: Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. 5214, Fax. 4880 Mexico: 5900 Gateway East, Suite 200, PASO, TEXAS 79905, Tel. +9-5 7381 Middle East: Italy Netherlands: Postbus 90050, 5600 EINDHOVEN, Bldg. Tel. 82785, Fax. 88399 Zealand: Wagener Place, C.P.O. 1041, AUCKLAND, Tel. 4160, Fax. 7811 Norway: Manglerud 0612, OSLO, Tel. 8000, Fax. 8341 Philippines: Philips Semiconductors Philippines Inc., Valero Salcedo Village, P.O. 2108 MCC, MAKATI, Metro MANILA, Tel. 6380, Fax. 3474 Poland: Lukiska 04-123 WARSZAWA, Tel. 2831, Fax. 2327 Portugal: Spain Romania: Italy Russia: Philips Russia, Usatcheva 35A, 119048 MOSCOW, Tel. 6918, Fax. 6919 Singapore: Lorong Payoh, SINGAPORE 1231, Tel. 2538, Fax. 6500 Slovakia: Austria Slovenia: Italy South Africa: S.A. PHILIPS Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. 7430 Johannesburg 2000, Tel. 5911, Fax. 5494 South America: Rocio 220, floor, Suite 04552-903 Paulo, PAULO Brazil, Tel. 2333, Fax. 1849 Spain: Balmes 08007 BARCELONA, Tel. 6312, Fax. 4107 Sweden: Kottbygatan Akalla, S-16485 STOCKHOLM, Tel. 2000, Fax. 2745 Switzerland: Allmendstrasse 140, CH-8027 Tel. 2686, Fax. 7730 Taiwan: Philips Semiconductors, Chien Rd., Sec. TAIPEI, Taiwan Tel. +886 2134 2865, Fax. +886 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. 4090, Fax. 0793 Turkey: Talatpasa Cad. 80640 Tel. 2770, Fax. 6707 Ukraine: PHILIPS UKRAINE, Patrice Lumumba str., Building Floor 252042 KIEV, Tel. +380 2776, Fax. +380 0461 United Kingdom: Philips Semiconductors Ltd., Bath Road, Hayes, MIDDLESEX 5BX, Tel. 5000, Fax. 8421 United States: East Arques Avenue, SUNNYVALE, 94088-3409, Tel. 7381 Uruguay: South America Vietnam: Singapore Yugoslavia: PHILIPS, Pasica 5/v, 11000 BEOGRAD, Tel. +381 344, Fax.+381
other countries apply Philips Semiconductors, Marketing Sales Communications, Building BE-p, P.O. 218, 5600 EINDHOVEN, Netherlands, Fax. 24825 Philips Electronics N.V. 1997
Internet:
SCA55
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights.
Printed Netherlands
657027/1200/01/pp60
Date release: 1997
Document order number:
9397 02136

SAA7348GP Compact Disc Engine (ACE) Preliminary specification Fil

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