AMD64 Architecture Programmer's Manual Volume General-Purpose System I
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AMD64 Technology
AMD64 Architecture Programmer's Manual Volume General-Purpose System Instructions
Publication 24594 Revision 3.09 Date September 2003
2002, 2003 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, arrow logo, combinations thereof, 3DNow! trademarks, AMD-K6 registered trademark Advanced Micro Devices, Inc. trademark Pentium registered trademark Intel Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
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Contents
Figures Tables Revision History xiii
Preface About This Book Audience Contact Information. Organization Definitions. Related Documents xxvii Instruction Formats
Instruction Byte Order Instruction Prefixes. Summary Legacy Prefixes Operand-Size Override Prefix Address-Size Override Prefix Segment-Override Prefixes Lock Prefix Repeat Prefixes Prefixes Opcode ModRM Bytes Displacement Bytes Immediate Bytes RIP-Relative Addressing Encoding. Prefix RIP-Relative Addressing. Address-Size Prefix RIP-Relative Addressing.
Instruction Overview
Instruction Subsets Reference-Page Format Summary Registers Data Types General-Purpose Instructions. System Instructions 128-Bit Media Instructions 64-Bit Media Instructions Floating-Point Instructions Summary Exceptions Notation
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Mnemonic Syntax Opcode Syntax Pseudocode Definitions
General-Purpose Instruction Reference
ADC. BOUND BSWAP CALL (Near). CALL (Far) CWDE CDQE CQO. CLFLUSH. CMOVcc CMPSx CMPXCHG CMPXCHG8B. CPUID. DAA. DEC. ENTER IDIV IMUL. INSx
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INTO JCXZ JECXZ JRCXZ (Near). (Far) LAHF LEAVE LFENCE LODSx. LOOPcc MFENCE MOVD MOVMSKPD. MOVMSKPS MOVNTI MOVS MOVSB MOVSW MOVSD MOVSQ MOVSX MOVSXD MOVZX NEG. NOP. OUT. OUTSx POPAx. POPFx. PREFETCHx PREFETCHlevel. PUSH PUSHAx
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PUSHFx RCR. (Near). (Far) ROR. SAHF SCASx SETcc SFENCE SHLD SHR. SHRD STOSx TEST XADD XCHG XLATx.
System Instruction Reference
ARPL CLTS INVD INVLPG IRETx LAR. LGDT LIDT LLDT. LMSW MOV(CRn) MOV(DRn) RDMSR.
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RDPMC. RDTSC SGDT. SIDT SLDT SMSW STI. SWAPGS SYSCALL SYSENTER. SYSEXIT. SYSRET VERR VERW WBINVD WRMSR
Appendix
Opcode Operand Encodings
Opcode-Syntax Notation Opcode Encodings One-Byte Opcodes Two-Byte Opcodes rFLAGS Condition Codes Two-Byte Opcodes ModRM Extensions One-Byte Two-Byte Opcodes. ModRM Extensions SWAPGS CLFLUSH Opcodes 3DNow!Opcodes Encodings rFLAGS Condition Codes Opcodes Operand Encodings ModRM Operand References Operand References.
Appendix
General-Purpose Instructions 64-Bit Mode
General Rules 64-Bit Mode. Operation Operand Size 64-Bit Mode Invalid Reassigned Instructions 64-Bit Mode Instructions with 64-Bit Default Operand Size. Single-Byte Instructions 64-Bit Mode 64-Bit Mode. Segment Override Prefixes 64-Bit Mode
Appendix Appendix
Differences Between Long Mode Legacy Mode Instruction Subsets CPUID Feature Sets
Instruction Subsets CPUID Feature Sets
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Instruction List
Appendix
Instruction Effects RFLAGS Index
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Figures
Figure 1-1. Instruction Byte-Order. Figure 1-2. Little-Endian Byte-Order Instruction Stored Memory Figure 1-3. Encoding Examples REX-Prefix Bits. Figure 1-4. ModRM-Byte Format Figure 1-5. SIB-Byte Format Figure 2-1. Format Instruction-Detail Pages Figure 2-2. General Registers Legacy Compatibility Modes Figure 2-3. General Registers 64-Bit Mode. Figure 2-4. Segment Registers Figure 2-5. General-Purpose Data Types. Figure 2-6. System Registers Figure 2-7. System Data Structures Figure 2-8. 128-Bit Media Registers. Figure 2-9. 128-Bit Media Data Types Figure 2-10.64-Bit Media Registers. Figure 2-11.64-Bit Media Data Types Figure 2-12.x87 Registers. Figure 2-13.x87 Data Types Figure 2-14.Syntax Typical Two-Operand Instruction Figure 3-1. Processor Signature (EAX Register) Figure 3-2. Initial APIC CLFLUSH Size, Brand (EBX Register) Figure 3-3. Advanced Power Management Features (EDX Register) Figure 3-4. MOVD Instruction Operation Figure A-1. ModRM-Byte Fields Figure A-2. ModRM-Byte Format Figure A-3. Byte Format Figure D-1. Instruction Subsets CPUID Feature Sets
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Tables
Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 1-7. Table 1-8. Table 1-9. Legacy Instruction Prefixes Operand-Size Overrides. Address-Size Overrides Pointer Count Registers Address-Size Prefix Segment-Override Prefixes Prefix Opcodes. REPE REPZ Prefix Opcodes REPNE REPNZ Prefix Opcodes Instruction Prefixes
Table 1-10. Instructions Requiring Size Prefix 64-Bit Mode Table 1-11. Prefix-Byte Fields Table 1-12. Special Encodings Registers Table 1-13. Encoding RIP-Relative Addressing Table 2-1. Table 2-2. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Interrupt-Vector Source Cause +rb, +rw, +rd, Register Value Processor Vendor Return Values Effective Family Computation Effective Model Computation. CPUID Standard Feature Support (Standard Function CPUID Feature Support (Extended Function 8000_0001h) Processor Name String Example CPUID Bits 2-Mbyte 4-Mbyte Pages CPUID Bits 4-Kbyte Pages CPUID Data Cache Bits
Table 3-10. CPUID Instruction Cache Bits Table 3-11. CPUID Bits 2-Mbyte 4-Mbyte Pages Table 3-12. CPUID Bits 4-Kbyte Pages Table 3-13. CPUID Cache Bits Table 3-14. CPUID Long-Mode Address Sizes. Table 3-15. Locality References Prefetch Instructions Table A-1. One-Byte Opcodes, Nibble 0-7h Table A-2. One-Byte Opcodes, Nibble 8-Fh Table A-3. Second Byte Two-Byte Opcodes, Nibble 0-7h.
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Table A-4. Second Byte Two-Byte Opcodes, Nibble 8-Fh Table A-5. rFLAGS Condition Codes CMOVcc, Jcc, SETcc Table A-6. One-Byte Two-Byte Opcode ModRM Extensions Table A-7. SWAPGS xFENCE ModRM Extensions Table A-8. Immediate Byte 3DNow!Opcodes, Nibble 0-7h Table A-9. Immediate Byte 3DNow!Opcodes, Nibble 8-Fh Table A-10. Opcodes ModRM Extensions Table A-11. rFLAGS Condition Codes FCMOVcc Table A-12. ModRM Register References, 16-Bit Addressing Table A-13. ModRM Memory References, 16-Bit Addressing Table A-14. ModRM Register References, 32-Bit 64-Bit Addressing Table A-15. ModRM Memory References, 32-Bit 64-Bit Addressing Table A-16. base Field References Table A-17. Memory References Table B-1. Operations Operands 64-Bit Mode Table B-2. Invalid Instructions 64-Bit Mode Table B-3. Reassigned Instructions 64-Bit Mode. Table B-4. Invalid Instructions Long Mode Table B-5. Instructions Defaulting 64-Bit Operand Size Table C-1. Differences Between Long Mode Legacy Mode. Table D-1. Instruction Subsets CPUID Feature Sets Table E-1. Instruction Effects RFLAGS
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Revision History
Date September 2003 Revision 3.09 Description Corrected table valid descriptor types instructions made several minor formatting, stylistic factual corrections. Clarified several technical defintions. Corrected description operation flags RCL, RCR, ROL, instructions. Clarified description MOVSXD IMUL instructions. Corrected operand specification STOS instruction. Corrected opcode SETcc, Jcc, instructions. Added thermal control thermal monitoring bits CPUID instruction. Corrected exception tables POPF, SFENCE, SUB, XLAT, IRET, LSL, MOV(CRn), SGDT/SIDT, SMSW, instructions. Corrected many small typos incorporated branding terminology.
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Preface
About This Book
This book part multivolume work entitled AMD64 Architecture Programmer's Manual. This table lists each volume order number.
Title Volume Application Programming Volume System Programming Volume General-Purpose System Instructions Volume 128-Bit Media Instructions Volume 64-Bit Media Floating-Point Instructions Order 24592 24593 24594 26568 26569
Audience
This volume (Volume intended programmers writing application system software processor that implements AMD64 architecture. Descriptions general-purpose instructions assume understanding application-level programming topics described Volume Descriptions system instructions assume understanding systemlevel programming topics described Volume
Contact Information
submit questions comments concerning this document, AMD64.Feedback@amd.com.
Organization
Volumes describe AMD64 architecture's instruction detail. Together, they cover each instruction's mnemonic syntax, opcodes, functions, affected flags, possible exceptions. AMD64 instruction divided into five subsets:
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General-purpose instructions System instructions 128-bit media instructions 64-bit media instructions floating-point instructions Several instructions belong to-and described identically in-multiple instruction subsets. This volume describes general-purpose system instructions. index cross-references topics within architecture, information instructions other subsets, tables contents indexes other volumes.
Definitions
Many following definitions assume in-depth knowledge legacy architecture. "Related Documents" page xxvii descriptions legacy architecture. Terms Notation addition notation described below, "Opcode-Syntax Notation" page describes notation relating specifically opcodes. 1011b binary value-in this example, 4-bit value. F0EAh hexadecimal value-in this example 2-byte value. [1,2) range that includes left-most value this case, excludes right-most value this case, range, from inclusive. high-order shown first. 128-bit media instructions Instructions that 128-bit registers. These combination SSE2 instruction sets. Preface
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64-bit media instructions Instructions that 64-bit registers. These instruction sets, with some additional instructions from SSE2 instruction sets. 16-bit mode Legacy mode compatibility mode which 16-bit address size active. legacy mode compatibility mode. 32-bit mode Legacy mode compatibility mode which 32-bit address size active. legacy mode compatibility mode. 64-bit mode submode long mode. 64-bit mode, default address size bits features, such register extensions, supported system application software. #GP(0) Notation indicating general-protection exception (#GP) with error code absolute Said displacement that references base code segment rather than instruction pointer. Contrast with relative. biased exponent floating-point value's exponent constant bias particular floating-point data type. bias makes range biased exponent always positive, which allows reciprocation without overflow. byte Eight bits. clear write value Compare set.
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compatibility mode submode long mode. compatibility mode, default address bits, legacy 16-bit 32-bit applications without modification. commit irreversibly write, program order, instruction's result software-visible storage, such register (including flags), data cache, internal write buffer, memory. Current privilege level. CR0-CR4 register range, from register through CR4, inclusive, with low-order register first. CR0.PE Notation indicating that register value direct Referencing memory location whose address included instruction's syntax immediate operand. address absolute relative address. Compare indirect. dirty data Data held processor's caches internal buffers that more recent than copy held main memory. displacement signed value that added base segment (absolute addressing) instruction pointer (relative addressing). Same offset. doubleword words, four bytes, bits. double quadword Eight words, bytes, bits. Also called octword.
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DS:rSI contents memory location whose segment address register whose offset relative that segment register. EFER.LME Notation indicating that EFER register value effective address size address size current instruction after accounting default address size address-size override prefix. effective operand size accounting default operand size operandsize override prefix. element vector. exception abnormal condition that occurs result executing instruction. processor's response exception depends type exception. exceptions except 128-bit media SIMD floating-point exceptions floating-point exceptions, control transferred handler service routine) that exception, defined exception's vector. floating-point exceptions defined IEEE standard, there both masked unmasked responses. When unmasked, exception handler called, when masked, default response provided instead calling handler. Notation indicating that first byte opcode, subopcode ModR/M byte value flush often ambiguous term meaning writeback, modified, invalidate, "flush cache line," invalidate, "flush pipeline," change value, "flush zero."
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Global descriptor table. Interrupt descriptor table. Ignore. Field ignored. indirect Referencing memory location whose address register other memory location. address absolute relative address. Compare direct. virtual-8086 mode interrupt-redirection bitmap. long-mode interrupt-stack table. real-address mode interrupt-vector table. Local descriptor table. legacy legacy architecture. "Related Documents" page xxvii descriptions legacy architecture. legacy mode operating mode AMD64 architecture which existing 16-bit 32-bit applications operating systems without modification. processor implementation AMD64 architecture either long mode legacy mode. Legacy mode three submodes, real mode, protected mode, virtual-8086 mode. long mode operating mode unique AMD64 architecture. processor implementation AMD64 architecture either long mode legacy mode. Long mode submodes, 64-bit mode compatibility mode.
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Least-significant bit. Least-significant byte. main memory Physical memory, such (but cache memory) that installed particular computer system. mask control that prevents occurrence floatingpoint exception from invoking exception-handling routine. field bits used control purpose. Must zero. software attempts general-protection exception (#GP) occurs. memory Unless otherwise specified, main memory. ModRM byte following instruction opcode that specifies address calculation based mode (Mod), register (R), memory variables. moffset 64-bit offset that specifies memory operand directly, without using ModRM byte. Most-significant bit. Most-significant byte. multimedia instructions combination 128-bit media instructions 64-bit media instructions. octword Same double quadword. offset Same displacement. Preface
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overflow condition which floating-point number larger magnitude than largest, finite, positive negative number that represented data-type format being used. packed vector. Physical-address extensions. physical memory Actual memory, consisting main memory cache. probe check address processor's caches internal buffers. External probes originate outside processor, internal probes originate within processor. protected mode submode legacy mode. quadword Four words, eight bytes, bits. Read zero (0), regardless what written. real-address mode real mode. real mode short name real-address mode, submode legacy mode. relative Referencing with displacement (also called offset) from instruction pointer rather than base code segment. Contrast with absolute. instruction prefix that specifies 64-bit operand size provides access additional registers.
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RIP-relative addressing Addressing relative 64-bit instruction pointer. write value Compare clear. byte following instruction opcode that specifies address calculation based scale (S), index (I), base (B). SIMD Single instruction, multiple data. vector. Streaming SIMD extensions instruction set. 128-bit media instructions 64-bit media instructions. SSE2 Extensions instruction set. 128-bit media instructions 64-bit media instructions. sticky that cleared hardware that remains that state until explicitly changed software. top-of-stack pointer. Task-priority register (CR8). Task-state segment. underflow condition which floating-point number smaller magnitude than smallest nonzero, positive negative number that represented data-type format being used. vector integer floating-point values, called elements, that packed into single operand. Most 128-bit 64-bit media instructions vectors operands. Preface xxiii
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Vectors also called packed SIMD (single-instruction multiple-data) operands. index into interrupt descriptor table (IDT), used access exception handlers. Compare exception. virtual-8086 mode submode legacy mode. word bytes, bits. legacy x86. Registers following list registers, names used refer either given register contents that register: AH-DH high 8-bit registers. Compare AL-DL. AL-DL 8-bit registers. Compare AH-DH. AL-r15B 8-bit SIL, DIL, BPL, SPL, R8B-R15B registers, available 64-bit mode. Base pointer register. Control register number Code segment register. eAX-eSP 16-bit registers 32-bit EAX, EBX, ECX, EDX, EDI, ESI, EBP, registers. Compare rAX-rSP. EFER Extended features enable register.
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eFLAGS 16-bit 32-bit flags register. Compare rFLAGS. EFLAGS 32-bit (extended) flags register. 16-bit 32-bit instruction-pointer register. Compare rIP. 32-bit (extended) instruction-pointer register. FLAGS 16-bit flags register. GDTR Global descriptor table register. GPRs General-purpose registers. 16-bit data size, these 32-bit data size, these EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP. 64-bit data size, these include RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8-R15. IDTR Interrupt descriptor table register. 16-bit instruction-pointer register. LDTR Local descriptor table register. Model-specific register. r8-r15 8-bit R8B-R15B registers, 16-bit R8W-R15W registers, 32-bit R8D-R15D registers, 64-bit R8-R15 registers. rAX-rSP 16-bit registers, 32-bit EAX, EBX, ECX, EDX, EDI, ESI, EBP, registers, 64-bit RAX, RBX, RCX, RDX, RDI, RSI, Preface
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RBP, registers. Replace placeholder with nothing 16-bit size, 32-bit size, 64-bit size. 64-bit version register. 64-bit version register. 64-bit version register. 64-bit version register. 64-bit version register. 64-bit version register. rFLAGS 16-bit, 32-bit, 64-bit flags register. Compare RFLAGS. RFLAGS 64-bit flags register. Compare rFLAGS. 16-bit, 32-bit, 64-bit instruction-pointer register. Compare RIP. 64-bit instruction-pointer register. 64-bit version register. 64-bit version register. Stack pointer register. Stack segment register. xxvi Preface
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Task priority register, register introduced AMD64 architecture speed interrupt management. Task register. Endian Order AMD64 architectures address memory using littleendian byte-ordering. Multibyte values stored with their least-significant byte lowest byte address, they illustrated with their least significant byte right side. Strings illustrated reverse order, because addresses their bytes increase from right left.
Related Documents
Peter Abel, Assembly Language Programming, Prentice-Hall, Englewood Cliffs, 1995. Rakesh Agarwal, 80x86 Architecture Programming: Volume Prentice-Hall, Englewood Cliffs, 1991. AMD, AMD-K6MMXEnhanced Processor Multimedia Technology, Sunnyvale, 2000. AMD, 3DNow!Technology Manual, Sunnyvale, 2000. AMD, Extensions 3DNow!and MMXInstruction Sets, Sunnyvale, 2000. Anderson Shanley, Pentium Processor System Architecture, Addison-Wesley, York, 1995. Nabajyoti Barkakati Randall Hyde, Microsoft Macro Assembler Bible, Sams, Carmel, Indiana, 1992. Barry Brey, 8086/8088, 80286, 80386, 80486 Assembly Language Programming, Macmillan Publishing Co., York, 1994. Barry Brey, Programming 80286, 80386, 80486, Pentium Based Personal Computer, Prentice-Hall, Englewood Cliffs, 1995. Ralf Brown Kyle, Interrupts, Addison-Wesley, York, 1994. Penn Brumm Brumm, 80386/80486 Assembly Language Programming, Windcrest McGraw-Hill, 1993. Geoff Chappell, Internals, Addison-Wesley, York, 1994. Preface xxvii
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Chips Technologies, Inc. Super386 Programmer's Reference Manual, Chips Technologies, Inc., Jose, 1992. John Crawford Patrick Gelsinger, Programming 80386, Sybex, Francisco, 1987. Cyrix Corporation, 5x86 Processor BIOS Writer's Guide, Cyrix Corporation, Richardson, 1995. Cyrix Corporation, Processor Data Book, Cyrix Corporation, Richardson, 1996. Cyrix Corporation, Processor Extension Opcode Table, Cyrix Corporation, Richardson, 1996. Cyrix Corporation, Processor Data Book, Cyrix Corporation, Richardson, 1997. Duncan, Extending DOS: Programmer's Guide Protected-Mode DOS, Addison Wesley, 1991. William Giles, Assembly Language Programming Intel 80xxx Family, Macmillan, York, 1991. Frank Gilluwe, Undocumented Addison-Wesley, York, 1994. John Hennessy David Patterson, Computer Architecture, Morgan Kaufmann Publishers, Mateo, 1996. Thom Hogan, Programmer's Sourcebook, Microsoft Press, Redmond, 1991. Katircioglu, Inside 486, Pentium, Pentium Pro, Peer-to-Peer Communications, Menlo Park, 1997. Corporation, 486SLC Microprocessor Data Sheet, Corporation, Essex Junction, 1993. Corporation, 486SLC2 Microprocessor Data Sheet, Corporation, Essex Junction, 1993. Corporation, 80486DX2 Processor Floating Point Instructions, Corporation, Essex Junction, 1995. Corporation, 80486DX2 Processor BIOS Writer's Guide, Corporation, Essex Junction, 1995. Corporation, Blue Lightning 486DX2 Data Book, Corporation, Essex Junction, 1994. Institute Electrical Electronics Engineers, IEEE Standard Binary Floating-Point Arithmetic, ANSI/IEEE 754-1985. xxviii Preface
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Institute Electrical Electronics Engineers, IEEE Standard Radix-Independent Floating-Point Arithmetic, ANSI/IEEE 854-1987. Muhammad Mazidi Janice Gillispie Mazidi, 80X86 Compatible Computers, Prentice-Hall, Englewood Cliffs, 1997. Hans-Peter Messmer, Indispensable Pentium Book, Addison-Wesley, York, 1995. Karen Miller, Assembly Language Introduction Computer Architecture: Using Intel Pentium, Oxford University Press, York, 1999. Stephen Morse, Eric Isaacson, Douglas Albert, 80386/387 Architecture, John Wiley Sons, York, 1987. NexGen Inc., Nx586 Processor Data Book, NexGen Inc., Milpitas, 1993. NexGen Inc., Nx686 Processor Data Book, NexGen Inc., Milpitas, 1994. Bipin Patwardhan, Introduction Streaming SIMD Extensions Pentium III, www.x86.org/articles/sse_pt1/ simd1.htm, June, 2000. Peter Norton, Peter Aitken, Richard Wilton, Programmer's Bible, Microsoft Press, Redmond, 1993. PharLap 386|ASM Reference Manual, Pharlap, Cambridge 1993. PharLap DOS-Extender Reference Manual, Pharlap, Cambridge 1995. Sen-Cuo Sheau-Chuen Her, i386/i486 Advanced Programming, Nostrand Reinhold, York, 1993. Jeffrey Royer, Introduction Protected Mode Programming, course materials onsite class, 1992. Shanley, Protected Mode System Architecture, Addison Wesley, 1996. SGS-Thomson Corporation, 80486DX Processor Programming Manual, SGS-Thomson Corporation, 1995. Walter Triebel, 80386DX Microprocessor, PrenticeHall, Englewood Cliffs, 1992. John Wharton, Complete x86, MicroDesign Resources, Sebastopol, California, 1994. sites newsgroups: Preface xxix
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Instruction Formats
format instruction encodes operation, well locations instruction's initial operands result operation. This section describes general format parameters used instructions. information specific format(s) each instruction, see: Chapter "General-Purpose Instruction Reference." Chapter "System Instruction Reference." "128-Bit Media Instruction Reference" Volume "64-Bit Media Instruction Reference" Volume "x87 Floating-Point Instruction Reference" Volume
Instruction Byte Order
instruction between bytes length. Figure shows byte order instruction format.
Legacy Prefix
Prefix
Opcode bytes)
ModRM
Displacement Immediate bytes) bytes)
Instruction Length Bytes
Figure 1-1.
Instruction Byte-Order Instructions stored memory little-endian order. least-significant byte instruction stored lowest memory address, shown Figure page
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Most-signifcant (highest) address
Bytes
Least-signifcant (lowest) address
Immediate Immediate Immediate Immediate Displacement Displacement Displacement Displacement ModRM Opcode Opcode Prefix Legacy Prefix Legacy Prefix Legacy Prefix Legacy Prefix
(all two-byte opcodes have their first byte) (available only 64-bit mode) optional, depending instruction optional, with most instructions
513-304.eps
Figure 1-2. Little-Endian Byte-Order Instruction Stored Memory basic operation instruction specified opcode. opcode bytes long, described "Opcode" page opcode preceded number legacy prefixes. These prefixes classified belonging five groups prefixes described "Instruction Prefixes" page legacy prefixes modify instruction's default address size, operand size, segment, they invoke special function such modification opcode, atomic buslocking, repetition. prefix used 64-bit "Application-Programming Register Set" Volume prefix used, must immediately precede first opcode byte. instruction's opcode consists bytes. several 128-bit 64-bit media instructions, legacy operand-size repeat prefix byte used special-purpose modify opcode. opcode followed mode-registermemory (ModRM) byte, which further describes operation Chapter Instruction Formats
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and/or operands. opcode, opcode ModRM byte, also followed scale-index-base (SIB) byte, which describes scale, index, base forms memory addressing. ModRM bytes described "ModRM Bytes" page their legacy functions modified prefix ("Instruction Prefixes" page 15-byte instruction-length limit only exceeded using redundant prefixes. limit exceeded, generalprotection exception occurs.
Instruction Prefixes
instruction prefixes shown Figure page types: legacy prefixes prefixes. Each legacy prefixes unique byte value. contrast, prefixes, which enable AMD64 register extensions 64-bit mode, organized group byte values which value prefix indicates combination register-extension features enabled.
1.2.1 Summary Legacy Prefixes
Table page shows legacy prefixes-that prefixes except prefixes, which described page legacy prefixes organized into five groups, shown left-most column Table 1-1. single instruction should include maximum prefix from each five groups. legacy prefixes appear order within position shown Figure legacy prefixes. result using multiple prefixes from single group unpredictable. Some restrictions legacy prefixes are: Operand-Size Override-This prefix affects only generalpurpose instructions instructions. When used with 128-bit 64-bit media instructions, this prefix acts special modify opcode. Address-Size Override-This prefix affects only memory operands. Segment Override-In 64-bit mode, segment override prefixes ignored. LOCK Prefix-This prefix allowed only with certain instructions that modify memory.
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Repeat Prefixes-These prefixes affect only certain string instructions. When used with 128-bit 64-bit media instructions, these prefixes special modify opcode. Table 1-1. Legacy Instruction Prefixes
Mnemonic none none Segment Override Lock LOCK REPE REPZ REPNE REPNZ
Note:
Prefix Group1 Operand-Size Override Address-Size Override
Prefix Byte (Hex)
Description Changes default operand size memory register operand, shown Table page Changes default address size memory operand, shown Table page Forces current segment memory operands. Forces current segment memory operands. Forces current segment memory operands. Forces current segment memory operands. Forces current segment memory operands. Forces current segment memory operands. Causes certain kinds memory read-modify-write instructions occur atomically. Repeats string operation (INS, MOVS, OUTS, LODS, STOS) until register equals
Repeat
Repeats compare-string scan-string operation (CMPSx SCASx) until register equals zero flag (ZF) cleared Repeats compare-string scan-string operation (CMPSx SCASx) until register equals zero flag (ZF)
single instruction should include maximum prefix from each five groups. When used with 128-bit 64-bit media instructions, this prefix acts special modify opcode. prefix ignored 64-bit media floating-point (3DNow!TM) instructions. "Instructions that Cannot Operand-Size Prefix" page This prefix also changes size register when used implied count register. 64-bit mode, segment overrides ignored. LOCK prefix should used instructions other than those listed "Lock Prefix" page This prefix should used only with compare-string scan-string instructions. When used with 128-bit 64-bit media instructions, prefix acts special modify opcode.
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1.2.2 Operand-Size Override Prefix
default operand size instruction determined combination opcode, (default) current code-segment descriptor, current operating mode, shown Table 1-2. operand-size override prefix (66h) selects non-default operand size. prefix used with general-purpose instruction that accesses non-fixedsize operands memory general-purpose registers (GPRs), also used with FLDENV, FNSTENV, FNSAVE, FRSTOR instructions. 64-bit mode, prefix allows mixing 16-bit, 32-bit, 64bit data instruction-by-instruction basis. compatibility legacy modes, prefix allows mixing 16-bit 32-bit operands instruction-by-instruction basis. Table 1-2. Operand-Size Overrides
Default Operand Size (Bits) Effective Operand Size (Bits) 64-Bit Mode Long Mode Compatibility Mode Instruction Prefix1 don't care Applicable REX.W3
Operating Mode
Legacy Mode (Protected, Virtual-8086, Real Mode)
Note:
"no' indicates that default operand size used. This typical default, although some instructions default other operand sizes. Appendix "General-Purpose Instructions 64-Bit Mode," details. "REX Prefixes" page
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64-bit mode, most instructions default 32-bit operand size. these instructions, prefix (page specify 64-bit operand size, prefix specifies 16-bit operand size. prefix takes precedence over prefix. However, instruction defaults 64-bit operand size, does need prefix only overridden 16-bit operand size. cannot overridden 32-bit operand size, because there 32-bit operand-size override prefix 64-bit mode. groups instructions have default 64-bit operand size 64-bit mode: Near branches. details, "Near Branches 64-Bit Mode" Volume instructions, except branches, that implicitly reference RSP. details, "Stack Operation" Volume Instructions that Cannot Operand-Size Prefix. operand-size prefix should used only with general-purpose instructions FLDENV, FNSTENV, FNSAVE, FRSTOR instructions, which prefix selects between 16-bit 32bit operand size. prefix ignored other instructions 64-bit media floating-point (3DNow!TM) instructions. When used with 64-bit media integer instructions, prefix acts special modify opcode. This modification typically causes access register 128-bit memory operand thereby converts 64-bit media instruction into comparable 128-bit media instruction. result using repeat prefix along with prefix 128-bit 64-bit media instructions unpredictable. Operand-Size Prefixes. operand-size prefix takes precedence over prefix. "REX.W: Operand Width" page details. 1.2.3 Address-Size Override Prefix default address size instructions that access non-stack memory determined current operating mode, shown Table 1-3. address-size override prefix (67h) selects non-default address size. Depending operating mode, this prefix allows mixing 16-bit 32-bit, 32-bit 64bit addresses, instruction-by-instruction basis. prefix changes address size memory operands. also changes
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size register instructions that implicitly. instructions that implicitly access stack segment (SS), address size stack accesses determined (default) stack-segment descriptor. 64-bit mode, ignored, stack references have 64-bit address size. However, instruction accesses both stack non-stack memory, address size non-stack access determined shown Table 1-3. Table 1-3. Address-Size Overrides
Default Address Size (Bits) Effective Address Size (Bits) AddressSize Prefix (67h)1 Required?
Operating Mode
64-Bit Mode Long Mode Compatibility Mode
Legacy Mode (Protected, Virtual-8086, Real Mode)
Note:
"no" indicates that default address size used.
Table shows, default address size bits 64-bit mode. size overridden bits, 16-bit addresses supported 64-bit mode. compatibility legacy modes, default address size bits bits, depending operating mode (see "Processor Initialization Long-Mode Activation" Volume details). these modes, address-size prefix selects non-default size, 64-bit address size available.
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Certain instructions reference pointer registers count registers implicitly, rather than explicitly. such instructions, address-size prefix affects size such addressing count registers, just does when such registers explicitly referenced. Table lists such instructions registers referenced using three possible address sizes. Table 1-4. Pointer Count Registers Address-Size Prefix
Pointer Count Register Instruction CMPS, CMPSB, CMPSW, CMPSD, CMPSQ-Compare Strings INS, INSB, INSW, INSD-Input String JCXZ, JECXZ, JRCXZ-Jump CX/ECX/RCX Zero LODS, LODSB, LODSW, LODSD, LODSQ-Load String LOOP, LOOPE, LOOPNZ, LOOPNE, LOOPZ-Loop MOVS, MOVSB, MOVSW, MOVSD, MOVSQ-Move String OUTS, OUTSB, OUTSW, OUTSD-Output String REP, REPE, REPNE, REPNZ, REPZ-Repeat Prefixes SCAS, SCASB, SCASW, SCASD, SCASQ-Scan String STOS, STOSB, STOSW, STOSD, STOSQ-Store String XLAT, XLATB-Table Look-up Translation 16-Bit Address Size 32-Bit Address Size ESI, EDI, 64-Bit Address Size RSI, RDI,
EDI, ESI, ESI, EDI, ESI, EDI, EDI,
RDI, RSI, RSI, RDI, RSI, RDI, RDI,
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1.2.4 SegmentOverride Prefixes
Segment overrides used only with instructions that reference non-stack memory. Most instructions that reference memory encoded with ModRM byte (page 20). default segment such memory-referencing instructions implied base register indicated ModRM byte, follows: Instructions that Reference Non-Stack Segment-If instruction encoding references base register other than rSP, instruction contains immediate offset, default segment data segment (DS). These instructions segment-override prefix select non-default segments, shown Table 1-5. String Instructions-String instructions reference memory operands. default, they reference both segments (DS:rSI ES:rDI). These instructions override their DS-segment reference, shown Table 1-5, they cannot override their ES-segment reference. Instructions that Reference Stack Segment-If instruction's encoding references base register, default segment stack segment (SS). instructions that reference stack (push, pop, call, interrupt, return from interrupt) default. These instructions cannot segment-override prefix. Table 1-5.
Mnemonic
Note:
Segment-Override Prefixes
Prefix Byte (Hex) Description Forces current segment memory operands. Forces current segment memory operands. Forces current segment memory operands. Forces current segment memory operands. Forces current segment memory operands. Forces current segment memory operands.
64-bit mode, segment overrides ignored.
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Segment Overrides 64-Bit Mode. 64-bit mode, segment-override prefixes have effect. These four prefixes treated segment-override prefixes purposes multiple-prefix rules. Instead, they treated null prefixes. segment-override prefixes treated true segment-override prefixes 64-bit mode. prefix causes their respective segment bases added effective address calculation. Registers 64Bit Mode" Volume details. 1.2.5 Lock Prefix LOCK prefix causes certain kinds memory read-modifywrite instructions occur atomically. mechanism doing implementation-dependent (for example, mechanism involve signaling packet messaging between processor memory controller). prefix intended give processor exclusive shared memory multiprocessor system. LOCK prefix only used with forms following instructions that write memory operand: ADC, ADD, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT, SBB, SUB, XADD, XCHG, XOR. invalidopcode exception occurs LOCK prefix used with other instruction. 1.2.6 Repeat Prefixes repeat prefixes cause repetition certain instructions that load, store, move, input, output strings. prefixes should only used with such string instructions. pairs repeat prefixes, REPE/REPZ REPNE/REPNZ, perform same repeat functions certain compare-string scan-string instructions. repeat function uses count register. size based address size, shown Table page REP. prefix repeats associated string instruction number times specified counter register (rCX). terminates repetition when value reaches prefix only used with INS, LODS, MOVS, OUTS, STOS instructions. Table shows valid prefix opcodes.
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Table 1-6.
Mnemonic
Prefix Opcodes
Opcode
reg/mem8, INSB reg/mem16/32, INSW INSD LODS mem8 LODSB LODS mem16/32/64 LODSW LODSD LODSQ MOVS mem8, mem8 MOVSB MOVS mem16/32/64, mem16/32/64 MOVSW MOVSD MOVSQ OUTS reg/mem8 OUTSB OUTS reg/mem16/32 OUTSW OUTSD STOS mem8 STOSB STOS mem16/32/64 STOSW STOSD STOSQ
REPE REPZ. identical opcodes. These prefixes repeat their associated string instruction number times specified counter Chapter Instruction Formats
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register (rCX). repetition terminates when value reaches when zero flag (ZF) cleared REPE REPZ prefixes only used with CMPS, CMPSB, instructions. Table shows valid REPE REPZ prefix opcodes. Table 1-7.
Mnemonic REPx CMPS mem8, mem8 REPx CMPSB REPx CMPS mem16/32/64, mem16/32/64 REPx CMPSW REPx CMPSD REPx CMPSQ REPx SCAS mem8 REPx SCASB REPx SCAS mem16/32/64 REPx SCASW REPx SCASD REPx SCASQ
REPE REPZ Prefix Opcodes
Opcode
REPNE REPNZ. REPNE REPNZ synonyms have identical opcodes. These prefixes repeat their associated string instruction number times specified counter register (rCX). repetition terminates when value reaches when zero flag (ZF) REPNE REPNZ prefixes only used with CMPS, CMPSB, instructions. Table page shows valid REPNE REPNZ prefix opcodes.
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Table 1-8.
Mnemonic
REPNE REPNZ Prefix Opcodes
Opcode
REPNx CMPS mem8, mem8 REPNx CMPSB REPNx CMPS mem16/32/64, mem16/32/64 REPNx CMPSW REPNx CMPSD REPNx CMPSQ REPNx SCAS mem8 REPNx SCASB REPNx SCAS mem16/32/64 REPNx SCASW REPNx SCASD REPNx SCASQ
Instructions that Cannot Repeat Prefixes. general, repeat prefixes should only used string instructions listed tables 1-6, 1-7, 1-8, 128-bit 64-bit media instructions. When used media instructions, prefixes special modify opcode rather than cause repeat operation. result using operand-size prefix along with prefix 128-bit 64-bit media instructions unpredictable. Optimization Repeats. Depending hardware implementation, repeat prefixes have setup overhead. repeated count variable, overhead sometimes avoided substituting simple loop move store data. Repeated string instructions expanded into equivalent sequences inline loads stores sequence stores used emulate STOS. repeated string moves, performance maximized moving largest possible operand size. example, MOVSD rather than MOVSW MOVSW rather than MOVSB. STOSD rather than STOSW STOSW rather than MOVSB.
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Depending hardware implementation, string moves with direction flag (DF) cleared (up) faster than string moves with (down). only needed certain cases overlapping MOVS, such when source destination overlap. 1.2.7 Prefixes prefixes group instruction-prefix bytes that used only 64-bit mode. They enable access AMD64 register extensions. Figure page Figure page show prefix fits within byte order instructions. prefixes enable following features 64bit mode: extended (Figure page registers (Figure page 36). 64-bit operand size when accessing GPRs. extended control debug registers, described "64-Bit-Mode Extended Control Registers" Volume "64-Bit-Mode Extended Debug Registers" Volume uniform byte registers (AL-R15). Table shows prefixes. value prefix range through 4Fh, depending particular combination AMD64 register extensions desired. Table 1-9. Instruction Prefixes
Mnemonic REX.W Register Extensions REX.R REX.X REX.B
Note:
Prefix Type
Prefix Code (Hex) through
Description
Access AMD64 register extension.
Table 1-11 encoding prefixes.
prefix normally required with instruction that accesses 64-bit extended registers. Only instructions have operand size that defaults fixed bits 64-bit mode, thus Chapter Instruction Formats
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need prefix. These exceptions normal rule listed Table 1-10. instruction have only prefix, although prefix express several extension features. prefix used, must immediately precede first opcode byte instruction format. other placement prefix, prefix instruction that does access extended register, ignored. legacy instruction-size limit bytes still applies instructions that contain prefix. Table 1-10.
CALL (Near) ENTER JrCXZ (Near) LEAVE LGDT LIDT LLDT LOOP LOOPcc CR(n)
Instructions Requiring Size Prefix 64-Bit Mode
reg/mem POPFQ PUSH imm8 PUSH imm32 PUSH reg/mem PUSH PUSH PUSH PUSHFQ (Near) DR(n)
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prefixes sixteen values that span main opcode occupy entries through 4Fh. Table 1-11 Figure page show prefix fields their uses. Table 1-11. Prefix-Byte Fields
Position 0100 Default operand size 64-bit operand size 1-bit (high) extension ModRM field1, thus permitting access registers. 1-bit (high) extension index field1, thus permitting access registers. 1-bit (high) extension ModRM field1, base field1, opcode field, thus permitting access registers. Definition
Mnemonic REX.W REX.R REX.X
REX.B
Note:
description ModRM bytes, "ModRM Bytes" page
REX.W: Operand Width. Setting REX.W specifies 64bit operand size. Like existing operand-size prefix, 64-bit operand-size override effect byte operations. non-byte operations, operand-size override takes precedence over prefix. prefix used together with prefix that REX.W prefix ignored. However, prefix used together with prefix that REX.W cleared prefix ignored operand size becomes bits. REX.R: Register. REX.R adds 1-bit (high) extension ModRM field (page when that field encodes GPR, XMM, control, debug register. REX.R does modify ModRM when that field specifies other registers opcodes. REX.R ignored such cases. REX.X: Index. REX.X adds 1-bit (high) extension index field (page 20).
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REX.B: Base. REX.B either adds 1-bit (high) extension base ModRM field base field, adds 1-bit (high) extension opcode field used accessing GPRs. (See Table page more about REX.B bit.) Encoding Examples. Figure page shows four examples bits prefixes concatenated with fields from ModRM byte, byte, opcode specify register memory addressing. bits described Table 1-11 page Byte-Register Addressing. legacy architecture, byte registers (AH, shown Figure page encoded ModRM field opcode field registers through prefix provides additional byte-register addressing capability that makes least-significant byte available byte operations (Figure page 31). This provides uniform byte, word, doubleword, quadword registers better suited register allocation compilers. Special Encodings Registers. Readers need know details instruction encodings should aware that certain combinations ModRM fields have special combinations, instruction fields expanded prefix decoded (treated don't cares), thereby creating aliases these encodings extended registers. Table 1-12 page describes each these cases behaves. Implications Instructions. prefix values taken from single-byte instructions, each eight GPRs. Therefore, these single-byte opcodes available 64-bit mode, although they available legacy compatibility modes. functionality these instructions still available 64-bit mode, however, using ModRM forms those instructions (opcodes /1).
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Case Register-Register Addressing Memory Operand) Prefix 4WRXB Opcode ModRM Byte
REX.X used
Rrrr Bbbb Case Memory Addressing Without Byte Prefix 4WRXB Opcode ModRM Byte
REX.X used ModRM field
Rrrr Bbbb
Case Memory Addressing With Byte Prefix 4WRXB Opcode ModRM Byte Byte scale index base
Rrrr
Xxxx Bbbb
Case Register Operand Coded Opcode Byte Prefix 4WRXB Opcode Byte REX.R used REX.X used
Bbbb
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Figure 1-3. Encoding Examples REX-Prefix Bits Chapter Instruction Formats
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Table 1-12.
Special Encodings Registers
Meaning Legacy Compatibility Modes Implications Legacy Compatibility Modes Additional Implications prefix adds fourth (b), which decoded modifies base register byte. Therefore, byte also required R12-based addressing. prefix adds fourth (x), which decoded (don't care). Therefore, using without displacement must done with displacement prefix adds fourth (x), which decoded. Therefore, there additional implications. expanded index field used distinguish from R12, allowing used index. prefix adds fourth (b), which decoded (don't care). Therefore, using without displacement must done with displacement (with without index register).
ModRM Encodings2
ModRM Byte: r/m1 (ESP)
byte present.
byte required ESP-based addressing.
ModRM Byte: r/m1 x101 (EBP)
Base register used.
Using without displacement must done setting with displacement (with without index register).
Byte: index1 x100 (ESP)
Index register used.
cannot used index register.
Byte: base b101 (EBP) ModRM.mod
Base register used ModRM.mod
Base register depends encoding. Using with scaled index without displacement must done setting with displacement
Notes:
REX-prefix shown fourth (most-significant) position encodings ModRM r/m, index, base fields. lower-case ModRM (rather than upper-case shown Figure page indicates that REX-prefix decoded (don't care). description ModRM bytes, "ModRM Bytes" page
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Opcode
Each instruction unique opcode, although assemblers support multiple mnemonics single instruction opcode. opcode specifies operation that instruction performs and, certain cases, kinds operands uses. opcode consists bytes, certain 128-bit media instructions also prefix byte special modify opcode. 3-bit field ModRM byte ("ModRM Bytes" page also used certain instructions either three additional opcode bits register specification. 128-Bit 64-Bit Media Instruction Opcodes. Many 128-bit 64-bit media instructions include 66h, F2h, prefix byte special modify opcode. These same byte values used certain general-purpose instructions modify operand size (66h) repeat operation (F2h, F3h). 128-bit 64-bit media instructions, however, such prefix bytes modify opcode. 128-bit 64-bit media instruction uses these three prefixes, also includes other unpredictable. opcodes 64-bit media instructions begin with byte. case 64-bit floating-point (3DNow!) instructions, byte followed second opcode byte. third opcode byte occupies same position 3DNow! instruction would immediate byte. value immediate byte shown third opcode byte-value syntax each instruction "64-Bit Media Instruction Reference" Volume format
ModRM [SIB] [displacement] 3DNow!_third_opcode_byte
details opcode encoding, Appendix "Opcode Operand Encodings."
ModRM Bytes
ModRM byte used certain instruction encodings Define register reference. Define memory reference.
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Provide additional opcode bits with which define instruction's function. ModRM bytes have three fields-mod, reg, r/m. field provides additional opcode bits with which define function instruction operands. fields used together with each other and, 64-bit mode, with REX.R REX.B bits prefix (page 14), specify location instruction's operands certain possible addressing modes (specifically, non-complex modes). Figure shows format ModRM byte.
Bits:
REX.R prefix extend this field bits REX.B prefix extend this field bits
ModRM
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Figure 1-4. ModRM-Byte Format some instructions, ModRM byte followed byte, which defines memory addressing complexaddressing modes described "Effective Addresses" Volume byte three fields-scale, index, base-that define scale factor, index-register number, base-register number 32-bit 64-bit complex addressing modes. 64-bit mode, REX.B REX.X bits extend encoding byte's base index fields. Figure shows format byte.
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Bits:
scale REX.X prefix extend this field bits
index
base
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REX.B prefix extend this field bits
Figure 1-5. SIB-Byte Format encodings ModRM bytes only define memory-addressing modes, they also specify operand registers. encodings this using 3-bit fields ModRM bytes, depending format: ModRM: fields ModRM byte. (Case Figure page shows example this). ModRM with SIB: field ModRM byte base index fields byte. (Case Figure page shows example this). Instructions without ModRM: field opcode. (Case Figure page shows example this). 64-bit mode, bits needed extend each field accessing additional registers provided prefixes, shown Figure Figure 1-5. details opcode encoding, Appendix "Opcode Operand Encodings."
Displacement Bytes
displacement (also called offset) signed value that added base code segment (absolute addressing) instruction pointer (relative addressing), depending addressing mode. size displacement bytes. addressing mode requires displacement, bytes displacement follow opcode, ModRM, byte (whichever comes last) instruction encoding.
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64-bit mode, same ModRM encodings used specify displacement sizes those used legacy compatibility modes. However, displacement signextended bits during effective-address calculations. Also, displacement immediate forms instruction. "Immediate Operand Size" Volume more information this.
Immediate Bytes
immediate value-typically operand value-encoded directly into instruction. Depending opcode operating mode, size immediate operand bytes. Immediate operands 64-bit mode limited these same sizes. 64-bit mode, support provided some 64-bit displacement immediate forms instruction. "Immediate Operand Size" Volume more information this. instruction takes immediate operand, bytes immediate follow opcode, ModRM, SIB, displacement bytes (whichever come last) instruction encoding. Some 128-bit media instructions immediate byte condition code.
RIP-Relative Addressing
64-bit mode, addressing relative contents 64-bit instruction pointer (program counter)-called RIP-relative addressing PC-relative addressing-is implemented certain instructions. such cases, effective address formed adding displacement 64-bit next instruction. legacy architecture, addressing relative instruction pointer available only control-transfer instructions. 64-bit mode, instruction that uses ModRM addressing RIP-relative addressing. This feature particularly useful addressing data positionindependent code code that addresses global data. Without RIP-relative addressing, ModRM instructions address memory relative zero. With RIP-relative addressing, ModRM
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instructions address memory relative 64-bit using signed 32-bit displacement. This provides offset range Gbytes from RIP. Programs usually have many references data, especially global data, that register-based. load such program, loader typically selects location program memory then adjusts program references global data based load location. RIP-relative addressing data makes this adjustment unnecessary. 1.7.1 Encoding Table 1-13 shows ModRM encodings RIPrelative addressing. Redundant forms 32-bit displacementonly addressing exist current ModRM encodings. There ModRM encoding with several encodings. RIPrelative addressing encoded using redundant forms. 64-bit mode, ModRM Disp32 (32-bit displacement) displacement-only.
Table 1-13.
Encoding RIP-Relative Addressing
Meaning Legacy Compatibility Modes Meaning 64-bit Mode Additional 64-bit Implications Zero-based (normal) displacement addressing must form (see next row).
ModRM Encodings ModRM Byte: (none) Byte: base (none) index (none) scale
Disp32
Disp32
Disp32
Same Legacy
None
1.7.2 Prefix RIP-Relative Addressing
ModRM encoding RIP-relative addressing does depend prefix. particular, encoding 101, used select RIP-relative addressing, affected prefix. example, selecting (REX.B 101) with still results RIP-relative addressing. four-bit field ModRM fully decoded. Therefore, order address with displacement, software must encode using one-byte displacement zero.
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1.7.3 Address-Size Prefix RIPRelative Addressing
RIP-relative addressing enabled 64-bit mode, 64bit address-size. Conversely, address-size prefix ("Address-Size Override Prefix" page does disable RIP-relative addressing. effect address-size prefix truncate zero-extend computed effective address bits, like other addressing mode.
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Instruction Overview
Instruction Subsets
easier reference, instruction descriptions divided into five instruction subsets. following sections describe function, mnemonic syntax, opcodes, affected flags, possible exceptions generated instructions AMD64 architecture: Chapter "General-Purpose Instruction Reference"-The general-purpose instructions used basic software execution. Most these load, store, operate data general-purpose registers (GPRs), memory, both. Other instructions used alter sequential program flow branching other locations within program entirely different programs. Chapter "System Instruction Reference"-The system instructions establish processor operating mode, access processor resources, handle program system errors, manage memory. "128-Bit Media Instruction Reference" Volume 4-The 128bit media instructions load, store, operate data located 128-bit registers. These instructions define both vector scalar operations floating-point integer data types. They include SSE2 instructions that operate registers. Some these instructions convert source operands registers destination operands GPR, MMX, registers otherwise affect state. "64-Bit Media Instruction Reference" Volume 5-The 64-bit media instructions load, store, operate data located 64-bit registers. These instructions define both vector scalar operations integer floating-point data types. They include legacy MMXinstructions, 3DNow!instructions, extensions 3DNow! instruction sets. Some these instructions convert source operands registers destination operands GPR, XMM, registers otherwise affect state.
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"x87 Floating-Point Instruction Reference" Volume 5-The instructions used legacy floating-point applications. Most these instructions load, store, operate data located ST(0)-ST(7) stack registers (the FPR0-FPR7 physical registers). remaining instructions within this category used manage floating-point environment. description each instruction covers behavior operating modes, including legacy mode (real, virtual-8086, protected modes) long mode (compatibility 64-bit modes). Details certain kinds complex behavior-such control-flow changes CALL, INT, FXSAVE instructions- have cross-references instruction-detail pages detailed descriptions volumes instructions-CMPSD MOVSD-use same mnemonic different instructions. Assemblers distinguish them basis number type operands with which they used.
Reference-Page Format
Figure page shows format instruction-detail page. instruction mnemonic shown bold top-left, along with name. this example, POPFD mnemonic EFLAGS Doubleword name. Next, there general description instruction's operation. Many descriptions have cross-references more detail other parts manual. Beneath general description, mnemonic shown again, together with related opcode(s) description summary. Related instructions listed below this, followed table showing flags that instruction affect. Finally, each instruction summary possible exceptions that occur when executing instruction. columns labeled "Real" "Virtual-8086" apply only execution legacy mode. column labeled "Protected" applies both legacy mode long mode, because long mode superset legacy protected mode. 128-bit 64-bit media instructions also have diagrams illustrating operation. instructions have examples pseudocode describing action.
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Mnemonic operands
Opcode
Description operation
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ASCII Adjust After Multiply
Converts value register from binary unpacked digits (most significant) (least significant) registers using following formula:
(AL/10d) 10d).
most modern assemblers, instruction adjusts base-10 values. However, coding instruction directly binary, adjust base specified immediate byte value (ib) suffixed onto opcode. example, code D408h octal, D40Ah decimal, D40Ch duodecimal (base 12). Using this instruction 64-bit mode generates invalid-opcode exception.
Mnemonic
Opcode
Description
(None)
Create pair unpacked values (Invalid 64-bit mode.) Create pair unpacked values immediate byte base. (Invalid 64-bit mode.)
Related Instructions AAA, AAD, rFLAGS Affected
IOPL 13-12
means flag either cleared, depending result.
Note: Bits 31-22, reserved. flag cleared Unaffected flags blank. Undefined flags
Exceptions
Exception Divide zero, Invalid opcode, Virtual Real 8086 Protected Cause Exception 8-bit immediate value This instruction executed 64-bit mode.
Possible exceptions causes, mode operation
"Protected" column covers both legacy long mode
Alphabetic mnemonic locator
Figure 2-1.
Format Instruction-Detail Pages
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Summary Registers Data Types
This section summarizes registers available software using five instruction subsets described "Instruction Subsets" page details organization these registers, their respective chapters volumes
2.3.1 General-Purpose Instructions
Registers. size number general-purpose registers (GPRs) depends operating mode, size flags instruction-pointer registers. Figure shows registers available legacy compatibility modes.
register encoding
high 8-bit
8-bit
16-bit
32-bit
FLAGS
FLAGS EFLAGS
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Figure 2-2.
General Registers Legacy Compatibility Modes
Figure page shows registers accessible 64-bit mode. Compared with legacy mode, registers become bits wide, eight data registers (R8-R15) added byte GPRs available byte operations, four high-byte registers legacy mode (AH, available prefix used. high bits Chapter Instruction Overview
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doubleword operands zero-extended bits, high bits word byte operands modified operations 64-bit mode. RFLAGS register bits wide, high bits reserved. They written with anything they read zeros (RAZ).
modified 8-bit operands modified 16-bit operands register encoding
zero-extended 32-bit operands
8-bit SIL** DIL** BPL** SPL** R10B R11B R12B R13B R14B R15B
16-bit R10W R11W R12W R13W R14W R15W
32-bit R10D R11D R12D R13D R14D R15D
64-bit
RFLAGS
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addressable when prefix used. Only addressable when prefix used.
Figure 2-3. Chapter Instruction Overview
General Registers 64-Bit Mode
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most instructions running 64-bit mode, access extended GPRs requires instruction prefix (page 14). Figure shows segment registers which, like instruction pointer, used instructions. legacy compatibility modes, segments accessible. 64-bit mode, which uses flat (non-segmented) memory model, only segments recognized, whereas contents segment registers ignored (the base each these segments assumed zero, neither their segment limit attributes checked). details, "Segmented Virtual Memory" Volume
Legacy Mode Compatibility Mode
64-Bit Mode
(Attributes only)
ignored ignored
(Base only)
(Base only)
ignored
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Figure 2-4.
Segment Registers
Data Types. Figure page shows general-purpose data types. They scalar, integer data types. 64-bit (quadword) data types only available 64-bit mode, most instructions they require instruction prefix.
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Signed Integer bytes (64-bit mode only)
Double Quadword bytes (64-bit mode only)
Quadword Doubleword bytes
bytes
Word Byte
Unsigned Integer
bytes (64-bit mode only) bytes (64-bit mode only)
Double Quadword Quadword Doubleword bytes Word Byte Packed Digit
bytes
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Figure 2-5. 2.3.2 System Instructions
General-Purpose Data Types Registers. system instructions several specialized registers shown Figure page System software uses these registers among other things, manage processor's operating environment, define system resource characteristics, monitor software execution. With exception RFLAGS register, system registers read written only from privileged software. system registers bits wide, except descriptortable registers task register, which include 64-bit baseaddress fields other fields.
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Control Registers
Extended-Feature-Enable Register EFER System-Configuration Register SYSCFG System-Linkage Registers
Memory-Typing Registers MTRRcap MTRRdefType MTRRphysBasen MTRRphysMaskn MTRRfixn TOP_MEM TOP_MEM2 Performance-Monitoring Registers PerfEvtSeln PerfCtrn Machine-Check Registers MCG_CAP MCG_STAT MCG_CTL MCi_CTL MCi_STATUS MCi_ADDR MCi_MISC
System-Flags Register RFLAGS
STAR LSTAR CSTAR SFMASK FS.base GS.base KernelGSbase SYSENTER_CS SYSENTER_ESP SYSENTER_EIP Debug-Extension Registers
Debug Registers
Descriptor-Table Registers GDTR IDTR LDTR
DebugCtlMSR LastBranchFromIP LastBranchToIP LastIntFromIP LastIntToIP
Task Register
Model-Specific Registers
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Figure 2-6.
System Registers Data Structures. Figure page shows system data structures. These created maintained system software protected mode. processor running protected mode uses these data structures manage memory protection, store program-state information when interrupt task switch occurs.
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Segment Descriptors (Contained Descriptor Tables) Code Stack Data Gate Task-State Segment Local-Descriptor Table
Task-State Segment
Descriptor Tables Global-Descriptor Table
Descriptor Descriptor
Interrupt-Descriptor Table
Gate Descriptor Gate Descriptor
Local-Descriptor Table
Descriptor Descriptor
Descriptor
Gate Descriptor
Descriptor
Page-Translation Tables Page-Map Level-4 Page-Directory Pointer Page Directory Page Table
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Figure 2-7. System Data Structures 2.3.3 128-Bit Media Instructions Registers. 128-bit media instructions 128-bit registers. number available data registers depends operating mode, shown Figure page legacy compatibility modes, eight legacy data registers (XMM0-XMM7) available. 64-bit mode, eight additional data registers (XMM8-XMM15) available when instruction prefix used. MXCSR register contains floating-point other control status flags used 128-bit media instructions. Some 128-bit media instructions also (Figure Chapter Instruction Overview
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Figure 2-3) registers (Figure 2-10 page clear flags rFLAGS register (see Figure Figure 2-3).
Data Registers
xmm0 xmm1 xmm2 xmm3 xmm4 xmm5 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11 xmm12 xmm13 xmm14 xmm15
Available modes Available only 64-bit mode
128-Bit Media Control Status Register
MXCSR
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Figure 2-8.
128-Bit Media Registers Data Types. Figure page shows 128-bit media data types. They include floating-point integer vectors floating-point scalars. floating-point data types include IEEE-754 single precision double precision types.
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Vector (Packed) Floating-Point Double Precision Single Precision
significand significand
significand significand
significand
significand
Vector (Packed) Signed Integer Quadword, Doubleword, Word, Byte
quadword doubleword word byte
quadword doubleword word byte
doubleword word byte
doubleword word byte
word byte
word byte
word byte
word byte
byte
byte
byte
byte
byte
byte
byte
byte
Vector (Packed) Unsigned Integer Quadword, Doubleword, Word, Byte quadword doubleword word byte
quadword doubleword word word byte
doubleword word byte
doubleword word byte
word byte
word byte
word byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
Scalar Floating-Point Double Precision Single Precision
significand
significand
Scalar Unsigned Integers
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double quadword quadword doubleword word byte
Figure 2-9.
128-Bit Media Data Types
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2.3.4 64-Bit Media Instructions
Registers. 64-bit media instructions eight 64-bit registers, shown Figure 2-10. These registers mapped onto floating-point registers, 64-bit media instructions write word that prevents instruction from using data. Some 64-bit media instructions also (Figure Figure 2-3) registers (Figure 2-8).
Data Registers
mmx0 mmx1 mmx2 mmx3 mmx4 mmx5 mmx6 mmx7
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Figure 2-10.
64-Bit Media Registers
Data Types. Figure 2-11 page shows 64-bit media data types. They include floating-point integer vectors integer scalars. floating-point data type, used 3DNow! instructions, consists packed vector IEEE-754 32-bit single-precision data types. Unlike other kinds floating-point instructions, however, 3DNow!instructions generate floating-point exceptions. this reason, there register reporting controlling status exceptions 64-bit-media instruction subset.
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Vector (Packed) Single-Precision Floating-Point
significand
significand
Vector (Packed) Signed Integers
doubleword word byte
doubleword word byte
word byte
word byte
byte
byte
byte
byte
Vector (Packed) Unsigned Integers doubleword word byte
doubleword word byte
word byte
word byte
byte
byte
byte
byte
Signed Integers
quadword
doubleword
word
byte
Unsigned Integers quadword
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doubleword word byte
Figure 2-11. 64-Bit Media Data Types
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2.3.5 FloatingPoint Instructions
Registers. floating-point instructions registers shown Figure 2-12. There eight 80-bit data registers, three 16-bit registers that hold control word, status word, word, three registers (last instruction pointer, last opcode, last data pointer) that hold information about last operation. physical data registers named FPR0-FPR7, although software references these registers stack registers, named ST(0)-ST(7). instructions store operands only their 80-bit floating-point registers memory. They access registers.
Data Registers
fpr0 fpr1 fpr2 fpr3 fpr4 fpr5 fpr6 fpr7
Instruction Pointer (rIP) Data Pointer (rDP)
Control Word Control Word Status Word Status Word Opcode
Word Word
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Figure 2-12.
Registers
Data Types. Figure 2-13 page shows data types. They include three floating-point formats (80-bit double-extended precision, 64-bit double precision, 32-bit single precision), three signed-integer formats (quadword, doubleword,
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word), 80-bit packed binary-coded decimal (BCD) format.
Floating-Point
significand
Double-Extended Precision Double Precision significand
significand
Single Precision
Signed Integer
bytes
Quadword bytes
Doubleword bytes
Word
Binary-Coded Decimal (BCD)
Packed Decimal
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Figure 2-13.
Data Types
Summary Exceptions
Table page lists possible exceptions. table shows interrupt-vector numbers, names, mnemonics, source, possible causes. Exceptions that apply specific instructions documented with each instruction instruction-detail pages that follow.
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Table 2-1.
Vector 20-31 0-255 0-255
Interrupt-Vector Source Cause
Interrupt (Exception) Divide-By-Zero-Error Debug Non-Maskable-Interrupt Breakpoint Overflow Bound-Range Invalid-Opcode Device-Not-Available Double-Fault Coprocessor-Segment-Overrun Invalid-TSS Segment-Not-Present Stack General-Protection Page-Fault Reserved Floating-Point Exception-Pending Alignment-Check Machine-Check SIMD Floating-Point Reserved (Internal External) External Interrupts (Maskable) Software Interrupts #INTR External Software Software Internal Internal External Internal Mnemonic #NMI Source Software Internal External Software Software Software Internal Internal Internal External Internal Internal Internal Internal Internal Cause DIV, IDIV, instructions Instruction accesses data accesses External signal INT3 instruction INTO instruction BOUND instruction Invalid instructions instructions Interrupt during interrupt Unsupported (reserved) Task-state segment access task switch Segment access through descriptor register loads stack references Memory accesses protection checks Memory accesses when paging enabled floating-point 64-bit media floating-point instructions Memory accesses Model specific 128-bit media floating-point instructions External interrupt signal INTn instruction
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Notation
Each instruction syntax that includes mnemonic operands that instruction take. Figure 2-14 shows example syntax which instruction takes operands. most instructions that take operands, first (left-most) operand both source operand (the first source operand) destination operand. second (right-most) operand serves only source, destination.
ADDPD xmm1, xmm2/mem128
2.5.1 Mnemonic Syntax
Mnemonic First Source Operand Destination Operand Second Source Operand
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Figure 2-14.
Syntax Typical Two-Operand Instruction
following notation used denote size type source destination operands: cReg-Control register. dReg-Debug register. imm8-Byte (8-bit) immediate. imm16-Word (16-bit) immediate. imm16/32-Word (16-bit) doubleword (32-bit) immediate. imm32-Doubleword (32-bit) immediate. imm32/64-Doubleword (32-bit) quadword (64-bit) immediate. imm64-Quadword (64-bit) immediate. mem-An operand unspecified size memory. mem8-Byte (8-bit) operand memory. mem16-Word (16-bit) operand memory. mem16/32-Word (16-bit) doubleword (32-bit) operand memory. mem32-Doubleword (32-bit) operand memory. Chapter Instruction Overview
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mem32/48-Doubleword (32-bit) 48-bit operand memory. mem48-48-bit operand memory. mem64-Quadword (64-bit) operand memory. mem128-Double quadword (128-bit) operand memory. mem16:16-Two sequential word (16-bit) operands memory. mem16:32-A doubleword (32-bit) operand followed word (16-bit) operand memory. mem32real-Single-precision (32-bit) floating-point operand memory. mem32int-Doubleword (32-bit) integer operand memory. mem64real-Double-precision (64-bit) floating-point operand memory. mem64int-Quadword (64-bit) integer operand memory. (80-bit) floatingpoint operand memory. mem80dec-80-bit packed operand memory, containing 4-bit digits. mem2env-16-bit control word status word. mem14/28env-14-byte 28-byte environment. environment consists control word, status word, word, last non-control instruction pointer, last data pointer, opcode last non-control instruction completed. mem94/108env-94-byte 108-byte environment register stack. mem512env-512-byte environment 128-bit media, 64-bit media, instructions. mmx-Quadword (64-bit) operand register. mmx1-Quadword (64-bit) operand register, specified left-most (first) operand instruction syntax. mmx2-Quadword (64-bit) operand register, specified right-most (second) operand instruction syntax. mmx/mem32-Doubleword (32-bit) operand register memory. Chapter Instruction Overview
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mmx/mem64-Quadword (64-bit) operand register memory. mmx1/mem64-Quadword (64-bit) operand register memory, specified left-most (first) operand instruction syntax. mmx2/mem64-Quadword (64-bit) operand register memory, specified right-most (second) operand instruction syntax. moffset-Direct memory offset that specifies operand memory. moffset8-Direct memory offset that specifies byte (8-bit) operand memory. moffset16-Direct memory offset that specifies word (16bit) operand memory. moffset32-Direct memory offset that specifies doubleword (32-bit) operand memory. moffset64-Direct memory offset that specifies quadword (64-bit) operand memory. pntr16:16-Far pointer with 16-bit selector 16-bit offset. pntr16:32-Far pointer with 16-bit selector 32-bit offset. reg-Operand unspecified size register. reg8-Byte (8-bit) operand register. reg16-Word (16-bit) operand register. reg16/32-Word (16-bit) doubleword (32-bit) operand register. reg32-Doubleword (32-bit) operand register. reg64-Quadword (64-bit) operand register. reg/mem8-Byte (8-bit) operand register memory. reg/mem16-Word (16-bit) operand register memory. reg/mem32-Doubleword (32-bit) operand register memory. reg/mem64-Quadword (64-bit) operand register memory. rel8off-Signed 8-bit offset relative instruction pointer.
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rel16off-Signed 16-bit offset relative instruction pointer. rel32off-Signed 32-bit offset relative instruction pointer. segReg sReg-Word (16-bit) operand segment register. ST(0)-x87 stack register ST(i)-x87 stack register where between xmm-Double quadword (128-bit) operand register. xmm1-Double quadword (128-bit) operand register, specified left-most (first) operand instruction syntax. xmm2-Double quadword (128-bit) operand register, specified right-most (second) operand instruction syntax. xmm/mem64-Quadword (64-bit) operand 128-bit register memory. xmm/mem128-Double quadword (128-bit) operand register memory. xmm1/mem128-Double quadword (128-bit) operand register memory, specified left-most (first) operand instruction syntax. xmm2/mem128-Double quadword (128-bit) operand register memory, specified right-most (second) operand instruction syntax. 2.5.2 Opcode Syntax addition notation shown above "Mnemonic Syntax" page following notation indicates size type operands syntax instruction opcode: /digit-Indicates that ModRM byte specifies only register memory (r/m) operand. digit specified ModRM field used instruction-opcode extension. Valid digit values range from /r-Indicates that ModRM byte specifies both register operand reg/mem (register memory) operand. cp-Specifies code-offset value possibly code-segment register value. value following opcode either byte (cb), bytes (cw), four bytes (cd), bytes (cp).
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id-Specifies immediate-operand value. opcode determines whether value signed unsigned. value following opcode, ModRM, byte either byte (ib), bytes (iw), four bytes (id). Word doubleword values start with low-order byte. +rb, +rw, +rd, +rq-Specifies register value that added hexadecimal byte left, forming one-byte opcode. result instruction that operates register specified register code. Valid register-code values shown Table 2-2. m64-Specifies quadword (64-bit) operand memory. +i-Specifies floating-point stack operand, ST(i). value used only with floating-point instructions. added hexadecimal byte left, forming onebyte opcode. Valid values range from Table 2-2. +rb, +rw, +rd, Register Value
REX.B Bit1 Value Prefix Specified Register SPL1 BPL1 SIL1 DIL1
"REX Prefixes" page
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Table 2-2. +rb, +rw, +rd, Register Value (continued)
REX.B Bit1 Value Specified Register R10B R11B R12B R13B R14B R15B R10W R11W R12W R13W R14W R15W R10D R11D R12D R13D R14D R15D
"REX Prefixes" page
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2.5.3 Pseudocode Definitions
Pseudocode examples given actions several complex instructions (for example, "CALL (Near)" pseudocode examples:
Basic Definitions comments start with these double slashes. REAL_MODE (cr0.pe=0) PROTECTED_MODE ((cr0.pe=1) (rflags.vm=0)) VIRTUAL_MODE ((cr0.pe=1) (rflags.vm=1)) LEGACY_MODE (efer.lma=0) LONG_MODE (efer.lma=1) 64BIT_MODE ((efer.lma=1) (cs.L=1) (cs.d=0)) COMPATIBILITY_MODE (efer.lma=1) (cs.L=0) PAGING_ENABLED (cr0.pg=1) ALIGNMENT_CHECK_ENABLED ((cr0.am=1) (eflags.ac=1) current privilege level (0-3) OPERAND_SIZE (depending current code ADDRESS_SIZE (depending current code STACK_SIZE (depending current code old_RIP old_RSP old_RFLAGS old_CS old_DS old_ES old_FS old_GS old_SS RFLAGS next_RIP
(cpl=3)) 66h/rex prefixes) prefixes) SS.attr.B)
start current instruction start current instruction RFLAGS start instruction selector start current instruction selector start current instruction selector start current instruction selector start current instruction selector start current instruction selector start current instruction current register current register current register current RFLAGS register start next instruction current base limit current base limit descriptor, including subfields: attr descriptor, including subfields: attr
DEST temp_*
instruction's Source operand instruction's Destination operand 64-bit temporary register
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temp_*_desc
temporary descriptor, with subfields: points block memory: base limit attr it's gate descriptor: offset segment attr null selector zeros
NULL 0x0000
V,Z,A,S integer variables, assigned value when instruction begins executing (they assigned different value middle instruction, needed) OPERAND_SIZE=16 OPERAND_SIZE=32 OPERAND_SIZE=64 OPERAND_SIZE=16 OPERAND_SIZE=32 OPERAND_SIZE=64 ADDRESS_SIZE=16 ADDRESS_SIZE=32 ADDRESS_SIZE=64 STACK_SIZE=16 STACK_SIZE=32 STACK_SIZE=64
Range Inside Register temp_data.[X:Y] through temp_data, with other bits register masked off.
Moving Data From Register Another temp_dest.b temp_src 1-byte move (copies lower bits temp_src temp_dest, preserving upper bits temp_dest) temp_dest.w temp_src 2-byte move (copies lower bits temp_src temp_dest, preserving upper bits temp_dest) temp_dest.d temp_src 4-byte move (copies lower bits temp_src temp_dest, zeros upper bits temp_dest) temp_dest.q temp_src 8-byte move (copies bits temp_src temp_dest) temp_dest.v temp_src 2-byte move V=2, 4-byte move V=4,
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8-byte move temp_dest.z temp_src 2-byte move Z=2, 4-byte move 2-byte move A=2, 4-byte move A=4, 8-byte move 2-byte move S=2, 4-byte move S=4, 8-byte move
temp_dest.a temp_src
temp_dest.s temp_src
Bitwise Operations temp temp temp temp temp temp
Logical Operations (FOO (FOO (FOO (FOO (FOO (FOO (FOO (FOO BAR) BAR) BAR) BAR) BAR) BAR) BAR) BAR)
IF-THEN-ELSE (FOO) (FOO) ELSIF (BAR)
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ELSE ((FOO BAR) (CONE HEAD))
Exceptions EXCEPTION [#GP(0)] EXCEPTION [#UD] possible exception types: Divide-By-Zero-Error Exception (Vector Debug Exception (Vector INT3 Breakpoint Exception (Vector INTO Overflow Exception (Vector Bound-Range Exception (Vector Invalid-Opcode Exception (Vector Device-Not-Available Exception (Vector Double-Fault Exception (Vector Invalid-TSS Exception (Vector Segment-Not-Present Exception (Vector Stack Exception (Vector General-Protection Exception (Vector Page-Fault Exception (Vector Floating-Point Exception-Pending (Vector Alignment-Check Exception (Vector Machine-Check Exception (Vector SIMD Floating-Point Exception (Vector error code parenthesis error code
READ_MEM General memory read. This zero-extends data bits returns usage: temp READ_MEM.x [seg:offset]
where denotes size memory read
definition: ((seg 0xFFFC) NULL) EXCEPTION [#GP(0)] ((seg=CS) (seg=DS) (seg=ES) (seg=FS) (seg=GS)) fault using null segment reference memory
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CS,DS,ES,FS,GS check segment limit canonical ((!64BIT_MODE) (offset outside seg's limit)) EXCEPTION [#GP(0)] fault segment limit violation non-64-bit mode ((64BIT_MODE) (offset non-canonical)) EXCEPTION [#GP(0)] fault non-canonical address 64-bit mode ELSIF (seg=SS) checks segment limit canonical ((!64BIT_MODE) (offset outside seg's limit)) EXCEPTION [#SS(0)] stack fault segment limit violation non-64-bit mode ((64BIT_MODE) (offset non-canonical)) EXCEPTION [#SS(0)] stack fault non-canonical address 64-bit mode ELSE ((seg=GDT) (seg=LDT) (seg=IDT) (seg=TSS)) GDT,LDT,IDT,TSS check segment limit canonical (offset seg.limit) EXCEPTION [#GP(0)] fault segment limit violation modes ((LONG_MODE) (offset non-canonical)) EXCEPTION [#GP(0)] fault non-canonical address long mode ((ALIGNMENT_CHECK_ENABLED) (offset misaligned, considering size alignment)) EXCEPTION [#AC(0)] ((64_bit_mode) ((seg=CS) (seg=DS) (seg=ES) (seg=SS)) temp_linear offset ELSE temp_linear seg.base offset ((PAGING_ENABLED) (virtual-to-physical translation temp_linear results page-protection violation)) EXCEPTION [#PF(error_code)] page fault page-protection violation (U/S violation, Reserved violation) ((PAGING_ENABLED) (temp_linear not-present page)) EXCEPTION [#PF(error_code)] page fault not-present page temp_data memory [temp_linear].x zero-extends data bits, saves temp_data return zero-extended data
RETURN (temp_data)
WRITE_MEM General memory write usage: WRITE_MEM.x [seg:offset] temp.x
where these:
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denotes size memory write definition: ((seg 0xFFFC)= NULL) EXCEPTION [#GP(0)] (seg isn't writable) EXCEPTION [#GP(0)] fault writing read-only segment fault using null segment reference memory
((seg=CS) (seg=DS) (seg=ES) (seg=FS) (seg=GS)) CS,DS,ES,FS,GS check segment limit canonical ((!64BIT_MODE) (offset outside seg's limit)) EXCEPTION [#GP(0)] fault segment limit violation non-64-bit mode ((64BIT_MODE) (offset non-canonical)) EXCEPTION [#GP(0)] fault non-canonical address 64-bit mode ELSIF (seg=SS) checks segment limit canonical ((!64BIT_MODE) (offset outside seg's limit)) EXCEPTION [#SS(0)] stack fault segment limit violation non-64-bit mode ((64BIT_MODE) (offset non-canonical)) EXCEPTION [#SS(0)] stack fault non-canonical address 64-bit mode ELSE ((seg=GDT) (seg=LDT) (seg=IDT) (seg=TSS)) GDT,LDT,IDT,TSS check segment limit canonical (offset seg.limit) EXCEPTION [#GP(0)] fault segment limit violation modes ((LONG_MODE) (offset non-canonical)) EXCEPTION [#GP(0)] fault non-canonical address long mode ((ALIGNMENT_CHECK_ENABLED) (offset misaligned, considering size alignment)) EXCEPTION [#AC(0)] ((64_bit_mode) ((seg=CS) (seg=DS) (seg=ES) (seg=SS)) temp_linear offset ELSE temp_linear seg.base offset ((PAGING_ENABLED) (the virtual-to-physical translation temp_linear results page-protection violation)) EXCEPTION [#PF(error_code)] page fault page-protection violation (U/S violation, Reserved violation)
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((PAGING_ENABLED) (temp_linear not-present page)) EXCEPTION [#PF(error_code)] page fault not-present page memory [temp_linear].x temp.x write bytes memory
PUSH Write data stack usage: PUSH.x temp
where these: denotes size push
definition: WRITE_MEM.x [SS:RSP.s temp.x RSP.s write stack point data just written
Read data from stack, zero-extend bits usage: POP.x temp
where these: denotes size
definition: temp READ_MEM.x [SS:RSP.s] RSP.s read from stack point above data just written
READ_DESCRIPTOR Read 8-byte descriptor from GDT/LDT, return descriptor usage: temp_descriptor READ_DESCRIPTOR (selector, chktype) chktype field following: cs_chk used call jump clg_chk used when reading call jump through call gate ss_chk used when reading iret_chk used when reading IRET RETF intcs_chk used when readin interrupts exceptions definition:
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temp_offset selector 0xfff8
upper bits give offset descriptor table
(selector.TI
read bytes from gdt, split into (base,limit,attr) type bits temp_desc READ_MEM.q [gdt:temp_offset] indicate block memory, split into (segment,offset,attr) type bits indicate gate, save result temp_desc temp_desc READ_MEM.q [ldt:temp_offset] read bytes from ldt, split into (base,limit,attr) type bits indicate block memory, split into (segment,offset,attr) type bits indicate gate, save result temp_desc
ELSE
(selector.rpl temp_desc.attr.dpl illegal current mode/cpl) EXCEPTION [#GP(selector)] (temp_desc.attr.type illegal current mode/chktype) EXCEPTION [#GP(selector)] (temp_desc.attr.p=0) EXCEPTION [#NP(selector)] RETURN (temp_desc)
READ_IDT Read 8-byte descriptor from IDT, return descriptor usage: temp_idt_desc READ_IDT (vector) "vector" interrupt vector number definition: (LONG_MODE) long-mode descriptors bytes long temp_offset vector*16 ELSE (LEGACY_MODE) legacy-protected-mode descriptors bytes long temp_offset vector*8 temp_desc READ_MEM.q [idt:temp_offset] read bytes from idt, split into (segment,offset,attr), save temp_desc (temp_desc.attr.dpl illegal current mode/cpl)
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exception, with error code that indicates this gate EXCEPTION [#GP(vector*8+2)] (temp_desc.attr.type illegal current mode) exception, with error code that indicates this gate EXCEPTION [#GP(vector*8+2)] (temp_desc.attr.p=0) EXCEPTION [#NP(vector*8+2)] segment-not-present exception, with error code that indicates this gate RETURN (temp_desc)
READ_INNER_LEVEL_STACK_POINTER Read stack pointer (rsp ss:esp) from usage: temp_SS_desc:temp_RSP READ_INNER_LEVEL_STACK_POINTER (new_cpl, ist_index) definition: (LONG_MODE) (ist_index>0) selected, read ISTn stack pointer from temp_RSP READ_MEM.q [tss:ist_index*8+28] ELSE (ist_index=0) otherwise read RSPn stack pointer from temp_RSP READ_MEM.q [tss:new_cpl*8+4] temp_SS_desc.sel NULL new_cpl long mode, changing lower sets SS.sel NULL+new_cpl ELSE (LEGACY_MODE) temp_RSP READ_MEM.d [tss:new_cpl*8+4] read ESPn from temp_sel READ_MEM.d [tss:new_cpl*8+8] read from temp_SS_desc READ_DESCRIPTOR (temp_sel, ss_chk) return (temp_RSP:temp_SS_desc)
READ_BIT_ARRAY Read from array memory
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usage: temp_value READ_BIT_ARRAY ([mem], bit_number) definition: temp_BYTE READ_MEM.b [mem (bit_number read byte containing temp_BIT temp_BYTE (bit_number shift requested position into return (temp_BIT 0x01) return
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General-Purpose Instruction Reference
This chapter describes function, mnemonic syntax, opcodes, affected flags, possible exceptions generated general-purpose instructions. General-purpose instructions used basic software execution. Most these instructions load, store, operate data located general-purpose registers (GPRs), memory, both. remaining instructions used alter sequential flow program branching other locations within program, entirely different programs. With exception MOVD, MOVMSKPD MOVMSKPS instructions, which operate MMX/XMM registers, instructions within category general-purpose instructions operate other register set. Most general-purpose instructions supported hardware implementations AMD64 architecture. following general-purpose instructions implemented only their associated CPUID function set: CMPXCHG8B, indicated CPUID standard function extended function 8000_0001h. CMOVcc (conditional moves), indicated CPUID standard function extended function 8000_0001h. CLFLUSH, indicated CPUID standard function PREFETCH, indicated CPUID extended function 8000_0001h. MOVD, indicated bits (MMXTM) (XMM) CPUID standard function MOVNTI, indicated CPUID standard function SFENCE, indicated CPUID standard function MFENCE, LFENCE, indicated CPUID standard function Long Mode instructions, indicated CPUID extended function 8000_0001h. general-purpose instructions used legacy mode 64-bit long mode. Compilation general-purpose programs execution 64-bit long mode offers three primary advantages: access eight extended, 64-bit general-purpose registers
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(for register consisting GPR0-GPR15), access 64bit virtual address space, access RIP-relative addressing mode. further information about general-purpose instructions register resources, see: "General-Purpose Programming" Volume "Summary Registers Data Types" page "Notation" page "Instruction Prefixes" page Appendix "General-Purpose Instructions 64-Bit Mode." particular, "General Rules 64-Bit Mode" page 405.
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ASCII Adjust After Addition
Adjusts value register unpacked value. instruction after using instruction unpacked numbers. value lower nibble greater than flag instruction increments register, adds register, sets flags Otherwise, does change register clears flags either case, clears bits register, leaving correct decimal digit bits 3-0. This instruction also makes possible ASCII numbers without having mask upper nibble `3'. Using this instruction 64-bit mode generates invalid-opcode exception.
Mnemonic
Opcode
Description
Create unpacked number. (Invalid 64-bit mode.)
Related Instructions AAD, AAM, rFLAGS Affected
IOPL 13-12
Note: Bits 31-22, reserved. flag cleared (modified). Unaffected flags blank. Undefined flags
Exceptions
Exception Invalid opcode, Virtual Real 8086 Protected Cause Exception This instruction executed 64-bit mode.
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ASCII Adjust Before Division
Converts unpacked digits (least significant) (most significant) registers single binary value register using following formula:
((10d (AL))
After conversion, cleared 00h. most modern assemblers, instruction adjusts from base-10 values. However, coding instruction directly binary, adjust from base specified immediate byte value (ib) suffixed onto opcode. example, code D508h octal, D50Ah decimal, D50Ch duodecimal (base 12). Using this instruction 64-bit mode generates invalid-opcode exception.
Mnemonic
Opcode
Description
(None)
Adjust digits (Invalid 64-bit mode.) Adjust digits immediate byte base. (Invalid 64-bit mode.)
Related Instructions AAA, AAM, rFLAGS Affected
IOPL 13-12
Note: Bits 31-22, reserved. flag cleared (modified). Unaffected flags blank. Undefined flags
Exceptions
Exception Invalid opcode, Virtual Real 8086 Protected Cause Exception This instruction executed 64-bit mode.
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ASCII Adjust After Multiply
Converts value register from binary unpacked digits (most significant) (least significant) registers using following formula:
(AL/10d) 10d).
most modern assemblers, instruction adjusts base-10 values. However, coding instruction directly binary, adjust base specified immediate byte value (ib) suffixed onto opcode. example, code D408h octal, D40Ah decimal, D40Ch duodecimal (base 12). Using this instruction 64-bit mode generates invalid-opcode exception.
Mnemonic
Opcode
Description
(None)
Create pair unpacked values (Invalid 64-bit mode.) Create pair unpacked values immediate byte base. (Invalid 64-bit mode.)
Related Instructions AAA, AAD, rFLAGS Affected
IOPL 13-12
Note: Bits 31-22, reserved. flag cleared Unaffected flags blank. Undefined flags
Exceptions
Exception Divide zero, Invalid opcode, Virtual Real 8086 Protected Cause Exception 8-bit immediate value This instruction executed 64-bit mode.
AMD64 Technology
24594
Rev. 3.09
September 2003
ASCII Adjust After Subtraction
Adjusts value register unpacked value. instruction after using instruction subtract unpacked numbers. value greater than flag instruction decrements value subtracts from register, sets flags Otherwise, clears flags register unchanged. either case, instruction clears bits register, leaving correct decimal digit bits 3-0. Using this instruction 64-bit mode generates invalid-opcode exception.
Mnemonic
Opcode
Description
Create unpacked number from contents register. (Invalid 64-bit mode.)
Related Instructions AAA, AAD, rFLAGS Affected
IOPL 13-12
Note: Bits 31-22, reserved. flag cleared (modified). Unaffected flags blank. Undefined flags
Exceptions
Exception Invalid opcode, Virtual Real 8086 Protected Cause Exception This instruction executed 64-bit mode.
24594 Rev. 3.09 September 2003
AMD64 Technology
with Carry
Adds carry flag (CF), value register memory location (first operand), immediate value value register memory location (second operand), stores result first operand location. instruction cannot memory operands. flag indicates pending carry from previous addition operation. instruction sign-extends immediate value length destination register memory location. This instruction evaluates result both signed unsigned data types sets flags indicate carry signed unsigned result, respectively. sets flag indicate sign signed result. instruction after instruction part multibyte multiword addition. forms instruction that write memory support LOCK prefix. details about LOCK prefix, "Lock Prefix" page
Mnemonic
Opcode
Description
imm8 imm16 EAX, imm32 RAX, imm32 reg/mem8, imm8 reg/mem16, imm16 reg/mem32, imm32 reg/mem64, imm32 reg/mem16, imm8 reg/mem32, imm8 reg/mem64, imm8 reg/mem8, reg8 reg/mem16, reg16 reg/mem32, reg32
imm8 imm16 imm32 sign-extended imm32 imm8 reg/mem8 imm16 reg/mem16 imm32 reg/mem32 sign-extended imm32 reg/mem64 sign-extended imm8 reg/mem16 sign-extended imm8 reg/mem32 sign-extended imm8 reg/mem64 reg8 reg/mem8 reg16 reg/mem16 reg32 reg/mem32
AMD64 Technology
24594
Rev. 3.09
September 2003
Mnemonic
Opcode
Description
reg/mem64, reg64 reg8, reg/mem8 reg16, reg/mem16 reg32, reg/mem32 reg64, reg/mem64
reg64 reg/mem64 reg/mem8 reg8 reg/mem16 reg16 reg/mem32 reg32 reg/mem64 reg64
Related Instructions ADD, SBB, rFLAGS Affected
IOPL 13-12
Note: Bits 31-22, reserved. flag cleared (modified). Unaffected flags blank. Undefined flags
Exceptions
Exception Stack, General protection, Virtual Real 8086 Protected Cause Exception memory address exceeded stack segment limit noncanonical. memory address exceeded data segment limit noncanonical. destination operand non-writable segment. null data segment used reference memory. page fault resulted from execution instruction. unaligned memory reference performed while alignment checking enabled.
Page fault, Alignment check,
24594 Rev. 3.09 September 2003
AMD64 Technology
Signed Unsigned
Adds value register memory location (first operand) immediate value value register memory location (second operand), stores result first operand location. instruction cannot memory operands. instruction sign-extends immediate value length destination register memory operand. This instruction evaluates result both signed unsigned data types sets flags indicate carry signed unsigned result, respectively. sets flag indicate sign signed result. forms instruction that write memory support LOCK prefix. details about LOCK prefix, "Lock Prefix" page
Mnemonic
Opcode
Description
imm8 imm16 EAX, imm32 RAX, imm32 reg/mem8, imm8 reg/mem16, imm16 reg/mem32, imm32 reg/mem64, imm32 reg/mem16, imm8 reg/mem32, imm8 reg/mem64, imm8 reg/mem8, reg8 reg/mem16, reg16 reg/mem32, reg32 reg/mem64, reg64 reg8, reg/mem8
imm8 imm16 imm32 EAX. sign-extended imm32 RAX. imm8 reg/mem8. imm16 reg/mem16 imm32 reg/mem32. sign-extended imm32 reg/mem64. sign-extended imm8 reg/mem16 sign-extended imm8 reg/mem32. sign-extended imm8 reg/mem64. reg8 reg/mem8. reg16 reg/mem16. reg32 reg/mem32. reg64 reg/mem64. reg/mem8 reg8.
AMD64 Technology
24594
Rev. 3.09
September 2003
Mnemonic
Opcode
Description
reg16, reg/mem16 reg32, reg/mem32 reg64, reg/mem64
reg/mem16 reg16. reg/mem32 reg32. reg/mem64 reg64.
Related Instructions ADC, SBB, rFLAGS Affected
IOPL 13-12
Note: Bits 31-22, reserved. flag cleared (modified). Unaffected flags blank. Undefined flags
Exceptions
Exception Stack, General protection, Virtual Real 8086 Protected Cause Exception memory address exceeded stack segment limit noncanonical. memory address exceeded data segment limit noncanonical. destination operand non-writable segment. null data segment used reference memory. page fault resulted from execution instruction. unaligned memory reference performed while alignment checking enabled.
Page fault, Alignment check,
24594 Rev. 3.09 September 2003
AMD64 Technology
Logical
Performs bitwise operation value register memory location (first operand) immediate value value register memory location (second operand), stores result first operand location. instruction cannot memory operands. instruction sets each result corresponding both operands set; otherwise, clears following table shows truth table operation:
forms instruction that write memory support LOCK prefix. details about LOCK prefix, "Lock Prefix" page
Mnemonic
Opcode
Description
imm8 imm16 EAX, imm32 RAX, imm32 reg/mem8, imm8 reg/mem16, imm16 reg/mem32, imm32 reg/mem64, imm32
contents with immediate 8-bit value store result contents with immediate 16-bit value store result contents with immediate 32-bit value store result EAX. contents with sign-extended immediate 32-bit value store result RAX. contents reg/mem8 with imm8. contents reg/mem16 with imm16. contents reg/mem32 with imm32. contents reg/mem64 with sign-extended imm32.
AMD64 Technology
24594
Rev. 3.09
September 2003
Mnemonic
Opcode
Description
reg/mem16, imm8 reg/mem32, imm8 reg/mem64, imm8 reg/mem8, reg8 reg/mem16, reg16 reg/mem32, reg32 reg/mem64, reg64 reg8, reg/mem8 reg16, reg/mem16 reg32, reg/mem32 reg64, reg/mem64
contents reg/mem16 with sign-extended 8-bit value. contents reg/mem32 with sign-extended 8-bit value. contents reg/mem64 with sign-extended 8-bit value. contents 8-bit register memory location with contents 8-bit register. contents 16-bit register memory location with contents 16-bit register. contents 32-bit register memory location with contents 32-bit register. contents 64-bit register memory location with contents 64-bit register. contents 8-bit register with contents 8-bit memory location register. contents 16-bit register with contents 16-bit memory location register. contents 32-bit register with contents 32-bit memory location register. contents 64-bit register with contents 64-bit memory location register.
Related Instructions TEST, NOT, NEG, rFLAGS Affected
IOPL 13-12
Note: Bits 31-22, reserved. flag cleared (modified). Unaffected flags blank. Undefined flags
24594 Rev. 3.09 September 2003
AMD64 Technology
Exceptions
Exception Stack, General protection, Virtual Real 8086 Protected Cause Exception memory address exceeded stack segment limit noncanonical. memory address exceeded data segment limit noncanonical. destination operand non-writable segment. null data segment used reference memory. page fault resulted from execution instruction. unaligned memory reference performed while alignment checking enabled.
Page fault, Alignment check,
AMD64 Technology
24594
Rev. 3.09
September 2003
BOUND
Check Array Bounds
Checks whether array index (first operand) within bounds array (second operand). array index signed integer specified register. operand-size attribute array operand memory location containing pair signed word-integers; operand-size attribute array operand pair signed doubleword-integers. first word doubleword specifies lower bound array second word doubleword specifies upper bound. array index must greater than equal lower bound less than equal upper bound. index within specified bounds, processor generates BOUND range-exceeded exception (#BR). bounds array, consisting words doublewords containing lower upper limits array, usually reside data structure just before array itself, making limits addressable through constant offset from beginning array. With address array register, this practice reduces number cycles required determine effective address array bounds. Using this instruction 64-bit mode generates invalid-opcode exception.
Mnemonic
Opcode
Description
BOUND reg16, mem16&mem16
Test whether 16-bit array index within bounds specified 16-bit values mem16&mem16. (Invalid 64-bit mode.) Test whether 32-bit array index within bounds specified 32-bit values mem32&mem32. (Invalid 64-bit mode.)
BOUND reg32, mem32&mem32
Related Instructions INT, INT3, INTO rFLAGS Affected None
BOUND
24594 Rev. 3.09 September 2003
AMD64 Technology
Exceptions
Exception Bound range, Invalid opcode, Virtual Real 8086 Protected Stack, General protection, Page fault, Alignment check, Cause Exception bound range exceeded. source operand register. Instruction executed 64-bit mode. memory address exceeded stack segment limit memory address exceeded data segment limit. null data segment used reference memory. page fault resulted from execution instruction. unaligned memory reference performed while alignment checking enabled.
BOUND
AMD64 Technology
24594
Rev. 3.09
September 2003
Scan Forward
Searches value register memory location (second operand) leastsignificant bit. found, instruction clears zero flag (ZF) stores index least-significant destination register (first operand). second operand contains instruction sets does change contents destination register. index unsigned offset from searched value.
Mnemonic
Opcode
Description
reg16, reg/mem16 reg32, reg/mem32 reg64, reg/mem64
scan forward contents reg/mem16. scan forward contents reg/mem32. scan forward contents reg/mem64
Related Instructions rFLAGS Affected
IOPL 13-12
Note: Bits 31-22, reserved. flag cleared (modified). Unaffected flags blank. Undefined flags
Exceptions
Exception Stack, General protection, Virtual Real 8086 Protected Cause Exception memory address exceeded stack segment limit noncanonical. memory address exceeded data segment limit noncanonical. null data segment used reference memory.
24594 Rev. 3.09 September 2003
AMD64 Technology
Exception Page fault, Alignment check,
Virtual Real 8086 Protected
Cause Exception page fault resulted from execution instruction. unaligned memory reference performed while alignment checking enabled.
AMD64 Technology
24594
Rev. 3.09
September 2003
Scan Reverse
Searches value register memory location (second operand) mostsignificant bit. found, ins
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