Volume Instruction Reference NOTE: IA-32 Intel Architecture Softw
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IA-32 Intel® Architecture Software Developer's Manual
Volume Instruction Reference
NOTE: IA-32 Intel Architecture Software Developer's Manual consists three volumes: Basic Architecture, Order Number 245470; Instruction Reference, Order Number 245471; System Programming Guide, Order Number 245472. Please refer three volumes when evaluating your design needs.
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COPYRIGHT 1997 2001 INTEL CORPORATION
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CHAPTER ABOUT THIS MANUAL 1.1. IA-32 PROCESSORS COVERED THIS MANUAL 1.2. OVERVIEW IA-32 INTEL® ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME INSTRUCTION REFERENCE 1.3. OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME BASIC ARCHITECTURE 1.4. OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME SYSTEM PROGRAMMING GUIDE 1.5. NOTATIONAL CONVENTIONS 1.5.1. Byte Order .1-6 1.5.2. Reserved Bits Software Compatibility .1-6 1.5.3. Instruction Operands .1-7 1.5.4. Hexadecimal Binary Numbers .1-8 1.5.5. Segmented Addressing .1-8 1.5.6. Exceptions .1-8 1.6. RELATED LITERATURE CHAPTER INSTRUCTION FORMAT 2.1. GENERAL INSTRUCTION FORMAT 2.2. INSTRUCTION PREFIXES 2.3. OPCODE 2.4. MODR/M BYTES 2.5. DISPLACEMENT IMMEDIATE BYTES 2.6. ADDRESSING-MODE ENCODING MODR/M BYTES
CHAPTER INSTRUCTION REFERENCE 3.1. INTERPRETING INSTRUCTION REFERENCE PAGES 3.1.1. Instruction Format .3-1 3.1.1.1. Opcode Column .3-1 3.1.1.2. Instruction Column .3-2 3.1.1.3. Description Column .3-5 3.1.1.4. Description .3-5 3.1.2. Operation. .3-5 3.1.3. Intel C/C++ Compiler Intrinsics Equivalents .3-8 3.1.3.1. Intrinsics .3-9 3.1.3.2. MMXTechnology Intrinsics .3-9 3.1.3.3. SSE2 Intrinsics .3-9 3.1.4. Flags Affected .3-11 3.1.5. Flags Affected .3-11 3.1.6. Protected Mode Exceptions. .3-11 3.1.7. Real-Address Mode Exceptions .3-12 3.1.8. Virtual-8086 Mode Exceptions. .3-13 3.1.9. Floating-Point Exceptions .3-13 3.1.10. SIMD Floating-Point Exceptions .3-13 3.2. INSTRUCTION REFERENCE 3-14
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AAA-ASCII Adjust After Addition. .3-15 AAD-ASCII Adjust Before Division .3-16 AAM-ASCII Adjust After Multiply .3-17 AAS-ASCII Adjust After Subtraction .3-18 ADC-Add with Carry .3-19 ADD-Add .3-21 ADDPD-Add Packed Double-Precision Floating-Point Values .3-23 ADDPS-Add Packed Single-Precision Floating-Point Values .3-25 ADDSD-Add Scalar Double-Precision Floating-Point Values .3-27 ADDSS-Add Scalar Single-Precision Floating-Point Values. .3-29 AND-Logical .3-31 ANDPD-Bitwise Logical Packed Double-Precision Floating-Point Values. .3-33 ANDPS-Bitwise Logical Packed Single-Precision Floating-Point Values. .3-35 ANDNPD-Bitwise Logical Packed Double-Precision Floating-Point Values. .3-37 ANDNPS-Bitwise Logical Packed Single-Precision Floating-Point Values. .3-39 ARPL-Adjust Field Segment Selector .3-41 BOUND-Check Array Index Against Bounds .3-43 BSF-Bit Scan Forward .3-45 BSR-Bit Scan Reverse .3-47 BSWAP-Byte Swap. .3-49 BT-Bit Test .3-50 BTC-Bit Test Complement .3-52 BTR-Bit Test Reset .3-54 BTS-Bit Test .3-56 CALL-Call Procedure .3-58 CBW/CWDE-Convert Byte Word/Convert Word Doubleword. .3-69 CDQ-Convert Double Quad .3-70 CLC-Clear Carry Flag .3-71 CLD-Clear Direction Flag .3-72 CLFLUSH-Flush Cache Line. .3-73 CLI-Clear Interrupt Flag .3-75 CLTS-Clear Task-Switched Flag CR0. .3-77 CMC-Complement Carry Flag. .3-78 CMOVcc-Conditional Move. .3-79 CMP-Compare Operands .3-83 CMPPD-Compare Packed Double-Precision Floating-Point Values. .3-85 CMPPS-Compare Packed Single-Precision Floating-Point Values .3-89 CMPS/CMPSB/CMPSW/CMPSD-Compare String Operands .3-93 CMPSD-Compare Scalar Double-Precision Floating-Point Values .3-96 CMPSS-Compare Scalar Single-Precision Floating-Point Values .3-100 CMPXCHG-Compare Exchange .3-104 CMPXCHG8B-Compare Exchange Bytes .3-106
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COMISD-Compare Scalar Ordered Double-Precision Floating-Point Values EFLAGS COMISS-Compare Scalar Ordered Single-Precision Floating-Point Values EFLAGS CPUID-CPU Identification CVTDQ2PD-Convert Packed Doubleword Integers Packed Double-Precision Floating-Point Values. CVTDQ2PS-Convert Packed Doubleword Integers Packed Single-Precision Floating-Point Values CVTPD2DQ-Convert Packed Double-Precision Floating-Point Values Packed Doubleword Integers CVTPD2PI-Convert Packed Double-Precision Floating-Point Values Packed Doubleword Integers CVTPD2PS-Covert Packed Double-Precision Floating-Point Values Packed Single-Precision Floating-Point Values CVTPI2PD-Convert Packed Doubleword Integers Packed Double-Precision Floating-Point Values. CVTPI2PS-Convert Packed Doubleword Integers Packed Single-Precision Floating-Point Values CVTPS2DQ-Convert Packed Single-Precision Floating-Point Values Packed Doubleword Integers CVTPS2PD-Covert Packed Single-Precision Floating-Point Values Packed Double-Precision Floating-Point Values CVTPS2PI-Convert Packed Single-Precision Floating-Point Values Packed Doubleword Integers CVTSD2SI-Convert Scalar Double-Precision Floating-Point Value Doubleword Integer CVTSD2SS-Convert Scalar Double-Precision Floating-Point Value Scalar Single-Precision Floating-Point Value. CVTSI2SD-Convert Doubleword Integer Scalar Double-Precision Floating-Point Value. CVTSI2SS-Convert Doubleword Integer Scalar Single-Precision Floating-Point Value. CVTSS2SD-Convert Scalar Single-Precision Floating-Point Value Scalar Double-Precision Floating-Point Value CVTSS2SI-Convert Scalar Single-Precision Floating-Point Value Doubleword Integer CVTTPD2PI-Convert with Truncation Packed Double-Precision Floating-Point Values Packed Doubleword Integers CVTTPD2DQ-Convert with Truncation Packed Double-Precision Floating-Point Values Packed Doubleword Integers CVTTPS2DQ-Convert with Truncation Packed Single-Precision Floating-Point Values Packed Doubleword Integers CVTTPS2PI-Convert with Truncation Packed Single-Precision Floating-Point Values Packed Doubleword Integers CVTTSD2SI-Convert with Truncation Scalar Double-Precision Floating-Point Value Signed Doubleword Integer
3-108 3-111 3-114 3-128 3-130 3-132 3-134 3-136 3-138 3-140 3-142 3-144 3-146 3-148 3-150 3-152 3-154 3-156 3-158 3-160 3-162 3-164 3-166 3-168
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CVTTSS2SI-Convert with Truncation Scalar Single-Precision Floating-Point Value Doubleword Integer .3-170 CWD/CDQ-Convert Word Doubleword/Convert Doubleword Quadword .3-172 CWDE-Convert Word Doubleword .3-173 DAA-Decimal Adjust after Addition .3-174 DAS-Decimal Adjust after Subtraction. .3-176 DEC-Decrement .3-177 DIV-Unsigned Divide. .3-179 DIVPD-Divide Packed Double-Precision Floating-Point Values .3-182 DIVPS-Divide Packed Single-Precision Floating-Point Values .3-184 DIVSD-Divide Scalar Double-Precision Floating-Point Values .3-186 DIVSS-Divide Scalar Single-Precision Floating-Point Values. .3-188 EMMS-Empty State .3-190 ENTER-Make Stack Frame Procedure Parameters .3-191 F2XM1-Compute 2x-1 .3-194 FABS-Absolute Value .3-196 FADD/FADDP/FIADD-Add .3-198 FBLD-Load Binary Coded Decimal .3-201 FBSTP-Store Integer .3-203 FCHS-Change Sign .3-206 FCLEX/FNCLEX-Clear Exceptions .3-208 FCMOVcc-Floating-Point Conditional Move .3-210 FCOM/FCOMP/FCOMPP-Compare Floating Point Values .3-212 FCOMI/FCOMIP/ FUCOMI/FUCOMIP-Compare Floating Point Values EFLAGS .3-215 FCOS-Cosine .3-218 FDECSTP-Decrement Stack-Top Pointer. .3-220 FDIV/FDIVP/FIDIV-Divide .3-221 FDIVR/FDIVRP/FIDIVR-Reverse Divide. .3-225 FFREE-Free Floating-Point Register .3-229 FICOM/FICOMP-Compare Integer .3-230 FILD-Load Integer .3-232 FINCSTP-Increment Stack-Top Pointer .3-234 FINIT/FNINIT-Initialize Floating-Point Unit .3-235 FIST/FISTP-Store Integer .3-237 FLD-Load Floating Point Value .3-240 Constant .3-242 FLDCW-Load Control Word .3-244 FLDENV-Load Environment. .3-246 FMUL/FMULP/FIMUL-Multiply .3-248 FNOP-No Operation .3-251 FPATAN-Partial Arctangent .3-252 FPREM-Partial Remainder .3-254 FPREM1-Partial Remainder .3-257 FPTAN-Partial Tangent. .3-260 FRNDINT-Round Integer .3-262
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FRSTOR-Restore State FSAVE/FNSAVE-Store State FSCALE-Scale FSIN-Sine FSINCOS-Sine Cosine FSQRT-Square Root FST/FSTP-Store Floating Point Value. FSTCW/FNSTCW-Store Control Word FSTENV/FNSTENV-Store Environment. FSTSW/FNSTSW-Store Status Word FSUB/FSUBP/FISUB-Subtract FSUBR/FSUBRP/FISUBR-Reverse Subtract FTST-TEST FUCOM/FUCOMP/FUCOMPP-Unordered Compare Floating Point Values. FWAIT-Wait FXAM-Examine FXCH-Exchange Register Contents FXRSTOR-Restore FPU, MMX, SSE, SSE2 State FXSAVE-Save FPU, MMX, SSE, SSE2 State. FXTRACT-Extract Exponent Significand FYL2X-Compute log2x FYL2XP1-Compute log2(x HLT-Halt IDIV-Signed Divide IMUL-Signed Multiply IN-Input from Port INC-Increment INS/INSB/INSW/INSD-Input from Port String n/INTO/INT 3-Call Interrupt Procedure INVD-Invalidate Internal Caches INVLPG-Invalidate Entry IRET/IRETD-Interrupt Return Jcc-Jump Condition JMP-Jump LAHF-Load Status Flags into Register LAR-Load Access Rights Byte LDMXCSR-Load MXCSR Register LDS/LES/LFS/LGS/LSS-Load Pointer LEA-Load Effective Address LEAVE-High Level Procedure Exit LES-Load Full Pointer LFENCE-Load Fence LFS-Load Full Pointer LGDT/LIDT-Load Global/Interrupt Descriptor Table Register LGS-Load Full Pointer LLDT-Load Local Descriptor Table Register LIDT-Load Interrupt Descriptor Table Register
3-263 3-265 3-268 3-270 3-272 3-274 3-276 3-279 3-281 3-284 3-287 3-290 3-293 3-295 3-298 3-299 3-301 3-303 3-305 3-311 3-313 3-315 3-317 3-318 3-321 3-324 3-326 3-328 3-331 3-343 3-345 3-346 3-354 3-358 3-365 3-366 3-369 3-371 3-374 3-376 3-378 3-379 3-380 3-381 3-383 3-384 3-386
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LMSW-Load Machine Status Word. .3-387 LOCK-Assert LOCK# Signal Prefix .3-389 LODS/LODSB/LODSW/LODSD-Load String .3-391 LOOP/LOOPcc-Loop According Counter .3-394 LSL-Load Segment Limit. .3-396 LSS-Load Full Pointer .3-399 LTR-Load Task Register .3-400 MASKMOVDQU-Store Selected Bytes Double Quadword .3-402 MASKMOVQ-Store Selected Bytes Quadword. .3-404 MAXPD-Return Maximum Packed Double-Precision Floating-Point Values .3-407 MAXPS-Return Maximum Packed Single-Precision Floating-Point Values .3-410 MAXSD-Return Maximum Scalar Double-Precision Floating-Point Value .3-413 MAXSS-Return Maximum Scalar Single-Precision Floating-Point Value .3-416 MFENCE-Memory Fence .3-419 MINPD-Return Minimum Packed Double-Precision Floating-Point Values .3-420 MINPS-Return Minimum Packed Single-Precision Floating-Point Values .3-423 MINSD-Return Minimum Scalar Double-Precision Floating-Point Value .3-426 MINSS-Return Minimum Scalar Single-Precision Floating-Point Value .3-429 MOV-Move .3-432 MOV-Move to/from Control Registers .3-437 MOV-Move to/from Debug Registers .3-439 MOVAPD-Move Aligned Packed Double-Precision Floating-Point Values .3-441 MOVAPS-Move Aligned Packed Single-Precision Floating-Point Values. .3-443 MOVD-Move Doubleword .3-445 MOVDQA-Move Aligned Double Quadword .3-447 MOVDQU-Move Unaligned Double Quadword. .3-449 MOVDQ2Q-Move Quadword from Register. .3-451 MOVHLPS- Move Packed Single-Precision Floating-Point Values High .3-452 MOVHPD-Move High Packed Double-Precision Floating-Point Value .3-453 MOVHPS-Move High Packed Single-Precision Floating-Point Values .3-455 MOVLHPS-Move Packed Single-Precision Floating-Point Values High. .3-457 MOVLPD-Move Packed Double-Precision Floating-Point Value. .3-458 MOVLPS-Move Packed Single-Precision Floating-Point Values .3-460 MOVMSKPD-Extract Packed Double-Precision Floating-Point Sign Mask .3-462 MOVMSKPS-Extract Packed Single-Precision Floating-Point Sign Mask .3-464 MOVNTDQ-Store Double Quadword Using Non-Temporal Hint .3-466 MOVNTI-Store Doubleword Using Non-Temporal Hint. .3-468 MOVNTPD-Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint .3-470 MOVNTPS-Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint .3-472 MOVNTQ-Store Quadword Using Non-Temporal Hint .3-474 MOVQ-Move Quadword .3-476 MOVQ2DQ-Move Quadword from Register. .3-478 MOVS/MOVSB/MOVSW/MOVSD-Move Data from String String. .3-479
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MOVSD-Move Scalar Double-Precision Floating-Point Value MOVSS-Move Scalar Single-Precision Floating-Point Values MOVSX-Move with Sign-Extension MOVUPD-Move Unaligned Packed Double-Precision Floating-Point Values MOVUPS-Move Unaligned Packed Single-Precision Floating-Point Values. MOVZX-Move with Zero-Extend MUL-Unsigned Multiply MULPD-Multiply Packed Double-Precision Floating-Point Values MULPS-Multiply Packed Single-Precision Floating-Point Values MULSD-Multiply Scalar Double-Precision Floating-Point Values MULSS-Multiply Scalar Single-Precision Floating-Point Values NEG-Two's Complement Negation NOP-No Operation NOT-One's Complement Negation OR-Logical Inclusive ORPD-Bitwise Logical Double-Precision Floating-Point Values ORPS-Bitwise Logical Single-Precision Floating-Point Values. OUT-Output Port OUTS/OUTSB/OUTSW/OUTSD-Output String Port PACKSSWB/PACKSSDW-Pack with Signed Saturation PACKUSWB-Pack with Unsigned Saturation PADDB/PADDW/PADDD-Add Packed Integers PADDQ-Add Packed Quadword Integers PADDSB/PADDSW-Add Packed Signed Integers with Signed Saturation PADDUSB/PADDUSW-Add Packed Unsigned Integers with Unsigned Saturation. PAND-Logical PANDN-Logical PAUSE-Spin Loop Hint PAVGB/PAVGW-Average Packed Integers PCMPEQB/PCMPEQW/PCMPEQD- Compare Packed Data Equal PCMPGTB/PCMPGTW/PCMPGTD-Compare Packed Signed Integers Greater Than. PEXTRW-Extract Word PINSRW-Insert Word PMADDWD-Multiply Packed Integers. PMAXSW-Maximum Packed Signed Word Integers PMAXUB-Maximum Packed Unsigned Byte Integers PMINSW-Minimum Packed Signed Word Integers PMINUB-Minimum Packed Unsigned Byte Integers PMOVMSKB-Move Byte Mask PMULHUW-Multiply Packed Unsigned Integers Store High Result PMULHW-Multiply Packed Signed Integers Store High Result PMULLW-Multiply Packed Signed Integers Store Result PMULUDQ-Multiply Packed Unsigned Doubleword Integers POP-Pop Value from Stack POPA/POPAD-Pop General-Purpose Registers
3-482 3-485 3-488 3-490 3-492 3-494 3-496 3-498 3-500 3-502 3-504 3-506 3-508 3-509 3-511 3-513 3-515 3-517 3-519 3-522 3-526 3-529 3-532 3-534 3-537 3-540 3-542 3-544 3-545 3-548 3-552 3-556 3-558 3-561 3-564 3-567 3-570 3-573 3-576 3-578 3-581 3-584 3-587 3-589 3-593
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POPF/POPFD-Pop Stack into EFLAGS Register .3-595 POR-Bitwise Logical .3-598 PREFETCHh-Prefetch Data Into Caches .3-600 PSADBW-Compute Absolute Differences .3-602 PSHUFD-Shuffle Packed Doublewords .3-605 PSHUFHW-Shuffle Packed High Words. .3-608 PSHUFLW-Shuffle Packed Words .3-610 PSHUFW-Shuffle Packed Words .3-612 PSLLDQ-Shift Double Quadword Left Logical .3-614 PSLLW/PSLLD/PSLLQ-Shift Packed Data Left Logical .3-615 PSRAW/PSRAD-Shift Packed Data Right Arithmetic .3-620 PSRLDQ-Shift Double Quadword Right Logical .3-624 PSRLW/PSRLD/PSRLQ-Shift Packed Data Right Logical .3-625 PSUBB/PSUBW/PSUBD-Subtract Packed Integers. .3-630 PSUBQ-Subtract Packed Quadword Integers .3-634 PSUBSB/PSUBSW-Subtract Packed Signed Integers with Signed Saturation. .3-636 PSUBUSB/PSUBUSW-Subtract Packed Unsigned Integers with Unsigned Saturation .3-639 High Data .3-642 Data .3-646 PUSH-Push Word Doubleword Onto Stack .3-650 PUSHA/PUSHAD-Push General-Purpose Registers. .3-653 PUSHF/PUSHFD-Push EFLAGS Register onto Stack .3-655 PXOR-Logical Exclusive .3-657 RCL/RCR/ROL/ROR-Rotate .3-660 RCPPS-Compute Reciprocals Packed Single-Precision Floating-Point Values. .3-665 RCPSS-Compute Reciprocal Scalar Single-Precision Floating-Point Values .3-668 RDMSR-Read from Model Specific Register .3-670 RDPMC-Read Performance-Monitoring Counters .3-672 RDTSC-Read Time-Stamp Counter .3-675 RDTSC-Read Time-Stamp Counter (Continued) .3-676 REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix .3-677 RET-Return from Procedure .3-680 ROL/ROR-Rotate .3-686 RSM-Resume from System Management Mode .3-687 RSQRTPS-Compute Reciprocals Square Roots Packed Single-Precision Floating-Point Values .3-688 RSQRTSS-Compute Reciprocal Square Root Scalar Single-Precision Floating-Point Value .3-690 SAHF-Store into Flags .3-692 SAL/SAR/SHL/SHR-Shift .3-693 SBB-Integer Subtraction with Borrow .3-697
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SCAS/SCASB/SCASW/SCASD-Scan String SETcc-Set Byte Condition SFENCE-Store Fence SGDT/SIDT-Store Global/Interrupt Descriptor Table Register SHL/SHR-Shift Instructions SHLD-Double Precision Shift Left SHRD-Double Precision Shift Right SHUFPD-Shuffle Packed Double-Precision Floating-Point Values. SHUFPS-Shuffle Packed Single-Precision Floating-Point Values SIDT-Store Interrupt Descriptor Table Register SLDT-Store Local Descriptor Table Register SMSW-Store Machine Status Word SQRTPD-Compute Square Roots Packed Double-Precision Floating-Point Values SQRTPS-Compute Square Roots Packed Single-Precision Floating-Point Values SQRTSD-Compute Square Root Scalar Double-Precision Floating-Point Value. SQRTSS-Compute Square Root Scalar Single-Precision Floating-Point Value. STC-Set Carry Flag STD-Set Direction Flag STI-Set Interrupt Flag STMXCSR-Store MXCSR Register State STOS/STOSB/STOSW/STOSD-Store String STR-Store Task Register SUB-Subtract. SUBPD-Subtract Packed Double-Precision Floating-Point Values SUBPS-Subtract Packed Single-Precision Floating-Point Values. SUBSD-Subtract Scalar Double-Precision Floating-Point Values. SUBSS-Subtract Scalar Single-Precision Floating-Point Values SYSENTER-Fast System Call. SYSEXIT-Fast Return from Fast System Call TEST-Logical Compare UCOMISD-Unordered Compare Scalar Double-Precision Floating-Point Values EFLAGS UCOMISS-Unordered Compare Scalar Single-Precision Floating-Point Values EFLAGS UD2-Undefined Instruction UNPCKHPD-Unpack Interleave High Packed Double-Precision Floating-Point Values UNPCKHPS-Unpack Interleave High Packed Single-Precision Floating-Point Values UNPCKLPD-Unpack Interleave Packed Double-Precision Floating-Point Values UNPCKLPS-Unpack Interleave Packed Single-Precision Floating-Point Values
3-699 3-702 3-704 3-705 3-707 3-708 3-710 3-712 3-715 3-718 3-719 3-721 3-723 3-725 3-727 3-729 3-731 3-732 3-733 3-735 3-737 3-740 3-742 3-744 3-746 3-748 3-750 3-752 3-756 3-759 3-761 3-764 3-767 3-768 3-771 3-774 3-777
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VERR, VERW-Verify Segment Reading Writing. .3-780 WAIT/FWAIT-Wait. .3-782 WBINVD-Write Back Invalidate Cache .3-783 WRMSR-Write Model Specific Register .3-785 XADD-Exchange Add. .3-787 XCHG-Exchange Register/Memory with Register .3-789 XLAT/XLATB-Table Look-up Translation .3-791 XOR-Logical Exclusive .3-793 XORPD-Bitwise Logical Double-Precision Floating-Point Values. .3-795 XORPS-Bitwise Logical Single-Precision Floating-Point Values .3-797 APPENDIX OPCODE A.1. ABBREVIATIONS A.1.1. Codes Addressing Method A.1.2. Codes Operand Type A.1.3. Register Codes A.2. OPCODE LOOK-UP EXAMPLES A.2.1. One-Byte Opcode Instructions A.2.2. Two-Byte Opcode Instructions A.2.3. Opcode Notes A.2.4. Opcode Extensions One- Two-byte Opcodes A-12 A.2.5. Escape Opcode Instructions A-14 A.2.5.1. Opcodes with ModR/M Bytes through Range A-14 A.2.5.2. Opcodes with ModR/M Bytes outside through Range A-14 A.2.5.3. Escape Opcodes with First Byte A-14 A.2.5.4. Escape Opcodes with First Byte A-16 A.2.5.5. Escape Opcodes with First Byte A-17 A.2.5.6. Escape Opcodes with First Byte A-18 A.2.5.7. Escape Opcodes with First Byte A-20 A.2.5.8. Escape Opcodes with First Byte A-21 A.2.5.9. Escape Opcodes with First Byte A-23 A.2.5.10. Escape Opcodes with First Byte A-24 APPENDIX INSTRUCTION FORMATS ENCODINGS B.1. MACHINE INSTRUCTION FORMAT B.1.1. Field (reg). B.1.2. Encoding Operand Size B.1.3. Sign Extend Bit. B.1.4. Segment Register Field (sreg). B.1.5. Special-Purpose Register (eee) Field B.1.6. Condition Test Field (tttn) B.1.7. Direction B.2. GENERAL-PURPOSE INSTRUCTION FORMATS ENCODINGS B.3. INSTRUCTION FORMATS ENCODINGS B-19 B.3.1. Granularity Field (gg). B-19 B.3.2. General-Purpose Register Fields (mmxreg reg) B-19 B.3.3. Instruction Formats Encodings Table B-19 B.4. FAMILY INSTRUCTION FORMATS ENCODINGS B-22 B.5. INSTRUCTION FORMATS ENCODINGS. B-23
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B.6. B.6.1. B.7.
SSE2 INSTRUCTION FORMATS ENCODINGS B-31 Granularity Field (gg) B-31 FLOATING-POINT INSTRUCTION FORMATS ENCODINGS B-44
APPENDIX INTEL C/C++ COMPILER INTRINSICS FUNCTIONAL EQUIVALENTS C.1. SIMPLE INTRINSICS C.2. COMPOSITE INTRINSICS. C-31
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TABLE FIGURES
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Figure 1-1. Figure 2-1. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 3-18. Figure 3-19. Figure 3-20. Figure 3-21. Figure A-1. Figure B-1.
Byte Order .1-6 IA-32 Instruction Format .2-1 Offset BIT[EAX,21] .3-8 Memory Indexing .3-8 Version Information Register .3-116 Feature Information Register .3-118 Operation PACKSSDW Instruction Using 64-bit Operands. .3-522 PMADDWD Execution Model Using 64-bit Operands .3-561 PMULHUW PMULHW Instruction Operation Using 64-bit Operands .3-578 PMULLU Instruction Operation Using 64-bit Operands .3-584 PSADBW Instruction Operation Using 64-bit Operands. .3-602 PSHUFD Instruction Operation. .3-605 PSLLW, PSLLD, PSLLQ Instruction Operation Using 64-bit Operand .3-615 PSRAW PSRAD Instruction Operation Using 64-bit Operand .3-620 PSRLW, PSRLD, PSRLQ Instruction Operation Using 64-bit Operand .3-625 PUNPCKHBW Instruction Operation Using 64-bit Operands .3-642 PUNPCKLBW Instruction Operation Using 64-bit Operands .3-646 SHUFPD Shuffle Operation .3-712 SHUFPS Shuffle Operation .3-715 UNPCKHPD Instruction High Unpack Interleave Operation .3-768 UNPCKHPS Instruction High Unpack Interleave Operation .3-771 UNPCKLPD Instruction Unpack Interleave Operation .3-774 UNPCKLPS Instruction Unpack Interleave Operation .3-777 ModR/M Byte Field (Bits A-12 General Machine Instruction Format
TABLE TABLES
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Table 2-1. Table 2-2. Table 2-3. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table A-9. Table A-10. Table A-11. Table A-12. Table A-13. Table A-14. Table A-15. Table A-16. Table A-17. Table A-18. Table A-19. Table A-20. Table B-1. Table B-2. Table B-3. Table B-4. Table B-5. Table B-6. Table B-7. Table B-8. Table B-9. Table B-10. Table B-11. Table B-12.
16-Bit Addressing Forms with ModR/M Byte .2-5 32-Bit Addressing Forms with ModR/M Byte .2-6 32-Bit Addressing Forms with Byte .2-7 Register Encodings Associated with +rb, +rw, Nomenclature. .3-2 IA-32 General Exceptions. .3-12 Floating-Point Exceptions .3-13 SIMD Floating-Point Exceptions .3-14 Comparison Predicate CMPPD CMPPS Instructions. .3-85 Information Returned CPUID Instruction .3-115 Highest CPUID Source Operand IA-32 Processors .3-116 Processor Type Field .3-117 CPUID Feature Flags Returned Register .3-119 Encoding Cache Descriptors .3-121 Mapping Brand Indices IA-32 Processor Brand Strings .3-124 Processor Brand String Returned with First Pentium Processor .3-125 Layout FXSAVE FXRSTOR Memory Region .3-305 MSRs Used SYSENTER SYSEXIT Instructions .3-752 Notes Instruction Encoding Tables One-byte Opcode Map: Two-byte Opcode Map: (First Byte OFH) Opcode Extensions One- Two-byte Opcodes Group Number. A-13 Opcode When ModR/M Byte Within BFH1 A-14 Opcode When ModR/M Byte Outside BFH1 A-15 Opcode When ModR/M Byte Within BFH1. A-16 Opcode When ModR/M Byte Outside BFH1 A-17 Opcode When ModR/M Byte Within BFH1 A-17 Opcode When ModR/M Byte Outside BFH1 A-18 Opcode When ModR/M Byte Within BFH1 A-19 Opcode When ModR/M Byte Outside BFH1 A-19 Opcode When ModR/M Byte Within BFH1 A-20 Opcode When ModR/M Byte Outside BFH4 A-21 Opcode When ModR/M Byte Within BFH1 A-22 Opcode When ModR/M Byte Outside BFH1 A-22 Opcode When ModR/M Byte Within BFH1 A-23 Opcode When ModR/M Byte Outside BFH1 A-24 Opcode When ModR/M Byte Within BFH1 A-25 Opcode When ModR/M Byte Outside BFH1 A-25 Special Fields Within Instruction Encodings Encoding Field When Field Present Instruction Encoding Field When Field Present Instruction. Encoding Operand Size Bit. Encoding Sign-Extend Encoding Segment Register (sreg) Field Encoding Special-Purpose Register (eee) Field. Encoding Conditional Test (tttn) Field. Encoding Operation Direction General Purpose Instruction Formats Encodings Encoding Granularity Data Field (gg) B-19 Instruction Formats Encodings. B-19
TABLE TABLES
PAGE
Table B-13. Table B-14. Table B-15. Table B-16. Table B-17. Table B-18. Table B-19. Table B-20. Table B-21. Table B-22. Table C-1. Table C-2.
Formats Encodings Family Instructions B-22 Formats Encodings SIMD Floating-Point Instructions B-23 Formats Encodings SIMD Integer Instructions B-29 Format Encoding Cacheability Memory Ordering Instructions B-30 Encoding Granularity Data Field (gg) B-31 Formats Encodings SSE2 SIMD Floating-Point Instructions B-31 Formats Encodings SSE2 SIMD Integer Instructions B-38 Format Encoding SSE2 Cacheability Instructions B-43 General Floating-Point Instruction Formats B-44 Floating-Point Instruction Formats Encodings B-45 Simple Intrinsics Composite Intrinsics C-31
About This Manual
CHAPTER ABOUT THIS MANUAL
IA-32 Intel Architecture Software Developer's Manual, Volume Instruction Reference (Order Number 245471) part three-volume that describes architecture programming environment IA-32 Intel® Architecture processors. other volumes this are:
IA-32 Intel Architecture Software Developer's Manual, Volume Basic Architecture (Order Number 245470). IA-32 Intel Architecture Software Developer's Manual, Volume System Programing Guide (Order Number 245472).
IA-32 Intel Architecture Software Developer's Manual, Volume describes basic architecture programming environment IA-32 processor; IA-32 Intel Architecture Software Developer's Manual, Volume describes instructions processor opcode structure. These volumes aimed application programmers writing programs under existing operating systems executives. IA-32 Intel Architecture Software Developer's Manual, Volume describes operating-system support environment IA-32 processor, including memory management, protection, task management, interrupt exception handling, system management mode. also provides IA-32 processor compatibility information. This volume aimed operating-system BIOS designers programmers.
1.1.
IA-32 PROCESSORS COVERED THIS MANUAL
This manual includes information pertaining primarily most recent IA-32 processors, which include Pentium® processors, family processors, Pentium® processors, Intel® Xeonprocessors. family processors those IA-32 processors based family micro-architecture. This family includes Pentium® Pro, Pentium® Pentium® processors. Pentium Intel Xeon processors first family IA32 processors based Intel® NetBurstmicro-architecture.
1.2.
OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME INSTRUCTION REFERENCE
contents IA-32 Intel Architecture Software Developer's Manual, Volume follows: Chapter About This Manual. Gives overview three volumes IA-32 Intel Architecture Software Developer's Manual. also describes notational conventions these
ABOUT THIS MANUAL
manuals lists related Intel manuals documentation interest programmers hardware designers. Chapter Instruction Format. Describes machine-level instruction format used IA-32 instructions gives allowable encodings prefixes, operand-identifier byte (ModR/M byte), addressing-mode specifier byte (SIB byte), displacement immediate bytes. Chapter Instruction Reference. Describes each IA-32 instructions detail, including algorithmic description operations, effect flags, effect operand- address-size attributes, exceptions that generated. instructions arranged alphabetical order. general-purpose, FPU, Intel MMXtechnology, Streaming SIMD Extensions (SSE), Streaming SIMD Extensions (SSE2), system instructions included this chapter. Appendix Opcode Map. Gives opcode IA-32 instruction set. Appendix Instruction Formats Encodings. Gives binary encoding each form each IA-32 instruction. Appendix Intel C/C++ Compiler Intrinsics Functional Equivalents. Lists Intel C/C++ compiler intrinsics their assembly code equivalents each IA-32 MMX, SSE, SSE2 instructions.
1.3.
OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME BASIC ARCHITECTURE
contents this manual follows: Chapter About This Manual. Gives overview three volumes IA-32 Intel Architecture Software Developer's Manual. also describes notational conventions these manuals lists related Intel manuals documentation interest programmers hardware designers. Chapter Introduction IA-32 Architecture. Introduces IA-32 architecture families Intel processors that based this architecture. also gives overview common features found these processors brief history IA-32 architecture. Chapter Basic Execution Environment. Introduces models memory organization describes register used applications. Chapter Data Types. Describes data types addressing modes recognized processor; provides overview real numbers floating-point formats floatingpoint exceptions. Chapter Instruction Summary. Lists IA-32 architecture instructions, divided into technology groups (general-purpose, FPU, technology, SSE, SSE2, system instructions). Within these groups, instructions presented functionally related groups.
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Chapter Procedure Calls, Interrupts, Exceptions. Describes procedure stack mechanisms provided making procedure calls servicing interrupts exceptions. Chapter Programming With General-Purpose System Instructions. Describes basic load store, program control, arithmetic, string instructions that operate basic data types general-purpose segment registers; describes system instructions that executed protected mode. Chapter Programming With Floating Point Unit. Describes floatingpoint unit (FPU), including floating-point registers data types; gives overview floating-point instruction set; describes processor's floating-point exception conditions. Chapter Programming with Intel Technology. Describes Intel technology, including registers data types, gives overview instruction set. Chapter Programming with Streaming SIMD Extensions (SSE). Describes extensions, including registers, MXCSR register, packed single-precision floating-point data types; gives overview instruction set; gives guidelines writing code that accesses extensions. Chapter Programming with Streaming SIMD Extensions (SSE2). Describes SSE2 extensions, including registers packed double-precision floating-point data types; gives overview SSE2 instruction set; gives guidelines writing code that accesses SSE2 extensions. This chapter also describes SIMD floating-point exceptions that generated with SSE2 instructions, gives general guidelines incorporating support SSE2 extensions into operating system applications code. Chapter Input/Output. Describes processor's mechanism, including port addressing, instructions, protection mechanism. Chapter Processor Identification Feature Determination. Describes determine type features that available processor. Appendix EFLAGS Cross-Reference. Summarizes IA-32 instructions affect flags EFLAGS register. Appendix EFLAGS Condition Codes. Summarizes conditional jump, move, byte condition code instructions condition code flags (OF, EFLAGS register. Appendix Floating-Point Exceptions Summary. Summarizes exceptions that raised floating-point SSE2 SIMD floating-point instructions. Appendix Guidelines Writing Exception Handlers. Describes design write MS-DOS* compatible exception handling facilities exceptions, including both software hardware requirements assembly-language code examples. This appendix also describes general techniques writing robust exception handlers. Appendix Guidelines Writing SIMD Floating-Point Exception Handlers. Gives guidelines writing exception handlers handle exceptions generated SSE2 SIMD floating-point instructions.
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1.4.
OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME SYSTEM PROGRAMMING GUIDE
contents IA-32 Intel Architecture Software Developer's Manual, Volume follows: Chapter About This Manual. Gives overview three volumes IA-32 Software Developer's Manual. also describes notational conventions these manuals lists related Intel manuals documentation interest programmers hardware designers. Chapter System Architecture Overview. Describes modes operation IA-32 processor mechanisms provided IA-32 architecture support operating systems executives, including system-oriented registers data structures systemoriented instructions. steps necessary switching between real-address protected modes also identified. Chapter Protected-Mode Memory Management. Describes data structures, registers, instructions that support segmentation paging explains they used implement "flat" (unsegmented) memory model segmented memory model. Chapter Protection. Describes support page segment protection provided IA-32 architecture. This chapter also explains implementation privilege rules, stack switching, pointer validation, user supervisor modes. Chapter Interrupt Exception Handling. Describes basic interrupt mechanisms defined IA-32 architecture, shows interrupts exceptions relate protection, describes architecture handles each exception type. Reference information each IA32 exception given this chapter. Chapter Task Management. Describes mechanisms that IA-32 architecture provides support multitasking inter-task protection. Chapter Multiple Processor Management. Describes instructions flags that support multiple processors with shared memory, memory ordering, advanced programmable interrupt controller (APIC). Chapter Processor Management Initialization. Defines state IA-32 processor after reset initialization. This chapter also explains IA-32 processor real-address mode operation protected mode operation, switch between modes. Chapter Memory Cache Control. Describes general concept caching caching mechanisms supported IA-32 architecture. This chapter also describes memory type range registers (MTRRs) they used memory types physical memory. Information using cache control memory streaming instructions introduced with Pentium Pentium processors also given. Chapter Intel Technology System Programming. Describes those aspects Intel technology that must handled considered system programming level,
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including task switching, exception handling, compatibility with existing system environments. Chapter SSE2 System Programming. Describes those aspects SSE2 extensions that must handled considered system programming level, including task switching, exception handling, compatibility with existing system environments. Chapter System Management. Describes IA-32 architecture's system management mode (SMM) thermal monitoring facilities. Chapter Machine-Check Architecture. Describes machine-check architecture. Chapter Debugging Performance Monitoring. Describes debugging registers other debug mechanism provided IA-32 architecture. This chapter also describes time-stamp counter performance-monitoring counters. Chapter 8086 Emulation. Describes real-address virtual-8086 modes IA32 architecture. Chapter Mixing 16-Bit 32-Bit Code. Describes 16-bit 32-bit code modules within same program task. Chapter IA-32 Architecture Compatibility. Describes architectural compatibility among IA-32 processors, which include Intel 286, Intel386TM, Intel486TM, Pentium, family, Pentium Intel Xeon processors. family includes Pentium Pro, Pentium Pentium processors. Pentium Xeon processors first family IA-32 processors based Intel NetBurst micro-architecture. differences among 32-bit IA-32 processors also described throughout three volumes IA-32 Software Developer's Manual, relevant particular features architecture. This chapter provides collection relevant compatibility information IA-32 processors also describes basic differences with respect 16-bit IA-32 processors (the Intel 8086 Intel processors). Appendix Performance-Monitoring Events. Lists events that counted with performance-monitoring counters codes used select these events. Appendix Model Specific Registers (MSRs). Lists MSRs available Pentium processors, family processors, Pentium Intel Xeon processors describes their functions. Appendix Dual-Processor (DP) Bootup Sequence Example (Specific Pentium Processors). Gives example protocol boot Pentium processors primary processor secondary processor) system initialize their APICs. Appendix Multiple-Processor (MP) Bootup Sequence Example (Specific Family Processors). Gives example protocol boot family processors multiple-processor (MP) system initialize their APICs. Appendix Programming LINT0 LINT1 Inputs. Gives example program LINT0 LINT1 pins specific interrupt vectors.
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Appendix Interpreting Machine-Check Error Codes. Gives example interpret error codes machine-check error that occurred family processor. Appendix APIC Message Formats. Describes message formats messages transmitted APIC family Pentium processors.
1.5.
NOTATIONAL CONVENTIONS
This manual uses special notation data-structure formats, symbolic representation instructions, hexadecimal numbers. review this notation makes manual easier read.
1.5.1.
Byte Order
illustrations data structures memory, smaller addresses appear toward bottom figure; addresses increase toward top. positions numbered from right left. numerical value equal raised power position. IA-32 processors "little endian" machines; this means bytes word numbered starting from least significant byte. Figure illustrates these conventions.
Highest Address
Data Structure
offset
Byte
Byte
Byte
Byte
Lowest Address
Byte Offset
Figure 1-1. Byte Order
1.5.2.
Reserved Bits Software Compatibility
many register memory layout descriptions, certain bits marked reserved. When bits marked reserved, essential compatibility with future processors that software treat these bits having future, though unknown, effect. behavior reserved bits should regarded only undefined, unpredictable. Software should follow these guidelines dealing with reserved bits:
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depend states reserved bits when testing values registers which contain such bits. Mask reserved bits before testing. depend states reserved bits when storing memory register. depend ability retain information written into reserved bits. When loading register, always load reserved bits with values indicated documentation, any, reload them with values previously read from same register.
NOTE
Avoid software dependence upon state reserved bits IA-32 registers. Depending upon values reserved register bits will make software dependent upon unspecified manner which processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors.
1.5.3.
Instruction Operands
When instructions represented symbolically, subset IA-32 assembly language used. this subset, instruction following format:
label: mnemonic argument1, argument2, argument3
where:
label identifier which followed colon. mnemonic reserved name class instruction opcodes which have same function. operands argument1, argument2, argument3 optional. There from zero three operands, depending opcode. When present, they take form either literals identifiers data items. Operand identifiers either reserved names registers assumed assigned data items declared another part program (which shown example).
When operands present arithmetic logical instruction, right operand source left operand destination. example:
LOADREG: EAX, SUBTOTAL
this example, LOADREG label, mnemonic identifier opcode, destination operand, SUBTOTAL source operand. Some assembly languages source destination reverse order.
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1.5.4.
Hexadecimal Binary Numbers
Base (hexadecimal) numbers represented string hexadecimal digits followed character (for example, F82EH). hexadecimal digit character from following set: Base (binary) numbers represented string sometimes followed character (for example, 1010B). designation only used situations where confusion type number might arise.
1.5.5.
Segmented Addressing
processor uses byte addressing. This means memory organized accessed sequence bytes. Whether more bytes being accessed, byte address used locate byte bytes memory. range memory that addressed called address space. processor also supports segmented addressing. This form addressing where program have many independent address spaces, called segments. example, program keep code (instructions) stack separate segments. Code addresses would always refer code space, stack addresses would always refer stack space. following notation used specify byte address within segment: Segment-register:Byte-address example, following segment address identifies byte address FF79H segment pointed register:
DS:FF79H
following segment address identifies instruction address code segment. register points code segment register contains address instruction.
CS:EIP
1.5.6.
Exceptions
exception event that typically occurs when instruction causes error. example, attempt divide zero generates exception. However, some exceptions, such breakpoints, occur under other conditions. Some types exceptions provide error codes. error code reports additional information about error. example notation used show exception error code shown below.
#PF(fault code)
This example refers page-fault exception under conditions where error code naming type fault reported. Under some conditions, exceptions which produce error codes
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able report accurate code. this case, error code zero, shown below general-protection exception.
#GP(0)
Chapter Interrupt Exception Handling, IA-32 Intel Architecture Software Developer's Manual, Volume list exception mnemonics their descriptions.
1.6.
RELATED LITERATURE
Literature related IA-32 processors listed on-line following Intel site:
Some documents listed this site viewed on-line; others ordered online. literature available listed Intel processor then following literature types: applications notes, data sheets, manuals, papers, specification updates. following literature interest:
Data Sheet particular Intel IA-32 processor. Specification Update particular Intel IA-32 processor. AP-485, Intel Processor Identification CPUID Instruction, Order Number 241618. Intel Pentium Optimization Reference Manual, Order Number 248966.
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1-10
Instruction Format
CHAPTER INSTRUCTION FORMAT
This chapter describes instruction format IA-32 processors.
2.1.
GENERAL INSTRUCTION FORMAT
IA-32 instruction encodings subsets general instruction format shown Figure 2-1. Instructions consist optional instruction prefixes order), primary opcode bytes, addressing-form specifier required) consisting ModR/M byte sometimes (Scale-Index-Base) byte, displacement required), immediate data field required).
Instruction Prefixes four prefixes 1-byte each (optional)
Opcode byte opcode
ModR/M byte required)
byte required)
Displacement Address displacement bytes none Index Base
Immediate Immediate data bytes none
Reg/ Opcode
Scale
Figure 2-1. IA-32 Instruction Format
2.2.
INSTRUCTION PREFIXES
instruction prefixes divided into four groups, each with allowable prefix codes:
Group Lock repeat prefixes:
F0H-LOCK. F2H-REPNE/REPNZ (used only with string instructions). F3H-REP (use only with string instructions). F3H-REPE/REPZ (use only with string instructions).
Group Segment override prefixes:
INSTRUCTION FORMAT
2EH-CS segment override (use with branch instruction reserved). 36H-SS segment override prefix (use with branch instruction reserved). 3EH-DS segment override prefix (use with branch instruction reserved). 26H-ES segment override prefix (use with branch instruction reserved). 64H-FS segment override prefix (use with branch instruction reserved). 65H-GS segment override prefix (use with branch instruction reserved).
Branch hints: 2EH-Branch taken (used only with instructions). 3EH-Branch taken (used only with instructions).
Group 66H-Operand-size override prefix. Group 67H-Address-size override prefix.
each instruction, prefix used from each these groups placed order. Using redundant prefixes (more than prefix from group) reserved cause unpredictable behavior. LOCK prefix forces atomic operation insure exclusive shared memory multiprocessor environment. "LOCK-Assert LOCK# Signal Prefix" Chapter Instruction Reference, detailed description this prefix instructions with which used. repeat prefixes cause instruction repeated each element string. They used only with string instructions: MOVS, CMPS, SCAS, LODS, STOS. repeat prefixes with other IA-32 instructions reserved cause unpredictable behavior (see note below). branch hint prefixes allow program give hint processor about most likely code path that will taken branch. These prefixes only used with conditional branch instructions (Jcc). these prefixes with other IA-32 instructions reserved cause unpredictable behavior. branch hint prefixes were introduced Pentium Intel Xeon processors part SSE2 extensions. operand-size override prefix allows program switch between 32-bit operand sizes. Either operand size default. This prefix selects non-default size. this prefix with MMX, SSE, and/or SSE2 instructions reserved cause unpredictable behavior (see note below). address-size override prefix allows program switch between 32-bit addressing. Either address size default. This prefix selects non-default size. Using this prefix when operands instruction reside memory reserved cause unpredictable behavior.
INSTRUCTION FORMAT
NOTE
Some SSE2 instructions have three-byte opcodes. these three-byte opcodes, third opcode byte F2H, F3H, 66H. example, SSE2 instruction CVTDQ2PD three-byte opcode third opcode byte these three-byte opcodes should thought prefix, even though same encoding operand size prefix (66H) repeat prefixes (F2H F3H). described above, using operand size repeat prefixes with SSE2 instructions reserved.
2.3.
OPCODE
primary opcode either bytes. additional 3-bit opcode field sometimes encoded ModR/M byte. Smaller encoding fields defined within primary opcode. These fields define direction operation, size displacements, register encoding, condition codes, sign extension. encoding fields opcode varies, depending class operation.
2.4.
MODR/M BYTES
Most instructions that refer operand memory have addressing-form specifier byte (called ModR/M byte) following primary opcode. ModR/M byte contains three fields information:
field combines with field form possible values: eight registers addressing modes. reg/opcode field specifies either register number three more bits opcode information. purpose reg/opcode field specified primary opcode. field specify register operand combined with field encode addressing mode.
Certain encodings ModR/M byte require second addressing byte, byte, fully specify addressing form. base-plus-index scale-plus-index forms 32-bit addressing require byte. byte includes following fields:
scale field specifies scale factor. index field specifies register number index register. base field specifies register number base register.
Section 2.6., "Addressing-Mode Encoding ModR/M Bytes", encodings ModR/M bytes.
INSTRUCTION FORMAT
2.5.
DISPLACEMENT IMMEDIATE BYTES
Some addressing forms include displacement immediately following ModR/M byte byte present). displacement required, bytes. instruction specifies immediate operand, operand always follows displacement bytes. immediate operand bytes.
2.6.
ADDRESSING-MODE ENCODING MODR/M BYTES
values corresponding addressing forms ModR/M bytes shown Tables through 2-3. 16-bit addressing forms specified ModR/M byte Table 2-1, 32-bit addressing forms specified ModR/M byte Table 2-2. Table shows 32-bit addressing forms specified byte. Tables 2-2, first column (labeled "Effective Address") lists different effective addresses that assigned operand instruction using fields ModR/M byte. first effective addresses give different ways specifying memory location; last eight (specified field encoding 11B) give ways specifying general-purpose, MMX, registers. Each register encodings list five possible registers. example, first register-encoding (selected field encoding 000B) indicates general-purpose registers EAX, register MM0, register XMM0. Which these five registers used determined opcode byte operand-size attribute, which select either register bits) register bits). second third columns Tables gives binary encodings fields ModR/M byte, respectively, required obtain associated effective address listed first column. possible combinations fields listed. Across Tables 2-2, eight possible values 3-bit Reg/Opcode field listed, decimal (sixth from top) binary (seventh from top). seventh labeled "REG=", which represents these bits give location second operand, which must general-purpose, MMX, register. instruction does require second operand specified, then bits Reg/Opcode field used extension opcode, which represented sixth row, labeled "/digit (Opcode)". five rows above give byte, word, doubleword general-purpose registers, registers, registers that correspond register numbers, with same assignments field when field encoding 11B. with field register options, which five possible registers used determined opcode byte along with operand-size attribute. body Tables (under label "Value ModR/M Byte Hexadecimal)") contains array giving values ModR/M byte, hexadecimal. Bits specified column table which byte resides, specifies bits also bits
INSTRUCTION FORMAT
Table 2-1. 16-Bit Addressing Forms with ModR/M Byte
r8(/r) r16(/r) r32(/r) mm(/r) xmm(/r) /digit (Opcode) XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
Effective Address [BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] disp162 [BX] [BX+SI]+disp83 [BX+DI]+disp8 [BP+SI]+disp8 [BP+DI]+disp8 [SI]+disp8 [DI]+disp8 [BP]+disp8 [BX]+disp8 [BX+SI]+disp16 [BX+DI]+disp16 [BP+SI]+disp16 [BP+DI]+disp16 [SI]+disp16 [DI]+disp16 [BP]+disp16 [BX]+disp16 EAX/AX/AL/MM0/XMM0 ECX/CX/CL/MM1/XMM1 EDX/DX/DL/MM2/XMM2 EBX/BX/BL/MM3/XMM3 ESP/SP/AHMM4/XMM4 EBP/BP/CH/MM5/XMM5 ESI/SI/DH/MM6/XMM6 EDI/DI/BH/MM7/XMM7 NOTES:
Value ModR/M Byte Hexadecimal)
default segment register effective addresses containing index, other effective addresses. disp16 nomenclature denotes 16-bit displacement that follows ModR/M byte that added index. disp8 nomenclature denotes 8-bit displacement that follows ModR/M byte that signextended added index.
INSTRUCTION FORMAT
Table 2-2. 32-Bit Addressing Forms with ModR/M Byte
r8(/r) r16(/r) r32(/r) mm(/r) xmm(/r) /digit (Opcode) XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
Effective Address [EAX] [ECX] [EDX] [EBX] [-][-]1 disp322 [ESI] [EDI] [EAX]+disp83 [ECX]+disp8 [EDX]+disp8 [EBX]+disp8 [-][-]+disp8 [EBP]+disp8 [ESI]+disp8 [EDI]+disp8 [EAX]+disp32 [ECX]+disp32 [EDX]+disp32 [EBX]+disp32 [-][-]+disp32 [EBP]+disp32 [ESI]+disp32 [EDI]+disp32 EAX/AX/AL/MM0/XMM0 ECX/CX/CL/MM/XMM1 EDX/DX/DL/MM2/XMM2 EBX/BX/BL/MM3/XMM3 ESP/SP/AH/MM4/XMM4 EBP/BP/CH/MM5/XMM5 ESI/SI/DH/MM6/XMM6 EDI/DI/BH/MM7/XMM7 NOTES:
Value ModR/M Byte Hexadecimal)
[-][-] nomenclature means follows ModR/M byte. disp32 nomenclature denotes 32-bit displacement that follows ModR/M byte byte present) that added index. disp8 nomenclature denotes 8-bit displacement that follows ModR/M byte byte present) that sign-extended added index.
INSTRUCTION FORMAT
Table organized similarly Tables 2-2, except that body gives possible values byte, hexadecimal. Which general-purpose registers will used base indicated across table, along with corresponding values base field (bits decimal binary. rows indicate which register used index (determined bits along with scaling factor (determined bits
Table 2-3. 32-Bit Addressing Forms with Byte
Base Base Scaled Index [EAX] [ECX] [EDX] [EBX] none [EBP] [ESI] [EDI] [EAX*2] [ECX*2] [EDX*2] [EBX*2] none [EBP*2] [ESI*2] [EDI*2] [EAX*4] [ECX*4] [EDX*4] [EBX*4] none [EBP*4] [ESI*4] [EDI*4] [EAX*8] [ECX*8] [EDX*8] [EBX*8] none [EBP*8] [ESI*8] [EDI*8] NOTE: nomenclature means disp32 with base [EBP] otherwise. This provides following addressing modes: disp32[index] (MOD=00). disp8[EBP][index](MOD=01). disp32[EBP][index](MOD=10). Index
Value Byte Hexadecimal)
INSTRUCTION FORMAT
Instruction Reference
CHAPTER INSTRUCTION REFERENCE
This chapter describes complete IA-32 instruction set, including general-purpose, FPU, MMX, SSE, SSE2, system instructions. instruction descriptions arranged alphabetical order. each instruction, forms given each operand combination, including opcode, operands required, description. Also given each instruction description instruction operands, operational description, description effect instructions flags EFLAGS register, summary exceptions that generated.
3.1.
INTERPRETING INSTRUCTION REFERENCE PAGES
This section describes information contained various sections instruction reference pages that make majority this chapter. also explains notational conventions abbreviations used these sections.
3.1.1.
Instruction Format
following example format used each IA-32 instruction description this chapter:
CMC-Complement Carry Flag
Opcode Instruction Description Complement carry flag
3.1.1.1.
OPCODE COLUMN
"Opcode" column gives complete object code produced each form instruction. When possible, codes given hexadecimal bytes, same order which they appear memory. Definitions entries other than hexadecimal bytes follows:
/digit-A digit between indicates that ModR/M byte instruction uses only (register memory) operand. field contains digit that provides extension instruction's opcode. /r-Indicates that ModR/M byte instruction contains both register operand operand.
INSTRUCTION REFERENCE
cp-A 1-byte (cb), 2-byte (cw), 4-byte (cd), 6-byte (cp) value following opcode that used specify code offset possibly value code segment register. id-A 1-byte (ib), 2-byte (iw), 4-byte (id) immediate operand instruction that follows opcode, ModR/M bytes scale-indexing bytes. opcode determines operand signed value. words doublewords given with low-order byte first. +rb, +rw, +rd-A register code, from through added hexadecimal byte given left plus sign form single opcode byte. register codes given Table 3-3. +i-A number used floating-point instructions when operands ST(i) from register stack. number (which range from added hexadecimal byte given left plus sign form single opcode byte.
Table 3-1. Register Encodings Associated with +rb, +rw, Nomenclature
3.1.1.2.
INSTRUCTION COLUMN
"Instruction" column gives syntax instruction statement would appear ASM386 program. following list symbols used represent operands instruction statements:
rel8-A relative address range from bytes before instruction bytes after instruction. rel16 rel32-A relative address within same code segment instruction assembled. rel16 symbol applies instructions with operand-size attribute bits; rel32 symbol applies instructions with operand-size attribute bits. ptr16:16 ptr16:32-A pointer, typically code segment different from that instruction. notation 16:16 indicates that value pointer parts. value left colon 16-bit selector value destined code segment register. value right corresponds offset within destination segment.
INSTRUCTION REFERENCE
ptr16:16 symbol used when instruction's operand-size attribute bits; ptr16:32 symbol used when operand-size attribute bits.
r8-One byte general-purpose registers r16-One word general-purpose registers r32-One doubleword general-purpose registers EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. imm8-An immediate byte value. imm8 symbol signed number between -128 +127 inclusive. instructions which imm8 combined with word doubleword operand, immediate value sign-extended form word doubleword. upper byte word filled with topmost immediate value. imm16-An immediate word value used instructions whose operand-size attribute bits. This number between -32,768 +32,767 inclusive. imm32-An immediate doubleword value used instructions whose operandsize attribute bits. allows number between +2,147,483,647 -2,147,483,648 inclusive. r/m8-A byte operand that either contents byte general-purpose register (AL, DH), byte from memory. r/m16-A word general-purpose register memory operand used instructions whose operand-size attribute bits. word general-purpose registers are: contents memory found address provided effective address computation. r/m32-A doubleword general-purpose register memory operand used instructions whose operand-size attribute bits. doubleword general-purpose registers are: EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI. contents memory found address provided effective address computation. 32-bit operand memory. m8-A byte operand memory, usually expressed variable array name, pointed DS:(E)SI ES:(E)DI registers. This nomenclature used only with string instructions XLAT instruction. m16-A word operand memory, usually expressed variable array name, pointed DS:(E)SI ES:(E)DI registers. This nomenclature used only with string instructions. m32-A doubleword operand memory, usually expressed variable array name, pointed DS:(E)SI ES:(E)DI registers. This nomenclature used only with string instructions. m64-A memory quadword operand memory. This nomenclature used only with CMPXCHG8B instruction. m128-A memory double quadword operand memory. This nomenclature used only with SSE2 instructions.
INSTRUCTION REFERENCE
m16:16, m16:32-A memory operand containing pointer composed numbers. number left colon corresponds pointer's segment selector. number right corresponds offset. m16&32, m16&16, m32&32-A memory operand consisting data item pairs whose sizes indicated left right side ampersand. memory addressing modes allowed. m16&16 m32&32 operands used BOUND instruction provide operand containing upper lower bounds array indices. m16&32 operand used LIDT LGDT provide word with which load limit field, doubleword with which load base field corresponding GDTR IDTR registers. moffs8, moffs16, moffs32-A simple memory variable (memory offset) type byte, word, doubleword used some variants instruction. actual address given simple offset relative segment base. ModR/M byte used instruction. number shown with moffs indicates size, which determined address-size attribute instruction. Sreg-A segment register. segment register assignments ES=0, CS=1, SS=2, DS=3, FS=4, GS=5. m32fp, m64fp, m80fp-A single-precision, double-precision, double extendedprecision (respectively) floating-point operand memory. These symbols designate floating-point values that used operands floating-point instructions. m16int, m32int, m64int-A word, doubleword, quadword integer (respectively) operand memory. These symbols designate integers that used operands integer instructions. ST(0)-The element register stack. ST(i)-The element from register stack. through mm-An register. 64-bit registers are: through MM7. mm/m32-The order bits register 32-bit memory operand. 64-bit registers are: through MM7. contents memory found address provided effective address computation. mm/m64-An register 64-bit memory operand. 64-bit registers are: through MM7. contents memory found address provided effective address computation. xmm-An register. 128-bit registers are: XMM0 through XMM7. xmm/m32-An register 32-bit memory operand. 128-bit registers XMM0 through XMM7. contents memory found address provided effective address computation. xmm/m64-An register 64-bit memory operand. 128-bit SIMD floatingpoint registers XMM0 through XMM7. contents memory found address provided effective address computation.
INSTRUCTION REFERENCE
xmm/m128-An register 128-bit memory operand. 128-bit registers XMM0 through XMM7. contents memory found address provided effective address computation. DESCRIPTION COLUMN
3.1.1.3.
"Description" column following "Instruction" column briefly explains various forms instruction. following "Description" "Operation" sections contain more details instruction's operation. 3.1.1.4. DESCRIPTION
"Description" section describes purpose instructions required operands. also discusses effect instruction flags.
3.1.2.
Operation
"Operation" section contains algorithmic description (written pseudo-code) instruction. pseudo-code uses notation similar Algol Pascal language. algorithms composed following elements:
Comments enclosed within symbol pairs "(*" "*)". Compound statements enclosed keywords, such THEN, ELSE, statement, statement, CASE ESAC case statement. register name implies contents register. register name enclosed brackets implies contents location whose address contained that register. example, ES:[DI] indicates contents location whose segment relative address register [SI] indicates contents address contained register relative register's default segment (DS) overridden segment. Parentheses around general-purpose register name, such (E)SI, indicates that offset read from register current address-size attribute read from register address-size attribute Brackets also used memory operands, where they mean that contents memory location segment-relative offset. example, [SRC] indicates that contents source operand segment-relative offset. indicates that value assigned symbols relational operators used compare values, meaning equal, equal, greater equal, less equal, respectively. relational expression such TRUE value equal otherwise FALSE. expression COUNT" COUNT" indicates that destination operand should shifted left right, respectively, number bits indicated count operand.
INSTRUCTION REFERENCE
following identifiers used algorithmic descriptions:
OperandSize AddressSize-The OperandSize identifier represents operand-size attribute instruction, which either bits. AddressSize identifier represents address-size attribute, which either bits. example, following pseudo-code indicates that operand-size attribute depends form CMPS instruction used.
instruction CMPSW THEN OperandSize ELSE instruction CMPSD THEN OperandSize
"Operand-Size Address-Size Attributes" Chapter IA-32 Intel Architecture Software Developer's Manual, Volume general guidelines these attributes determined.
StackAddrSize-Represents stack address-size attribute associated with instruction, which value bits (see "Address-Size Attribute Stack" Chapter IA-32 Intel Architecture Software Developer's Manual, Volume SRC-Represents source operand. DEST-Represents destination operand.
following functions used algorithmic descriptions: ZeroExtend(value)-Returns value zero-extended operand-size attribute instruction. example, operand-size attribute zero extending byte value converts byte from doubleword value 000000F6H. value passed ZeroExtend function operand-size attribute same size, ZeroExtend returns value unaltered. SignExtend(value)-Returns value sign-extended operand-size attribute instruction. example, operand-size attribute sign extending byte containing value converts byte from doubleword value FFFFFFF6H. value passed SignExtend function operand-size attribute same size, SignExtend returns value unaltered. signed 16-bit value signed 8-bit value. signed 16-bit value less than -128, represented saturated value (80H); greater than 127, represented saturated value (7FH). signed 32-bit value signed 16-bit value. signed 32-bit value less than -32768, represented saturated value -32768 (8000H); greater than 32767, represented saturated value 32767 (7FFFH). signed 16-bit value unsigned 8-bit value. signed 16-bit value less than zero, represented saturated
INSTRUCTION REFERENCE
value zero (00H); greater than 255, represented saturated value (FFH).
SaturateToSignedByte-Represents result operation signed 8-bit value. result less than -128, represented saturated value -128 (80H); greater than 127, represented saturated value (7FH). SaturateToSignedWord-Represents result operation signed 16-bit value. result less than -32768, represented saturated value -32768 (8000H); greater than 32767, represented saturated value 32767 (7FFFH). result operation signed 8-bit value. result less than zero represented saturated value zero (00H); greater than 255, represented saturated value (FFH). result operation signed 16-bit value. result less than zero represented saturated value zero (00H); greater than 65535, represented saturated value 65535 (FFFFH). LowOrderWord(DEST SRC)-Multiplies word operand word operand stores least significant word doubleword result destination operand. HighOrderWord(DEST SRC)-Multiplies word operand word operand stores most significant word doubleword result destination operand. Push(value)-Pushes value onto stack. number bytes pushed determined operand-size attribute instruction. "Operation" section "PUSH-Push Word Doubleword Onto Stack" this chapter more information push operation. Pop() removes value from stack returns statement Pop(); assigns 32-bit value from stack. will return either word doubleword depending operand-size attribute. "Operation" section Chapter "POP-Pop Value from Stack" more information operation. PopRegisterStack-Marks ST(0) register empty increments register stack pointer (TOP) Switch-Tasks-Performs task switch. Bit(BitBase, BitOffset)-Returns value within string, which sequence bits memory register. Bits numbered from low-order high-order within registers within memory bytes. base operand register, offset range 0.31. This offset addresses within indicated register. example, function Bit[EAX, illustrated Figure 3-1. BitBase memory address, BitOffset range from GBits GBits. addressed numbered (Offset within byte address (BitBase (BitOffset 8)), where signed division with rounding towards negative infinity, returns positive number. This operation illustrated Figure 3-2.
INSTRUCTION REFERENCE
BitOffset
Figure 3-1. Offset BIT[EAX,21]
BitBase
BitBase
BitBase
BitOffset
BitBase
BitBase BitOffset
BitBase
Figure 3-2. Memory Indexing
3.1.3.
Intel C/C++ Compiler Intrinsics Equivalents
Intel C/C++ compiler intrinsics equivalents special C/C++ coding extensions that allow using syntax function calls variables instead hardware registers. Using these intrinsics frees programmers from having manage registers assembly programming. Further, compiler optimizes instruction scheduling that executables runs faster. following sections discuss intrinsics technology SIMD floatingpoint intrinsics. Each intrinsic equivalent listed with instruction description. There additional intrinsics that have instruction equivalent. strongly recommended that reader reference compiler documentation complete list supported intrinsics. Please refer Intel C/C++ Compiler User's Guide With Support Streaming SIMD Extensions
(Order Number 718195-2001). Appendix Intel C/C++ Compiler Intrinsics Functional Equivalents more information using intrinsics.
INSTRUCTION REFERENCE
3.1.3.1.
INTRINSICS
benefit coding with technology intrinsics SSE2 intrinsics that syntax function calls variables instead hardware registers. This frees from managing registers programming assembly. Further, compiler optimizes instruction scheduling that your executable runs faster. each computational data manipulation instruction instruction set, there corresponding intrinsic that implements directly. intrinsics allow specify underlying implementation (instruction selection) algorithm leave instruction scheduling register allocation compiler. 3.1.3.2. TECHNOLOGY INTRINSICS
technology intrinsics based _m64 data type represent specific contents technology register. specify values bytes, short integers, 32-bit values, 64-bit object. _m64 data type, however, basic ANSI data type, therefore must observe following usage restrictions:
_m64 data only left-hand side assignment, return value, parameter. cannot with other arithmetic expressions ("+", ">>", on). _m64 objects aggregates, such unions access byte elements structures; address _m64 object taken. _m64 data only with technology intrinsics described this guide Intel C/C++ Compiler User's Guide With Support Streaming SIMD Extensions (Order Number 718195-2001). Refer Appendix Intel C/C++ Compiler Intrinsics Functional Equivalents more information using intrinsics. SSE2 INTRINSICS
3.1.3.3.
SSE2 intrinsics make registers Pentium Pentium Processors. There three data types supported these intrinsics: _m128, _m128d, _m128i.
_m128 data type used represent contents register used intrinsic. This either four packed single-precision floating-point values scalar single-precision floating-point value. _m128d data type holds packed double-precision floating-point values scalar double-precision floating-point value. _m128i data type hold sixteen byte, eight word, four doubleword, quadword integer values.
compiler aligns _m128, _m128d, _m128 local global data 16-byte boundaries stack. align integer, float, double arrays, declspec statement described Intel C/C++ Compiler User's Guide With Support Streaming SIMD Extensions (Order Number 718195-2001).
INSTRUCTION REFERENCE
_m128, _m128d, _m128i data types basic ANSI data types therefore some restrictions placed usage:
_m128, _m128d, _m128i only left-hand side assignment, return value, parameter. other arithmetic expressions such ">>". initialize _m128, _m128d, _m128i with literals; there express 128-bit constants. _m128, _m128d, _m128i objects aggregates, such unions (for example, access float elements) structures. address these objects taken. _m128, _m128d, _m128i data only with intrinsics described this user's guide. Refer Appendix Intel C/C++ Compiler Intrinsics Functional Equivalents more
information using intrinsics.
compiler aligns _m128, _m128d, _m128i local data 16-byte boundaries stack. Global _m128 data also aligned 16-byte boundaries. align float arrays, alignment declspec described following section.) Because instruction treats SIMD floating-point registers same whether using packed scalar data, there _m32 data type represent scalar data might expect. scalar operations, should _m128 objects "scalar" forms intrinsics; compiler processor implement these operations with 32-bit memory references. suffixes used denote "packed single" "scalar single" precision operations. packed floats represented right-to-left order, with lowest word (right-most) being used scalar operations: explain memory storage reflects this, consider following example. operation
float a[4] 1.0, 2.0, 3.0, _m128 _mm_load_ps(a);
produces same result follows:
_m128 _mm_set_ps(4.0, 3.0, 2.0, 1.0);
other words,
4.0, 3.0, 2.0,
where "scalar" element 1.0. Some intrinsics "composites" because they require more than instruction implement them. should familiar with hardware features provided SSE, SSE2, technology when writing programs with intrinsics. Keep following three important issues mind:
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Certain intrinsics, such _mm_loadr_ps _mm_cmpgt_ss, directly supported instruction set. While these intrinsics convenient programming aids, mindful their implementation cost. Data loaded stored _m128 objects must generally 16-byte-aligned.
INSTRUCTION REFERENCE
Some intrinsics require that their argument immediates, that constant integers (literals), nature instruction. result arithmetic operations acting (Not Number) arguments undefined. Therefore, floating-point operations using arguments will match expected behavior corresponding assembly instructions.
more detailed description each intrinsic additional information related usage, refer Intel C/C++ Compiler User's Guide With Support Streaming SIMD Extensions
(Order Number 718195-2001). Refer Appendix Intel C/C++ Compiler Intrinsics Functional Equivalents more information using intrinsics.
3.1.4.
Flags Affected
"Flags Affected" section lists flags EFLAGS register that affected instruction. When flag cleared, equal when set, equal arithmetic logical instructions usually assign values status flags uniform manner (see Appendix EFLAGS Cross-Reference, IA-32 Intel Architecture Software Developer's Manual, Volume Non-conventional assignments described "Operation" section. values flags listed undefined changed instruction indeterminate manner. Flags that listed unchanged instruction.
3.1.5.
Flags Affected
floating-point instructions have "FPU Flags Affected" section that describes each instruction affect four condition code flags status word.
3.1.6.
Protected Mode Exceptions
"Protected Mode Exceptions" section lists exceptions that occur when instruction executed protected mode reasons exceptions. Each exception given mnemonic that consists pound sign followed letters optional error code parentheses. example, #GP(0) denotes general protection exception with error code Table associates each two-letter mnemonic with corresponding interrupt vector number exception name. Chapter Interrupt Exception Handling, IA-32 Intel Architecture Software Developer's Manual, Volume detailed description exceptions. Application programmers should consult documentation provided with their operating systems determine actions taken when exceptions occur.
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INSTRUCTION REFERENCE
Table 3-2. IA-32 General Exceptions
Vector Protected Mode Real Address Mode Virtual 8086 Mode
Name #DE-Divide Error #DB-Debug #BP-Breakpoint #OF-Overflow #BR-BOUND Range Exceeded #UD-Invalid Opcode (Undefined Opcode) #NM-Device Available Math Coprocessor) #DF-Double Fault
Source IDIV instructions. code data reference. instruction. INTO instruction. BOUND instruction. instruction reserved opcode. Floating-point WAIT/FWAIT instruction. instruction that generate exception, NMI, INTR. Task switch access. Loading segment registers accessing system segments. Stack operations register loads. memory reference other protection checks. memory reference. Floating-point WAIT/FWAIT instruction. data reference memory. Model dependent machine check errors. SSE2 floating-point instructions.
#TS-Invalid #NP-Segment Present #SS-Stack Segment Fault #GP-General Protection* #PF-Page Fault #MF-Floating-Point Error (Math Fault) #AC-Alignment Check #MC-Machine Check #XF-SIMD Floating-Point Numeric Error
Reserved Reserved Reserved Reserved
NOTE: real-address mode, vector segment overrun exception.
3.1.7.
Real-Address Mode Exceptions
"Real-Address Mode Exceptions" section lists exceptions that occur when instruction executed real-address mode (see Table 3-2).
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INSTRUCTION REFERENCE
3.1.8.
Virtual-8086 Mode Exceptions
"Virtual-8086 Mode Exceptions" section lists exceptions that occur when instruction executed virtual-8086 mode (see Table 3-2).
3.1.9.
Floating-Point Exceptions
"Floating-Point Exceptions" section lists exceptions that occur when floating-point instruction executed. these exception conditions result floating-point error exception (#MF, vector number being generated. Table associates one- twoletter mnemonic with corresponding exception name. "Floating-Point Exception Conditions" Chapter IA-32 Intel Architecture Software Developer's Manual, Volume detailed description these exceptions.
Table 3-3. Floating-Point Exceptions
Mnemonic Name Floating-point invalid operation: Stack overflow underflow Invalid arithmetic operation Floating-point divide-by-zero Floating-point denormal operand Floating-point numeric overflow Floating-point numeric underflow Floating-point inexact result (precision) Source stack overflow underflow Invalid arithmetic operation Divide-by-zero Source operand that denormal number Overflow result Underflow result Inexact result (precision)
3.1.10. SIMD Floating-Point Exceptions
"SIMD Floating-Point Exceptions" section lists exceptions that occur when SSE2 floating-point instruction executed. these exception conditions result SIMD floating-point error exception (#XF, vector number being generated. Table associates one-letter mnemonic with corresponding exception name. detailed description these exceptions, refer "SSE SSE2 Exceptions", Chatper IA-32 Intel Architecture Software Developer's Manual, Volume
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INSTRUCTION REFERENCE
Table 3-4. SIMD Floating-Point Exceptions
Mnemonic Name Floating-point invalid operation Floating-point divide-by-zero Floating-point denormal operand Floating-point numeric overflow Floating-point numeric underflow Floating-point inexact result Source Invalid arithmetic operation source operand Divide-by-zero Source operand that denormal number Overflow result Underflow result Inexact result (precision)
3.2.
INSTRUCTION REFERENCE
remainder this chapter provides detailed descriptions each IA-32 instructions.
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INSTRUCTION REFERENCE
AAA-ASCII Adjust After Addition
Opcode Instruction Description ASCII adjust after addition
Description Adjusts unpacked values create unpacked result. register implied source destination operand this instruction. instruction only useful when follows instruction that adds (binary addition) unpacked values stores byte result register. instruction then adjusts contents register contain correct 1-digit unpacked result. addition produces decimal carry, register incremented flags set. there decimal carry, flags cleared register unchanged. either case, bits through register cleared Operation
((AL 0FH) THEN ELSE 0FH;
Flags Affected flags adjustment results decimal carry; otherwise they cleared flags undefined. Exceptions (All Operating Modes) None.
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INSTRUCTION REFERENCE
AAD-ASCII Adjust Before Division
Opcode Instruction mnemonic) Description ASCII adjust before division Adjust before division number base imm8
Description Adjusts unpacked digits (the least-significant digit register mostsignificant digit register) that division operation performed result will yield correct unpacked value. instruction only useful when precedes instruction that divides (binary division) adjusted value register unpacked value. instruction sets value register AH)), then clears register 00H. value register then equal binary equivalent original unpacked two-digit (base number registers generalized version this instruction allows adjustment unpacked digits number base (see "Operation" section below), setting imm8 byte selected number base (for example, octal, decimal, base numbers). mnemonic interpreted assemblers mean adjust ASCII (base values. adjust values another number base, instruction must hand coded machine code imm8). Operation
tempAL tempAH (tempAL (tempAH imm8)) FFH; imm8 mnemonic
immediate value (imm8) taken from second byte instruction. Flags Affected flags according resulting binary value register; flags undefined. Exceptions (All Operating Modes) None.
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INSTRUCTION REFERENCE
AAM-ASCII Adjust After Multiply
Opcode Instruction mnemonic) Description ASCII adjust after multiply Adjust after multiply number base imm8
Description Adjusts result multiplication unpacked values create pair unpacked (base values. register implied source destination operand this instruction. instruction only useful when follows instruction that multiplies (binary multiplication) unpacked values stores word result register. instruction then adjusts contents register contain correct 2-digit unpacked (base result. generalized version this instruction allows adjustment contents create unpacked digits number base (see "Operation" section below). Here, imm8 byte selected number base (for example, octal, decimal, base numbers). mnemonic interpreted assemblers mean adjust ASCII (base values. adjust values another number base, instruction must hand coded machine code imm8). Operation
tempAL tempAL imm8; imm8 mnemonic tempAL imm8;
immediate value (imm8) taken from second byte instruction. Flags Affected flags according resulting binary value register. flags undefined. Exceptions (All Operating Modes) None with default immediate value 0AH. however, immediate value used, will cause (divide error) exception.
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INSTRUCTION REFERENCE
AAS-ASCII Adjust After Subtraction
Opcode Instruction Description ASCII adjust after subtraction
Description Adjusts result subtraction unpacked values create unpacked result. register implied source destination operand this instruction. instruction only useful when follows instruction that subtracts (binary subtraction) unpacked value from another stores byte result register. instruction then adjusts contents register contain correct 1-digit unpacked result. subtraction produced decimal carry, register decremented flags set. decimal carry occurred, flags cleared, register unchanged. either case, register left with nibble Operation
((AL 0FH) THEN ELSE 0FH;
Flags Affected flags there decimal borrow; otherwise, they cleared flags undefined. Exceptions (All Operating Modes) None.
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INSTRUCTION REFERENCE
ADC-Add with Carry
Opcode Instruction AL,imm8 AX,imm16 EAX,imm32 r/m8,imm8 r/m16,imm16 r/m32,imm32 r/m16,imm8 r/m32,imm8 r/m8,r8 r/m16,r16 r/m32,r32 r8,r/m8 r16,r/m16 r32,r/m32 Description with carry imm8 with carry imm16 with carry imm32 with carry imm8 r/m8 with carry imm16 r/m16 with imm32 r/m32 with sign-extended imm8 r/m16 with sign-extended imm8 into r/m32 with carry byte register r/m8 with carry r/m16 with r/m32 with carry r/m8 byte register with carry r/m16 with r/m32
Description Adds destination operand (first operand), source operand (second operand), carry (CF) flag stores result destination operand. destination operand register memory location; source operand immediate, register, memory location. (However, memory operands cannot used instruction.) state flag represents carry from previous addition. When immediate value used operand, sign-extended length destination operand format. instruction does distinguish between signed unsigned operands. Instead, processor evaluates result both data types sets flags indicate carry signed unsigned result, respectively. flag indicates sign signed result. instruction usually executed part multibyte multiword addition which instruction followed instruction. This instruction used with LOCK prefix allow instruction executed atomically. Operation
DEST DEST
Flags Affected flags according result.
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INSTRUCTION REFERENCE
ADC-Add with Carry (Continued)
Protected Mode Exceptions #GP(0) destination located non-writable segment. memory operand effective address outside segment limit. register used access memory contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
ADD-Add
Opcode Instruction AL,imm8 AX,imm16 EAX,imm32 r/m8,imm8 r/m16,imm16 r/m32,imm32 r/m16,imm8 r/m32,imm8 r/m8,r8 r/m16,r16 r/m32,r32 r8,r/m8 r16,r/m16 r32,r/m32 Description imm8 imm16 imm32 imm8 r/m8 imm16 r/m16 imm32 r/m32 sign-extended imm8 r/m16 sign-extended imm8 r/m32 r/m8 r/m16 r/m32 r/m8 r/m16 r/m32
Description Adds first operand (destination operand) second operand (source operand) stores result destination operand. destination operand register memory location; source operand immediate, register, memory location. (However, memory operands cannot used instruction.) When immediate value used operand, sign-extended length destination operand format. instruction performs integer addition. evaluates result both signed unsigned integer operands sets flags indicate carry (overflow) signed unsigned result, respectively. flag indicates sign signed result. This instruction used with LOCK prefix allow instruction executed atomically. Operation
DEST DEST SRC;
Flags Affected flags according result.
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INSTRUCTION REFERENCE
ADD-Add (Continued)
Protected Mode Exceptions #GP(0) destination located non-writable segment. memory operand effective address outside segment limit. register used access memory contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
ADDPD-Add Packed Double-Precision Floating-Point Values
Opcode Instruction ADDPD xmm1, xmm2/m128 Description packed double-precision floating-point values from xmm2/m128 xmm1.
Description Performs SIMD packed double-precision floating-point values from source operand (second operand) destination operand (first operand), stores packed double-precision floating-point results destination operand. source operand register 128-bit memory location. destination operand register. Figure 11-3 IA-32 Intel Architecture Software Developer's Manual, Volume illustration SIMD double-precision floating-point operation. Operation
DEST[63-0] DEST[63-0] SRC[63-0]; DEST[127-64] DEST[127-64] SRC[127-64];
Intel C/C++ Compiler Intrinsic Equivalent
ADDPD _m128d _mm_add_pd (m128d m128d
SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments. memory operand aligned 16-byte boundary, regardless segment. #SS(0) #PF(fault-code) illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR
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INSTRUCTION REFERENCE
ADDPD-Add Packed Double-Precision Floating-Point Values (Continued)
CPUID feature flag SSE2 Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment. part operand lies outside effective address space from FFFFH. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault
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INSTRUCTION REFERENCE
ADDPS-Add Packed Single-Precision Floating-Point Values
Opcode Instruction ADDPS xmm1, xmm2/m128 Description packed single-precision floating-point values from xmm2/m128 xmm1.
Description Performs SIMD four packed single-precision floating-point values from source operand (second operand) destination operand (first operand), stores packed single-precision floating-point results destination operand. source operand register 128-bit memory location. destination operand register. Figure 10-5 IA-32 Intel Architecture Software Developer's Manual, Volume illustration SIMD single-precision floating-point operation. Operation
DEST[31-0] DEST[31-0] SRC[31-0]; DEST[63-32] DEST[63-32] SRC[63-32]; DEST[95-64] DEST[95-64] SRC[95-64]; DEST[127-96] DEST[127-96] SRC[127-96];
Intel C/C++ Compiler Intrinsic Equivalent
ADDPS _m128 _mm_add_ps(_m128 _m128
SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments. memory operand aligned 16-byte boundary, regardless segment. #SS(0) #PF(fault-code) illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT
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INSTRUCTION REFERENCE
ADDPS-Add Packed Single-Precision Floating-Point Values (Continued)
set. OSFXSR CPUID feature flag Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment. part operand lies outside effective address space from FFFFH. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault.
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INSTRUCTION REFERENCE
ADDSD-Add Scalar Double-Precision Floating-Point Values
Opcode Instruction ADDSD xmm1, xmm2/m64 Description double-precision floating-point value from xmm2/m64 xmm1.
Description Adds double-precision floating-point values from source operand (second operand) destination operand (first operand), stores double-precision floating-point result destination operand. source operand register 64-bit memory location. destination operand register. high quadword destination operand remains unchanged. Figure 11-4 IA-32 Intel Architecture Software Developer's Manual, Volume illustration scalar double-precision floating-point operation. Operation
DEST[63-0] DEST[63-0] SRC[63-0]; DEST[127-64] remains unchanged
Intel C/C++ Compiler Intrinsic Equivalent
ADDSD _m128d _mm_add_sd (m128d m128d
SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) illegal memory operand effective address segments. illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2
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INSTRUCTION REFERENCE
ADDSD-Add Scalar Double-Precision Floating-Point Values (Continued)
#AC(0) alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions Interrupt part operand lies outside effective address space from FFFFH. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) #AC(0) page fault. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
ADDSS-Add Scalar Single-Precision Floating-Point Values
Opcode Instruction ADDSS xmm1, xmm2/m32 Description single-precision floating-point value from xmm2/m32 xmm1.
Description Adds single-precision floating-point values from source operand (second operand) destination operand (first operand), stores single-precision floating-point result destination operand. source operand register 32-bit memory location. destination operand register. three high-order doublewords destination operand remain unchanged. Figure 10-6 IA-32 Intel Architecture Software Developer's Manual, Volume illustration scalar single-precision floating-point operation. Operation
DEST[31-0] DEST[31-0] SRC[31-0]; DEST[127-32] remain unchanged
Intel C/C++ Compiler Intrinsic Equivalent
ADDSS _m128 _mm_add_ss(_m128 _m128
SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) illegal memory operand effective address segments. illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag
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INSTRUCTION REFERENCE
ADDSS-Add Scalar Single-Precision Floating-Point Values (Continued)
#AC(0) alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions Interrupt part operand lies outside effective address space from FFFFH. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) #AC(0) page fault. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
AND-Logical
Opcode Instruction AL,imm8 AX,imm16 EAX,imm32 r/m8,imm8 r/m16,imm16 r/m32,imm32 r/m16,imm8 r/m32,imm8 r/m8,r8 r/m16,r16 r/m32,r32 r8,r/m8 r16,r/m16 r32,r/m32 Description imm8 imm16 imm32 r/m8 imm8 r/m16 imm16 r/m32 imm32 r/m16 imm8 (sign-extended) r/m32 imm8 (sign-extended) r/m8 r/m16 r/m32 r/m8 r/m16 r/m32
Description Performs bitwise operation destination (first) source (second) operands stores result destination operand location. source operand immediate, register, memory location; destination operand register memory location. (However, memory operands cannot used instruction.) Each result both corresponding bits first second operands otherwise, This instruction used with LOCK prefix allow instruction executed atomically. Operation
DEST DEST SRC;
Flags Affected flags cleared; flags according result. state flag undefined. Protected Mode Exceptions #GP(0) destination operand points nonwritable segment. memory operand effective address outside segment limit. register contains null segment selector.
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INSTRUCTION REFERENCE
AND-Logical (Continued)
#SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
ANDPD-Bitwise Logical Packed Double-Precision Floating-Point Values
Opcode Instruction ANDPD xmm1, xmm2/m128 Description Bitwise logical xmm2/m128 xmm1.
Description Performs bitwise logical packed double-precision floating-point values from source operand (second operand) destination operand (first operand), stores result destination operand. source operand register 128-bit memory location. destination operand register. Operation
DEST[127-0] DEST[127-0] BitwiseAND SRC[127-0];
Intel C/C++ Compiler Intrinsic Equivalent
ANDPD _m128d _mm_and_pd(_m128d _m128d
SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments. memory operand aligned 16-byte boundary, regardless segment. #SS(0) #PF(fault-code) illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2
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INSTRUCTION REFERENCE
ANDPD-Bitwise Logical Packed Double-Precision Floating-Point Values (Continued)
Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment. part operand lies outside effective address space from FFFFH. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault.
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INSTRUCTION REFERENCE
ANDPS-Bitwise Logical Packed Single-Precision Floating-Point Values
Opcode Instruction ANDPS xmm1, xmm2/m128 Description Bitwise logical xmm2/m128 xmm1.
Description Performs bitwise logical four packed single-precision floating-point values from source operand (second operand) destination operand (first operand), stores result destination operand. source operand register 128-bit memory location. destination operand register. Operation
DEST[127-0] DEST[127-0] BitwiseAND SRC[127-0];
Intel C/C++ Compiler Intrinsic Equivalent
ANDPS _m128 _mm_and_ps(_m128 _m128
SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments. memory operand aligned 16-byte boundary, regardless segment. #SS(0) #PF(fault-code) illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag
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INSTRUCTION REFERENCE
ANDPS-Bitwise Logical Packed Single-Precision Floating-Point Values (Continued)
Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment. part operand lies outside effective address space from FFFFH. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault.
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INSTRUCTION REFERENCE
ANDNPD-Bitwise Logical Packed Double-Precision Floating-Point Values
Opcode Instruction ANDNPD xmm1, xmm2/m128 Description Bitwise logical xmm2/m128 xmm1.
Description Inverts bits packed double-precision floating-point values destination operand (first operand), performs bitwise logical packed double-precision floating-point values source operand (second operand) temporary inverted result, stores result destination operand. source operand register 128-bit memory location. destination operand register. Operation
DEST[127-0] (NOT(DEST[127-0])) BitwiseAND (SRC[127-0]);
Intel C/C++ Compiler Intrinsic Equivalent
ANDNPD _m128d _mm_andnot_pd(_m128d _m128d
SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments. memory operand aligned 16-byte boundary, regardless segment. #SS(0) #PF(fault-code) illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR
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INSTRUCTION REFERENCE
ANDNPD-Bitwise Logical Packed Double-Precision Floating-Point Values (Continued)
CPUID feature flag SSE2 Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment. part operand lies outside effective address space from FFFFH. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault.
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INSTRUCTION REFERENCE
ANDNPS-Bitwise Logical Packed Single-Precision Floating-Point Values
Opcode Instruction ANDNPS xmm1, xmm2/m128 Description Bitwise logical xmm2/m128 xmm1.
Description Inverts bits four packed single-precision floating-point values destination operand (first operand), performs bitwise logical four packed single-precision floating-point values source operand (second operand) temporary inverted result, stores result destination operand. source operand register 128-bit memory location. destination operand register. Operation
DEST[127-0] (NOT(DEST[127-0])) BitwiseAND (SRC[127-0]);
Intel C/C++ Compiler Intrinsic Equivalent
ANDNPS _m128 _mm_andnot_ps(_m128 _m128
SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments. memory operand aligned 16-byte boundary, regardless segment. #SS(0) #PF(fault-code) illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR
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INSTRUCTION REFERENCE
ANDNPS-Bitwise Logical Packed Single-Precision Floating-Point Values (Continued)
CPUID feature flag Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment. part operand lies outside effective address space from FFFFH. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault.
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INSTRUCTION REFERENCE
ARPL-Adjust Field Segment Selector
Opcode Instruction ARPL r/m16,r16 Description Adjust r/m16 less than
Description Compares fields segment selectors. first operand (the destination operand) contains segment selector second operand (source operand) contains other. (The field located bits each operand.) field destination operand less than field source operand, flag field destination operand increased match that source operand. Otherwise, flag cleared change made destination operand. (The destination operand word register memory location; source operand must word register.) ARPL instruction provided operating-system procedures (however, also used applications). generally used adjust segment selector that been passed operating system application program match privilege level application program. Here segment selector passed operating system placed destination operand segment selector application program's code segment placed source operand. (The field source operand represents privilege level application program.) Execution ARPL instruction then insures that segment selector received operating system lower (does have higher privilege) than privilege level application program. (The segment selector application program's code segment read from stack following procedure call.) "Checking Caller Access Privileges" Chapter IA-32 Intel Architecture Software Developer's Manual, Volume more information about this instruction. Operation
DEST[RPL) SRC[RPL) THEN DEST[RPL) SRC[RPL); ELSE
Flags Affected flag field destination operand less than that source operand; otherwise, cleared
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INSTRUCTION REFERENCE
ARPL-Adjust Field Segment Selector (Continued)
Protected Mode Exceptions #GP(0) destination located nonwritable segment. memory operand effective address outside segment limit. register used access memory contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions ARPL instruction recognized real-address mode.
Virtual-8086 Mode Exceptions ARPL instruction recognized virtual-8086 mode.
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INSTRUCTION REFERENCE
BOUND-Check Array Index Against Bounds
Opcode Instruction BOUND r16, m16&16 BOUND r32, m32&32 Description Check (array index) within bounds specified m16&16 Check (array index) within bounds specified m16&16
Description Determines first operand (array index) within bounds array specified second operand (bounds operand). array index signed integer located register. bounds operand memory location that contains pair signed doubleword-integers (when operand-size attribute pair signed word-integers (when operand-size attribute 16). first doubleword word) lower bound array second doubleword word) upper bound array. array index must greater than equal lower bound less than equal upper bound plus operand size bytes. index within bounds, BOUND range exceeded exception (#BR) signaled. (When this exception generated, saved return instruction pointer points BOUND instruction.) bounds limit data structure (two words doublewords containing lower upper limits array) usually placed just before array itself, making limits addressable constant offset from beginning array. Because address array already will present register, this practice avoids extra cycles obtain effective address array bounds. Operation
(ArrayIndex LowerBound ArrayIndex UppderBound) Below lower bound above upper bound THEN #BR;
Flags Affected None. Protected Mode Exceptions #GP(0) bounds test fails. second operand memory location. memory operand effective address outside segment limit. register contains null segment selector.
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INSTRUCTION REFERENCE
BOUND-Check Array Index Against Bounds (Continued)
#SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions bounds test fails. second operand memory location. memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) bounds test fails. second operand memory location. memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
BSF-Bit Scan Forward
Opcode Instruction r16,r/m16 r32,r/m32 Description scan forward r/m16 scan forward r/m32
Description Searches source operand (second operand) least significant bit). least significant found, index stored destination operand (first operand). source operand register memory location; destination operand register. index unsigned offset from source operand. contents source operand contents destination operand undefined. Operation
THEN DEST undefined; ELSE temp WHILE Bit(SRC, temp) temp temp DEST temp;
Flags Affected flag source operand otherwise, flag cleared. flags undefined. Protected Mode Exceptions #GP(0) memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
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INSTRUCTION REFERENCE
BSF-Bit Scan Forward (Continued)
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
BSR-Bit Scan Reverse
Opcode Instruction r16,r/m16 r32,r/m32 Description scan reverse r/m16 scan reverse r/m32
Description Searches source operand (second operand) most significant bit). most significant found, index stored destination operand (first operand). source operand register memory location; destination operand register. index unsigned offset from source operand. contents source operand contents destination operand undefined. Operation
THEN DEST undefined; ELSE temp OperandSize WHILE Bit(SRC, temp) temp temp DEST temp;
Flags Affected flag source operand otherwise, flag cleared. flags undefined. Protected Mode Exceptions #GP(0) memory operand effective address outside segment limit. register contains null se
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