536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM MH8S64AQFC

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536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM MH8S64AQFC

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MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
MH8S64AQFC 8388608 word 64-bit Synchronous DRAM module. This consists four industry standard 8Mx16 Synchronous DRAMs TSOP industory standard EEPROM TSSOP. mounting TSOP card edge Dual Inline package provides application where high densities large quantities memory required. This socket type memory modules, suitable easy interchange addition modules.
Utilizes industry standard nchronous DRAMs TSOP industry standard EEPROM TSSOP 144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply Max. Clock frequency -6:133MHz,-7,8:100MHz Fully synchronous operation referenced clock rising edge bank operation controlled BA0,1(Bank Address) /CAS latency- 2/3(programmable)
FEATURES
Frequency -6,-6L -7,-7L -8,-8L 133MHz 100MHz 100MHz Access Time
(Component SDRAM)
Burst length- 1/2/4/8/Full Page(programmable) Burst type- sequential interleave(programmable) Column access random Auto precharge bank precharge controlled Auto refresh Self refresh 4096 refresh cycle /64ms LVTTL Interface
5.4ns(CL=3) 6.0ns(CL=2) 6.0ns(CL=3)
APPLICATION
main memory graphic memory computer systems
Outline
(Front) (Back)
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
CONFIGURATION
Number Front side Name Number Back side Name Number Front side Name Number Back side Name
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CLK0 /RAS
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CKE0 /CAS CKE1
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB2 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
CLK1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB6 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Connection
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM Block Diagram
DQMB0 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQML
DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQML
DQMU
DQMU
DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQML
DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CLK1
DQML
DQMU
DQMU
CLK0 CKE0 /RAS /CAS BA0,BA1,A<11:0>
SERIAL
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Serial Presence Detect Table
Byte Function described Defines bytes written into serial memory module mfgr Total bytes memory device Fundamental memory type Addresses this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly. Data Width continuation Voltage interface standard this assembly
SDRAM Cycletime Max.Supported Latency (CL). -6,-6L -7,-7L,-8,-8L -6,-6L -7,-7L,-8,-8L
enrty data Bytes SDRAM A0-A11 A0-A8 1BANK LVTTL 7.5ns 10ns 5.4ns
Non-PARITY
DATA(hex)
Cycle time CL=3 SDRAM Access from Clock CL=3 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
self refresh(15.625uS) 1/2/4/8/Full page 4bank
non-buffered,non-registered Precharge All,Auto precharge -6,-6L,-7,-7L -8,-8L -6,-6L,-7,-7L -8,-8L
Minimum Clock Delay,Back Back Random Column Addresses
Burst Lengths Supported Banks Each SDRAM device CAS# Latency Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest latency) Cycle time CL=2
SDRAM Access form Clock(2nd highest latency)
10ns 13ns 20ns
CL=2 SDRAM Cycle time(3rd highest latency)
SDRAM Access form Clock(3rd highest latency)
Precharge Active Minimum
-6,-6L
Active Active Min. Delay Active Precharge
15ns 20ns 20ns
-7,-7L,-8,-8L
-6,-6L -7,-7L,-8,-8L
45ns 50ns
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Serial Presence Detect Table
Density each bank module Command Address signal input setup time
-6,-6L -7,-7L,-8,-8L
64MByte 1.5ns 0.8ns 1.5ns 0.8ns option 1.2B Check -6,-6L
1CFFFFFFFFFFFFFF
Command Address signal input hold time
-6,-6L -7,-7L,-8,-8L -6,-6L
Data signal input setup time
-7,-7L,-8,-8L -6,-6L
36-61
Data signal input hold time
-7,-7L,-8,-8L
Superset Information (may used future) Revision
64-71
Checksum bytes 0-62 Manufactures Jedec code JEP-108E
Check -7,-7L Check -8,-8L MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany MH8S64AQFC-6 MH8S64AQFC-6L
Manufacturing location
73-90
Manufactures Part Number
MH8S64AQFC-7 MH8S64AQFC-7L MH8S64AQFC-8 MH8S64AQFC-8L
91-92 93-94 95-98 99-125 128+
Revision Code Manufacturing date Assembly Serial Number Manufacture Specific Data Intetl specification frequency Intel specification CAS# Latency support Unused storage locations
-6,-6L,-7,7L -8,8L
revision year/week code serial number option 100MHz CL=2/3,AP,CK0,1 CL=3,AP,CK0,1 open
rrrr yyww ssssssss
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
FUNCTION
CLK0 Master Clock:All other inputs referenced rising edge Clock Enable:CKE controls internal clock.When low,internal clock following cycle ceased. also used select auto self refresh. After self refresh mode started, becomes asynchronous input.Self refresh maintained long low. Chip Select: When high,any command means Operation. Combination /RAS,/CAS,/WE defines basic commands. A0-11 specify Row/Column Address conjunction with BA0,1.The Address specified A0-11.The Column Address specified A0-8.A10 also used indicate precharge option.When high read write command, auto precharge performed. When high precharge command, both banks precharged. Bank Address:BA0,1 simply BA.BA specifies bank which command applied.BA0,1 must with ACT,PRE,READ,WRITE commands
Input
CKE0
Input
Input Input
/RAS,/CAS,/WE
A0-11
Input
BA0,1
Input
DQ0-63
Input/Output Data Data referenced rising edge Input Mask/Output Disable:When DQMB high burst write.Din current cycle masked.When DQMB high burst read,Dout disabled next cycle.
DQMB0-7
Vdd,Vss
Power Supply Power Supply memory mounted module. Input Output Serial clock serial Serial data serial
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
MH8S64AQFC provides basic read write, bank(row)precharge,and auto self refresh. Each command defined control signals /RAS,/CAS rising edge. addition signals,/S,CKE used chip select,refresh option,and precharge option,respectively. know detailed definition commands please command truth table.
/RAS /CAS
Chip Select L=select, H=deselect Command Command Command resh Option @ref resh command Precharge Option @precharge read/write command basic commands
Activate(ACT) [/RAS /CAS command activates idle bank indicated Read(READ) [/RAS =H,/CAS READ command starts burst read from active bank indicated BA.First output data appears after /CAS latency. When this command,the bank deactivated after burst read(auto-precharge,READA). Write(WRITE) [/RAS /CAS WRITE command starts burst write active bank indicated Total data length written burst length. When this command, bank deactivated after burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS /CAS =H,/WE command deactivates active bank indicated This command also term inates burst read write operation. When this command, both banks deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =CKE PEFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically.
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND Deselect Operation Adress Entry Bank Activate Single Bank Precharge Precharge Bank Column Address Entry Write Column Address Entry Write with AutoPrecharge Column Address Entry Read Column Address Entry Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register MNEMONIC DESEL PREA WRITE /RAS /CAS BA0,1 A0-9
WRITEA
READ
READA REFA REFS REFSX TERM
=High Level, Level, Valid, Don't Care, cycle number NOTE: 1.A7-9 A0-6 Mode Address
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Current State IDLE ACTIVE READ /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 Address Command DESEL TBST PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST ILLEGAL*2 Bank Active,Latch NOP*4 Auto-Refresh*5 Mode Register Set*5 Begin Read,Latch Determine Auto-Precharge Begin Write,Latch Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine Auto-Precharge*3 Terminate Burst,Latch BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 BA,RA BA,A10 Op-Code, Mode-Add PRE/PREA REFA Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State WRITE /RAS /CAS Address BA,CA,A10 Command DESEL TBST Action NOP(Continue Burst END)
NOP(Continue Burst END) Terminate Burst Terminate Burst,Latch READ/READA Begin Read,Determine AutoPrecharge*3 WRITE/ WRITEA PRE/PREA REFA DESEL TBST READ/READA WRITE/ WRITEA PRE/PREA REFA DESEL TBST Terminate Burst,Latch Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst END) NOP(Continue Burst END) ILLEGAL
READ with PRECHARGE WRITE with PRECHARGE
BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add
READ/READA ILLEGAL WRITE/ ILLEGAL WRITEA PRE/PREA REFA Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State CHARGING IVATING WRITE RECOVERING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA DESEL TBST PRE/PREA REFA Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING MODE REGISTER SETTING /RAS /CAS BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add BA,CA,A10 BA,RA BA,A10 Op-Code, Mode-Add Address Command DESEL TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA DESEL TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL PRE/PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: Hige Level, Level, Don't Care Bank Address, Address, Column Address, Operation NOTES: entries assume that High during preceding clock cycle current clock cycle. ILLEGAL bank specified state; function legal bank indicated depending state that bank. satisfy contention, turn around, write recovery requirements. bank precharging idle state.May precharge bank indicated ILLEGAL bank idle. ILLEGAL Device operation date-integrity guaranteed.
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Current State SELF REFRESH*1 POWER DOWN BANKS IDLE*2 STATE other than listed above /RAS /CAS INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down Idle NOP(Maintain Self-Refresh) Refer Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer Current State Power Down Refer Function Truth Table Begin Suspend Next Cycle*3 Exit Suspend Next Cycle*3 Maintain Suspend Action
ABBREVIATIONS: High Level, Level, Don't Care NOTES: High transition will re-enable other inputs asynchronously. minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only form banks idle State. legal command.
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX
MODE REGISTER
REFA
IDLE
AUTO REFRESH
CKEL
SUSPEND
CKEL CKEH
CKEH
POWER DOWN
ACTIVE
WRITE WRITEA READA READ WRITE READ
CKEL
CKEL
WRITE SUSPEND
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
CKEL
WRITEA SUSPEND
WRITEA
CKEH
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER
CHARGE Automatic Sequence Command Sequence
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
POWER SEQUENCE
Before tarting normal operation, following power sequence necessary prevent SDRAM from damaged malfunctioning. Apply power start clock.Attempt maintain high,DQM0-7 high condition inputs. Maintain table power, stable cock, input conditions inimum 200us. Issue precharge commands banks. (PRE PREA) After banks become idle state (after tRP), issue more auto-refresh commands. Issue mode register command initialize mode register. After these sequence, SDRAM idle state ready normal operation.
MODE REGISTER
Burst Length, Burst Type /CAS Latency programmed setting mode register(MRS). mode register stores these date until next command, which issued when both banks idle state. After tRSC from command, SDRAM ready command.
/RAS /CAS LTMODE BA0,1 A11-0 SEQUENTIAL INTERLEAVED
LATENCY MODE
/CAS LATENCY BURST SINGLE
BURST LENGTH
BURST TYPE
WRITE MODE
R:Reserved Future Full Page
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Command Address /CAS Latency
Read Write
Burst Length Burst Type
Burst Length
Initial Address
Sequential
Column Addressing Interleaved
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
OPERATION BANK ACTIVATE four banks activated command. bank selected BA0-1. selected A0-11. Multiple banks active state concurrently issuing multiple commands. Minimum activation interval between bank another bank tRRD. PRECHARGE open bank deactivated command. bank deactivated designated BA0-1. When multiple banks active, precharge command (PREA, A10=H) deactivates open banks same time. BA0-1 "Don't Care" this case. Minimum delay time command after command same bank tRP. Bank Activation Precharge (BL=4, CL=2)
Command
tRRD tRCD READ
A0-9,11 BA0,1
Precharge
READ READ command issued active bank. start address specified A0-8 (x16) output data available after /CAS Latency from READ. consecutive data length defined Burst Length. address sequence burst data defined Burst Type. Minimum delay time READ command after command same bank tRCD. When high READ command, auto-precharge (READA) performed. command (READ, WRITE, PRE, ACT, TBST) same bank inhibited till internal precharge complete. internal precharge starts after READA. next command issued after tRP) from previous READA. case, tRCD+BL tRASmin must met.
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=2)
Command
tRCD
READ
tRCD
READ
A0-9, BA0,1
READ with Auto-Precharge (BL=4, CL=2)
Command
tRCD READ
A0-9, BA0,1
Internal precharge starts
Auto-Precharge Timing (READ BL=4)
Command
tRCD READ
CL=3 CL=2
Internal precharge starts
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
WRITE WRITE command issued active bank. start address specified A0-8 (x16). input data same cycle WRITE. consecutive data length written defined Burst Length. address sequence burst data defined Burst Type. Minimum delay time WRITE command after command same bank tRCD. From last input data command, write recovery time (tWR) required. When high WRITE command, auto-precharge (WRITEA) performed. command (READ, WRITE, PRE, ACT, TBST) same bank inhibited till internal precharge complete. internal precharge starts after last input data cycle. next command issued after tRP) from previous WRITEA. case, tRCD tRASmin must met.
WRITE (BL=4)
Command
tRCD Write
A0-9, BA0,1
WRITE with Auto-Precharge (BL=4)
Command
tRCD Write
A0-9, BA0,1
Internal precharge begins
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
BURST INTERRUPTION Read Interrupted Read Burst read oparation interrupted read same other bank. Random column access allowed READ READ interval minimum Read Interrupted Read (BL=4, CL=2)
Command A0-9,11 BA0,1
READ READ READ
Read Interrupted Write Burs read operation interrupted write active bank. Random column access allowed. this case, should controlled adequately using DQMB0-7 prevent contention. output disabled automatically cycle after WRITE assertion. Read Interrupted Write (BL=4, CL=2)
Command A0-9,11 BA0,1 DQMB0-7
READ Write
Output disable
WRITE
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Read Interrupted Precharge burst read operation interrupted precharge same bank Read interval minimum command output disable latency equivalent /CAS Latency. Read Interrupted Precharge (BL=4)
Command
READ
CL=3
Command Command
READ READ
Command
READ
CL=2
Command Command
READ READ
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Read Interrupted Burst Terminate Similarly precharge, burst terminate command interrupt burst read operation disable data output. term inated bank remains active,READ TBST interval minimum TBSTcommand output disable latency equivalent /CAS Latency. Read Interrupted Terminate (BL=4)
Command Command
READ
TBST
READ
TBST
CL=3
Command
READ TBST
Command Command
READ
TBST
READ
TBST
CL=2
Command
READ TBST
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Write Interrupted Write Burs write operation interrupted write active bank. Random column access allowed. WRITE WRITE interval minimum Write Interrupted Write (BL=4)
Command A0-9, BA0,1
Write Write Write
Write Interrupted Read Burs write operation interrupted read active bank. Random column access allowed. WRITE READ interval minimum input data interrupting READ cycle "don't care". Write Interrupted Read (BL=4, CL=2)
Command A0-9,11 BA0,1
Write READ
don't care
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Write Interrupted Precharge Burs write operation interrupted precharge same bank Write recovery time(tWR) required from last data command. During write recovery, data inputs must masked DQM. Write Interrupted Precharge (BL=4)
Command A0-9,11 BA0,1 DQMB0-7
Write
Write Interrupted Burst Terminate Burs terminate command terminate burst write operation. this case, write recovery time required bank remains active.The WRITE TBST minimum interval 1CK. Write Interrupted Burst Terminate (BL=4)
Command A0-9,11 BA0,1
Write TBST Write
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Write with Auto-Precharge interrupted Write Read anotehr Bank Burs write with auto-precharge interrupted write read toanother bank Next command issued after (BL+tWR-1+tRP) from WRITEA. Autoprecharge interrrupted command same bank inhibited. WRITEA Interrupted WRITE another bank (BL=4)
Command A0-9,11 BA0,1
Write Write
auto-precharge interrupted
activate
WRITEA interrupted READ another bank (CL=2,BL=4)
Command A0-9,11 BA0,1
Write Read
auto-precharge interrupted
activate
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Read with Auto-Precharge interrupted Read anotehr Bank Burs read with auto-precharge interrupted read toanother bank Next command issued after (BL+tRP) from READA. Auto-precharge interrrupted command same bank inhibited. READA Interrupted READ another bank (CL=2,BL=4)
Command A0-9,11 BA0,1
Read Read
auto-precharge interrupted
activate
Full Page Burst Full page burst length available only sequential burst type. Full page burst read write repeated untill aPrecharge Burst Terminate command issued. case full page burst read write with auto-precharge command illegal. Single Write When single write mode set, burst length write always one, independently Burs Length defined (A2-0).
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
AUTO REFRESH Single cycle auto-refresh initiated with REFA(/CS=/RAS=/CAS=L, /WE=/CKE=H) command. refresh address generated internally. 4096 REFA cycle within 64ms refresh 128Mbit memory cells. auto-refresh performed 4banks concurrently. Before performing auto-refresh, banks must idle state. Auto-refresh auto-refresh interval minimum tRFC. command must issued before tRFC from REFA command.
Auto-Refresh
DESLECT /RAS /CAS A0-11 BA0,1
minimum tRFC
Auto Refresh Banks
Auto Refresh Banks
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
SELF REFRESH Self-refresh mode entered issuing REFS command (/CS=/RAS=/CAS=L, /WE=H, CKE=L). Once self-refresh initiated, maintained kept low.During self-refresh mode, asynchronous only enabled input other inputs including disabled ignored, that power consumption synchronous inputs saved. exit self-refresh, supplying stable inputs, asserting DESEL command then asserting CKE=H. After tRFC from edge follwing CKE=H, banks idle state command issued after, DESEL commands must asserted till then. Self-Refresh
Stable
/RAS /CAS
command
A0-11 BA0,1
Self Refresh Entry
Self Refresh Exit
minimum tRFC recovery
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
SUSPEND POWER DOWN controls internal following cycle. Figure below shows works. negating CKE, next internal suspended. purpose suspend power down, output suspend input suspend. synchronous input except during self-refresh mode. suspend performed either when banks active idle. command suspended cycle ignored.
(ext.CLK)
int.CLK
Power Down
Command
Standby Power Down
Command
Activ Power Down
Suspend
Command
Write READ
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
CONTROL DQMB0-7 dual function signal defined data mask writes output disable reads. During writes, DQMB0-7 masks input data word word. DQMB0-7 Data latency During reads, DQMB0-7 forces output Hi-Z word word. DQMB0-7 output Hi-Z latency Function
Command DQMB0-7
Write READ
masked DQMB=H
disabled DQMB=H
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25°C Condition with respect with respect with respect Ratings -0.5 -0.5 -0.5 Unit
RECOM ENDED OPERATING CONDITION
(Ta=0 70°C, unless otherwise noted) Symbol Parameter Min. Supply Voltage Supply Voltage High-Level Input Voltage inputs Low-Level Input Voltage inputs -0.3 Limits Typ. Max. Vdd+0.3 Unit
Note) 1:VIH(max)=5.5V pulse width less than 10ns. 2.VIL(min)=-1.0 pulse width less than 10ns.
CAPACITANCE
(Ta=0 70°C, 0.3V, unless otherwise noted) Symbol CI(A) Parameter Input Capacitance, address @1MHz CI(C) CI(K) CI/O
MIT-DS-0374-0.4
Test Condition
Limits(max.)
Unit
26.Jan.2001
1.4V bias 200mV swing
Input Capacitance, /RAS,/CAS,/WE
Input Capacitance, Input Capacitance,
MITSUBISHI ELECTRIC
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from
(Ta=0 ~70°C, 0.3V, unless otherwise noted)
Parameter
operating current bank activ (discrete)
Symbol
Test Condition tRC=min.tCLK=min, BL=1,CL=3
Limits (max) -7,-7L -6,-6L -8,-8L
Unit
Icc1
precharge stanby Icc2P CKE=L,tCLK=15ns, /CS>Vcc-0.2V current power-down mode Icc2PS CKE=CLK=L, /CS>Vcc-0.2V precharge stanby current Icc2N power-down mode Icc2NS ixed) active stanby current CKE=H,tCLK=15ns power-down mode Icc3N bank activ (discrete) Icc3NS CKE=H,CLK=L tCLK=min, BL=4, CL=3,all banks activ e(discerte) burst current Icc4 tRC=min, tCLK=min Icc5 auto-refresh current self-refresh current Icc6 <0.2V -6,-7,-8 -6L,-7L,-8L
Note) 1:Icc(max) specif output open condition. 2.Input signals changed time during 30ns.
OPERATING CONDITIONS CHARACTERISTICS
(Ta=0 70°C, 0.3V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) VOH(AC) VOL(AC) Limits Min. Max. Unit High-Level Output Voltage(DC) IOH=-2mA Low-Level Output Voltage(DC) IOL=2mA floating VO=0 Off-stare Output Current High-Level Output Voltage(AC) CL=50pF, IOH=2 Input Current VIH=0 Low-Level Output Voltage(AC) Vdd+0.3V CL=50pF, IOL=2mA Parameter Test Condition
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 70°C, 0.3V, unless otherwise noted) Input Pulse Levels: 0.8V 2.0V Input Timing Measurement Level: 1.4V -6,-6L Min. Max. CL=2 CL=3 Limits -7,-7L Min. Max.
Symbol Parameter
-8,-8L Unit Min. Max. 100K
tCLK cycle time tRCD tRAS tRRD tRSC tSRX tPDE tREF
High pulse width pilse width Transition time Input Setup time(all inputs) Input Hold time(all inputs) cycle time 67.5 Column Delay Active time Precharge time Write Recovery time Deley Mode Register Cycle time Self Refresh Exit time Power Down Exit time Refresh Interval time
100K
100K
1.4V
timing referenced input
Signal
1.4V
signal crossing through 1.4V.
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 70°C, 0.3V, unless otherwise note3) Symbol Parameter Min. Access time from CL=2 CL=3 Output Hold time from CL=2 CL=3 tOLZ tOHZ Delay time, output impedance from Delay time, output high impedance from Max. Limits Min. Max. Min. Max.
Unit
Note) clock rising time longer than 1ns,(tT/2-0.5)ns should added parameter.
Output Load Condition
50pF 1.4V
1.4V
Output Timing Measurement Reference Point
tOLZ
1.4V
MIT-DS-0374-0.4
tOHZ
1.4V
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
tRAS
/RAS
tRCD tRCD
/CAS
A0-8 A9,11 BA0,1
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
/RAS
tRRD
tRRD
tRAS tRCD
tRCD
/CAS
A0-8 A9,11
BA0,1
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=3
tRAS
/RAS
tRCD tRCD
/CAS
read latency
A0-7 A8,9,11
BA0,1
CL=3
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ allows full data
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=3
/RAS
tRRD tRAS tRCD
tRRD
tRCD
/CAS
read latency
A0-8 A9,11 BA0,1
CL=3
CL=3
ACT#0
READ#0 ACT#1
PRE#0 READ#1
ACT#0 READ#0 PRE#1 ACT#2
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
tRRD tRRD
/RAS
tRCD tRCD tRCD
/CAS
BL-1+ BL-1+
A0-8 A9,11
BA0,1
ACT#0 ACT#1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS
read latency
A0-8 A9,11 BA0,1
CL=3
CL=3
CL=3
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Page Mode Burst Write (multi bank) @BL=4
tRRD
/RAS
tRCD
/CAS A0-8 A9,11
BA0,1
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
tRRD
/RAS
tRCD
/CAS
read latency=2
A0-8 A9,11 BA0,1
CL=3
CL=3
CL=3
ACT#0
READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Write Interrupted Write Read @BL=4
tRRD
/RAS
tRCD tCCD
/CAS
A0-8
A9,11
BA0,1
CL=3
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write interrupted Write Read active bank. Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Read Interrupted Read Write @BL=4 CL=3
tRRD
/RAS
tRCD
/CAS
read latency=2
A0-8 A9,11 BA0,1
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank prevent contention
Burst Read interrupted Read Write active bank. Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Write Interrupted Precharge @BL=4
tRRD
/RAS
tRCD
/CAS A0-8 A9,11
BA0,1
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write interrupted Precharge other bank.
Burst Write interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Read Interrupted Precharge @BL=4 CL=3
tRRD
/RAS
tRCD tRCD
/CAS
read latency=2
A0-8 A9,11 BA0,1
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read interrupted Precharge other bank.
Burst Read interrupted Precharge same bank. Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Mode Register Setting
tRSC
/RAS
tRCD
/CAS A0-8 A9,11 BA0,1
Auto-Ref (last cycles) Mode Register Setting ACT#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Auto-Refresh @BL=4
/RAS
tRCD
/CAS A0-8 A9,11
BA0,1
Auto-Refresh Before Auto-Refresh, banks must idle state.
ACT#0
WRITE#0
After from Auto-Refresh, banks idle state. Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Self-Refresh
stopped
/RAS /CAS
tSRX
must maintain Self-Refresh
A0-8 A9,11 BA0,1
Self-Refresh Entry Before Self-Refresh Entry, banks must idle state. Self-Refresh Exit ACT#0
After from Self-Refresh Exit, banks idle state. Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Write Mask @BL=4
/RAS
tRCD
/CAS A0-8 A9,11
BA0,1
masked
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Read Mask @BL=4 CL=3
/RAS
tRCD
/CAS
read latency=2
A0-8 A9,11
BA0,1
masked
masked
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Power Down
/RAS /CAS
Standby Power Down Active Power Down
latency=1
A0-8 A9,11
BA0,1
Precharge
ACT#0
Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Suspend @BL=4 CL=3
/RAS
tRCD
/CAS
latency=1 latency=1
A0-8 A9,11 BA0,1
ACT#0
WRITE#0 READ#0 suspended
suspended Italic parameter indicates minimum case
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
OUTLINE
31.75 20.00 4.00 6.00
MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM
Keep safety first your circuit designs!
Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap.
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MIT-DS-0374-0.4
MITSUBISHI ELECTRIC
26.Jan.2001

536,870,912-BIT (8,388,608 WORD 64-BIT)SynchronousDRAM MH8S64AQFC

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