Mobile Pentium processor speeds On-die, primary 16-K Instruction cache

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Pentium Processor Mobile Module: Mobile Module Connector (MMC-2)
Mobile Pentium processor speeds On-die, primary 16-K Instruction cache 16-K Write Back Data cache On-die, 256-K cache Eight-way associative Runs speed processor core Fully compatible with previous Intel mobile microprocessors Binary compatible with applications Support technology Supports streaming SIMD Power management features that provide low-power dissipation Quick Start mode Deep Sleep mode Integrated math co-processor Integrated Active Thermal Feedback (ATF) system Programmable trip point interrupt poll mode temperature reading
Intel 82443BX Host Bridge system controller DRAM controller supports 3.3-V SDRAM Supports CLKRUN# protocol SDRAM clock enable support selfrefresh SDRAM during Suspend mode control 3.3V only, Specification Revision compliant Supports single 66-MHz, 3.3-V device Two-piece thermal transfer plate (TTP) heat dissipation made nickel-plated copper made aluminum Pentium processor core voltage regulation supports input voltages from 7.5V 21.0V Above peak efficiency Integrated solution
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Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium processor mobile module contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. MPEG international standard video compression/decompression promoted ISO. Implementations MPEG CODECs, MPEG enabled platforms require licenses from various entities, including Intel Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1999, 2000 *Other brands names property their respective owners.
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Contents
Introduction. References Architecture Overview Signal Information Signal Definitions. 3.1.1 Signal List.5 3.1.2 Memory Signal Description 3.1.3 Signals 3.1.4 Signals. 3.1.5 Processor PIIX4E/M Sideband Signals 3.1.6 Power Management Signals 3.1.7 Clock Signals.13 3.1.8 Voltage Signals 3.1.9 JTAG Pins.15 3.1.10 Miscellaneous Pins.15 Connector Assignments Assignments Pentium Processor Mobile Module MMC-2.20 Cache 82443BX Host Bridge System Controller 4.3.1 Memory Organization 4.3.2 Reset Strap Options 4.3.3 Interface 4.3.4 Interface.22 Power Management 4.4.1 Clock Control Architecture.22 4.4.1.1 Normal State 4.4.1.2 Auto Halt State 4.4.1.3 Stop Grant State.25 4.4.1.4 Quick Start State 4.4.1.5 HALT/Grant Snoop State 4.4.1.6 Sleep State 4.4.1.7 Deep Sleep State Power Consumption Power Management Mode System Clock Signal Quality Specifications.28 5.1.1 BCLK Specifications.28 5.1.2 BCLK Specifications.28 System Power Requirements.30 Processor Core Voltage Regulation 5.3.1 Voltage Regulator Efficiency 5.3.2 Voltage Regulator Control
Functional Description.20
Electrical Specifications.28
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Power Planes: Bulk Capacitance Requirements. System Power Supply Protection Guidelines 5.3.4.1 Power System Protection. 5.3.4.2 V_DC Power Supply. 5.3.4.3 Overcurrent Protection 5.3.4.4 Current Limit Shift Point 5.3.4.5 Slew Rate Control 5.3.4.6 Undervoltage Lockout 5.3.4.7 Overvoltage Lockout Active Thermal Feedback Thermal Sensor Configuration Register. Module Dimensions. 6.1.1 Location MMC-2 Connector 6.1.2 Printed Circuit Board 6.1.3 Height Restrictions Thermal Transfer Plate Module Physical Support 6.3.1 Module Mounting Requirements 6.3.2 Module Weight Thermal Design Power.
5.3.3 5.3.4
Mechanical Specification.
Thermal Specification. Labeling Information. Environmental Standards.
Figures
Pentium Processor Mobile Module Block Diagram MMC-2 Connector Footprint Clock Control States BCLK Waveform Processor Core Pins Efficiency Chart Power Sequence Timing V_DC Ripple Current V_DC Power System Protection Block Diagram. Overcurrent Protection Circuit. Current Shift Model Undervoltage Lockout Undervoltage Lockout Model Overvoltage Lockout Overvoltage Lockout Model Recommended Power Supply Protection Circuit System Electronics Simulation V_DC Voltage Skew. Board Dimensions MMC-2 Connector Orientation. Board Dimensions MMC-2 Connector-Pin Orientation
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Printed Circuit Board Thickness Keep-out Zone.51 82443BX Thermal Transfer Plate (Reference Only) 82443BX Thermal Transfer Plate Detail.52 Thermal Transfer Plate (Reference Only).53 Standoff Holes, Board Edge Clearance, Containment Ring Product Tracking Code.57
Tables
Connector Signal Summary Memory Signal Descriptions. Signal Descriptions Signal Descriptions. Processor PIIX4E/M Sideband Signal Descriptions Power Management Signal Descriptions Clock Signal Descriptions.13 Voltage Descriptions JTAG Pins.15 Miscellaneous Descriptions.15 Connector Assignment.16 Connector Specifications.19 Configuration Straps 82443BX Host Bridge System Controller Clock State Characteristics Power Consumption Values Power Consumption Values BCLK Specifications.28 BCLK Specifications Processor Core Pins.28 BCLK Signal Quality Specifications Processor Core.29 System Power Requirements.30 Vcore Power Conversion Efficiency Voltage Signal Definitions Sequences VR_ON In-rush Current.33 Bulk Capacitance Requirements Thermal Sensor SMBus Address Thermal Sensor Configuration Register Thermal Design Power Specification Environmental Standards
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Revision History
Date October 1999 February 2000 Revision Updates
Initial Release Revision contains following updates: PIIX4M references have changed PIIX4E/M because both parts used Section 4.5, which contains power consumption values power management modes entire Sections clarity 5.3.4 updated accuracy clarity efficiency values were updated Table Figure Previously, values were shown 1.35V Figure Intel SpeedStep technology signal removed Table consistent with schematics note Figure clarification added additional thermal transfer plate detail clarifications were made Section Section 6.3.1 Revision contains following updates: Table "Power Consumption Values II", which contains power management data conversion modules B-step modules Table "BCLK Signal Quality Specifications Processor Core" note updated clarification maximum minimum designators Figure "BCLK Waveform Processor Core Pins" clarity Section 5.3.3, "Power Planes: Bulk Capacitance Requirements" clarity Revision contains following updates: product tracking numbers Table
April 2000
September 2000
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Introduction
This document provides technical specifications integrating Intel Pentium processor mobile module connector (MMC-2) into latest notebook systems today's notebook market. Building around this design gives system manufacturer these advantages:
Avoids complexities associated with designing high-speed processor core logic boards. Provides upgrade path from previous Intel mobile modules using standard interface.
References
Refer following documents additional information relating Pentium processor mobile module. Mobile Pentium Processor Datasheet Intel 440BX AGPSet: 82443BX Host Bridge/Controller Datasheet (Order Number: 290633-001) 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) (Order Number: 290562-001) Intel 82371MB (PIIX4E/M) Specification Update* CK97 Clock Synthesizer/Driver Specification (OR-1089) Intel Pentium Processor Mobile Module MMC-2 Simulation Validation Rev. (OR1781) Intel Pentium Processor Mobile Module System Electronics 100-MHz Layout Guidelines Rev. (OR-1780) Mobile Pentium Processor/440BX AGPset Recommended Design Debug Practices (RDDP-A) Rev. (SC-2760) 66/100MHz SDRAM Unbuffered SO-DIMM Specification 1.0* Intel Mobile Module Design Guide (AP-590) Pentium® Processor Mobile Module MMC-2 Insertion Extraction User Manual 1.0* Mobile Pentium Processor Mobile Module 400-Pin Connector Assembly Development Guide Rev. 1.0* Focused Discussion Intel Mobile Modules Design Mfg. Best Methods MHPG Customers Rev. (OR-1385) Design Guide (ORMD6-0859) Intel Mobile Module Newsletters* Intel Mobile Module Thermal Diode Temperature Sensor Application Note* Intel MMC-2 Standoff/Receptacle Height Spreadsheet* Interface Specification Revision 2.0*
*Available now, contact your Intel Field Representative
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Architecture Overview
highly integrated assembly, Pentium processor mobile module contains mobile Pentium processor core that runs speeds with 100-MHz processor system speed (PSB). Intel 440BX AGPset provides immediate system-level support includes PIIX4E/M PCI/ISA Bridge 82443BX Host Bridge. PIIX4E/M provides extensive power management capabilities supports Intel 82443BX Host Bridge. notebook's system electronics must include PIIX4E/M device connect Pentium processor mobile module. features Intel 82443BX Host Bridge include: DRAM controller supporting SDRAM 3.3Vwith burst read 4-1-1-1; CLKRUN# signal request PIIX4E/M regulate clock bus; 82443BX clock enables Self-Refresh mode SDRAM during Suspend mode compatible with SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM) modes power management; E_SMRAM mode supports write-back cacheable SMRAM thermal transfer plates (TTP) mobile Pentium processor 82443BX Host Bridge provide heat dissipation thermal attach points manufacturer's thermal solution. on-board voltage regulator converts system voltage processor's core voltage. Isolating processor voltage requirements allows system manufacturer incorporate different processor variants into single notebook system. Supporting input voltages from 7.5V 21.0V, integrated module voltage regulator enables above peak efficiency de-couples processor voltage requirements from system. Also incorporated active thermal feedback (ATF) sensing, compliant with ACPI Specification 1.0. Figure illustrates block diagram mobile module.
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Figure Pentium Processor Mobile Module Block Diagram
Processor Core Voltage
Mobile Pentium Processor Core
Voltage
Sense
Sideband Pullup (V_CPUPU)
Clock Driver (V_CLK)
V_DC (7.5V- 21.0V)
Memory
GCLKO
400-Pin, Board-to-Board Connector
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GCLKI
PCLK
PIIX4E/M Sidebands
HCLK0
82443BX "Northbridge"
DCLKWR SMBUS
DCLKO
Pentium Processor Mobile Module MMC-2
Signal Information
This section provides information signal groups Pentium processor mobile module. signals defined compatibility with future Intel mobile modules.
Signal Definitions
Table provides list signals category corresponding number signals each category. proper signal termination, please contact your Intel Field Representative more information.
Table
Connector Signal Summary
Signal Group Memory Processor/PIIX4E/M Sideband Power Management Clocks Voltage: V_DC Voltage: V_3S Voltage: Voltage: Voltage: VCCAGP Voltage: V_CPUPU Voltage: V_CLK ITP/JTAG Module Ground Reserved Total Number Pins
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3.1.1
Signal List
following notations used denote signal type: Input Output Open-drain output requiring pullup resistor Open-drain input requiring pullup resistor Input/Open-drain output requiring pullup resistor Bi-directional input/output
signal description also includes type buffer used particular signal: GTL+ CMOS Open-drain GTL+ interface signal interface signals interface signals CMOS signals, depending functional group, 1.5V, 2.5V, 3.3V.
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3.1.2
Memory Signal Description
Table provides descriptions memory interface signals.
Table
Memory Signal Descriptions
Name Type CMOS CMOS CMOS Voltage Description Memory Data: These signals carry Memory data during access DRAM. supported mobile module. Chip Select (SDRAM): These pins activate SDRAMs. SDRAM accepts command when active low. Input/Output Data Mask (SDRAM): These pins synchronized output enables during read cycle byte mask during write cycle. Memory Address (SDRAM): This column address DRAM. 82443BX Host Bridge system controller identical sets address lines (MAA MAB#). mobile module supports only address lines. additional addressing features, please refer Intel 440BX AGPSet: 82443BX Host Bridge/ Controller Datasheet (Order Number: 290633-001). Memory Write Enable (SDRAM): MWEA# should used write enable memory data bus. SDRAM Address Strobe (SDRAM): When active low, this signal latches Address positive edge clock. This signal also allows access pre-charge. SDRAM Column Address Strobe (SDRAM): When active low, this signal latches Column Address positive edge clock. This signal also allows Column access. SDRAM Clock Enable (SDRAM): SDRAM clock enable pin. When these signals deasserted, SDRAM enters power-down mode. Each individually controlled clock enable. Memory Data: These signals connected DRAM data bus. They terminated mobile module.
MECC[7:0]
CSA[5:O]#
DQMA[7:0]
MAB[9:0]# MAB[10] MAB[12:11]# MAB[13] MWEA# CMOS CMOS CMOS CMOS CMOS CMOS
SRASA#
SCASA#
CKE[5:0]
MD[63:0]
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3.1.3
Signals
Table provides descriptions interface signals.
Table
Signal Descriptions
Name Type Voltage Description Address/Data: standard address data lines. This functions same AD[31:0] bus. address driven with FRAME# assertion, data driven received following clocks. Command/Byte Enable: This carries command information during cycles when PIPE# used. During write, this contains byte enable information. command driven with FRAME# assertion, byte enables corresponding supplied requested data driven following clocks. Frame: GFRAME# used during transactions. This signal remains deasserted internal pullup resistor. Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: This signal provides same function DEVSEL#, used during transactions. 82443BX Host Bridge system controller drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: GIRDY# indicates AGP-compliant target ready provide write data current transaction. This signal asserted when initiator ready data transfer. Target Ready: This signal indicates AGP-compliant master ready provide write data current transaction. GTRDY# asserted when target ready data transfer. Stop: This signal provides same function STOP#, used during transactions. GSTOP# asserted target request master stop current transaction. Request: master requests AGP. Grant: GGNT# provides same function PCI. Additional information provided ST[2:0] bus. Grant: Permission given master PCI. Parity: single parity provided over GAD[31:0] BE[3:0]. This signal used during transactions. Pipelined Request: PIPE# asserted current master indicate that full-width address queued target. master queues request each rising clock edge while PIPE# asserted. Sideband Address: This provides additional conduit pass address commands 82443BX Host Bridge System Controller from master. Read Buffer Full: Indicates master ready accept previously requested, low-priority read data.
GAD[31:]
GC/BE[3:0]#
GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GREQ#
GGNT#
GPAR
PIPE#
SBA[7:0]
RBF#
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Table
Signal Descriptions
Name ST[2:0] Type SBSTB Sideband Strobe: This signal provides timing sideband bus. SBA[7:0] (AGP master) drives sideband strobe. Voltage Description Status Bus: This provides information from arbiter Master what These bits only have meaning when GGNT asserted. Strobes: These signals provide timing double-clocked data bus. agent providing data drives these signals, signals identical copies each other.
ADSTB[B:A]
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3.1.4
Signals
Table provides descriptions signals.
Table
Signal Descriptions
Name AD[31:0] Type Voltage Description Address/Data: standard address data lines. address driven with FRAME# assertion, data driven received following clocks. Command/Byte Enable: command driven with FRAME# assertion, byte enables corresponding supplied requested data driven following clocks. Frame: Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: 82443BX Host Bridge drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Asserted when initiator ready data transfer. Target Ready: Asserted when target ready data transfer. Stop: Asserted target request master stop current transaction. Lock: Indicates exclusive operation require multiple transactions complete. When LOCK# asserted, non-exclusive transactions proceed. 82443BX supports lock initiated cycles only. initiated locked cycles supported. Request: master requests PCI. Grant: Permission given master PCI. Hold: This signal comes from expansion bridge. bridge request PCI. 82443BX Host Bridge will drain DRAM write buffers, drain processor-to-PCI posting buffers, acquire host before granting request PHLDA#. These processes ensure that timing masters. PHOLD# protocol been modified include support passive release. Hold Acknowledge: 82443BX Host Bridge drives this signal grant expansion bridge. PHLDA# protocol been modified include support passive release. Parity: single parity provided over AD[31:0] C/BE[3:0]#.
C/BE[3:0]
FRAME#
DEVSEL#
IRDY# TRDY# STOP#
PLOCK#
REQ[4:0]# GNT[4:0]#
PHOLD#
PHLDA#
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Table
Signal Descriptions
Name Type Voltage Description System Error: 82443BX asserts this signal indicate error condition. further information, refer Intel 440BX AGPSet: 82443BX Host Bridge/Controller Datasheet (Order Number: 290633001). Clock Run: open-drain output input. 82443BX Host Bridge requests central resource, PIIX4E/M, start maintain clock asserting CLKRUN#. 82443BX Host Bridge tristates CLKRUN# upon deassertion Reset (since running upon deassertion Reset). Reset: When asserted, this signal asynchronously resets 82443BX Host Bridge. signals also tri-state, compliant with Revision Specifications.
SERR#
CLKRUN#
PCI_RST#
CMOS
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3.1.5
Processor PIIX4E/M Sideband Signals
Table provides descriptions processor PIIX4E/M sideband signals.
Table
Processor PIIX4E/M Sideband Signal Descriptions
Name Type CMOS CMOS CMOS CMOS Voltage Description Numeric Co-processor Error: This signal functions FERR# signal supporting co-processor errors. This signal tied coprocessor error signal processor pulled active processor PIIX4E/M. Ignore Error: This open-drain signal connected Ignore Error processor driven PIIX4E/M. Initialization: INIT# asserted PIIX4E/M processor system initialization. This signal open-drain. Processor Interrupt: PIIX4E/M drives INTR signal processor that interrupt request pending needs serviced. This signal open-drain. Non-maskable Interrupt: used force non-maskable interrupt processor. PIIX4E/M bridge generates when either SERR# IOCHK# asserted, depending Status Control Register programmed. This signal opendrain. Address Mask: When enabled, this open-drain signal causes processor emulate address wraparound which occurs Intel 8086 processor. System Management Interrupt: SMI# active-low synchronous output from PIIX4E/M that asserted response many enabled hardware software events. SMI# open-drain signal asynchronous input processor. However, this chipset SMI# synchronous PCLK. Stop Clock: STPCLK# active-low, synchronous open-drain output from PIIX4E/M that asserted response many hardware software events. STPCLK# connects directly processor synchronous PCICLK. When processor samples STPCLK# asserted, responds entering low-power state (Quick Start). processor will only exit this mode when this signal deasserted.
FERR#
V_CPUPU
IGNNE# INT#
V_CPUPU V_CPUPU
INTR
V_CPUPU
CMOS
V_CPUPU
A20M#
CMOS
V_CPUPU
SMI#
CMOS
V_CPUPU
STPCLK#
CMOS
V_CPUPU
NOTE: Table V_CPUPU definition.
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3.1.6
Power Management Signals
Table provides descriptions power management signals. SM_CLK SM_DATA signals refer two-wire serial SMBus interface. Although this interface currently used solely digital thermal sensor, SMBus contains reserved serial addresses future use.
Table
Power Management Signal Descriptions
Name SUS_STAT1# Type CMOS Voltage V_3ALWAYS Description Suspend Status: This signal connects SUS_STAT1# output PIIX4E/M. provides information host clock status asserted during suspend states. VR_ON: Voltage regulator This 3.3-V (5.0-V tolerant) signal controls operation voltage regulator. VR_ON should generated function PIIX4E/M SUSB# signal, which used controlling "Suspend State voltage planes. This signal should driven digital signal with rise/fall time less than equal (VIL (max) 0.4V, (min) 3.0V.) VR_PWRGD: mobile module drives this signal high indicate that voltage regulator stable. signal pulled using 100-K resistor when inactive, used some combination generate system PWRGOOD signal. Power This signal must active least after power rail stable prior deassertion PCIRST#. Serial Clock: This clock signal used SMBus interface digital thermal sensor. Serial Data: Open-drain data signal SMBus interface digital thermal sensor. Interrupt: This signal open-drain output signal digital thermal sensor.
VR_ON
CMOS
VR_PWRGD
BXPWROK
CMOS CMOS CMOS CMOS
SM_CLK SM_DATA ATF_INT#
NOTE: V_3ALWAYS 3.3-V supply. generated whenever V_DC available supplied PIIX4E/M resume well.
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3.1.7
Clock Signals
Table provides descriptions clock signals.
Table
Clock Signal Descriptions
Name Type Voltage Description Clock PCLK, input mobile module, system's clocks. 82443BX Host Bridge logic uses this clock clock domain. This clock stopped when PIIX4E/ PCI_STP# signal asserted and/or during suspend states. Host Clock This clock input mobile module from CK100-M/CK100-SM clock source. processor 82443BX Host Bridge system controller HCLK0. This clock stopped when PIIX4E/M CPU_STP# signal asserted and/or during suspend states. Note: HCLK0 BCLK used interchangeably. HCLK1 CMOS CMOS V_CLK Host Clock This clock input mobile module from CK100-M/CK100-SM clock source. This signal implemented mobile module. SDRAM Clock Out: 66-MHz SDRAM clock reference generated internally 82443BX Host Bridge system controller onboard PLL. feeds external buffer that produces multiple copies SODIMMs. SDRAM Read Clock: Feedback reference from SDRAM clock buffer. 82443BX Host Bridge System Controller uses this clock when reading data from SDRAM array. This signal implemented mobile module. DCLKWR CMOS CMOS SDRAM Write Clock: Feedback reference from SDRAM clock buffer. 82443BX Host Bridge system controller uses this clock when writing data SDRAM array. Clock GCLKIN input feedback reference from GCLKO signal. Clock Out: This signal generated 82443BX Host Bridge system controller onboard from HCLK0 host clock reference. frequency GCLKO MHz. GCLKO output used feed both reference input pins 82443BX Host Bridge system controller device. board layout must maintain complete symmetry loading trace geometry minimize clock skew. Frequency Select: This output indicates desired host clock frequency mobile module.
PCLK
HCLK0
CMOS
V_CLK
DCLK0
DCLKRD
CMOS
GCLKIN
GCLKO
CMOS
CMOS
V_3S
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3.1.8
Voltage Signals
Table provides descriptions voltage signals.
Table
Voltage Descriptions
Name V_DC V_3S Type Number pins Input: 7.5V 21.0V SUSB# Controlled 3.3V: Power managed 3.3-V supply. output voltage regulator system electronics. This rail during STR, STD, Soff. SUSC# Controlled 5.0V: Power managed 5.0-V supply. output voltage regulator system electronics. This rail during Soff. SUSC# Controlled 3.3V: Power managed 3.3-V supply. output voltage regulator system electronics. This rail during Soff. Voltage: This voltage rail implemented mobile module defined upgrade purposes only. Intel recommends that this voltage rail connected system electronics. Processor Ring: mobile module drives V_CPUPU power processor interface signals, such PIIX4E/M opendrain pullups processor PIIX4E/M sideband signals. V_CPUPU tied 1.5V. Processor Clock Rail: mobile module drives V_CLK power CK100-M VDDCPU rail. Description
VCCAGP
V_CPUPU
V_CLK
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3.1.9
JTAG Pins
Table provides descriptions JTAG signals, which system manufacturer implement JTAG chain port desired.
Table
JTAG Pins
Name TCLK TRST# FS_PREQ# FS_PRDY# FS_RESET# Type Voltage V_CPUPU Description JTAG Test Data Out: serial output port. instructions data shifted processor from this port. JTAG Test Data serial input port. instructions data shifted into processor from this port. JTAG Test Mode Select: Controls controller change sequence. JTAG Test Clock: Testability clock clocking JTAG boundary scan sequence. JTAG Test Reset: Asynchronously resets controller processor. Debug Mode Request: Driven makes request enter debug mode. Debug Mode Ready: Driven processor informs that processor debug mode. Processor Reset: Processor reset status ITP. GTL+ Termination Voltage: POWERON uses debug port determine when target system POWERON pulled using resistor VTT. Other signals might this power rail pullup.
NOTE: FS_RESET# FS_PRDY# pulled inside mobile Pentium processor core.
3.1.10
Miscellaneous Pins
Table provides descriptions miscellaneous signal pins.
Table Miscellaneous Descriptions
Name Module ID[3:0] Ground Reserved Type CMOS RSVD Number Reserved pins must connected. Description Module Revision These pins track revision level mobile module. 100-K pullup resistor V_3S must placed system electronics these signals. Section more detail. Ground Unallocated Reserved pins.
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Connector Assignments
Table lists signals each connector system electronics. Refer Section assignments.
Table Connector Assignment
Number SBA5 GAD25 GAD30 RBF# BXPWROK MD36 MD41 MD43 MD14 MECC4 SCASA# CSA1# SRASA# RESERVED RESERVED RESERVED MAB8# RESERVED MAB13 CKE1 CKE5 RESERVED FS_RESET# FS_PRDY# RESERVED RESERVED ADSTBB GAD24 GAD29 VCCAGP GAD1 RESERVED MD33 MD38 MD42 MD11 MD45 MECC0 MWEA# MID1 DQMA4 CSA2# CSA5# RESERVED MAB4# RESERVED RESERVED MAB11# MID2 CKE2 RESERVED SMCLK SMDAT SBA6 GAD26 GAD4 GAD3 GAD2 MD37 MD40 MD44 ND15 MECC5 DQMA0 MID0 CSA4# MAB0# MAB2# MAB5# RESERVED MAB12# CKE3 MID3 DQMA2 RESERVED MD26 MD58 GAD31 SBA4 GAD27 GAD6 GAD5 ADSTBA CLKRUN# MD32 MD35 MD39 MD10 MD13 ND47 RESERVED DQMA1 DQMA5 CSA3# MAB1# RESERVED RESERVED RESERVED MSB9# RESERVED CKE0 RESERVED DCLKWR FS_PREQ# MD57 TCLK SBA7 SBA0 GDA8 GC/BE0# GAD7 MD34 MD34 MD12 ND46 RESERVED CSA# RESERVED MAB3# MAB6# MAB7# MAB10 DCLK0 DCLKRD RESERVED# DQMA3 MD25 MD60 FERR# IGNNE#
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Table Connector Assignment
Number RESERVED RESERVED V_CPUPU V_CLK RESERVED V_DC V_DC RESERVED V_DC V_DC RESERVED V_3S V_3S V_3S RESERVED V_DC V_DC TRST# V_3S V_3S V_3S RESERVED V_DC V_DC ATF_INT# V_3S V_3S V_3S RESERVED V_DC V_DC
Number
GREQ# GGNT# GAD13 GAD12 GAD10 GAD11 GAD9 VCCAGP MECC1 SERR# AD16 AD19 AD23 AD27 PCI_RST# RESERVED IRDY# GNT1# DQMA6 MECC2
GSTOP# GPAR GAD15 GC/BE1# GAD14 VCCAGP C/BE0# AD10 AD13 TRDY# AD30 AD22 PHOLD# FRAME# GNT2# GNT4# PHLDA# MECC7 MD48
PIP# SBA1 SBA2 GAD16 GAD18 GFRAME# GTRDY# GDEVESEL# AD15 STOP# AD17 AD24 C/BE3# AD20 AD31 REQ2# GNT0# MD50 MD18
SBA3 SBSTB GAD20 GAD17 GC/BE2# GIRDY# VCCAGP AD12 C/BE1# DEVSEL# C/BE2# AD26 AD28 AD29 REQ1# REQ3# REQ4# MD51 MD52
GCLKI CGLK0 GAD23 GC/BE3# GAD22 GAD21 GAD19 GAD28 AD11 AD14 PLOCK# AD18 AD21 PCLK AD25 REQ0# GNT3# MD59 MD54 MD24
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DQMA7 MECC6 MECC3 MD27 DMI# A20M# RESERVED V_DC V_DC
MD16 MD17 MD49 MD28 MD29 INTR SUS_STAT1# STPCLK# RESERVED V_DC V_DC
MD19 MD21 MD20 MD61 VR_ON VR_PWRGD INIT# RESERVED V_DC V_DC
MD53 MD22 MD62 MD30 RESERVED V_DC V_DC
MD23 MD55 MD56 MD63 MD31 HCLK0 HCLK1 RESERVED V_DC V_DC
Assignments
400-pin MMC-2 connector 1.27-mm pitch style surface mount. Refer Section 6.1.3 size information. Figure shows MMC-2 connector assignments.
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Figure MMC-2 Connector Footprint
400-Pin Connector Footprint Assignments
Table summarizes some connector specifications. Table Connector Specifications
Parameter Contact Material Housing Current Voltage Electrical Insulation Resistance Termination Resistance Capacitance Mating Cycles Mechanical Connector Mating Force Contact Unmating Force Thermo-Plastic Molded Compound: 0.5A 20-m maximum 20-mV open circuit with 5-pF maximum contact Cycles (22.7 maximum (13.6 maximum Condition Copper Alloy Specification
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Functional Description
Pentium Processor Mobile Module MMC-2
mobile Pentium processor core runs speeds with 100-MHz PSB.
Cache
on-die cache eight-way associative, runs speed processor core.
82443BX Host Bridge System Controller
Intel's 82443BX Host Bridge system controller highly integrated device that combines controller, DRAM controller, controller into component. 82443BX Host Bridge multiple power management features designed specifically notebook systems such
CLKRUN#, feature that enables controlling clock off. 82443BX Host Bridge suspend modes, which include Suspend-To-RAM (STR), SuspendTo-Disk (STD), Power-On-Suspend (POS).
System Management (SMRAM) power management modes, which include Compatible
SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM). C_SMRAM traditional SMRAM feature implemented Intel chipsets. E_SMRAM feature that supports write-back cacheable SMRAM space minimize power consumption while system idle, internal 82443BX Host Bridge clock turned (gated off) when there processor activity. This accomplished setting G_CLK enable power management register 82443BX through system BIOS.
4.3.1
Memory Organization
memory interface 82443BX Host Bridge available connector. This allows following:
memory control signals, sufficient support three SO-DIMM sockets
banks SDRAM MHz.
signal each bank.
Memory features supported 82443BX Host Bridge system controller standard MMC-2 mode are:
Eight banks memory 256-Mb memory devices Second memory address lines (MAA[13:0])
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Extended Data (EDO) DRAM 66-MHz memory
clocking architecture supports SDRAM. clocking mode 100-MHz SDRAM memory configurations allows host SDRAM clocks generated from same clocking source system electronics. complete details about memory device support, organization, size, addressing when using SDRAM memory trace length guidelines, refer Intel® Pentium® Processor Mobile Module System Electronics 100-MHz Layout Guidelines Revision. (OR-1780).
4.3.2
Reset Strap Options
Several strap options memory address define behavior Pentium processor mobile module after reset. Other straps allowed override default settings. Table shows various straps their implementation.
Table Configuration Straps 82443BX Host Bridge System Controller
Signal MAB[12]# MAB[11]# MAB[10]# MAB[9]# MAB[7]# MAB[6]# Function Host Frequency Select Order Queue Depth Quick Start Select Disable Configuration Host Buffer Mode Select Module Default Setting Strapped high module strap, maximum queue depth Strapped high module Quick Start mode strap (AGP enabled) strap (standard MMC-2 mode) Strapped high module mobile buffers Optional Override System Electronics None None None Strap high disable None None
4.3.3
Interface
interface 82443BX Host Bridge available MMC-2 connector. 82443BX Host Bridge supports Clockrun protocol power management. this protocol, devices assert CLKRUN# open-drain signal when they require interface. Refer Mobile Design Guide complete details Clockrun protocol. 82443BX Host Bridge responsible arbitrating bus. 82443BX Host Bridge support five masters. There five Request/Grant pairs (REQ[4:0]# GNT[4:0]#) available connector system electronics. Note: interface MMC-2 connector 3.3V only. devices that 5.0V supported. 82443BX Host Bridge system controller compliant with Specification, which improves worst case access latency from earlier specifications. 82443BX Host Bridge supports only Mechanism accessing configuration space. This implies that signals AD[31:11] available IDSEL signals. However, since 82443BX Host Bridge
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always device AD11 will never asserted during configuration cycles IDSEL. 82443BX reserves AD12 AGPbus. Thus, AD13 first available address line usable IDSEL. Intel recommends that AD18 used PIIX4E/M.
4.3.4
Interface
82443BX Host Bridge system controller compliant with Interface Specification Revision 2.0, which supports asynchronous interface coupling 82443BX core frequency. interface achieve real data throughput excess second using graphics device. Actual bandwidth vary depending specific hardware software implementations.
4.4.1
Power Management
Clock Control Architecture
clock control architecture been optimized notebook designs. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep, Deep Sleep states. Auto Halt state provides low-power clock state that controlled through software execution instruction. Quick Start state provides very low-power, low-exit latency clock state that used hardware controlled "idle" states. Deep Sleep state provides extremely low-power state that used Power-On-Suspend states, which alternative shutting processor's power. exit latency Deep Sleep state mobile module. Stop Grant state Quick Start clock state mutually exclusive. example, strapping option signal A15# chooses which state entered when STPCLK# signal asserted. Strapping A15# signal ground Reset enables Quick Start state. Otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Table provides information clock control states Figure illustrates clock control architecture. Performing state transitions shown Figure neither recommended supported.
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Table Clock State Characteristics
Clock State Normal Auto Halt Stop Grant Approximately clocks clocks Through Snoop, HALT/Grant Snoop state: immediate Through STPCLK#, Normal state: clocks clocks after snoop activity Stop Grant state clocks Exit Latency Snooping System Uses Normal program execution Software controlled entry idle mode Hardware controlled entry/exit mobile throttling Hardware controlled entry/exit mobile throttling Supports snooping lowpower states Hardware controlled entry/exit desktop idle mode support Hardware controlled entry/exit mobile support Note Note Notes Note Note Note
Quick Start
Note
HALT/Grant Snoop Sleep Deep Sleep
NOTES: Intel mobile modules support Sleep Stop Grant clock states. These values 100% tested specified 50°C design characterization. This value 100% tested specified 35°C design characterization. Specification labeled available.
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Figure Clock Control States
STPCLK#
Normal State
HS=false
(!STPCLK# !HS) RESET# halt cycle halt break STPCLK# !STPCLK#
Quick Start
BCLK stopped BCLK
STPCLK# !QSE (!STPCLK# !HS) stop break !STPCLK# STPCLK# !QSE
Auto Halt
HS=true
Snoop serviced
Snoop occurs
Deep Sleep
Snoop occurs Snoop serviced Snoop occurs Snoop serviced
Stop Grant
HALT/Grant Snoop
SLP# !SLP# RESET# BCLK stopped
BCLK !QSE
Sleep
NOTES: Halt break A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI# instruction executed Processor Halt State Quick Start State Enabled Stop Grant Acknowledge cycle issued Stop break BINIT#, FLUSH#, RESET# Intel mobile modules support shaded clock control states
4.4.1.1
Normal State
Normal states normal operating mode where processor's core clock running, processor actively executing instructions.
4.4.1.2
Auto Halt State
This low-power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, SMI#).
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Asserting STPCLK# signal while Auto Halt state will cause processor transition Stop Grant state Quick Start state, where Stop Grant Acknowledge cycle will issued. Deasserting STPCLK# will cause processor return Auto Halt state without issuing Halt cycle. SMI# (System Management Interrupt) recognized Auto Halt state. return from handler either Normal state Auto Halt state. Intel® Architecture Software Developer's Manual, Volume III: System Programmer's Guide more information. Halt cycle issued when returning Auto Halt state from System Management Mode (SMM). FLUSH# signal serviced Auto Halt state. After flushing on-chip, processor will return Auto Halt state without issuing Halt cycle. Transitions A20M# PREQ# signals recognized while Auto Halt state.
4.4.1.3
Stop Grant State
Intel mobile modules support Stop Grant state. desktop systems, processor enters this mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still able respond snoop requests latch interrupts. Latched interrupts will serviced when processor returns Normal state. Only occurrence each interrupt event will latched. transition back Normal state made deassertion STPCLK# signal, occurrence stop break event BINIT#, FLUSH#, RESET# assertion). processor will return Stop Grant state after completion BINIT# initialization unless STPCLK# been deasserted. RESET# assertion will cause processor immediately initialize itself. However, processor will stay Stop Grant state after initialization until STPCLK# deasserted. FLUSH# signal asserted, processor will flush on-chip caches return Stop Grant state. transition Sleep state made assertion SLP# signal. While Stop Grant state, assertions SMI#, INIT#, INTR, LINT[1:0]) will latched processor. These latched events will serviced until processor returns Normal state. Only each event will recognized upon return Normal state.
4.4.1.4
Quick Start State
This mode entered processor with assertion STPCLK# signal when configured Quick Start state (via A15# strapping option). Quick Start state processor only capable acting snoop transactions generated priority device. Because snooping behavior, Quick Start only used single processor configurations. transition Deep Sleep state made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state processor limited ability respond input. incapable latching interrupts, servicing snoop transactions from symmetric masters, responding FLUSH# BINIT# assertions. Quick Start state, processor will respond properly input signal other than STPCLK#, RESET#, BPRI#. other input signal changes, then behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state.
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RESET# assertion will cause processor immediately initialize itself, processor will stay Quick Start state after initialization until STPCLK# deasserted.
4.4.1.5
HALT/Grant Snoop State
processor will respond snoop transactions while Auto Halt, Stop Grant, Quick Start state. When snoop transaction presented system bus, processor will enter HALT/Grant Snoop state. processor will remain this state until snoop been serviced quiet. After snoop been serviced, processor will return previous state. HALT/Grant Snoop state entered from Quick Start state, then input signal restrictions Quick Start state still apply HALT/Grant Snoop state (except those signal transitions that required perform snoop).
4.4.1.6
Sleep State
Intel mobile modules support Sleep state. desktop systems, Sleep state very low-power state which processor maintains context phase locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop Grant state SLP# signal asserted, causing processor enter Sleep state. SLP# signal recognized Normal state Auto Halt state. processor reset RESET# signal while Sleep state. RESET# driven active while processor Sleep state, then SLP# STPCLK# must immediately driven inactive ensure that processor correctly initializes itself. Input signals (other than RESET#) change while processor transitioning into Sleep state. Input signal changes these times will cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. While Sleep state processor enter lowest power state, Deep Sleep state. Removing processor's input clock puts processor Deep Sleep state. PICCLK removed Sleep state.
4.4.1.7
Deep Sleep State
Deep Sleep state lowest power mode processor enter while maintaining context. Stopping BCLK input processor enters Deep Sleep state, while Sleep state Quick Start state. proper operation, BCLK input should stopped state. processor will return Sleep state Quick Start state from Deep Sleep state when BCLK input restarted. lock latency, there 30-µS delay after clocks have started before this state transition happens. PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns when transitioning Deep Sleep state. input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion will result unpredictable behavior.
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Power Consumption Power Management Mode
power data broken down into each power rail. Each power rail supplied module through MMC-2 connector. total power values based typical power consumption. data captured Tamb 25°C, V_DC 18.0V. Note: power comumption values 100% tested have been characterized design. Table Table provide module power consumption values various power management modes. Because mobile modules with same frequencies have different printed circuit board (PCB) revisions, refer product tracking code (PTC) lists before each table below match correct power consumption information with correct mobile module. Table applies mobile modules with following PTCs.
PML50002001AB PML45002001AB PML50002201AC PML45002201AC
Table Power Consumption Values
State Auto Halt Quick Start Deep Sleep V_DC 2.19W 1.77W 1.29W 0.04W 0.08W 0.08W 0.08W 0.01W 2.27W 2.04W 0.24W 0.01W V_3S 0.57W 0.62W 0.45W 0.00W Total Power 4.17W 3.43W 1.35W 0.05W
NOTE: These power values should used power supply guidelines power management modes. They have some guardband added design margin. Therefore, total power does necessarily each power rail. "Total Power" individual "raw" power requirements with guardband added.
Table applies mobile modules with following PTCs.
PML50002101AA PML45002101AA
Table Power Consumption Values
State Auto Halt Quick Start Deep Sleep V_DC 2.19W 1.77W 1.29W 0.04W 0.08W 0.08W 0.08W 0.01W 2.27W 2.04W 0.24W 0.01W V_3S 0.57W 0.62W 0.45W 0.00W Total Power 4.17W 3.43W 1.35W 0.05W
NOTE: These power values should used power supply guidelines power management modes. They have some guardband added design margin. Therefore, total power does necessarily each power rail. "Total Power" individual "raw" power requirements with guardband added.
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Electrical Specifications
following section provides electrical specifications Pentium processor mobile module.
System Clock Signal Quality Specifications
HCLK0 BCLK signal names used interchangeably.
5.1.1
BCLK Specifications
Table BCLK Specifications
Symbol VIL,BCLK VIH,BCLK Parameter Input Voltage, BCLK Input High Voltage, BCLK 2.625 Unit
NOTE: VILX,min VIH,max only apply when BCLK stopped. BCLK should stopped state. Table BCLK voltage range specifications when BCLK running.
5.1.2
BCLK Specifications
Table BCLK Specifications Processor Core Pins
Parameter System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 2.85 2.55 0.175 0.175 100.0 10.0
Unit
Note Notes Notes Notes 1.7V, Notes 0.7V, Notes 0.9V 1.6V, Notes 1.6V 0.9V, Notes
0.875 0.875
NOTES: timings GTL+ CMOS signals referenced BCLK rising edge 1.25V. CMOS signals referenced 0.75V. internal core clock frequency derived from clock. clock core clock ratio determined during initialization predetermined Intel mobile module. BCLK period allows +0.5 tolerance clock driver variation. This value measured rising edge adjacent BCLKs 1.25V. jitter present must accounted component BCLK skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. -20.0 attenuation point, measured into 10.0-pF 2.0-pF load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. CK97 Clock Synthesizer/Driver Specification (OR-1089) further details. These values 100% tested specified design characterization clock driver requirement. Specifications labeled available.
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Table describes signal quality specifications processor core clock (BCLK) signal. Figure describes signal quality waveforms clock processor core pins proper signal termination, refer "Clocking Guidelines" section Mobile Pentium Processor/440BX AGPset Recommended Design Debug Practices (RDDP-A) Rev. (SC-2760). Table BCLK Signal Quality Specifications Processor Core
VIL,BCLK VIH,BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback BCLK Rising/Falling Slew Rate Parameter -0.3 -0.7 2.625 Unit V/nS Notes Notes Undershoot, Overshoot, Note Absolute Value, Notes Absolute Value, Notes Notes
NOTES: rising edge BCLK, there must minimum overshoot 2.0V. clock must rise monotonically between VIL,BCLK 2.0V fall monotonically between VIH,BCLK VIL,BCLK. These specifications apply only when BCLK running. Table specifications when BCLK stopped. BCLK above VIH,BCLK,MAX below VIL,BCLK,MIN more than clock cycle. rising edge ringback voltage specified minimum (rising) absolute voltage that BCLK signal back after passes VIH,BCLK,MIN (rising) voltage limits.The falling edge ringback voltage specified maximum (falling) absolute voltage that BCLK signal back after passes VIL,BCLK,MAX (falling) voltage limits. Specifications labeled available.
Figure BCLK Waveform Processor Core Pins
V3MAX
V2MIN
V1MAX
V3MIN
V0012-00
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System Power Requirements
Table provides power supply design criteria.
Table System Power Requirements
Symbol IDC_RMS IDC_Surge I5_Surge I3_Surge VCPUPU ICPUPU VCLK ICLK Parameter Input Voltage Input Current Ripple Current Maximum Surge Current Power Managed 5.0-V Supply Power Managed 5.0-V Current, Operating Maximum Surge Current Power Managed 3.3-V Supply Power Managed 3.3-V Current Maximum Surge Current Processor Ring Voltage Processor Ring Current Processor Clock Rail Voltage Processor Clock Rail Current 4.75 20.0 3.135 1.375 2.375 24.0 12.0 50.0 10.0 35.0 21.0 20.0 5.25 100.0 3.465 1.625 20.0 2.625 80.0 Unit Note Notes Notes Notes Notes Notes Notes
NOTES: V_DC 12.0V order determine typical V_DC current. V_DC 7.5V order determine maximum V_DC current. 20-µS duration. This V_DC dependent. Figure data IDC-RMS V_DC. These values system dependent. Specifications labeled applicable.
Processor Core Voltage Regulation
voltage regulator (DC/DC converter) supports core voltage ring voltage. voltage regulator provides appropriate processor core voltage, GTL+ termination voltage, processor sideband signal pullup voltage, clock driver buffer voltage. these voltages, only processor sideband pullup voltage (V_CPUPU) clock driver buffer voltage (V_CLK) delivered system electronics. voltage range 7.5V 21.0V from system battery power supply mobile applications.
5.3.1
Voltage Regulator Efficiency
There three voltage regulators mobile module. These voltage regulators generate core voltage used voltage ring voltage. core voltage regulator provides required current from V_DC supply relative efficiencies shown Table Figure V_CLK voltage regulators plane.
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Table Vcore Power Conversion Efficiency
Vcore Icore Efficiency V_DC 7.50V Efficiency V_DC 12.0V Efficiency V_DC 21.0V
Figure Efficiency Chart
Efficiency
Icore(A)
Efficiency(%)
V_DC 7.5V V_DC V_DC
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5.3.2
Voltage Regulator Control
VR_ON connector allows 3.3-V signal control voltage regulator. system manufacturer this signal turn voltage regulator off. VR_ON should controlled function same signal (SUSB#) used control system's switched 5.0-V 3.3-V power planes. PIIX4E/M defines Suspend Power Management state which power physically removed from processor voltage regulator. this state, SUSB# PIIX4E/M controls these power planes. mobile module provides VR_PWRGD signal, which indicates that voltage regulator power operating stable voltage level. system manufacturer should this signal system electronics control power inputs gate PWROK PIIX4E/M South Bridge. Table provides detailed definitions sequences voltage signals.
Table Voltage Signal Definitions Sequences
Signal Source Definitions Sequences V_DC required between 7.5V 21.0V driven system electronics' power supply. V_DC powers Pentium processor mobile module DC-to-DC converter processor core voltages. mobile module cannot inserted removed while V_DC powered System Electronics System Electronics supplied system electronics voltage regulator. supplied system electronics 82443BX powers mobile module's linear regulators generating V_CLK V_CPUPU voltage rails. stays during suspend. V_3S supplied system electronics, V_3S shut during suspend. VR_ON 3.3-V signal that enables voltage regulator circuit. When driven active high, voltage regulator circuit activated. signal driving VR_ON should digital signal with rise fall time less than equal (VIL (max)= 0.4V, (min)= 3.0V.) result VR_ON being asserted, V_CORE output DCDC regulator mobile module driven core voltage processor. Upon sampling voltage level V_CORE (minus tolerances ripple), VR_PWRGD driven active high. VR_PWRGD sampled active within second assertion VR_ON, then system electronics should deassert VR_ON. After V_CORE stabilized, VR_PWRGD will assert logic high (3.3V). This signal must pulled system electronics. VR_PWRGD should "logically ANDed" with V_3S generate PIIX4E/M input signal, PWROK. system electronics should monitor VR_PWRGD verify that asserted high prior active high assertion PIIX4E/M PWROK. V_CPUPU 1.5V. system electronics uses this voltage power PIIX4E/M-to-processor interface circuitry. V_CLK 2.5V. system electronics uses this voltage power HCLK[0:1] drivers processor clock.
V_DC
System Electronics
V_3S
System Electronics
VR_ON
System Electronics
V_CORE
Module
VR_PWRGD
Module
V_CPUPU V_CLK
Module Module
following list includes additional specifications clarifications power sequence timing Figure provides illustration.
VR_ON signal only asserted logical high digital signal after V_DC
7.5V, 4.5V, 3.0V.
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Rise Time Fall Time VR_ON must less than equal VR_ON (max) +0.4V (min) +3.0V. VR_PWRGD will asserted logic high (3.3V) after V_CORE stabilized V_DC
reaches 7.5V. This signal should pulled system electronics.
power-on process, Intel recommends raise higher voltage power plane first
(V_DC), followed lower power planes (V_5, V_3), finally assert VR_ON after above voltage levels rails. powering off, follow reverse process, i.e. VR_ON gets deasserted, followed lower power planes, finally higher power planes.
VR_ON must monotonically rise through fall through points.
sign slope change between rising falling. following values listed Table Table VR_ON In-rush Current
Instantaneous Maximum Typical 41.0 Operating
VR_ON must provide instantaneous in-rush current mobile module with
VR_ON Valid-Low Time specifies long VR_ON needs valid off, before
VR_ON turned back again. going from valid then back following conditions must prevent damage system mobile module: VR_ON must original voltage level requirements turn-on must before assertion VR_ON (i.e. V_DC 7.5V, 4.5V, 3.0V).
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Figure Power Sequence Timing
V_DC V_3S NOTE
VR_ON VR_PWRGD V_CPUPU V_CLK
NOTE NOTE NOTE NOTE
NOTES: PWROK board should active when VR_PWRGD active V_3S good. CPU_RST from board should active minimum after PWROK active PLL_STP# CPU_STP# inactive. Note that PLL_STP# condition RSMRST# SUSB# PIIX4E/M. This power supplied MMC-2 connector. This should first 5.0-V plane power Stays during suspend. V_DC 7.5V, V_5>=4.5V, V_3S>=3.0V. VR_PWRGD specified active module regulator within less than equal 6.0-mS maximum after assertion VR_ON. V_CPUPU V_CLK generated mobile module.
5.3.3
Power Planes: Bulk Capacitance Requirements
placement sufficient bulk capacitance system electronics board critical operation mobile module ensure that system design accommodate future high frequency modules. Intel provided maximum possible bulk capacitance mobile module. However, order achieve proper filtering in-rush current protection, imperative that additional filtering provided system electronics board. Table details bulk capacitance requirements system electronics. Note: Observe voltage rating requirement capacitors each respective voltage rail.
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Table details bulk capacitance requirements system electronics. Table Bulk Capacitance Requirements
Bulk Capacitance Requirements Power Plane V_DC V_3S VCC_AGP V_CPUPU V_CLK Total Capacitance 100.0 100.0 470.0 100.0 22.0 10.0 20.0 100.0 100.0 100.0 100.0 Ripple Current 3.0A~ 5.0A 1.0A 1.0A 1.0A High Frequency Capacitance Requirements 0.01 0.01 0.01 0.01 0.01 8200.0 8200.0 Notes
Notes 1,3,4,5,6 Notes 1,4,5,6 Notes 1,4,5,6 Notes 1,4,5,6 Notes 1,4,5,6 Notes 1,5,6,7 Notes 1,2,5,6,7
NOTES: Placement above capacitance requirements should located near connector. V_CLK filtering should located next system clock synthesizer. Ripple current specification depends V_DC input mobile module. Figure below. Tantalum* Capacitors used, voltage derating practice must observed. example, 5.0-V rail requires 10.0-V rated capacitor. order reduce ESR, Intel recommends multiple bulk capacitors rather than single large capacitor. Intel strongly recommends that system manufacturers close attention capacitor design considerations. Specifically, "Capacitance Temperature De-rating Curve," "Capacitance Applied Voltage Derating Curve," "Capacitance Frequency De-rating Curve." Some capacitor dielectrics particularly susceptible these conditions, example ceramic capacitors. Specifications labeled available.
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Figure shows dependence V_DC ripple current V_DC. Figure V_DC Ripple Current
V_DC Input Ripple Current V_DC Voltage
6.00 5.50
Input Ripple Current(A)
5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00
V_DC(V)
5.3.4
5.3.4.1
System Power Supply Protection Guidelines
Power System Protection
recommended Power System Protection consists following:
Power Supply capable delivering 7.5V 21.0V mobile module Overcurrent Protection circuit providing means limit maximum current available
system
Slew Rate Control circuit providing controlled voltage slew rate turn which provides
protection components sensitive fast voltage rise times
Undervoltage Lockout circuit protect against potentially damaging high currents, which
might encountered Power Supply voltage
Overvoltage Lockout circuit providing protection from potentially damaging high
Power Supply voltages
Bulk Decoupling Capacitors providing filtering reservoir energy that give faster
transient response than power supply
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Figure V_DC Power System Protection Block Diagram
V_DC Power Supply
(See Table
Overcurrent Protection
(See Section 5.3.4.3)
Slew Rate Control
(See Section 5.3.4.5)
Bulk Decoupling Capacitors
Module
Undervoltage Lockout
(See Section 5.3.4.6)
Overvoltage Lockout
(See Section 5.3.4.7)
5.3.4.2
V_DC Power Supply
power supply must able deliver 7.5V 21.0V mobile module, measured mobile module.
5.3.4.3
Overcurrent Protection
overcurrent protection circuit provides limit current drawn mobile module. Under normal operating conditions, I_DC should expected exceed 3.0A V_DC 7.5V. allow component variations margining issues, reasonable I_DC current limit would 6.0A.
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Figure Overcurrent Protection Circuit
V_DC Power Supply 2.5V 2N2222A LM4040
NOTE: must able operate with inputs near V_DC rail. Consider LMC6762.
Over Current Protection
Slew Rate Control Si4435DY
V_DC
2N7000
V_DC
other V_DC input range, current will somewhat less. 14.0V, example, corresponding power could produced with only 3.0A. this example, comparator, U1A, will used sense when V_DC over 14.0V will shift current limit from 6.0A 3.0A.
I_DC(limit)= 6.0A I_DC(limit2)= 3.0A b(Q1)= R1=5.0 0.005 R12= 100.0 R13= 100.0 V(R14) 1.8V I(R20) 100.0 C36= 2.0K
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Figure Current Shift Model
V_DC
5.3.4.4
Current Limit Shift Point
Comparator should switch when non-inverting input equal 2.5-V reference inverting input, when voltage applied V_DC equal selected switch point voltage dropped across 2.5V. This drop should occur when V_DC= 14.0V.
Equation
V_DC Vref) Vref 2.5)
2000
(The nearest standard value 9.01 Comparator will pull output when V_DC falls below 14.0V. This drop will effectively parallel with R14. When power initially applied circuit, charges 2.5V through R20. This slowly rising voltage applied base current source, voltage approximately 2.5V minus base-emitter drop about 0.7V 25°C): V(R14) 1.8V. 2N2222A with moderate about 100. Therefore, current through approximately equal current through R14. charging C18, provides small increment delay will allow pull Gate until pulled non-inverting input down slightly. voltage developed across function load. Equation V(R1)= I_DC*R1
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maximum I_DC expected 3.0A, consider setting I_DC Current Limit 6.0A. Current Sense resistor, selected (0.005), maximum voltage developed across this resistor calculated. below. Consider case where V_DC above 14.0V. Equation I_DC(limit)*Rsense= 3.0A*5E-3= 15.0 Offset voltage applied inverting input comparator, U1B, should then 15.0 selected 100.0, current then calculated shown Equation below. Equation Ioffset= 15.0 mV/100= 150.0 Note: successful design, input offset comparator must considered. option that design offset least times greater than device offsets. value calculated shown Equation below. Equation R14= 1.8V/150.0 12.0 (The nearest value 12.1K.) Consider case when V_DC drops below 14.0V current limits shift 6.0A. Equation I_DC(limit)*Rsense= 6.0A*5E-3= 30.0 Offset voltage applied inverting input comparator, U1B, should then selected 100, current then calculated shown Equation below. Equation Ioffset= 30.0 mV/100= 300.0 value parallel combination calculated shown Equation below. Equation Rcombo= 1.8V/300.0 12.0-K resistor. also 12.0-K resistor, parallel combination will 6.0K. R20, LM4040-2.5 very wide operating current range from 60.0 15.0 order provide Current Source Base drive will need Equation Equation Ibase Ic/b= 300.0 µA/100=
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selected I(R20), would adequate Reference Current Source Base drive. Since both these currents must satisfied low-power supply margin, V_DC 7.5V will assumed. Equation (V_DC-Vref)/I(R20) (7.5-2.50)/100.0 50.0 allow component tolerances, 51.0 recommended.)
5.3.4.5
Slew Rate Control
Slew Rate Control regulates rate that power supply voltage applied system.
Threshold voltage -1.0V VGS(sat) -2.4V, also denoted Vsat 100.0 t_delay 500.0 Ctotal Bulk capacitors module capacitors 22.0 119.4
RDS(on) P-Channel MOSFET such Siliconix* Si4435DY. When power supply voltage applied increased value that exceeds Lockout value, (7.5V will used this example), Undervoltage Lockout circuit, allows pull gate start turn-on sequence. pulls drain toward ground, forcing current flow through will start source current until after t_delay, with t_delay defined shown Equation Equation below. Equation
t_delay R2.C9.ln V_DC
Equation
V_DC
published minimum threshold Si4435DY -1.0V, i.e. must charge 1.0V before starts turn delay, t_delay, time required charge 1.0V. Assuming negligible voltage drop across when voltage Gate with respect ground, voltage developed across V(R2). minimum steadystate bias -4.5V, this will voltage dropped across R16. V_DC margin, i.e. 7.5V, then derived from Equation below. Equation V_DC+VGS 7.5V- 4.5V 3.0V (with respect ground)
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Equation Vg.R16 V_DC 66.67
(The nearest standard value 66.5 example will continue with 66.5 Rearranging Equation solve yields following result, shown Equation Equation
R2.ln t_delay V_DC
value calculated. Equation below. Equation 0.354 close standard value 0.33 will yield t_delay 466.0 µS.) ramp-up time, t_ramp, defined shown Equation below. Equation
t_ramp R2.C9.ln Vsat t_delay
VGS(sat) -2.4V, then Equation below. Equation t_ramp 948.8 maximum current during power-up ramp shown Equation below. Equation
V_DC Imax Ctotal Ctotal t_ramp
total capacitance, Ctotal V_DC bus, 119.4 then Equation below. Equation Imax 0.994A From values assumed calculated, t_delay 466.0 t_ramp 949.0 Imax
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5.3.4.6
Undervoltage Lockout
circuit below shows Undervoltage Lockout portion V_DC Supply circuit. This circuit protects locks applied voltage mobile module prevent accidental turn-on V_DC supply voltages.
Warning:
voltage applied mobile module could result destructive current levels.
Figure Undervoltage Lockout V_DC_A V_DC_UVlock=7.5V R17=10 R25=1 VCEsat= 0.3V Vref=2.5V Gate V_DC Vref 2.5V
V_DC LM339
Undervoltage Lockout
output LM339 comparator open-collector when applied voltage V_DC less than 7.5V, which holds Gate low. Consequently, Slew Rate Controller allowed turn 2.5-V reference, Vref, voltage derived from Figure When non-inverting input comparator exceeds Vref, 2.5V, comparator trips allows output High state. Gate then pulled starting controlled Power-up Slew. model Figure will used calculate Undervoltage Lockout trip point.
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Figure Undervoltage Lockout Model
V_DC
2.5V VCEsat Undervoltage Lockout Model
VCEsat saturation voltage comparator output transistor. comparator trip point voltage calculated with Equation Equation
V_DC_UVlock Vref Vref Vref VCEsat
power mobile module held until V_DC exceeds 7.5V, Equation rearranged solve R18. Equation
Vref.R17.R25 R25.( V_DC_UVlock Vref) R17.( Vref VCEsat)
value determined plugging these values into Equation Equation 11.0 (4.99 standard resistor value, which would provide lockout below 7.532V.)
5.3.4.7
Overvoltage Lockout
mobile module operates with maximum input voltage 21.0V. This circuit lock input voltage exceeds desired input.
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Figure Overvoltage Lockout
V_DC_A R4=100K R24=100K R26=1M R27=1K
Gate
Vref 2.5V
V_DC V_DC LM339 Overvoltage Lockout
LM339 comparator open-collector output pulled when applied voltage V_DC high, thus disabling Slew-rate circuit. model Figure below will used component calculations. Figure Overvoltage Lockout Model V_DC_A V_DC
Vinv Vnoninv Vref
Overvoltage Lockout Model
Assume that desired V_DC Overvoltage Lockout 21.0V. Using Equation input non-inverting input Lockout comparator calculated with following equations.
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Equation
Vnoninv Vref R27.( V_DC_OVlock Vref)
Equation Vnoninv= 2.517V Equation
Vinv V_DC_OVlockR23)
output Lockout comparator will become active pull down when inverting input becomes greater than 2.517V input non-inverting input. Equation rearranged solve R23. Equation
R24.Vinv V_DC_OVlock Vinv
Lockout comparator trip point defined Vinv Vnoninv 2.517V. Equation provides solution R23. Equation R23= 13.618 (The nearest standard value 13.7 V_DC exceeds 6.0V, voltage Lockout comparator inverting input will exceed 2.517V causing comparator trip, pulling output disabling Power Skew Control circuit which, turn, will disconnect V_DC from mobile module.
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Figure Recommended Power Supply Protection Circuit System Electronics
V_DC Adaptor 27uF 2.5V LM339 2N2222A LM4040 V_DC V_DC LM339 LM339 V_DC 2N7000 V_DC 27uF 27uF 27uF 27uF 4.7uF 4.7uF V_DC
Over Current Protection
Slew Rate Control
Si4435DY
Input Bulk Decoupling Capacitors
Processor Module
Components values assumed calculated
5.62 100, 100, 12.1 0.33 71.5 12.1
2.5V
Under Voltage Lockout
V_DC V_DC LM339
Over Voltage Lockout
Figure Simulation V_DC Voltage Skew
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Active Thermal Feedback
Table Thermal Sensor SMBus Address
Function Thermal Sensor SMBus Address 1001
Thermal Sensor Configuration Register
configuration register thermal sensor controls operating mode (Auto Convert Standby) device. Since processor temperature varies dynamically during normal operation, Auto Convert mode should used exclusively monitor processor temperature. Table shows format configuration register. RUN/STOP low, then thermal sensor enters Auto Convert mode. RUN/STOP high, then thermal sensor immediately stops converting enters Standby mode. thermal sensor will still perform temperature conversions Standby mode when receives one-shot command. However, result one-shot command during Auto Convert mode guaranteed. Intel does recommend using one-shot command monitor temperature when processor active, only Auto Convert mode should used. thermal sensor configured various interface modes temperature sampling. Intel recommends interfacing thermal sensor using Interrupt mode. more detailed information regarding interface methods, please Intel Mobile Module Thermal Diode Temperature Sensor Application Note available through your Intel Field Representative.
Table Thermal Sensor Configuration Register
Name MASK RUN/STOP Reset State Function Masks SMBALERT# when high Standby mode control bit. low, device enters Auto Convert mode. high, device immediately stops converting enters Standby mode where one-shot command performed. Reserved future
NOTE: bits should written read "don't care" programming purposes.
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Mechanical Specification
This section provides physical dimensions Pentium processor mobile module.
Module Dimensions
Figure shows board dimensions connector orientation.
Figure Board Dimensions MMC-2 Connector Orientation
Module Mechanical X-Y-Z Dimensions Thermal Attach Points Unless otherwise specified: Tolerances Angles 0.5° 0.15 .XXX 0.075 Dimensions
6.1.1
Location MMC-2 Connector
Figure shows location 400-pin connector.
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Figure Board Dimensions MMC-2 Connector-Pin Orientation
6.1.2
Printed Circuit Board
Figure shows Pentium processor mobile module associated minimum maximum thickness printed circuit board (PCB). range thickness allows different technologies used with current future Intel mobile modules. Note: system manufacturer must ensure that mechanical restraining method and/or system-level contacts able support this range compatibility with future Intel mobile modules.
Figure Printed Circuit Board Thickness
Min: 0.90 Max: 1.10
Printed Circuit Board
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6.1.3
Height Restrictions
Figure shows mechanical stack-up associated component clearance requirements. This module keep-out zone should entered. system manufacturer establishes board-to-board clearance between module system electronics selecting three mating connectors available heights approximately three sizes provide flexibility choosing system electronics components between boards. Information these connectors obtained from your Intel sales representative.
Figure Keep-out Zone
Note
Note
NOTES: values nominal unless otherwise specified. model (PRO/E Native) Available upon request. These dimensions have changed.
Thermal Transfer Plate
thermal transfer plates (TTP) provide heat dissipation mobile Pentium processor 82443BX. vary different generations Intel mobile modules. provides thermal attach point, where system manufacturer transfer heat through notebook system using heat pipe, heat spreader plate, thermal solution. Attachment dimensions thermal interface block provided Figure Figure Figure mobile module designed high efficiency spreader. fully take advantage mobile module thermal design optimize system thermal performance, contact area (Ac) needs minimum While crucial maximize contact area, equally important ensure that contact area and/or mobile module free from warpage assembled configuration.
Warning:
warpage occurs, thermal resistance mobile module could adversely affected. When attaching mating block either TTP, Intel recommends that thermal elastomer used interface material. This material reduces thermal resistance. thermal interface block should secured with screws using maximum torque Kg*cm Kg*cm (equivalent 0.147 to.197 N*m). thread length screws should
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2.25-mm gageable thread (2.25-mm minimum 2.80-mm maximum). mobile module designed ensure that thermal resistance between processor center point directly above surface 0.35° C/W, under following conditions.
RTTP-a (center point) ambient ~2.4° Contact area centered between attach points
Figure 82443BX Thermal Transfer Plate (Reference Only)
Rivets Mounting
Figure 82443BX Thermal Transfer Plate Detail
3.150
1.000 0.89 1.050 3.569 6.280
NOTE: tolerances 0.015 unless otherwise noted.
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Figure Thermal Transfer Plate (Reference Only)
6.3.1
Module Physical Support
Module Mounting Requirements
Three mounting holes available securing module system base system electronics. Figure mounting hole locations. These hole locations board edge clearances will remain fixed Intel mobile modules. three mounting holes should used ensure long term mechanical reliability integrity system. board edge clearance includes 0.762-mm (0.030-inches) wide containment ring around perimeter mobile module. This ring each layer grounded. hole patterns also have plated surrounding ring metal standoff shielding purposes. Standoffs should used provide support installed mobile module. However, warpage baseboard vary should calculated into final dimensions standoffs used. calculations made with Intel MMC-2 Standoff/Receptacle Height Spreadsheet. Information this spreadsheet obtained from your local Intel Field Representative. Figure shows standoff support hole details, board edge clearance, dimensions containment ring. components placed board keep-out area.
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Figure Standoff Holes, Board Edge Clearance, Containment Ring
Hole detail, places
3.81+/-0.19
2.413
0.050 0.025 hole diameter
4.45 diameter grounded ring
1.27+/- 0.19 board edge ring
0.762 width containment ring
2.54+/-0.19 keep-out area
3.81+/-0.19 board edge hole centerline
6.3.2
Module Weight
Pentium processor mobile module weighs approximately grams.
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Thermal Specification
Thermal Design Power
power handling capability system thermal solution reduced less than recommended typical Thermal Design Power (TDP) shown Table with implementation firmware/software control "throttling" that reduces power consumption dissipation. typical typical power dissipation under normal operating conditions nominal V_CORE (CPU power supply) while executing worst case power instruction mix. This includes power dissipated relevant components. During operating environments, processor junction temperature, must within specified range
Table Thermal Design Power Specification
Symbol Module Parameter Module Thermal Design Power Typical 14.1W Typical 15.0W Notes Module core 82443BX voltage regulator
NOTES: During operating environments, processor temperature, must within special range 100°C. TDPModule thermal-solution design reference point thermal solution readiness total module power.
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Labeling Information
Intel mobile modules tracked ways. first product tracking code (PTC). Intel uses label determine assembly level module. Figure shows where found module. contains characters provides following information. Example: PML50002001AA Key: AABCCCDDEEEFFF Definition: Processor Module Pentium processor mobile module Speed Identity 450, Cache Size (256K) Notifiable Design Revision (Start 001) Notifiable Processor Revision (Start
Note: other Intel mobile modules, second field defined Pentium Processor Mobile Module (MMC-1) Pentium Processor Mobile Module (MMC-2) Pentium Processor Mobile Module With On-die Cache (MMC-1) Pentium Processor Mobile Module With On-die Cache (MMC-2) Celeron Processor Mobile Module (MMC-1) Celeron Processor Mobile Module (MMC-2)
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Figure Product Tracking Code
Intel Assembly Identification Intel Serial Number
ISYWW6666
XXXXXX-XXX XXXXXXXXXXXXX
Product Tracking Code Secondary Side Module
second tracking method generated software utility. Four strapping resistors located module determine production level. connected terminated properly, module-revision levels determined. generated software utility then read these bits with stepping provide complete module manufacturing revision level. current module information, please refer latest Intel mobile module product change notification (PCN) letter, which obtained from your local Intel Field Representative.
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Environmental Standards
environmental standards defined Table
Table Environmental Standards
Parameter Temperature Cycle Humidity Voltage Condition Non-operating Operating Unbiased Non-operating Shock Unpackaged Packaged Packaged Unpackaged Vibration Packaged Packaged Damage Human Body Model relative humidity 55°C 5.0V 3.3V Half Sine, Trapezoidal, 50G, Inclined impact feet/S Half Sine, inches simulated free fall 2.2-gRMS random gRMS 11,800 impacts (low frequency) Non-powered test mobile module only noncatastrophic failure. module tested then inserted system functional test. Specification
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Mobile Pentium processor speeds On-die, primary 16-K Instruction cache

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