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AP-972

Pentium® III Xeon Processor System Compatibility Guidelines

AP-972
Application Note
Pentium® III Xeon Processor System Compatibility Guidelines
Order Number 245248-003 August, 2000
Pentium® III Xeon Processor System Compatibility Guidelines
Table of Contents
Pentium® III Xeon Processor System Compatibility Guidelines
1.0 Introduction
2.0 Terminology
Pentium® III Xeon Processor System Compatibility Guidelines
3.0 Upgradeability
Table 1: Pentium® III Xeon Processor System Level Compatibility. Pentium III Xeon processor at 500 MHz and 550 MHz Supported Pentium III Xeon processor with 256KB L2 cache Not supported Not supported Supported at 133 MHz only Pentium III Xeon processor with 1MB and 2MB L2 cache Supported1
System
4-way systems based on Intel® 450NX PCIset and Profusion Chipsets 2-way systems based on Intel® 440GX AGPset 2-way systems based on Intel® 840 Chipset
Supported Not supported
Not supported Not supported
1. To determine whether or not the Pentium III Xeon processor with 256KB L2 cache or Pentium III Xeon processor with 1MB and 2MB L2 cache will operate reliably in a platform, a developer has to ensure that the requirements listed in the appropriate processor datasheet and this document are fully satisfied.
4.0 Power and Thermal Requirements
Table 2 shows the power and Max TPLATE requirements for SC330 processors that support 100 MHz system bus frequency. "FMB" stands for Flexible Mother Board and is a suggested design guideline for a flexible motherboard design targeted to allow forward compatibility with existing and future processors.
Pentium® III Xeon Processor System Compatibility Guidelines
Table 2: Power & Thermal Requirements1, 2 Processor Pentium® II Xeon processor Pentium III Xeon processor Pentium III Xeon processor with 256KB L2 cache Pentium III Xeon processor with 1MB and 2MB L2 cache Processor Core Frequency 450 MHz 550 MHz FMB FMB Thermal Plate Power 46.7 W 40.5 W 37.0 W 50 W Max TPLATE 75° C 68° C 55° C 65° C
1. Information in table is for reference only. Refer to the appropriate processor datasheet for valid and specifications. 2. Power and thermal numbers in this table are specific to each processor. Operating conditions for one processor type may not be applied to another processor type.
Pentium® III Xeon Processor System Compatibility Guidelines
5.0 New ICCSMBus Specification
The Pentium® III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache cartridge implement additional logic for OCVR control and miscellaneous logic. The ICCSMBus specification changed from 10 mA on the Pentium II Xeon processor and Pentium III Xeon processor at 500 MHz and 550 MHz to 22.5 mA for the Pentium III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache. Refer to the appropriate processor datasheet for details on this specification.
Table 4: ICCSMBus Current Considerations. System Design Pentium III Xeon processor with 256KB L2 cache or Pentium III Xeon processor with 1MB and 2MB L2 cache systems Implications System designers need to ensure ICCSMBus can supply at least 22.5 mA.
6.0 L2 Cache VID Settings
Pentium® III Xeon Processor System Compatibility Guidelines
Table 5: L2 VID Setting Considerations. System Design · Pentium® III Xeon processor with 256KB L2 cache systems without Pentium III Xeon processor at 500 MHz and 550 MHz support Pentium III Xeon processor with 1MB and 2MB L2 cache systems without Pentium III Xeon processor at 500 MHz and 550 MHz support Pentium III Xeon processor with 256KB L2 cache systems with Pentium III Xeon processor at 500 MHz and 550 MHz support Pentium III Xeon processor with 1MB and 2MB L2 cache systems with Pentium III Xeon processor at 500 MHz and 550 MHz support Implications A separate L2 VRM and L2 VID setting scheme is not required since the Pentium III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache have integrated L2 cache.
Pentium® III Xeon Processor System Compatibility Guidelines
8.0 SC330.1 Pin Changes over SC330 Definition
The SC330.1 definition is mechanically and electrically compatible with the SC330 definition. However, the new SC330.1 definition used by the Pentium III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache redefine the following pins.
Pentium® III Xeon Processor System Compatibility Guidelines
1. Information in table is for reference only. Refer to the appropriate processor datasheet for valid specifications.
Pentium® III Xeon Processor System Compatibility Guidelines
5 / 12V Pentium III Xeon processor systems
10.0 OCVR (On Cartridge Voltage Regulator)
Pentium® III Xeon Processor System Compatibility Guidelines
RESET# logic
· Servers can enable / disable OCVRs and Cores independently
Figure 1. OCVR Control Lines Implementation (New Systems)
5V 10K
Existing Logic
PWRGOOD
RESET# logic
Figure 2. OCVR Control Lines Implementation (Legacy Systems)
Pentium® III Xeon Processor System Compatibility Guidelines
0.5 mS (max)
Vin (OCVR)
Vout (OCVR)
11.0 Remote Sense Lines
The Pentium® III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache cartridges provide remote sensing capabilities at both the input and out-
Pentium® III Xeon Processor System Compatibility Guidelines
12.0 2.5V Signal Voltage Clamps
12.1 Signal Timings and I / O Capacitance The Pentium® III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache cartridges contain a new 2.5 V signal voltage clamp device intended to provide 2.5V-signal level compatibility between platforms and the processor core, which uses 1.5 V level signals. The voltage clamp helps reduce overshoot levels seen at the core. These clamps are included on CMOS, TAP, and APIC (PICD1:0) signals and result in an increased I / O Capacitance value (Con) compared to previous Pentium II Xeon processors and Pentium III Xeon at 500 MHz and 550 MHz processors. Con is approximately 25 pF max. This max value includes the total capacitance contribution from the voltage clamp and processor core buffer. It does not include cartridge trace capacitance, which is 3 pF / inch and approximately 4 inches total length. This Con value applies to all CMOS, TAP, Clock, and APIC signals except BCLK and PICCLK, which are not connected to the voltage clamp devices.
Pentium® III Xeon Processor System Compatibility Guidelines
4-way Example: Consider a 4-way system with the following APIC bus parameters: Total trace routing of 30 inches. This defines the total trace length contribution from all individual trace segments (e.g., processors, termination resistor stubs, SC330.1 connectors, and additional APIC agent routing). This total length already includes four Pentium III Xeon processor with 1MB and 2MB L2 cache cartridges, each with 4 inches (720 ps) total trace between the core and edge finger. · Longest component point-to-point routing distance of 20 inches. · Nominal board impedance of 60 ohms. · Worst-case (slowest) propagation delay of 180 ps / inch. · Transmission line capacitance of 3.0 pF / inch (From the above impedance and propagation delay). · Effective pull-up resistance of 150 ohms.
For this board design:
Pentium® III Xeon Processor System Compatibility Guidelines
Table 13: Voltage Clamp Considerations System Design Pentium® III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache systems. Implications Since the voltage clamp introduces additional delay (loading) on 2.5 V signals, Intel recommends complete validation, testing and signal integrity analysis to ensure that the specifications published in the processor datasheets are fully met. Since APIC bus signals are synchronous, verify layout will meet Pentium III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache setup and hold timings.
13.0 2.5V Signal Output Low Voltage
The CMOS, TAP, and APIC signal VOL (Output Low Voltage) capability of the Pentium® III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache is weaker than the previous Pentium III Xeon processor at 500 MHz and 550 MHz specification. The Pentium III Xeon Processor at 500 MHz and 550 MHz Datasheet specifies a VOL of 0.5V while sinking 24 mA. The VOL specification for the Pentium III Xeon processor with 1MB and 2MB L2 cache is 0.55V while sinking 20 mA for the APIC PICD signals, and 0.5V while sinking 14 mA for the CMOS and TAP signals. Another change is that VOL specifications are now defined at the processor edge fingers for the Pentium III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache in order to comprehend the electrical effects of the voltage clamp device.
Pentium® III Xeon Processor System Compatibility Guidelines
Table 14: 2.5V Signal VOL System Design Pentium® III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache systems Implications Since the VOL capability for the Pentium III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache is less than the Pentium III Xeon processor at 500 MHz and 550 MHz, make sure the baseboard layout, timing, and termination for the CMOS, TAP, and APIC buses will satisfy the VILMAX requirements for all devices interfacing with these signals. A bus designed to the Pentium III Xeon processor at 500 MHz and 550 MHz VOL specification may not support the Pentium III Xeon processor with 256KB L2 cache or Pentium III Xeon processor with 1MB and 2MB L2 cache if the pull-up resistance is too strong (i.e., if the resistance value is small). Since 2.5V signal bus design is dependent on the electrical requirements of the devices which interface with the processor, perform a DC (e.g., paper calculation) and AC (simulation and measurements) signal analysis to identify any potential problems.
14.0 SELFSB1:0 Pins Implementation
14.1 SELFSB1:0 Functionality The new definition of the SELFSB 1:0 pins is compatible with legacy systems as well as new platforms. This definition provides the means for the clock synthesizer and additional baseboard logic to auto detect the expected system bus frequency required by a specific cartridge. In addition, this implementation eliminates a baseboard jumper that would be necessary to select between a Pentium III Xeon processor that only supports 100 MHz system bus frequency versus a Pentium III Xeon processor that only supports 133 MHz. As an output from the cartridge, the value of SELFSB1 offers a way for baseboards to automatically determine the correct system bus frequency (100 MHz or 133 MHz). The SELFSB1 signal is grounded on processors that support 100 MHz system bus frequency, no-connect on processors that support 133 MHz. See Table 15 for processor SELFSB1 details.
Pentium® III Xeon Processor System Compatibility Guidelines
The processors use SELFSB0 (input) to select system bus frequency. A high signal applied to this input pin is required to operate the processor at the supported frequency. Table 16 summarizes SELFSB0 functionality.
Table 15: SELFSB1 Functionality Summary Processor Pin Pin Name SELFSB1 Functionality Output: Frequency Identifier N / C (floating) on cartridge (identifies 133 MHz) Pentium II Xeon and Pentium III Xeon processor at 500 MHz and 550 MHz Pentium III Xeon processor with 1MB and 2MB L2 cache A7 SELFSB1 (previously VSS) Output: Frequency Identifier Grounded on cartridge (identifies 100 MHz) A7 SELFSB1 Output: Frequency Identifier Grounded on cartridge (identifies 100 MHz)
Pentium® III Xeon proA7 cessor with 256KB L2 cache
Table 16: SELFSB0 Functionality Summary Processor Pentium® III Xeon processor with 256KB L2 cache Pin A9 Pin Name SELFSB0 Functionality Input: Frequency Selection High: 133 MHz operation Low: 100 MHz operation (unsupported) Pentium II Xeon processor and Pentium III Xeon processor at 500 MHz and 550 MHz A9 SELFSB0 (previously Reserved) Input: Frequency Selection High: 100 MHz operation Low: 66 MHz operation (unsupported) Pentium III Xeon processor with 1MB and 2MB L2 cache A9 SELFSB0 Unconnected on processor cartridge (100 MHz operation only)
Pentium® III Xeon Processor System Compatibility Guidelines
14.2 SELFSB1:0 Baseboard Recommendation The recommended SELFSB1:0 baseboard implementation is summarized as follows: SELFSB1: Pull up to 2.5V through 3.3 Kohm resistor. Add resistor dividers as needed to supply the correct high / low voltage values to additional components using this signal (e.g., Intel 840 MCH). SELFSB0: Pull up to 2.5V through 500 ohm resistor. Table 17 gives the SELFSB1:0 line levels when each of the various processors are installed in a new or legacy system. For "New Systems", the table assumes the baseboard follows the recommendations given in this section.
Table 17: SELFSB1:0 Signal Values SELFSB1:0 levels seen on New Systems SELFSB1(A7) Pentium® III Xeon processor with 256KB L2 cache Pentium III Xeon processor at 500 MHz and 550 MHz Pentium III Xeon processor with 1MB and 2MB L2 cache 1 0 0 SELSFB0(A9) 0 1 1
SELFSB1:0 levels seen on Legacy Systems SELFSB1(A7) Pentium III Xeon processor with 256KB L2 cache Pentium III Xeon processor at 500 MHz and 550 MHz Pentium III Xeon processor with 1MB and 2MB L2 cache 0 0 0 SELSFB0(A9) Floating (N / C) Floating (N / C) Floating (N / C)
The following figures illustrate the recommended SELFSB1:0 baseboard implementation, along with the results of various processor and baseboard combinations. The Pentium III Xeon processor with 256KB L2 cache is only supported at 133 MHz system bus frequency and may not function at 100 MHz. Also, the Pentium III Xeon processor with 1MB and 2MB L2 cache is only supported
Pentium® III Xeon Processor System Compatibility Guidelines
at 100 MHz system bus frequency and may not function at 133 MHz. Note that a "legacy system" refers to a platform originally designed for the Pentium III Xeon processor at 500 MHz and 550 MHz, whereas a "new system" refers to a platform originally designed for the Pentium III Xeon processor with 256KB L2 cache or Pentium III Xeon processor with 1MB and 2MB L2 cache.
C lock C hip
10 SELFSB0
C hipset or M isc. C lock Logic
SELFSB1
Figure 4. New system with Pentium® III Xeon processor with 256KB L2 cache installed (133 MHz selected)
Pentium® III Xeon Processor System Compatibility Guidelines
P entium III Xe on processor with 1M B and 2M B L2 cache
C lock C hip
10 SELFSB0
C hipset or M isc. C lock Logic
Figure 5. New system with Pentium® III Xeon processor with 1MB and 2MB L2 cache installed (100 MHz selected)
C lock C hip
C hipset or M isc. C lock Logic
Figure 6. New system with Pentium® III Xeon processor at 500 MHz and 550 MHz installed (100 MHz selected)
Pentium® III Xeon Processor System Compatibility Guidelines
SELFSB1
Figure 7. Legacy system with Pentium® III Xeon processor with 256 KB L2 cache installed (100 MHz selected)
P entium III Xeon processor at 700 M H z with 1M B and 2M B L2 cache
SELFSB1
Figure 8. Legacy system with Pentium® III Xeon processor with 1MB and 2MB L2 cache installed (100 MHz selected)
Pentium® III Xeon Processor System Compatibility Guidelines
SELFSB0
GND 10K SELFSB1
Figure 9. Legacy system with Pentium® III Xeon processor at 500 MHz and 550 MHz installed (100 MHz selected)
15.0 SC330 vs. SC330.1 Termination Cards
The previous section discusses the SELFSB1:0 signals and their intended implementation. For systems that will support the Pentium® III Xeon processor with 256KB L2 cache, a new SC330.1 termination card may be necessary. Earlier revisions of the bus terminator design guidelines define pin A7 as VSS (refer to the Pentium® III Xeon Processor Bus Terminator Design Guidelines for details). In the event these types of termination cards are installed in a system that connects the SELFSB1 output signal together from both connectors, the SELFSB1 line will always be grounded by the termination card, regardless of whether the processor installed in the other connector is 133 MHz or 100 MHz-capable. To support designs that detect the requested clock frequency from both processors before supplying a clock input, the termination card guidelines have been modified to redefine pin A7 as a NC (no-connect). This allows the SELFSB1 line to float high in the case where a Pentium III Xeon processor with 256KB L2 cache is installed.
16.0 BR0# (I / O), BR3:1# (I) Lines
The Pentium® III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache use the same BR#3:1 and BR0# methodology implemented for previous generations of SC300 processors. Therefore, BREQ connectivity remains the same. However, a reduced set of signals is used in the Pentium III Xeon processor with 256KB L2 cache since this processor supports 2-way configurations only. Attempting to run these processors in a 4-way configuration will result in unsupported and unpredictable behavior. On a Pentium III Xeon processor with 256KB L2 cache cartridge, only BR0#, BR1# and BR3# (Bus Request) pins drive the
Pentium® III Xeon Processor System Compatibility Guidelines
Table 18: BR3:0# Rotating Interconnect, 4-way System1, 2 Bus Signal BREQ0# BREQ1# BREQ2# BREQ3# Agent 0 Pins BR0# BR1# BR2# BR3# Agent 1 Pins BR3# BR0# BR1# BR2# Agent 2 Pins BR2# BR3# BR0# BR1# Agent 3 Pins BR1# BR2# BR3# BR0#
1. Information in table is for reference only. Refer to the appropriate processor datasheet for valid specifications. 2. During power-up configuration, the central agent must assert its BR0# signal. All symmetric agents sample their BR3:0# pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent ID. This is summarized in the table below for 4-way systems. All agents then configure their BREQ3:0# signals to match the appropriate bus signal protocol.
Table 19: Agent ID Configuration1 BR0# L H H H H H H L BR1# H L L H BR3# H H H H A5# 0 1 2 3 Agent ID
1. Information in table is for reference only. Refer to the appropriate processor datasheet for valid specifications.
Pentium® III Xeon Processor System Compatibility Guidelines
17.0 Processor Information ROM Information Changes
Pentium® III Xeon Processor System Compatibility Guidelines
Table 20: PI-ROM Table Excerpt for the Pentium® III Xeon Processor with 1MB and 2MB L2 cache1 Offset / Section # of Bits 4 8 OTHER: 7Eh 16 Function Reserved Checksum Reserved Notes Reserved for future use 1 byte checksum Reserved for future use
1. Information in table is for reference only. Refer to the appropriate processor datasheet for valid power and thermal specifications.
Table 21: New PI-ROM Information for the Pentium® III Xeon Processor with 256KB L2 Cache and Pentium III Xeon Processor with 1MB and 2MB L2 Cache. System Design Pentium® III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache systems Implications Systems that rely on PI-ROM information to detect voltage requirements need to evaluate the new fields present in the Pentium III Xeon processor with 256KB L2 cache and Pentium III Xeon processor with 1MB and 2MB L2 cache PI-ROM. Ensure software and / or embedded logic on the baseboard can properly detect the various processors supported by the system.