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Pentium® XeonProcessor System Compatibility Guidelines
Order Number 245248-003 August, 2000
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined". Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® Pentium® Xeonprocessor contain design defects errors known errata which cause product deviate from published specifications. Such errata covered Intel's warranty. Current characterized errata available request. THIS DOCUMENT PROVIDED WITH WARRANTIES WHATSOEVER, INCLUDING WARRANTY MERCHANTABILITY, NONINFRINGEMENT, FITNESS PARTICULAR PURPOSE, WARRANTY OTHERWISE ARISING PROPOSAL, SPECIFICATION SAMPLE. Intel disclaims liability, including liability infringement proprietary rights, relating information this specification. license, express implied, estoppel otherwise, intellectual property rights granted herein. Intel does warrant represent that such will infringe such rights. *Third-party brands names property their respective owners. Copies documents which have order number referenced this document, other Intel literature, obtained calling1-800-548-4725, visiting Intel's website http://www.intel.com. Copyright Intel Corporation 1999, 2000
Pentium® XeonProcessor System Compatibility Guidelines
Table Contents
Introduction.7 Terminology.7 Upgradeability Power Thermal Requirements.9 ICCSMBus Specification Cache Settings Core Voltage Identification HV_EN# SC330.1 Changes over SC330 (a.k.a. Slot Definition TEST_VCC Pins 10.0 OCVR Cartridge Voltage Regulator) 10.1 OCVR Control Signals 10.2 OCVR_OK (Pin B3).18 10.3 OCVR_EN (Pin A26) 10.4 Power sequencing considerations 11.0 Remote Sense Lines.21 11.1 VIN_SENSE 11.2 CORE_AN_VSENSE.22 11.3 L2_SENSE.22 12.0 2.5V Signal Voltage Clamps 12.1 Signal Timings Capacitance 12.2 Design Impact.24 12.3 Design Examples 13.0 2.5V Signal Output Voltage 14.0 SELFSB[1:0] Pins Implementation 14.1 SELFSB[1:0] Functionality 14.2 SELFSB[1:0] Baseboard Recommendation 15.0 SC330 SC330.1 Termination Cards 16.0 BR0# (I/O), BR[3:1]# Lines 17.0 PI-ROM Information Changes.35
Pentium® XeonProcessor System Compatibility Guidelines
Introduction
This document describes main differences that exist between Pentium® Xeonprocessors with cache previous generations Pentium Xeon processors. These guidelines intended "checklist" determine whether system designed previous SC330 processors will able support Pentium Xeon processor with cache Pentium Xeon processor with 256KB cache, summary requirements platforms intending support either these processors. information contained herein should used conjunction with specifications presented latest versions datasheets Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache, well information provided other Pentium Xeon processor design guides. latest collection collateral Pentium Xeon processor family, visit Intel's site Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache same mechanical form factor physical connector previous Pentium Xeon Pentium Xeon processors additional functionality including Cartridge Voltage Regulation (OCVR). determine whether Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache will operate reliably platform, developer must ensure that requirements this guideline fully satisfied. Intel strongly encourages complete signal integrity analysis careful examination signal timings. Some Pentium Xeon processors with cache timing requirements tolerances more stringent than those found previous processors. addition Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache require thermal cooling solutions voltage current delivery schemes.
Terminology
following terms used this document defined here clarification: Pentium® Xeonprocessor with 256KB cache refers Pentium Xeon processor which utilizes Cartridge Voltage Regulator technology, "OCVR", which 256KB Level cache. OCVR regulates VCC_CORE (the appropriate cartridge input voltage) required processor core voltage (VCC_CPU). OCVR developed provide necessary regulation guarantee highest possible frequency operation Pentium Xeon processor above. Pentium® Xeonprocessor with cache refers Pentium Xeon processor which utilizes Cartridge Voltage Regulator technology, "OCVR", which either Level cache. OCVR regulates VCC_CORE (the appropriate cartridge input voltage) required processor core voltage (VCC_CPU). OCVR developed provide necessary regulation guarantee highest possible frequency operation Pentium Xeon processor frequencies above.
Pentium® XeonProcessor System Compatibility Guidelines
Pentium® Xeonprocessor refers Pentium Xeon processor without OCVR, requires separate VCC_CORE voltage sources. Pentium® Xeonprocessor refers Pentium Xeon processor with 256KB cache, Pentium Xeon processor with cache, Pentium Xeon processor MHz. cache -The cache integrated directly processor core Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache, located substrate Pentium Xeon processor MHz. 2.8V Pentium® Xeonprocessor refers Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache which powered with +2.8 volts applied VCC_CORE pins. 5/12V Pentium® Xeonprocessor refers Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache which powered with either +5.0 +12.0 volts applied VCC_CORE pins.
Pentium® XeonProcessor System Compatibility Guidelines
Upgradeability
Table Pentium® XeonProcessor System Level Compatibility. Pentium Xeon processor Supported Pentium Xeon processor with 256KB cache supported supported Supported only Pentium Xeon processor with cache Supported1
System
4-way systems based Intel® 450NX PCIset Profusion Chipsets 2-way systems based Intel® 440GX AGPset 2-way systems based Intel® Chipset
Supported supported
supported supported
determine whether Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache will operate reliably platform, developer ensure that requirements listed appropriate processor datasheet this document fully satisfied.
Power Thermal Requirements
Table shows power TPLATE requirements SC330 processors that support system frequency. "FMB" stands Flexible Mother Board suggested design guideline flexible motherboard design targeted allow forward compatibility with existing future processors.
Pentium® XeonProcessor System Compatibility Guidelines
Table Power Thermal Requirements1,2 Processor Pentium® Xeonprocessor Pentium Xeon processor Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache Processor Core Frequency Thermal Plate Power 46.7 40.5 37.0 TPLATE
Information table reference only. Refer appropriate processor datasheet valid specifications. Power thermal numbers this table specific each processor. Operating conditions processor type applied another processor type.
Pentium® XeonProcessor System Compatibility Guidelines
Table Power Thermal Solution Considerations System Platform Pentium® Xeonprocessor with 256KB cache systems with support Pentium Xeon processor Impact Implications System developers need ensure planned cooling solution meet TPLATE Pentium Xeon processor MHz, TPLATE Pentium Xeon processor with 256KB cache. ICC_CORE requirement 2.8V Pentium Xeon processor with 256K cache maximum Pentium Xeon processor with 256KB cache systems without Pentium Xeon processor support System developers need ensure planned cooling solution meet TPLATE Pentium Xeon processor with 256KB cache. Developers will have flexibility create Pentium Xeon processor with 256KB cache platform using VCC_CORE supply, thus eliminating need baseboard VCC_CORE VRM. Pentium Xeon processor with cache systems with support Pentium Xeon processor Pentium Xeon processor with cache systems without Pentium Xeon processor support System developers need ensure planned cooling solution meet TPLATE Pentium Xeon processor TPLATE Pentium Xeon processor with cache. System developers need ensure planned cooling solution meet TPLATE Pentium Xeon processor with cache. Developers will have flexibility create Pentium Xeon processor with cache platform using VCC_CORE supply, thus eliminating need baseboard VCC_CORE VRM.
Pentium® XeonProcessor System Compatibility Guidelines
ICCSMBus Specification
Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache cartridge implement additional logic OCVR control miscellaneous logic. ICCSMBus specification changed from Pentium Xeon processor Pentium Xeon processor 22.5 Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache. Refer appropriate processor datasheet details this specification.
Table ICCSMBus Current Considerations. System Design Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache systems Implications System designers need ensure ICCSMBus supply least 22.5
Cache Settings
Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache offer processor core with integrated cache, which eliminates need power cache. support platforms that intend provide backward compatibility with Pentium Xeon processor MHz, Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache implement legacy pins cache, with lines encoded processor Core", VID_L2 [4:0] 11111. When Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache installed these legacy platforms, VRMs expected disable themselves response this Core" setting specified legacy processor datasheet documentation. Pentium Xeon processor compatibility concern, OEMs decide depopulate cache regulator remove entire VCC_L2 delivery designs since VCC_L2 required Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache (the VCC_L2 pins connected inside these processor cartridges).
Pentium® XeonProcessor System Compatibility Guidelines
Table Setting Considerations. System Design Pentium® Xeonprocessor with 256KB cache systems without Pentium Xeon processor support Pentium Xeon processor with cache systems without Pentium Xeon processor support Pentium Xeon processor with 256KB cache systems with Pentium Xeon processor support Pentium Xeon processor with cache systems with Pentium Xeon processor support Implications separate setting scheme required since Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache have integrated cache.
needed. expected disable itself Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache installed. System designers must ensure baseboard able provide valid PWRGOOD RESET# generation spite getting "Not Present" VID_L2 from Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache cartridge. Baseboard developers need accommodate necessary logic detect Pentium Xeon processors enable VRM.
Core Voltage Identification HV_EN#
2.8V Pentium® Xeonprocessor uses legacy scheme DCDC Converter Design Guidelines (please refer processor datasheet further details). expected operating voltage input OCVR 2.8V Pentium Xeon processor Therefore, 2.8V Pentium Xeon processor VID_CORE[4:0] inputs will encode value VID[4:0] 10111. 5/12V Pentium Xeon processor will encode value Core", VID[4:0] 11111 since this processor type meant eliminate need VRMs. help identify 5/12V Pentium Xeon processors, (documented Pentium Xeon processor MHz) defined HV_EN# Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache. HV_EN# connected inside 5/12V Pentium Xeon processor car-
Pentium® XeonProcessor System Compatibility Guidelines
tridges left unconnected 2.8V Pentium Xeon processors Pentium Xeon processors. This allows baseboard logic determine whether high voltage 12V) applied VCC_CORE pins, whether VCC_CORE must provided through VRM. Proper baseboard logic will: Disable processor apply VCC_CORE pins when 5/12V Pentium Xeon processor installed. 5/12V available, system should disable 5/12V Pentium Xeon processor prevent unexpected unsupported operation. Enable processor apply appropriate voltage VCC_CORE pins when Pentium Xeon processor 2.8V Pentium Xeon processor installed. Disable 5/12V VCC_CORE pins when Pentium Xeon processor 2.8V Pentium Xeon processor installed prevent damage and/or improper operation. option using additional line chosen following table summarizes coding presented processor cartridge seen regulator (and additional baseboard logic responsible providing correct voltage). VID[4:0] 11111 defined Core" DC-DC Converter Design Guidelines.
Table 2.8V 5/12V Pentium® XeonProcessor Settings1,2,3 Cartridge Version HV_EN# VID4 VID3 VID2 VID1 VID0
Information table reference only. Refer appropriate processor datasheet valid specifications. HV_EN# connected (floating) 2.8V Pentium Xeon processors. means cartridge pulling this line (i.e., floating).
HV_EN# used, baseboard responsible ensuring power sequencing problems (including power supply race conditions) occur between circuitry that bypasses either 12V.
Pentium® XeonProcessor System Compatibility Guidelines
Table Core Voltage Identification HV_EN# considerations System Design Systems with only VCC_CORE supply (without 5/12V) Implications These designs will able Pentium® Xeonprocessor. Power delivery solutions that scheme impacted Baseboard logic should: Disable 5/12V Pentium Xeon processor prevent unexpected operation potential damage. Enable processor apply voltage VCC_CORE pins when Pentium Xeon processor 2.8V Pentium Xeon processor installed.
Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache systems with both 5/12V VCC_CORE supplies
Baseboard logic should: Disable processor apply VCC_CORE when Pentium Xeon processor installed. Disable 5/12V supply VCC_CORE pins enable processor (apply appropriate VCC_CORE voltage) when 2.8V Pentium Xeon processor Pentium Xeon processor installed.
Pentium® XeonProcessor System Compatibility Guidelines
Table Core Voltage Identification HV_EN# considerations System Design Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache systems with only 5/12V VCC_CORE supply VRM) Implications Baseboard logic should: Apply VCC_CORE when 5/12V Pentium Xeon processor installed. Disable 5/12V supply VCC_CORE pins disable Pentium Xeon processor 2.8V Pentium Xeon processor prevent unexpected operation potential damage.
SC330.1 Changes over SC330 Definition
SC330.1 definition mechanically electrically compatible with SC330 definition. However, SC330.1 definition used Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache redefine following pins.
Table SC330.1 Changes1 number SC330 Name SELFSB0 TEST_VSS_A11 TEST_VCC_CORE_ RESERVED_A26 RESERVED SC330.1 Name RESERVED_A1 HV_EN# SELFSB1 SELFSB0 RESERVED_A11 TEST_2.5_A23 OCVR_EN OCVR_OK Signal Buffer Type connect Open grounded processor CMOS Output CMOS Input connect Pull 2.5V baseboard CMOS Input Open Drain Output
Pentium® XeonProcessor System Compatibility Guidelines
Table SC330.1 Changes1 number B164 B165 SC330 Name TEST_VCC_CORE_ RESERVED_A56 RESERVED_B57 RESERVED_B83 SC330.1 Name TEST_2.5_B27 VIN_SENSE L2_SENSE CORE_AN_VSENSE RESERVED_B164 RESERVED_B165 Signal Buffer Type Pull 2.5V baseboard OCVR input Analog sense VCC_L2 remote sense OCVR output remote sense connect connect
Information table reference only. Refer appropriate processor datasheet valid specifications.
Pentium® XeonProcessor System Compatibility Guidelines
Table Definition Considerations System Design Pentium® Xeonprocessor with 256KB cache systems with Pentium Xeon processor support. Pentium Xeon processor with cache systems with Pentium Xeon processor support Implications Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache, verify compatible connection OCVR_EN, OCVR_OK, VIN_SENSE, L2_SENSE, CORE_AN_SENSE, SELFSB[1:0] signals (more detail signal usage described Sections 10.1, Pins formerly labeled have effect Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache left unconnected tied GND. Verify that pins previously specified TEST_VCC_CORE_A23 TEST_VCC_CORE_B27 don't voltage higher than These pins tied either VCC_2.5 (recommended) VCC_CORE. Pentium Xeon processor with 256KB cache systems without Pentium Xeon processor support Pentium Xeon processor with cache systems without Pentium Xeon processor support Suggested OCVR_EN, OCVR_OK usage given section 10.1. TEST_2.5_XX pins should connected VCC_2.5V supply through separate Kohm resistors connect VCC_CORE).
TEST_VCC Pins
Intel recommends tying formerly defined pins TEST_VCC_CORE_A23 TEST_VCC_CORE_B27 VCC_2.5V supply through separate Kohm resistors baseboard. Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache, these pins specified TEST_2.5_XX pins. However, there will damage these processors platforms based Pentium Xeon pro-
Pentium® XeonProcessor System Compatibility Guidelines
cessor Pentium Xeon processor provide 2.8V pull-up resistors. systems where VCC_CORE 12V, strongly recommended connect TEST_2.5_XX pins through separate Kohm resistors prevent potential damage processor.
Table TEST_2.5_XX Pins Considerations System Design 2.8V Pentium® Xeonprocessor systems Implications Systems with these signals tied VCC_CORE (2.8 less) require modifications. Tying these pins through separate Kohm resistors recommended. Connect TEST_2.5_XX pins 2.5V (not VCC_CORE) through separate Kohm resistors prevent potential damage processor.
5/12V Pentium Xeon processor systems
10.0 OCVR Cartridge Voltage Regulator)
Cartridge Voltage Regulator (OCVR) device located inside Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache cartridge that provides necessary power delivery precision processor core integrated cache. both 2.8V 5/12V Pentium Xeon processors, OCVR regulates VCC_CORE (2.8V 5/12V) required processor core voltage. previously defined SC330 VCC_CORE pins used provide input voltage OCVR. order accommodate legacy support guarantee stable operation, OCVR incorporates control signals discussed below. Refer Figure Figure illustration OCVR interaction with legacy systems. 10.1 OCVR Control Signals control signals newly defined SC330.1 specification. They provide reliable operation OCVR cartridge connectivity existing platforms. 10.2 OCVR_OK (Pin This valid high signal pulled cartridge VCC_SMB. OCVR expected provide valid OCVR_OK signal assertion within seeing input voltage. OCVR_OK signal also guaranteed valid until (max) after OCVR reaches nominal voltage. Prior this time, possible OCVR_OK signal incorrectly asserted (high). This signal also logically AND-gated with PWRGOOD input signal guarantee valid PWRGOOD assertion when cartridge installed existing platforms. OCVR output must valid stable before processor will receive asserted
Pentium® XeonProcessor System Compatibility Guidelines
PWRGOOD signal. However, baseboard needs make sure there enough delay between valid PWRGOOD seen core release RESET# signal from baseboard. (Refer Figure Section 10.4 further details). platforms, OCVR_OK signal should used power logic that determines assertion PWRGOOD avoid power sequencing concerns determine proper generation RESET#. 10.3 OCVR_EN (Pin A26) OCVR_EN signal provides means disable OCVR systems. This valid high signal pulled through Kohm resistor cartridge. OCVR_EN signal provides safe mechanism avoid false OCVR turn-on systems where been removed from design. existing systems, this signal routed previously reserved (NC) internal pull-up will, default, enable OCVR. 10.4 Power sequencing considerations specification requires POWERGOOD active when output within nominal value. Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache, PWRGOOD logically AND-gated with OCVR_OK before being applied core's PWRGOOD input. According legacy datasheet documents, RESET# release must happen minimum after core sees PWRGOOD asserted. However, OCVR expected provide valid OCVR_OK signal maximum after seeing input voltage. This delay OCVR_OK assertion cause race condition between RESET# asserted POWERGOOD that seen core. example, systems that monitor OCVR_OK signal and/or account this additional delay PWRGOOD path asserting RESET# prior after PWRGOOD assertion. Therefore, systems should incorporate OCVR_OK signal PWRGOOD/ RESET# generation logic. Those systems that incorporate this signals should relax (further delay) deassertion processor RESET# meet this critical constrain. Careful analysis needs done existing platforms. Refer Figure timing relationship requirements Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache.
Pentium® XeonProcessor System Compatibility Guidelines
Vcc_smb
OCVR OCVR_EN OCVR_OK
OCVR_EN CPUx_OCVR_EN CPUx_OCVR_OK SYS_PWRGD Logic PWRGOOD CPU_PWRGD CORE OCVR_OK
RESET# logic
Servers enable/disable OCVRs Cores independently
Figure OCVR Control Lines Implementation (New Systems)
OCVR_EN (N/C)
Vcc_Smb
OCVR OCVR_EN OCVR_OK
OCVR_OK (N/C)
Existing Logic
CPUx_PWRGD
PWRGOOD
CPU_PWRGD
RESET# logic
gate implemented meet legacy system requirements against early CPU_PWRGD assertion PWRGOOD leading OCVR_OK independent disable individual Core through deassertion PWRGOOD Potential Race condition between CPU_PWRGD RESET# system dependent. legacy Systems RESET# timing needs reevaluated.
Figure OCVR Control Lines Implementation (Legacy Systems)
Pentium® XeonProcessor System Compatibility Guidelines
RESET# VRM_PWRGD
(max)
OCVR_OK
CPU_PWR_GD
2.8/5/12V
(OCVR)
Nominal
VCC_CPU
Vout (OCVR)
Figure OCVR_OK POWERGOOD Timing Requirements Table OCVR Timing Requirements Relative Baseboard PWRGOOD System Design Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache systems Implications valid turn-on time OCVR_OK line cause race condition between RESET# valid PWRGOOD that seen core. recommended relax deassertion RESET# meet this critical constraint. Careful analysis needs done existing platforms. Refer Figure timing relationship requirements. designs should incorporate appropriate logic (described above) OCVR_EN OCVR_OK signals.
11.0 Remote Sense Lines
Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache cartridges provide remote sensing capabilities both input out-
Pentium® XeonProcessor System Compatibility Guidelines
OCVR. Please note that neither signal specified Pentium Xeon processor Pentium Xeon processor should should unconnected legacy platforms. 11.1 VIN_SENSE This line provided accurately compensate trace losses guarantee efficient voltage delivery OCVR input. Intel continues recommend sense feedback VRM, from either location SC330 connector through this pin. This pin's functionality available 5/12V Pentium Xeon processors. 11.2 CORE_AN_VSENSE This signal tied seen core represents output OCVR. This signal provides ability detect events which OCVR behave expected regulation tolerance. voltage seen this actual operating voltage core with integrated cache minus drops trace routing cartridge. 11.3 L2_SENSE This line provided systems that will support Pentium Xeon processors MHz. allows monitoring delivery VCC_L2 voltage Pentium Xeon processor MHz. This line specified legacy systems recommended connected Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache systems that will support Pentium Xeon processors MHz.
Pentium® XeonProcessor System Compatibility Guidelines
Table Remote Sense Lines Considerations System Design Pentium® Xeonprocessor with 256KB cache systems without Pentium Xeon Pentium Xeon processor Pentium Xeon processor with cache systems without Pentium Xeon Pentium Xeon processor support Pentium Xeon processor with 256KB cache systems with Pentium Xeon Pentium Xeon processor support Pentium Xeon processor with cache systems with Pentium Xeon Pentium Xeon processor support L2_SENSE used feedback systems supporting Pentium Xeon processors. None Implications
12.0 2.5V Signal Voltage Clamps
12.1 Signal Timings Capacitance Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache cartridges contain signal voltage clamp device intended provide 2.5V-signal level compatibility between platforms processor core, which uses level signals. voltage clamp helps reduce overshoot levels seen core. These clamps included CMOS, TAP, APIC (PICD[1:0]) signals result increased Capacitance value (Con) compared previous Pentium Xeon processors Pentium Xeon processors. approximately max. This value includes total capacitance contribution from voltage clamp processor core buffer. does include cartridge trace capacitance, which pF/inch approximately inches total length. This value applies CMOS, TAP, Clock, APIC signals except BCLK PICCLK, which connected voltage clamp devices.
Pentium® XeonProcessor System Compatibility Guidelines
Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache PICD[1:0] Valid Delay timing specification different from Pentium Xeon Pentium Xeon processors. Pentium Xeon processor with cache Valid Delay timings differentiate between rising falling-edge transitions follows: PICD[1:0] Valid Delay (Rising Edge) PICD[1:0] Valid Delay (Falling Edge) 12.0 Please note that these timings still specified core with resistor load pulled-up 2.5V. addition, Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache PICD[1:0] Setup Time much lower compared Pentium Xeon processor Pentium Xeon processor. Signal specifications contained this section reference only. Refer appropriate processor datasheet valid specifications. 12.2 Design Impact additional capacitance associated with voltage clamp will increase signal propagation time (compared Pentium Xeon processor system) since time constant signal path increases. This increased capacitance will most likely impact APIC since synchronous uses PICCLK. increased propagation time affect receiver setup margin. APIC flight time will likely limited rising edge transitions since resistance term used would effective pull-up resistance this signal (assumed ohms). resistance term falling edges equal core nMOS on-resistance plus voltage clamp on-resistance (approximately ohms). Improvements rising edge PICD Valid Delay spec will provide some relief propagation delay effects. Also, improved PICD setup time will provide substantial relief timing paths where processor receiving agent. However, since APIC behavior strongly dependent baseboard layout APIC components chosen, Intel highly recommends that system designers perform analysis better understand impact these changes. following section provides examples performing first-pass timing calculation. 12.3 Design Examples following analysis 4-way Pentium Xeon processor with cache system will help determine impact various systems APIC topologies. similar analysis performed other system configurations appropriately entering required parameters. APIC timing analysis, system flight time broken into components: straight propagation delay (TPROP), delay time constant (TRC). Equation below. derived from effective pull-up resistance total system capacitance.
Pentium® XeonProcessor System Compatibility Guidelines
Nevertheless, this simple analysis meant starting point understanding capacitance loading effects should reinforced APIC simulations. Equation Total System Flight Time TSYSTEM TPROP (Longest point-to-point distance) (Worst-case propagation delay) derived from solving V(t) V(0)e-TRC/t TRC.
[V(t)/V(0)]
V(0) 2.5V since signal terminated 2.5V. V(t) 1.25V since this voltage reference used timings. REFF CTOTAL CTOTAL CT-LINE CCPU
4-way Example: Consider 4-way system with following APIC parameters: Total trace routing inches. This defines total trace length contribution from individual trace segments (e.g., processors, termination resistor stubs, SC330.1 connectors, additional APIC agent routing). This total length already includes four Pentium Xeon processor with cache cartridges, each with inches (720 total trace between core edge finger. Longest component point-to-point routing distance inches. Nominal board impedance ohms. Worst-case (slowest) propagation delay ps/inch. Transmission line capacitance pF/inch (From above impedance propagation delay). Effective pull-up resistance ohms.
this board design:
Pentium® XeonProcessor System Compatibility Guidelines
TPROP inches ps/inch 3.60 CT-LINE inches pF/inch CCPU processors CTOTAL ohms 28.5 19.8 TSYSTEM 3.60 19.8 23.4
Using simple timing equation below (with driver TCO, TSYSTEM, receiver TSETUP), this system shows margin running 25.0 (40.0 period). This timing equation specifically applies processor-to-processor flight path. Timing analysis involving additional APIC agents requires using their appropriate timing parameters timing equation below. Note that clock skew jitter effects must still considered. TSYSTEM TSETUP TPERIOD 23.4 37.1 Margin 25.0 37.1
Pentium® XeonProcessor System Compatibility Guidelines
Table Voltage Clamp Considerations System Design Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache systems. Implications Since voltage clamp introduces additional delay (loading) signals, Intel recommends complete validation, testing signal integrity analysis ensure that specifications published processor datasheets fully met. Since APIC signals synchronous, verify layout will meet Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache setup hold timings.
13.0 2.5V Signal Output Voltage
CMOS, TAP, APIC signal (Output Voltage) capability Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache weaker than previous Pentium Xeon processor specification. Pentium Xeon Processor Datasheet specifies 0.5V while sinking specification Pentium Xeon processor with cache 0.55V while sinking APIC PICD signals, 0.5V while sinking CMOS signals. Another change that specifications defined processor edge fingers Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache order comprehend electrical effects voltage clamp device.
Pentium® XeonProcessor System Compatibility Guidelines
Table 2.5V Signal System Design Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache systems Implications Since capability Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache less than Pentium Xeon processor MHz, make sure baseboard layout, timing, termination CMOS, TAP, APIC buses will satisfy VILMAX requirements devices interfacing with these signals. designed Pentium Xeon processor specification support Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache pull-up resistance strong (i.e., resistance value small). Since 2.5V signal design dependent electrical requirements devices which interface with processor, perform (e.g., paper calculation) (simulation measurements) signal analysis identify potential problems.
14.0 SELFSB[1:0] Pins Implementation
14.1 SELFSB[1:0] Functionality definition SELFSB [1:0] pins compatible with legacy systems well platforms. This definition provides means clock synthesizer additional baseboard logic auto detect expected system frequency required specific cartridge. addition, this implementation eliminates baseboard jumper that would necessary select between Pentium Xeon processor that only supports system frequency versus Pentium Xeon processor that only supports MHz. output from cartridge, value SELFSB1 offers baseboards automatically determine correct system frequency (100 MHz). SELFSB1 signal grounded processors that support system frequency, no-connect processors that support MHz. Table processor SELFSB1 details.
Pentium® XeonProcessor System Compatibility Guidelines
processors SELFSB0 (input) select system frequency. high signal applied this input required operate processor supported frequency. Table summarizes SELFSB0 functionality.
Table SELFSB1 Functionality Summary Processor Name SELFSB1 Functionality Output: Frequency Identifier (floating) cartridge (identifies MHz) Pentium Xeon Pentium Xeon processor Pentium Xeon processor with cache SELFSB1 (previously VSS) Output: Frequency Identifier Grounded cartridge (identifies MHz) SELFSB1 Output: Frequency Identifier Grounded cartridge (identifies MHz)
Pentium® XeonproA7 cessor with 256KB cache
Table SELFSB0 Functionality Summary Processor Pentium® Xeonprocessor with 256KB cache Name SELFSB0 Functionality Input: Frequency Selection High: operation Low: operation (unsupported) Pentium Xeon processor Pentium Xeon processor SELFSB0 (previously Reserved) Input: Frequency Selection High: operation Low: operation (unsupported) Pentium Xeon processor with cache SELFSB0 Unconnected processor cartridge (100 operation only)
Pentium® XeonProcessor System Compatibility Guidelines
14.2 SELFSB[1:0] Baseboard Recommendation recommended SELFSB[1:0] baseboard implementation summarized follows: SELFSB1: Pull 2.5V through Kohm resistor. resistor dividers needed supply correct high/low voltage values additional components using this signal (e.g., Intel MCH). SELFSB0: Pull 2.5V through resistor. Table gives SELFSB[1:0] line levels when each various processors installed legacy system. "New Systems", table assumes baseboard follows recommendations given this section.
Table SELFSB[1:0] Signal Values SELFSB[1:0] levels seen Systems SELFSB1(A7) Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor Pentium Xeon processor with cache SELSFB0(A9)
SELFSB[1:0] levels seen Legacy Systems SELFSB1(A7) Pentium Xeon processor with 256KB cache Pentium Xeon processor Pentium Xeon processor with cache SELSFB0(A9) Floating (N/C) Floating (N/C) Floating (N/C)
following figures illustrate recommended SELFSB[1:0] baseboard implementation, along with results various processor baseboard combinations. Pentium Xeon processor with 256KB cache only supported system frequency function MHz. Also, Pentium Xeon processor with cache only supported
Pentium® XeonProcessor System Compatibility Guidelines
system frequency function MHz. Note that "legacy system" refers platform originally designed Pentium Xeon processor MHz, whereas "new system" refers platform originally designed Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache.
ache
lock
SELFSB0
hipset isc. lock Logic
isc. ivid
SELFSB1
Figure system with Pentium® Xeonprocessor with 256KB cache installed (133 selected)
Pentium® XeonProcessor System Compatibility Guidelines
entium processor with cache
lock
SELFSB0
SELFSB1
hipset isc. lock Logic
isc. ivid
Figure system with Pentium® Xeonprocessor with cache installed (100 selected)
lock
SELFSB0
SELFSB1
hipset isc. lock Logic
isc. ivid
Figure system with Pentium® Xeonprocessor installed (100 selected)
Pentium® XeonProcessor System Compatibility Guidelines
ache
SELFSB0
SELFSB1
Figure Legacy system with Pentium® Xeonprocessor with cache installed (100 selected)
entium Xeon processor with cache
SELFSB0
SELFSB1
Figure Legacy system with Pentium® Xeonprocessor with cache installed (100 selected)
Pentium® XeonProcessor System Compatibility Guidelines
SELFSB0
SELFSB1
Figure Legacy system with Pentium® Xeonprocessor installed (100 selected)
15.0 SC330 SC330.1 Termination Cards
previous section discusses SELFSB[1:0] signals their intended implementation. systems that will support Pentium® Xeonprocessor with 256KB cache, SC330.1 termination card necessary. Earlier revisions terminator design guidelines define (refer Pentium® XeonProcessor Terminator Design Guidelines details). event these types termination cards installed system that connects SELFSB1 output signal together from both connectors, SELFSB1 line will always grounded termination card, regardless whether processor installed other connector MHz-capable. support designs that detect requested clock frequency from both processors before supplying clock input, termination card guidelines have been modified redefine (no-connect). This allows SELFSB1 line float high case where Pentium Xeon processor with 256KB cache installed.
16.0 BR0# (I/O), BR[3:1]# Lines
Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache same BR#[3:1] BR0# methodology implemented previous generations SC300 processors. Therefore, BREQ connectivity remains same. However, reduced signals used Pentium Xeon processor with 256KB cache since this processor supports 2-way configurations only. Attempting these processors 4-way configuration will result unsupported unpredictable behavior. Pentium Xeon processor with 256KB cache cartridge, only BR0#, BR1# BR3# (Bus Request) pins drive
Pentium® XeonProcessor System Compatibility Guidelines
BREQ[3:0]# signals system. assertion BR2# effect since seen processor. BR[3]# BR[1:0]# pins interconnected rotating manner other processor's BR[3]# BR[1:0]# pins. following table from Pentium Xeon processor with cache datasheet shows rotating interconnect baseboard connectivity between processor signals 4-way systems. 2-way systems, only BREQ0 BREQ1 signals need implemented.
Table BR[3:0]# Rotating Interconnect, 4-way System1,2 Signal BREQ0# BREQ1# BREQ2# BREQ3# Agent Pins BR0# BR1# BR2# BR3# Agent Pins BR3# BR0# BR1# BR2# Agent Pins BR2# BR3# BR0# BR1# Agent Pins BR1# BR2# BR3# BR0#
Information table reference only. Refer appropriate processor datasheet valid specifications. During power-up configuration, central agent must assert BR0# signal. symmetric agents sample their BR[3:0]# pins active-to-inactive transition RESET#. which agent samples active level determines agent This summarized table below 4-way systems. agents then configure their BREQ[3:0]# signals match appropriate signal protocol.
Table Agent Configuration1 BR0# BR1# BR3# Agent
Information table reference only. Refer appropriate processor datasheet valid specifications.
Pentium® XeonProcessor System Compatibility Guidelines
17.0 Processor Information Information Changes
Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache implement previously defined fields Processor Information (PI-ROM) allow visibility core OCVR voltage requirements. These features present SC330 products, used different Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache. These processors implement Cartridge Voltage Regulation (OCVR) device. This provides flexibility accommodate products with voltage input 2.8V product version different product version. implementation PI-ROM Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache allow software view desired voltage outputs feeding OCVR OCVR itself. Software could compare those values actual VRM/OCVR outputs (using converter) determine VRMs OCVRs operating correctly. implementation PI-ROM gives system designers means determining proper processor core voltage requirements. fields defined Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache coincide closely possible with those Pentium Xeon processor MHz. irrelevant Cache Voltage" field (for Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache) replaced with useful "core voltage" field. Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache (SC330.1) have (A56, "VIN_SENSE") which allows baseboard directly measure actual OCVR voltage (B83, "AN_CORE_VSENSE") which analog representation voltage input seen core. These voltages compared with desired voltage (indicated PI-ROM field) determine OCVR input output voltage varying from desired levels. following table excerpt taken from PI-ROM table listed Pentium Xeon processor with cache datasheet reference purposes only. entire valid PIROM specification, refer appropriate processor datasheet.
Table PI-ROM Table Excerpt Pentium® XeonProcessor with cache1 Offset/Section PROCESSOR: Bits Function S-spec/QDF Number Sample/Production Reserved Notes 8-bit ASCII characters Sample only Reserved future
Pentium® XeonProcessor System Compatibility Guidelines
Table PI-ROM Table Excerpt Pentium® XeonProcessor with cache1 Offset/Section Bits CORE: Function Checksum Processor Core Type Processor Core Family Notes byte checksum From CPUID From CPUID (Family Processor Core Model From CPUID (Model Processor Core Stepping Reserved OCVR option Input Voltage OCVR option Input Voltage Tolerance (0=2.8V, 600=5/12V) Reserved Maximum Core Frequency OCVR option Input Voltage OCVR option Input Voltage Tolerance (85=2.8V, 250=5/12V) CACHE: Reserved Checksum Reserved Reserved future byte checksum Reserved Reserved future 16-bit binary number MHz) Voltage (2800=2.8V, 5000=5/ 12V) Edge finger tolerance +/Voltage (0=2.8V, 12000=5/12V Edge finger tolerance +/From CPUID
Pentium® XeonProcessor System Compatibility Guidelines
Table PI-ROM Table Excerpt Pentium® XeonProcessor with cache1 Offset/Section Bits FEATURES: Function Cache Size Reserved OCVR Output Voltage OCVR Output Voltage Tolerance, High OCVR Output Voltage Tolerance, Reserved Checksum Processor Core Feature Flags Cartridge Feature Flags OCVR Present Serial Signature Electronic signature present Thermal Sense Device Present Thermal Reference Byte Present EEPROM Present Core present Cache present Number Devices Chain Present Present Present Present Present Present Present Present Present Present Present Present Present Present Always Zero 4-bit digit Voltage Core tolerance Core tolerance Reserved future byte checksum From CPUID Notes 16-Bit binary number Kbytes)
Pentium® XeonProcessor System Compatibility Guidelines
Table PI-ROM Table Excerpt Pentium® XeonProcessor with cache1 Offset/Section Bits OTHER: Function Reserved Checksum Reserved Notes Reserved future byte checksum Reserved future
Information table reference only. Refer appropriate processor datasheet valid power thermal specifications.
Table PI-ROM Information Pentium® XeonProcessor with 256KB Cache Pentium Xeon Processor with Cache. System Design Pentium® Xeonprocessor with 256KB cache Pentium Xeon processor with cache systems Implications Systems that rely PI-ROM information detect voltage requirements need evaluate fields present Pentium Xeon processor with 256KB cache Pentium Xeon processor with cache PI-ROM. Ensure software and/or embedded logic baseboard properly detect various processors supported system.

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