NTSC/PAL Digital Video Decoder MSDS Multimedia SLAS267
|
|
|
Top Searches for this datasheet
TVP5031
NTSC/PAL Digital Video Decoder
MSDS Multimedia
SLAS267
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Contents
Section
Title
Page
2-10 2-10 2-11 2-11 2-12 2-12 2-13 2-14 2-16 2-16 2-22 2-24 2-26 2-27 2-28 2-29 2-29 2-30
Introduction Features Applications Functional Block Diagram Terminal Assignments Ordering Information Terminal Functions Strapping Terminals Description Functional Description Analog Video Processing Converters 2.1.1 Video Input Selection 2.1.2 Analog Input Clamping Automatic Gain Control Circuits 2.1.3 Converter Digital Processing 2.2.1 Decimation Filter 2.2.2 Separation 2.2.3 Luminance Processing 2.2.4 Chrominance Processing 2.2.5 Clock Circuits Genlock Control Video Output Format 2.4.1 Sampling Frequencies Patterns 2.4.2 Video Port 20-Bit 16-Bit 4:2:2 Output Format Timing 2.4.3 Video Port 10-Bit 8-Bit 4:2:2 ITU-R BT.656 Output Format Timing Synchronization Signals Host Interface 2.6.1 Host Interface 2.6.2 Parallel Host Interface 2.6.3 Parallel Host Interface 2.6.4 Parallel Host Interface 2.6.5 Parallel Host Interface Register 2.6.6 Parallel Host Interface Microcode Write Operation 2.6.7 Parallel Host Interface Microcode Read Operation Data Processor 2.7.1 Teletext Data Byte Order
2.10 2.11
2.7.2 Teletext Ancillary Data Video Stream Video Data Output Reset Initialization Internal Control Registers Register Definitions 2.11.1 Video Input Source Selection 2.11.2 Analog Channel Controls 2.11.3 Operation Mode Controls 2.11.4 Miscellaneous Control 2.11.5 Color Killer Threshold Control 2.11.6 Luminance Processing Control 2.11.7 Luminance Processing Control 2.11.8 Brightness Control 2.11.9 Color Saturation Control 2.11.10 Control 2.11.11 Contrast Control 2.11.12 Outputs Data Rates Select 2.11.13 Horizontal Sync HSYN Start NTSC/PAL 2.11.14 Vertical Blanking VBLK Start 2.11.15 Vertical Blanking VBLK Stop 2.11.16 Chrominance Control 2.11.17 Chrominance Control 2.11.18 Interrupt Reset Register 2.11.19 Interrupt Enable Register 2.11.20 Interrupt Configuration Register 2.11.21 Program Write 2.11.22 Microprocessor Reset Clear 2.11.23 Major Software Revision Number 2.11.24 Status Register 2.11.25 Status Register 2.11.26 Status Register 2.11.27 Status Register 2.11.28 Interrupt Status Register 2.11.29 Interrupt Active Register 2.11.30 Minor Software Revision Number 2.11.31 Status Register 2.11.32 Program Read 2.11.33 Filter Parameters 2.11.34 Filter Parameters 2.11.35 Error Filtering Enables 2.11.36 Transaction Processing Enables 2.11.37 Control Register 2.11.38 Line Enable Registers 2.11.39 Sync Pattern Register
2-31 2-32 2-32 2-33 2-35 2-35 2-35 2-35 2-37 2-38 2-38 2-39 2-39 2-39 2-40 2-40 2-40 2-41 2-42 2-42 2-43 2-43 2-44 2-44 2-45 2-45 2-45 2-45 2-46 2-47 2-47 2-47 2-48 2-48 2-48 2-49 2-49 2-50 2-51 2-52 2-52 2-53 2-53 2-54
2.11.40 Teletext FIFO 2.11.41 Closed Caption Data 2.11.42 Buffer Status 2.11.43 Interrupt Threshold 2.11.44 Interrupt Line Number 2.11.45 FIFO Control 2.11.46 FIFO Test 2.11.47 Interrupt Status Register 2.11.48 Interrupt Enable Register 2.11.49 Parallel Host Interface Teletext FIFO 2.11.50 Parallel Host Interface Status/Interrupt Electrical Specifications Absolute Maximum Ratings Recommended Operating Conditions 3.2.1 Crystal Specifications Electrical Characteristics Over Recommended Voltage Temperature Ranges, DVDD AVDD 70°C 3.3.1 Electrical Characteristics 3.3.2 Analog Processing Converters 3.3.3 Clocks, Video Data, Sync Timing 3.3.4 Host Port Timing 3.3.5 Parallel Host Interface 3.3.6 Parallel Host Interface 3.3.7 Parallel Host Interface Mechanical Data
2-54 2-54 2-55 2-55 2-55 2-56 2-56 2-57 2-57 2-58 2-58
List Illustrations
Figure Title Analog Video Processors Converters Digital Video Signal Processing Block Diagram Decimation Filter Frequency Response Separation Block Diagram Color Low-Pass Filter Frequency Response Color Low-Pass Filter With Notch Filter Frequency Response (NTSC PAL-M Square Pixel Sampling) Color Low-Pass Filter With Notch Filter Characteristics (13.5 Sampling) Color Low-Pass Filter With Notch Filter Frequency Response (PAL Square Pixel Sampling) 3-Line Adaptive Comb Filtering 2-10 Comb Filters Frequency Response 2-11 Chroma Trap Filter Frequency Response 2-12 Chroma Trap Filter Frequency Response (13.5 Sampling) 2-13 Chroma Trap Filter Frequency Response (PAL Square Pixel Sampling) 2-14 Luminance Edge-Enhancer Peaking Block Diagram 2-15 Peaking Filter Response, NTSC PAL-M Square Pixel Sampling 2-16 Peaking Filter Response, 13.5 Sampling Rate 2-17 Peaking Filter Response, Square Pixel 2-18 Clock Circuit Diagram 2-19 Example Reference Clock Configurations 2-20 GLCO Timing 2-21 4:2:2 Sampling 2-22 20-Bit 4:2:2 Output Format 2-23 20-Bit 4:2:2 Output Format 2-24 Vertical Synchronization Signals 2-25 Horizontal Synchronization Signals 2-26 Data Transfer Example 2-27 Parallel Host Interface Timing 2-28 Parallel Host Interface Timing 2-29 Parallel Host Interface Timing 2-30 Address Register Page
2-10 2-10 2-11 2-12 2-12 2-13 2-14 2-15 2-17 2-23 2-25 2-26 2-27
Parallel Host Interface Timing Parallel Host Interface Timing Parallel Host Interface Timing
List Tables
Table Title Summary Line Frequencies, Data Rates, Pixel Counts Host Port Mode Select Host Port Terminal Description Parallel Host Interface Terminal Description Parallel Host Interface Terminal Description Parallel Host Interface Terminal Description Teletext Data Byte Order NABTS 525-Line Ancillary Data Sequence Dummy Timing Ancillary Data Sequence 2-10 Data 2-11 Reset Sequence 2-12 Registers Summary 2-13 Analog Channel Video Mode Selection 2-14 Digital Output Control 2-15 Vertical Blanking Interval Start 2-16 Chrominance Comb Filter Selection Page 2-12 2-16 2-17 2-22 2-24 2-26 2-30 2-31 2-31 2-32 2-32 2-33 2-35 2-37 2-42 2-43
viii
Introduction
TVP5031 high quality single-chip digital video decoder that converts base-band analog National Television System Committee (NTSC) phase alternating line (PAL) video into digital component video. TVP5031 includes 9-bit converter with sampling. Sampling square-pixel ITU-R BT.601 MHz) line-locked correct pixel alignment. output formats 8-bit, 10-bit 16-bit 4:2:2, 8-bit 10-bit ITU-R BT.656 with embedded synchronization. TVP5031 utilizes Texas Instruments patented technology locking weak, noisy, unstable signals, chroma frequency control output generated synchronizing downstream video encoders. Complementary three-line adaptive (2-H delay) comb filtering available both luma chroma data paths reduce both cross-luma cross-chroma artifacts; chroma trap filter also available. Video characteristics including hue, contrast, saturation programmed using four supported host port interfaces; three parallel host interface (PHI) modes. TVP5031 generates synchronization, blanking, field, lock clock signals addition digital video outputs. TVP5031 includes methods advanced vertical blanking interval (VBI) data retrieval. data processor slices, parses, performs error checking teletext data several formats. built-in FIFO stores lines teletext data, with proper host synchronization full-screen teletext retrieval enabled. data processor also retrieves closed-caption data. TVP5031 also pass through over sampled composite data host-based software processing. main blocks TVP5031 include: Analog processors converters separation Chrominance processor Luminance processor Clock/timing processor power-down control Output formatter Host port interface data processor
Features
Accepts NTSC composite video analog video inputs composite video fully differential CMOS analog preprocessing channel with clamping best performance High speed over-sampling 9-bit converter Patented architecture locking weak, noisy, unstable signals Single 14.31818 reference crystal standards Line-locked clock sampling square-pixel rates Programmable output data rates: 12.2727 Square-Pixel (NTSC) 14.7500 Square-Pixel (PAL) 13.5 ITU-R BT.601 (NTSC PAL)
Optional automatic switching between NTSC standards
Complementary 3-line (2-H delay) adaptive comb filters both cross-luminance cross-chrominance noise reduction Subcarrier genlock output synchronizing color subcarrier external encoder Standard programmable video output formats: 16-bit 4:2:2 YCbCr 20-bit 4:2:2 YCbCr 8-bit 4:2:2 YCbCr 10-bit 4:2:2 YCbCr ITU-R BT.656 8-bit 4:2:2 with embedded syncs ITU-R BT.656 10-bit 4:2:2 with embedded syncs
Advanced programmable video output formats: oversampled data during active video Sliced data ancillary data video stream
Teletext (NABTS, WST) closed-caption decode with FIFO Programmable host port options including three parallel host interface (PHI) modes Brightness, contrast, saturation control through host port tolerant digital ports 80-pin TQFP package
Applications
Digital image processing Video conferencing Multimedia Digital video Desktop video Video capture Video editing Security applications
Functional Block Diagram
VI_1A VI_1B Channel Luma/Chroma Separation
Luminance Processing Output Formatter Chrominance Processing
Y[9:0] UV[9:0]
D[7:0]
Interface Parallel Host Interface
XTAL1 XTAL2 SCLK PCLK PREF GLCO
Line Chroma PLLs
Sync Processor
HSYN VSYN PALI GPCL RSTINB
Terminal Assignments
TQFP PACKAGE (TOP VIEW)
DGND DVDD DGND DVDD DVDD DGND DVDD INTREQ
GPCL DGND XTAL2 XTAL1 DVDD PALI GLCO HSYN VSYN AVID PCLK PREF SCLK RSTINB RSTOUTB TESTE PLL_AGND
Ordering Information
DEVICE: PFP: TVP5031CPFP Plastic flat-pack with PowerPAD
PowerPAD trademark Texas Instruments.
REFM REFP AGND CLAMP2 AFE_GND NSUB AFE_V PLL_AV
CLAMP1 AGND VI_1B VI_1A
Terminal Functions
TERMINAL NAME Analog Video VI_1A VI_1B Clock Signals PCLK PREF SCLK XTAL1 XTAL2 Pixel clock output. frequency 12.2727 square-pixel NTSC, 14.75 square-pixel PAL, 13.5 ITU-R.BT.601 sampling modes. Clock phase reference signal. This signal qualifies clock edges when SCLK used clock data that changing pixel clock rate. System clock output with twice frequency pixel clock (PCLK). External clock reference. user connect XTAL1 TTL-compatible oscillator terminal crystal oscillator. user connect XTAL2 other terminal crystal oscillator connect XTAL2 all. single 14.31818 crystal oscillator needed square pixel sampling ITU-R BT.601 sampling. 10-bit digital chrominance outputs. These terminals also configured output data from channel converter. Analog video inputs. composite inputs. inputs must coupled. recommended coupling DESCRIPTION
Digital Video UV[9:0]
Y[9:0]
10-bit digital luminance outputs, 10-bit multiplexed luminance chrominance outputs. These terminals also configured output data from channel converter.
Host Port-Bus A[1:0] D[7:0] mode: address port. mode: data port-bit [7:0].
INTREQ
mode: Interrupt Request (INTREQ). Pullup required configured open drain. mode: Interrupt Request (INTREQ). Pullup required configured open drain. mode: port data acknowledgement ready signal (DTACK) mode: Serial clock (SCL) pullup required. mode: port read-write write (RW/WR) mode: Serial data (SDA) pullup required. mode: port data strobe read signal (DS/RD) mode: port chip select (VC) mode: Slave address select (I2CA)
Terminal Functions (Continued)
TERMINAL NAME RSTOUTB RSTINB GLCO Miscellaneous Signals Reset output, active Reset input, active Output enable terminals. Output enable also controllable host port. When this terminal logic forces output terminals high impedance states (active low). This serial output carries color information. slave device decode information allow chroma frequency control TVP5031. Data transmitted SCLK rate. Additionally, this terminal, conjunction with PALI FID, used determine host port mode configuration during initial powerup. General-purpose control logic. This terminal three functions: General-purpose output. this mode state GPCL directly programmed host port. Vertical blank output. this mode GPCL terminal used indicate vertical blanking interval output video. beginning times this signal programmable host port. Sync lock control input. this mode when GPCL high, output clock frequencies sync timing forced nominal values. Clamp voltage outputs. Connect decoupling capacitor from each terminal AGND. connection Connect 1.0-µF capacitor from this terminal AGND. Analog supply. Connect 3.3-V analog supply Analog ground Analog grounds Analog supply. Connect 3.3-V analog supply Digital grounds ground. Connect analog ground supply. Connect 3.3-V analog supply Digital supply. Connect 3.3-V Substrate ground. Connect analog ground reference supply. Connect 4.7-µF capacitor from each terminal AGND. Connect 1.0-µF capacitor across REFM REFP terminals. DESCRIPTION
GPCL
CLAMP1, CLAMP2 Power Supplies AFE_VDD AFE_GND AGND AVDD DGND PLL_AGND PLL_AVDD DVDD NSUB REFP REFM Sync Signals AVID
Active video indicator. This signal high during horizontal active time video output terminals. AVID continues toggle during vertical blanking intervals. This terminal placed high-impedance state. During reset, AVID input, used program behavior Y[9:0], UV[9:0], HSYN, VSYN, AVID immediately after completion reset. AVID pulled during reset, Y[9:0], UV[9:0], HSYN, VSYN, AVID, PALI will actively driving after reset. AVID pulled down during reset, Y[9:0], UV[9:0], HSYN, VSYN, AVID, PALI will remain high-impedance state after reset.
Odd/even field indicator vertical lock indicator. odd/even indicator, logic indicates field. vertical lock indicator, logic indicates internal vertical locked state. Additionally, this terminal conjunction with GLCO PALI used determine host port configuration during initial power reset.
Terminal Functions (Continued)
TERMINAL NAME PALI Sync Signals (Continued) line indicator horizontal lock indicator. line indicator, logic indicates noninverted line, logic indicates inverted line. horizontal lock indicator, logic indicates internal horizontal locked state. This terminal input terminal during reset used conjunction with GLCO select mode host interface. During reset, this terminal pulled pulled down VSYN Vertical sync signal DESCRIPTION
Strapping Terminals Description
following terminals have reset strapping options. states these terminals sampled during reset configure TVP5031 various modes operation. These terminals temporarily turned into inputs with weak internal pulldowns (~40 resistor) during reset return their normal operation after reset. Each following terminals pulled with 10-K resistor corresponding left undriven during reset, relying internal pulldown resistor pull terminal corresponding bit.
TERMINAL NAME AVID PREF PALI GLCO DESCRIPTION output enable (bit HSYN, VSYN, AVID, FID, PALI output enable (bit miscellaneous control Register Clock enable (bit miscellaneous control Register Host interface mode (see Table 2-2). Host interface mode (see Table 2-2). Host interface mode (see Table 2-2).
Functional Description
Analog Video Processing Converters
Figure shows functional diagram analog video preprocessor converter. This block provides analog interface video inputs. accepts inputs performs source selection, video clamping, video amplification, analog-to-digital conversion, fine gain offset adjustments center digitized video signal. TVP5031 ANALOG FRONT
CH1_CLAMP_MODE CH1_MUX_CTRL VI_1A VI_1B CLAMP CH1_GAIN_OFFSET CH1_FINE_ADJUST BITS BITS CH1_OUT
FINE GAIN, OFFSET ADJUST
BANDGAP REFM
BUFFER
SCLK
CLAMP1
CLAMP BUFFER
CLAMP2
REFP
Figure 2-1. Analog Video Processors Converters
2.1.1
Video Input Selection
TVP5031 analog channel that accepts video inputs coupled through capacitors. internal video multiplexers configured host port. analog video inputs connected selectable individual composite video inputs.
2.1.2
Analog Input Clamping Automatic Gain Control Circuits
internal clamping circuit restores coupled video signal fixed level. clamping circuit provides line-by-line restoration video sync level fixed reference voltage. modes clamping provided, coarse fine. coarse mode, most negative portion input signal (typically sync tip) clamped fixed level. Fine clamp mode enabled prevent spurious level shifting caused noise more negative than sync input signal. fine clamp mode selected, clamping only enabled during sync period. S-video requires fine clamp mode chroma channel proper operation. External capacitors terminal CLAMP1 CLAMP2 required store filter clamp voltage. Input video signal amplitude vary significantly from nominal level 1Vpp. automatic gain control circuit (AGC) adjusts signal amplitude utilize maximum range converter without clipping. adjusts gain achieve desired sync amplitude. Some nonstandard video signals contain peak white levels that saturate converter. these cases, automatically cuts back gain avoid clipping. digital data path, scaling applied output data reach CCIR601 levels. This scaling introduces distortion digitized sync back porch levels precise. fine gain offset adjustment block precisely controls sync back porch levels achieve best linearity performance.
2.1.3
Converter
TVP5031 contains 9-bit oversampling converter that digitizes analog video inputs. input digitized greater than times Nyquist sampling rate, only simple external antialiasing pass filter needed prevent out-of-band frequencies. converter reference voltages terminals REFP REFM require external capacitor network filtering, shown Figure 2-1.
Digital Processing
Figure block diagram TVP5031 digital video decoder processing. This block receives digitized composite video signal from converter performs separation, signal enhancements. also generates horizontal vertical syncs. digital output programmed into various formats: 20-bit, 16-bit, 10-bit 8-bit 4:2:2, 10-bit 8-bit ITU-R BT.656 parallel interface standard. This block also retrieves data stores FIFO. data from FIFO read either through host port output ancillary data video port. TVP5031 DIGITAL PROCESSING
COMPOSITE DECIMATION FILTER
GAIN CLAMP CTRL INPUT FINE CTRL
ANALOG PROCESSOR CONTROL DATA SLICER HOST PORT
INTREQ VC[3:0] A[1:0] D[7:0]
AVID VSYN HSYN PALI GLCO
SYNCHRONIZATION SEPARATION
LUMA/CHROMA PROCESSING XTAL1 XTAL2 SCLK PCLK PREF RSTOUTB RSTINB CLOCK SIGNAL GENERATION POWER CONTROL
DATA BYPASS
OUTPUT FORMATTER
Y[9:0] UV[9:0]
Figure 2-2. Digital Video Signal Processing Block Diagram
2.2.1
Decimation Filter
Digitized composite video PCLK rate first passes through decimation filter that reduces data rate from PCLK. decimation filter half-band filter whose frequency response shown Figure 2-3. applications that cannot tolerate high frequency rolloff, decimation filter bypassed host port. oversampling decimation filtering effectively increase overall signal-to-noise ratio This advantage lost decimation filtering bypassed.
Amplitude CCIR 6.10 NTSC 5.54 Frequency
6.66
Figure 2-3. Decimation Filter Frequency Response
2.2.2
Separation
Figure illustrates luminance/chrominance (Y/C) separation process TVP5031. 9-bit composite video multiplied subcarrier signals quadrature demodulator generate color difference signals then low-pass filtered achieve desired bandwidth. adaptive 3-line comb filter separates from based unique property color phase shift from line line. Chroma remodulated through quadrature modulator subtracted from line-delayed composite video generate luma. This form separation completely complementary, thus there loss information. However some applications, desirable limit bandwidth avoid crosstalk. that case, notch filters turned accommodate some viewing preferences, peaking filter also available luma path. Contrast, brightness, hue, saturation programmable. TVP5031 SEPARATION
Composite Line Delay
Peaking Quadrature Modulation
Subcarrier Generation
Contrast Brightness Saturation Control Notch Filter
Color 3-Line Adaptive Comb Filter
Notch Filter
Quadrature Demodulation
Burst Accum
Notch Filter Notch Filter
Delay
Color
Delay
Burst Accum
Sync Block
Figure 2-4. Separation Block Diagram
2.2.2.1 Color Low-Pass Filter
Color low-pass filter frequency responses shown Figures 2-8. High filter bandwidth preserves sharp color transitions produces crisp color boundaries. However nonstandard video sources that have asymmetrical side bands, desirable limit filter bandwidth avoid crosstalk. Color low-pass filter bandwidth programmable enabling three notch filters.
Amplitude Frequency NTSC 1.11 CCIR 1.22 1.33 Amplitude Frequency Notch1 Filter Notch2 Filter Notch Filter 1.11 Notch3 Filter
Figure 2-5. Color Low-Pass Filter Frequency Response
Figure 2-6. Color Low-Pass Filter With Notch Filter Frequency Response (NTSC PAL-M Square Pixel Sampling)
Amplitude Frequency Notch2 Filter Notch Filter 1.22 Amplitude Notch3 Filter Notch1 Filter
Notch2 Filter Notch Filter 1.33 Notch3 Filter Notch1 Filter
Frequency
Figure 2-7. Color Low-Pass Filter With Notch Filter Characteristics (13.5 Sampling)
Figure 2-8. Color Low-Pass Filter With Notch Filter Frequency Response (PAL Square Pixel Sampling)
2.2.2.2 Adaptive Comb Filter
separation done using adaptive 3-line (2-H delay), fixed 3-line, fixed 2-line comb filters, chroma trap filter shown Figure 2-9. Adaptive comb filtering available both luminance chrominance. adaptive comb filter algorithm computes vertical horizontal contours color based block pixels. there sharp color transition, comb filtering applied lines that have less color changes. there color transition, 3-line comb filtering used with choice filter coefficients [1/4, 1/2, 1/4] [1/2, 1/2] programmable host port. Characteristics 2-line 3-line comb filters shown Figure 2-10. filter frequency plots show that both 2-line 3-line (with filter coefficients [1/4,1/2,1/4] comb filters have zeros horizontal line frequency separate interleaved spectrum NTSC. 3-line comb filter less cross-luma cross-chroma noise slightly sharper filter off. 3-line comb filter with filter coefficients[1/2, 1/2] zeros horizontal line frequency. This should used only because degrees phase shifting from line line. comb filter selectively bypassed luma chroma path. comb filter bypassed luma path, then chroma trap filters used which shown Figures 2-11 2-13. TI's patented adaptive comb filter algorithm reduces artifacts such hanging dots color boundary detects properly handles false colors high frequency luminance images such multiburst pattern circle pattern. Adaptive comb filtering recommended mode operation. ADAPTIVE COMB FILTER
Adap_EN Comb_EN Adaptive Comb Filter Algorithm Filter Select
Comb12 Luma Comb
Line Delay
Comb123
Comb23
Line Delay
Comb13 Comb Bypass
Chroma Comb
Figure 2-9. 3-Line Adaptive Comb Filtering
Amplitude Amplitude 0.25, 0.5, 0.25 Frequency 0.5, 0.5, 0.5,
Frequency Notch Filter Notch1 Filter Notch3 Filter Notch2 Filter
Figure 2-10. Comb Filters Frequency Response
Figure 2-11. Chroma Trap Filter Frequency Response
Amplitude Amplitude Frequency Notch Filter Notch1 Filter Notch3 Filter Notch2 Filter
Notch Filter Notch1 Filter Notch3 Filter
Notch2 Filter
Frequency
Figure 2-12. Chroma Trap Filter Frequency Response (13.5 Sampling)
Figure 2-13. Chroma Trap Filter Frequency Response (PAL Square Pixel Sampling)
2.2.3
Luminance Processing
digitized composite video signal passes through either luminance comb filter chroma trap filter, either which removes chrominance information from composite signal generate luminance signal. luminance signal then input peaking circuit. Figure 2-14 illustrates basic functions luminance data path. High frequency components luminance signal enhanced peaking filter (edge-enhancer). Figure 2-15, Figure 2-16, Figure 2-17 show characteristics peaking filter four different gain settings programmable host port.
Gain
BANDPASS Filter
Peaking Filter
Delay
Figure 2-14. Luminance Edge-Enhancer Peaking Block Diagram
2.40 Gain Amplitude Amplitude Gain Frequency Frequency Gain Gain Gain Gain Gain Gain 2.64
Figure 2-15. Peaking Filter Response, NTSC PAL-M Square Pixel Sampling
Figure 2-16. Peaking Filter Response, 13.5 Sampling Rate
2.89
Gain Gain Amplitude Gain Gain Frequency
Figure 2-17. Peaking Filter Response, Square Pixel
2.2.4
Chrominance Processing
quadrature demodulator extracts components from composite signal. signals then pass through gain control stage chroma saturation adjustment. comb filter applied both eliminate cross-chrominance noise. control achieved with phase shift digitally controlled oscillator. automatic color killer (ACK) circuit also included this block. will suppress chroma processing when color burst video signal weak present.
2.2.5
Clock Circuits
internal line-locked generates system pixel clocks. Figure 2-18 shows simplified clock circuit diagram. digital control oscillator (DCO) generates reference signal horizontal PLL. 14.318 clock required drive DCO. This input TVP5031 level XTAL1 terminal, crystal 14.318 fundamental resonant frequency connected across terminals XTAL1 XTAL2. Figure 2-19 shows reference clock configurations. example crystal circuit shown Figure 2-19 parallel-resonant crystal with 14.31818 fundamental frequency), external capacitors should have following relationship: Cstray Where Cstray terminal capacitance with respect ground.
Digitized Video Lowpass Filter Sync Detector Phase Detector Loop Filter
Digital Control Oscillator
Crystal Clock Generator
XTAL1 XTAL2
Clock Generation Circuit
Line-Locked Clock
SCLK PCLK
Figure 2-18. Clock Circuit Diagram
14.31818 Crystal
TVP5031 14.31818 Clock
TVP5031
XTAL1
XTAL1
XTAL2
XTAL2
Figure 2-19. Example Reference Clock Configurations TVP5031 generates three signals PCLK, SCLK, PREF used clocking data. PCLK, pixel clock, used clocking data 20-bit 16-bit 4:2:2 output formats. SCLK twice PCLK frequency used clocking data 10-bit 8-bit 4:2:2 well ITU-R BT.656 formats. PREF used clock qualifier with SCLK clock data 20-bit 16-bit 4:2:2 formats.
2-10
Genlock Control
frequency control word internal color subcarrier digital control oscillator (DCO) sub-carrier phase reset transmitted GLCO terminal. frequency control word 23-bit binary number. frequency calculated from following equation:
Fctrl
sclk
where Fdco frequency DCO, Fctrl 23-bit frequency control Fsclk frequency SCLK. last (bit frequency control always write chrominance control register host port sub-address causes sub-carrier phase reset sent next scan line GLCO. active reset occurs SCLKs after transmission last frequency control. Upon transmission reset bit, phase TVP5031 internal sub-carrier reset zero. genlocking slave device connected GLCO terminal information GLCO synchronize internal color phase achieve clean line color lock. Figure 2-20 shows timing GLCO.
SCLK
GLCO
>128 SCLK
SCLK
SCLK
SCLK Start 23-Bit frequency control
SCLK reset
Figure 2-20. GLCO Timing
Video Output Format
TVP5031 supports both square-pixel ITU-R BT.601 sampling formats multiple Y-UV output formats: 20-bit 4:2:2 16-bit 4:2:2 10-bit 4:2:2 8-bit 4:2:2 10-bit ITU-R BT.656 8-bit ITU-R BT.656
2-11
2.4.1
Sampling Frequencies Patterns
sampling frequencies that control number pixels line differ depending video format standards. Table shows summary sampling frequencies. TVP5031 outputs data 4:2:2 sampling pattern. Every second sample both luminance chrominance sample. remainder luminance-only samples. Table 2-1. Summary Line Frequencies, Data Rates, Pixel Counts
STANDARDS NTSC, square-pixel NTSC, ITU-R BT.601 PAL(B,D,G,H,I), square-pixel PAL(B,D,G,H,I),ITU-R BT.601 PAL(M),square-pixel PAL(M),ITU-R BT.601 PAL(N),square-pixel PAL(N),ITU-R BT.601 HORIZONTAL LINE RATE (kHz) 15.73426 15.73426 15.625 15.625 15.73426 15.73426 15.625 15.625 PIXELS LINE ACTIVE PIXELS LINE Y716 U358 V358 PCLK FREQUENCY (MHz) 12.2727 13.50 14.75 13.50 12.2727 13.50 14.75 13.50 Y717 Y718 U359 V359 SCLK FREQUENCY (MHz) 24.54 27.00 29.50 27.00 24.54 27.00 29.50 27.00 Y719
Luminance-Only Sample Luminance Chrominance Sample Numbering shown 13.5 sampling
Figure 2-21. 4:2:2 Sampling
2.4.2
Video Port 20-Bit 16-Bit 4:2:2 Output Format Timing
SCLK
PREF
PCLK
Y[9:0]
Y716
Y717
Y718
Y719
UV[9:0]
U358
V358
U359
V359
Numbering shown 13.5 sampling
Figure 2-22. 20-Bit 4:2:2 Output Format
2-12
2.4.3
Video Port 10-Bit 8-Bit 4:2:2 ITU-R BT.656 Output Format Timing
SCLK
Y[9:0]
U359
Y718
V359
Y719
UV[9:0] HIGH Numbering shown 13.5 sampling
Figure 2-23. 20-Bit 4:2:2 Output Format
2-13
Synchronization Signals
525-Line Composite Video Field VSYN GPCL/VBLK
Composite Video Even Field VSYN GPCL/VBLK
625-Line Composite Video Field VSYN
GPCL/VBLK
Composite Video Even Field VSYN GPCL/VBLK
Note: Line numbering conforms ITU-R BT-470 Horizontal Detail (default HSYN timing) HSYN
Figure 2-24. Vertical Synchronization Signals
2-14
10-bit 4:2:2 timing with pixel clock (SCLK) reference. ITU-R BT.656 timing also shown NTSC Datastream NTSC Datastream Datastream 1436 1436 1276 1532 1437 1437 1438 1439 1440 1441 1438 1439 1440 1441 1471 1463 1472 1464 1599 1591 1600 1592 1711 1712 1713 1714 1715 1723 1724 1725 1726 1727
1277 1278
1279 1280 1281 1535
1323 1324
1451
1452 1555 1556 1557 1558 1559
1533 1534
1536 1537
1587 1588
1715
1716
1883 1884 1885 1886 1887
HSYN AVID
NOTE: AVID rising edge occurs SCLK cycles early when ITU656 output mode
HSYN timing shown valid when HSYN start (register 16/17) default value 80h.
20-bit 4:2:2 timing with pixel clock (PCLK) reference. NTSC NTSC
HSYN
AVID
HSYN timing shown valid when HSYN start (register 16/17) default value 80h. Figure 2-25. Horizontal Synchronization Signals
2-15
Host Interface
host interface used initialize internal microprocessor, read write status registers control registers, access sliced data. interface modes supported TVP5031 I2C, three parallel interface modes. host interface configured powerup reset using GLCO, PALI, terminals shown Table 2-2. Table 2-2. Host Port Mode Select
INTERFACE CONFIGURATION Parallel Parallel Parallel NOTE: pullup pulldown TERMINALS GLCO PALI
2.6.1
Host Interface
TVP5031 host interface configured operation attaching external pullup pulldown resistors GLCO, PALI, terminals. following combination resistors required select host mode pullup pulldown).
GLCO host port enabled PALI
2.6.1.1 Host Port Select
standard consists signals, serial input/output data line (VC1) input/output clock line (VC0), which carry information between devices connected bus. third signal (VC3) used slave address selection. Although system multi-mastered, TVP5031 will function slave device only. Both bidirectional lines connected positive supply voltage pull resistor. When free, both lines high. slave address select terminal (VC3) enables TVP5031 devices tied same bus.
2-16
Table summarizes terminal functions I2C-mode host interface. Table 2-3. Host Port Terminal Description
SIGNAL (I2CA) (SCL) (SDA) (open drain) (open drain) TYPE DESCRIPTION Slave address selection Input/output clock line Input/output data line
VC1(SDA)
VC0(SCL) ADDRESS DATA DATA
Start Condition
VC1(SDA)
VC0(SCL)
DATA
DATA
Data Transfer
Stop
Figure 2-26. Data Transfer Example Data transfer rate kbits/s. number interfaces connected dependent capacitance limit data line must stable during high period clock. high state data line only change with clock signal line being low. multiple bytes transferred during read write operation, internal subaddress automatically incremented. high transition line while high indicates start condition. high transition line while high indicates stop condition. Acknowledge (SDA Low) Not-Acknowledge (SDA High)
Every byte placed line must 8-bits long. number bytes which transferred unrestricted. Each byte must followed acknowledge bit. slave cannot receive another complete byte data until performed another function, hold clock line (SCL) force master into wait state. Data transfer then continues when slave ready another byte data release clock line (SCL). Data transfer with acknowledge obligatory. acknowledge related clock pulse generated master. master releases line high during acknowledge clock pulse. slave must pull down line during acknowledge clock pulse that remains stable during high period this clock pulse.
2-17
When slave does acknowledge slave address, data line must left high slave. master then generate stop condition abort transfer. slave does acknowledge slave address some time later transfer cannot receive more data bytes, master must again abort transfer. This indicated slave generating acknowledge first byte follow. slave leaves data line high master generates stop condition. master-receiver involved transfer, must signal data slave-transmitter generating acknowledge last byte that clocked slave. slave-transmitter must release data line allow master generate stop repeated start condition.
2.6.1.2 Write Operation
Data transfers occur utilizing following illustrated formats. master initiates write operation TVP5031 generating start condition followed TVP5031s address 101110X TVP5031 address when terminal tied when terminal tied high, first order, followed indicate write cycle. After receiving acknowledge from TVP5031, master presents subaddress register, first block registers wants write, followed more bytes data, first. TVP5031 acknowledges each byte after completion each transfer. master terminates write operation generating stop condition.
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Write register address (master) STEP Acknowledge (slave) STEP Write data (master) STEP Acknowledge (slave) addr Data Data Data Data Data Data Data Data addr addr addr addr addr addr addr
Repeat steps until data been written STEP Stop (master)
2.6.1.3 Read Operation
read operation consists phases. first phase address phase. this phase, master initiates write operation TVP5031 generating start condition followed TVP5031s address 101110X, first order, followed indicate write cycle. After receiving acknowledge from TVP5031, master presents subaddress register, first block registers wants read. After cycle acknowledged, master terminates cycle immediately generating stop condition. second phase data phase. this phase, master initiates read operation TVP5031 generating start condition followed
2-18
TVP5031s address 101110X, first order, followed indicate read cycle. After acknowledge from TVP5031, master receives more bytes data from TVP5031. master acknowledges transfer each byte. After last data byte desired been transferred from TVP5031 master, master generates acknowledge followed stop.
2.6.1.4 Read Phase
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Read register address (master) STEP Acknowledge (slave) STEP Stop (master) addr addr addr addr addr addr addr addr
2.6.1.5 Read Phase
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Read data (slave) STEP Acknowledge (master) Data Data Data Data Data Data Data Data
Repeat steps last byte read STEP Read data (slave) STEP acknowledge (master) STEP Stop (master) Data Data Data Data Data Data Data Data
2-19
2.6.1.6 Microcode Write Operation
Data written during micro-code write operation will written TVP5031 program RAM. During write cycle microprocessor will reset point location zero program will remain reset. Upon completion write operation, microprocessor clear-reset operation required. This performed writing into register clear reset resume microprocessor function. (There specific data requirement written into register, data will resume microprocessor function.)
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Write register address (master)
Write program address=7E
STEP Acknowledge (slave) STEP Write data (master) STEP Acknowledge (slave) Data Data Data Data Data Data Data Data
Repeat steps until data been written. STEP Stop (master)
2-20
2.6.1.7 Microprocessor Clear Reset
Start (master) General address (master) Acknowledge (slave) Write register address (master)
Write microprocessor clear reset address=7F
Acknowledge (slave) Write data (master) Data Data Data Data Data Data Data Data
data written will start microprocessor.
Acknowledge (slave) Stop (master)
2.6.1.8 Microcode Read Operation
Data read during microcode write operation will read from TVP5031 program RAM. During read cycle microprocessor will reset point location zero program will remain reset. Upon completion read operation, microprocessor clear-reset operation required. This performed writing into register clear reset resume microprocessor function. (There specific data requirement written into register, data will resume microprocessor function.)
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Read register address (master)
Read address=8E
STEP Acknowledge (slave) STEP Stop (master)
2-21
2.6.1.9 Read Phase
STEP Start (master) STEP General address (master) STEP Acknowledge (slave) STEP Read data (slave) STEP Acknowledge (master) Data Data Data Data Data Data Data Data
Repeat STEP STEP last byte read from program RAM.
STEP Read Data (slave) STEP acknowledge (master) STEP Stop (master) Data Data Data Data Data Data Data Data
2.6.2
Parallel Host Interface
Parallel host interface compatible with Video Electronics Standards Association (VESA) Video Module Interface (VMI) proposal version mode terminal descriptions defined Table 2-4. Table 2-4. Parallel Host Interface Terminal Description
TERMINAL A[1:0] D[7:0] INTREQ SIGNAL HA[1:0] HD[7:0] RD/WR DTACK INTREQ TYPE Address from host Bidirectional data Chip select, active Data strobe, active Read, active high Data acknowledge Interrupt request, Open drain default, active low, pullup resistor required configured, subaddress conventional CMOS buffer, active high, pullup required. Write, active DESCRIPTION
Parallel host interface timing shown Figure 2-27. cycle initiated host when VC2-DS transitions low. TVP5031 responds pulling VC0-DTACK indicate data been received that requested data present bus. host then completes cycle pulling VC2-DS high. Once host completed cycle, TVP5031 sets VC0-DTACK high impedance. pullup required pull VC0-DTACK high indicate operation complete.
2-22
A[0:1]
D[7:0] WRITE
Write Data
(CS)
(VC1)
(VC2)
DTACK (VC0) D[7:0] READ
Read Data
Figure 2-27. Parallel Host Interface Timing
PARAMETER A[1:0],D[0:7],VC1 setup until Delay after A[1:0], D[0:7],VC1 hold after Delay high after high Delay low(next cycle) after high (Read cycle) D[7:0] setup until TEST CONDITIONS UNIT
2-23
2.6.3
Parallel Host Interface
Parallel host interface compatible with Video Electronics Standards Association (VESA) Video Module Interface (VMI) proposal version mode terminal descriptions defined Table 2-5. Table 2-5. Parallel Host Interface Terminal Description
TERMINAL A[1:0] D[7:0] INTREQ SIGNAL HA[1:0] HD[7:0] TYPE Address from host Bidirectional data Chip select, active Read, active Write, active high Data acknowledge Interrupt request, Open drain default, active low, pullup resistor required configured, subaddress conventional CMOS buffer, active high, pullup required. DESCRIPTION
Parallel host interface timing shown Figure 2-28. cycle initiated host when VC2-RD VC1-WR transitions low. TVP5031 responds pulling VC0-RDY low. TVP5031 will then VC0-RDY high impedance, pullup resistor required, indicate data received that requested data present bus. host then completes cycle pulling asserted signal, VC2-RD VC1-WR high.
2-24
A[0:1]
(VC3)
(VC1) (VC2)
(VC0) D[7:0] WRITE
Write Data
D[7:0] READ
Read Data
Figure 2-28. Parallel Host Interface Timing
PARAMETER Delay active after valid A[1:0] A[1:0] hold after inactive Delay after active D[7:0] setup until active D[7:0] hold after inactive inactive pulse width inactive until command active (Read cycle) until D[7:0] 3-state (Read cycle) D[7:0] setup until inactive (Read cycle) D[7:0] hold after inactive Hold active after active TEST CONDITIONS UNIT
2-25
2.6.4
Parallel Host Interface
terminal descriptions defined Table 2-6. Table 2-6. Parallel Host Interface Terminal Description
TERMINAL A[1:0] D[7:0] INTREQ SIGNAL HA[1:0] HD[7:0] RD/WR TYPE Address from host Bidirectional data Chip select, active Data strobe, active Read, active high Write, active Ready, active high Interrupt request, Open drain default, active low, pullup resistor required configured, subaddress conventional CMOS buffer, active high, pullup required. DESCRIPTION
Parallel host interface timing shown Figure 2-29. cycle initiated host when VC2-DS transitions low. TVP5031 responds pulling VC0-RDY low. TVP5031 will then VC0-RDY high impedance, pullup resistor required, indicate data received that requested data present bus. host then completes cycle pulling VC2-DS high.
(CS)
A[0:1]
(R/W) D[7:0] WRITE
Write Data
(DS)
(DTACK) READ PARAMETER A[1:0],D[0:7],VC1 setup until Delay after A[1:0], D[0:7],VC1 hold after Delay high after high Delay low(next cycle) after high (Read cycle) D[7:0] setup until (Read cycle) D[7:0] hold after high
Figure 2-29. Parallel Host Interface Timing
TEST CONDITIONS UNIT
2-26
D[7:0]
Read Data
2.6.5
Parallel Host Interface Register
parallel host interface (PHI) module contains only four registers that directly accessible host (see Figure 2-30). address register holds indirect address internal register access. When host accesses data register module reads writes internal register selected indirect address register. other registers provided direct access. FIFO register provides direct access FIFO. other direct access register status/Interrupt register. This register contains state interrupt sources.
A[1:0] Address Register Data Register FIFO Status Register
Figure 2-30. Address Register Normally read write operations require accesses. read FIFO register, A[1:0] 2'b10 perform read cycle. FIFO read data will placed D[7:0] bus. read/write status/interrupt register, A[1:0] 2'b11 perform read/write cycle. read/write data will appropriately muxed to/from external data bus. Indirect register read/write accesses except FIFO status/interrupt register require two-step operation. access indirect register desired internal address must first written address register PHI. This done setting A[1:0] performing write cycle with D[7:0] indirect register address. write indirect register, second step consists writing desired data address read indirect register, second step consists reading requested data from address Read Indirect Register
Step Write register address Step Read register data Register address
Data from register
Write Indirect Register
Step Write register address Step Read register data Register address
Data register
Latency accesses indirect addresses 00-8F require special consideration response latencies these addresses. Latency occurs between steps read operation, following step write operation. avoid violating cycle time requirements host poll cycle complete status register following step read step write. Alternatively, cycle complete enable interrupt enable register (indirect address generate interrupt host when access been completed. accesses indirect addresses 90-CF occur with minimal latency interrupts will generated completion access cycles these addresses.
2-27
FIFO FIFO containing sliced data read directly host.
Read FIFO Data from FIFO
Status/Interrupt Register status/interrupt register provides host with information regarding source interrupt. After interrupt condition reset writing appropriate status/interrupt register. Section 2.14 contains description status/interrupt register.
Access status/interrupt register Data from status/interrupt register
2.6.6
Parallel Host Interface Microcode Write Operation
Data written indirect register will written TVP5031 program RAM. During write cycle microprocessor will reset point location zero program will remain reset. Upon completion write operation, microprocessor clear-reset operation required. This performed writing into register clear reset resume microprocessor function. (There specific data requirement written into register, data will resume microprocessor function.) avoid violating cycle time requirements during microcode write operation host poll cycle complete status register after writing each byte data data register. Alternatively, cycle complete enable interrupt enable register (indirect address generate interrupt host when write been completed.
Write microcode register address Write microcode register data Write microcode register data Write microcode register data
First byte microcode data (Wait cycle complete status interrupt.) Second byte microcode data (Wait cycle complete status interrupt.) Last byte microcode data (Wait cycle complete status interrupt.)
Write clear reset dummy data
Dummy data
2-28
2.6.7
Parallel Host Interface Microcode Read Operation
Data read from indirect register will read from TVP5031 program RAM. During read cycle microprocessor will reset point location zero program will remain reset. Upon completion read operation, microprocessor clear-reset operation required. This performed writing into register clear reset resume microprocessor function. (There specific data requirement written into register, data will resume microprocessor function.) avoid violating cycle time requirements during microcode read operation host poll cycle complete status register after writing address register. Alternatively, cycle complete enable interrupt enable register (indirect address generate interrupt host when read data available data register.
Step Write program read address
(Wait cycle complete status interrupt) Step Read program read data data
NOTE: Repeat Steps until program data been read. Step Write reset clear register address Step Write reset clear register data
(Wait cycle complete status interrupt)
Data Processor
TVP5031 data processor slices, parses, performs error checking teletext data contained vertical blanking interval during active lines. Teletext formats supported North American Basic Teletext Specification (NABTS) equivalent ITU-R BT.653 system World System Teletext (WST) equivalent ITU-R BT.653 system Data stored internal FIFO read host port transmitted ancillary data digital video stream BT.656 mode. data FIFO holds lines NABTS lines data. Interrupts generated data processor configurable enable host synchronization retrieval full-field teletext data. Closed caption data also sliced data processor stored register accessible host port.
2-29
2.7.1
Teletext Data Byte Order
Table shows order which teletext data read from FIFO. Table 2-7. Teletext Data Byte Order
BYTE NUMBER NABTS LINE SYSTEM Video Line [7:0] Hamming Error, Parity Error, Error, Match number Match number Video Line Packet address Packet address Packet address Continuity index Packet structure Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block Data block suffix Data block suffix Padding byte LINE SYSTEM Video Line [7:0] Hamming Error, Parity Error, Match number Match number Video Line Magazine address Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte
padding byte used ensure even number writes. This byte does contain useful information. read pointer automatically advances past this byte user does have read padding byte.
2-30
2.7.2
Teletext Ancillary Data Video Stream
Sliced teletext data output ancillary data video stream ITU-R BT.656 mode. Teletext data output Y[7:0] terminals during horizontal blanking period following line from which data retrieved. Dummy ancillary data blocks with special timing header information inserted during certain horizontal blanking periods provide data synchronization information. Table Table show format sequence ancillary data inserted into video stream. Table 2-8. NABTS 525-Line Ancillary Data Sequence
BYTE Hamming error Parity error error DID2 Match DID1 Match DID0 Video line Data Secondary data Number 32-bit data words Internal data Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Checksum Fill byte Fill byte Ancillary data preamble DESCRIPTION
Video line number Packet address Packet address Packet address Continuity index Packet structure Teletext data Teletext data Teletext data Teletext data 27/suffix Teletext data 28/suffix Checksum
Table 2-9. Dummy Timing Ancillary Data Sequence
BYTE DID2 DID1 DID0 Data Secondary data Number 32-bit data words Ancillary data preamble DESCRIPTION
tables above, even parity lower bits negated even parity. checksum teletext data blocks LSBs data bytes. data byte provides timing information. Table 2-10 shows possible values data byte their meanings.
2-31
Table 2-10. Data
DATA EVENT SOURCE STREAM Start first, field Sliced data lines 1-23 first field nominal first field, line Sliced data line first field Start second, even field Sliced data lines 1-23 second field nominal second field, line Sliced data line second field DATA TYPE Dummy timing block data Dummy timing block Full field teletext data Dummy timing block data Dummy timing block Full field teletext data
dummy timing block will inserted into video stream during horizontal blanking period following line each field. teletext data available from line will inserted into video stream prior dummy timing block.
Video Data Output
TVP5031 output samples ITU-656 video stream desired order process data externally. data occurs pixel rate. data preceded preamble sequence preamble sequence occurs immediately following start active video (SAV) sequence.
Reset Initialization
Reset initiated power time RSTINB terminal brought low. Table 2-11 describes status TVP5031s terminals during immediately after reset. Following power reset, host must download microcode TVP5031s program memory internal microprocessor. Table 2-11. Reset Sequence
SIGNAL NAMES Y[9:0], UV[9:0], HSYN, VSYN, FID, PALI AVID SCLK, PCLK PREF GLCO D[7:0] A[1:0] mode RSTINB, SDA, SCL, I2CA, OEB, GPCL Input Input High-impedance PREF pulled down during reset. Active PREF pulled during reset. Input Input High impedance Input Input Input DURING RESET RESET COMPLETED High-impedance AVID pulled down during reset. Active output AVID pulled during reset. High-impedance AVID pulled down during reset. Active output AVID pulled during reset. Active output Active output Active output High impedance High impedance Input Input
2-32
2.10 Internal Control Registers
TVP5031 initialized controlled internal registers which device operating parameters. Communication between external controller TVP5031 through standard host port interface port. Table 2-12 shows summary these registers. reserved bits must written with detailed programming information each register described following sections. Table 2-12. Registers Summary
REGISTER FUNCTION Video input source selection Analog channel controls Operation mode controls Miscellaneous controls Reserved Color killer threshold control Luminance processing control Luminance processing control Brightness control Color saturation control Color control Contrast control Outputs data rate select Luminance processing control Reserved Horizontal sync start NTSC Horizontal sync start Vertical blanking start Vertical blanking stop Chroma processing control Chroma processing control Interrupt reset Interrupt enable Interrupt configuration Reserved Program write Microprocessor reset clear Major software revision Status Status Status Status Interrupt status Interrupt active 04-05 0F-15 001C 001D 001E F1-7D 04-05h 0F-15h 1F-7Dh
NOTE: Read only interfaces Write only interfaces Read write host interfaces Read write host interface. Write only host interfaces.
2-33
Table 2-12. Registers Summary (Continued)
REGISTER FUNCTION Minor software revision Status Reserved Program read Reserved filter params filter params error filtering enable transaction processing enables Reserved control register Line enable register Line enable register Custom sync pattern Reserved Teletext FIFO Field data Field data Buffer status Interrupt threshold Interrupt line number FIFO control FIFO test Reserved Interrupt status register Interrupt enable Interrupt configuration Reserved teletext FIFO status/interrupt 86-8F 9C-9F 86-8Fh 9C-9Fh
NOTE: Read only interfaces Write only interfaces Read write host interfaces Read write host interface. Write only host interfaces.
2-34
2.11 Register Definitions
2.11.1 Video Input Source Selection
Address Channel source selection Reserved
Reserved
Channel source selection: VI1A selected (default) VI1B selected Table 2-13. Analog Channel Video Mode Selection
ADDRESS INPUT(S) SELECTED Composite
2.11.2 Analog Channel Controls
Address Reserved Automatic offset control
Reserved
Automatic gain control
Automatic offset control: Reserved Automatic clamping enabled (default) Reserved Clamping level frozen Automatic gain control: Disabled (fixed gain value) enabled using luma input reference (default). Reserved frozen
2.11.3
Address
Operation Mode Controls
Reserved Reserved Color subcarrier frozen Reserved Powerdown mode
Reserved
TV/VCR mode
TV/VCR mode: Automatic, mode determined internal detection circuit (default) Reserved (nonstandard video) mode (standard video) mode
2-35
With automatic detection enabled, unstable nonstandard syncs input video will force device into mode. This turns luminance chrominance comb filters turns chroma trap filter.
TV/VCR MODE CM[2:0] XXX/000 1XX/000 10/00 01/00 11/00 11/00 NTSC NTSC STANDARD NTSC NOTE Auto detection switching between VCR/TV Manual programming mode mode
Adaptive comb filter enable. Comb filter enable. CM[2:0] Comb filter mode. Luminance filter select. Chrominance filter select. Luminance filter select. change
Chrominance control register register Chrominance control register register Chrominance control register register bits 7-5. Luminance processing control register Chrominance control register bits Luminance control register bits
Color subcarrier frozen: Color subcarrier increments internally generated phase increment. (default) GLCO terminal outputs phase increment Color subcarrier stops incrementing frozen nominal. GLCO terminal outputs zero. Power-down mode: Normal operation (default) Power-down mode. A/Ds turned internal clocks reduced minimum.
2-36
2.11.4
Address
Miscellaneous Control
PALI function select output enable HSYN, VSYN, AVID, FID, PALI output enable Reserved Vertical blanking on/off Clock output enable
GPCL function select
GPCL terminal function select: GPCL logic output (default) GPCL logic output GPCL vertical blank output GPCL external sync lock control input When GPCL configured vertical blank output, vertical blanking on/off used activate output. When GPCL configured sync lock control, used force internal PLLs their normal settings. This causes clocks synchronization signals assume nominal values. sync lock control input active high. PALI terminal terminal function select: PALI outputs indicator signal terminal outputs field signal (default) PALI outputs horizontal lock indicator (HLK) terminal outputs vertical lock indicator (VLK) output enable: high impedance (default) active Horizontal sync (HSYN), vertical sync (VSYN), active video indicator (AVID), PALI, output enables: HSYN, VSYN, AVID, PALI, high impedance HSYN, VSYN, AVID, PALI, active This default after reset AVID terminal pulled down during reset default AVID terminal pulled during reset. Vertical blanking on/off control: Vertical blanking (default) Vertical blanking Clock enable: SCLK PCLK outputs high impedance SCLK PCLK outputs enabled This default after reset PREF terminal pulled down during reset default AVID pulled during reset. Table 2-14. Digital Output Control
AVID during reset during reset (TVPOE) (VDPOE) OUTPUT High impedance Active after reset High impedance after reset High impedance High impedance Active times After reset before output enable bits programmed. TVPOE default VDPOE After reset before output enable bits programmed. TVPOE default VDPOE After both output enable bits programmed After both output enable bits programmed After both output enable bits programmed NOTES
2-37
2.11.5
Address Reserved
Color Killer Threshold Control
Color killer threshold
Automatic color killer
Automatic color killer: Automatic mode (default) Reserved Color killer enabled. terminals forced zero color state. Color killer disabled Color killer threshold (ref. nominal burst amplitude): 11111 10000 (default) 00000
2.11.6
Address
Luminance Processing Control
Pedestal present Reserved Luma bypass during vertical blank
Luma bypass mode
Luminance signal delay with respect chrominance signal
Luma bypass mode select: Input video bypasses chroma trap comb filters. Chroma outputs forced zero. (default) Input video bypasses whole luma processing. data output alternatively data data SCLK rate. output data properly clipped comply CCIR601 coding range. Only valid 10-bit output format (YUV output format register Pedestal present: pedestal present analog video input signal (default) Pedestal present analog video input signal Luminance bypass mode during vertical blanking: (default) When luminance bypass enabled, luminance comb notch filters turned chrominance components output video sent zero color state. Luminance bypass will occur duration vertical blanking defined register This feature used prevent distortion test data signals present during vertical blanking interval. Luma signal delay with respect chroma signal pixel clock increments (range pixel clocks): 1111 pixel clocks delay 1011 pixel clocks delay 1000 pixel clocks delay 0000 pixel clocks delay (default) 0011 pixel clocks delay 0111 pixel clocks delay
2-38
2.11.7
Address Reserved
Luminance Processing Control
Luminance filter select Reserved Peaking gain Reserved
Luminance filter select: Luminance comb filter enabled (default) Luminance chroma trap filter enabled Peaking gain: Peaking disabled (default) Peaking frequency: Square-pixel sampling rate: NTSC
ITU-R BT.601 sampling rate: standards Refer Figures 2-16, 2-17 2-18.
2.11.8
Address
Brightness Control
Brightness control
Brightness: (bright) (ITU-R BT.601 level) (default) (dark)
2.11.9
Address
Color Saturation Control
Saturation control
Saturation: (maximum) (default) color)
2-39
2.11.10 Control
Address control
Hue: degrees degrees (default) -180 degrees
2.11.11 Contrast Control
Address Contrast control
Contrast: (maximum contrast) (default) (minimum contrast)
2.11.12 Outputs Data Rates Select
Address Reserved output code range code format output format
data path bypass
output code range: ITU-R BT.601 coding range ranges from 235. range from 240) Extended coding range range from 254) (default) code format: Offset binary code complement 128) (default) Straight binary code complement) data path bypass: Normal operation. (default) output pins connected decimation filter output, decoder function bypassed, test purpose only. Both busses output data PCLK rate. output pins connected output, decoder function bypassed, test purpose only. Both busses output data SCLK rate. Reserved output format: 20-bit 4:2:2 (default) Reserved Reserved Reserved 10-bit 4:2:2 101= Reserved Reserved 10-Bit ITU-R interface
2-40
Address
Reserved
Luminance filter select
Luminance Filter Stopband bandwidth (MHz): NTSC CCIR601 1.2129 0.8701 0.5010 NTSC Square pixel 1.1026 0.7910 0.4554 CCIR601 1.2129 0.8701 0.5010 Square pixel 1.3252 0.9507 0.5474
Luminance filter select[1:0] selects four chroma trap filters produce luminance signal removing chrominance signal from composite video signal. stop band chroma trap filter centered chroma subcarrier frequency with stopband bandwidth controlled control bits. Refer Figure 2-12, 2-13 2-14 frequency responses filters. control default mode.
2.11.13 Horizontal Sync HSYN Start NTSC/PAL
Address HSYN start NTSC HSYN start
HSYN Start: -127 pixel clocks 10000000= pixel clocks (defaults) pixel clocks
2-41
2.11.14 Vertical Blanking VBLK Start
Address VBLK start
VBLK Start: lines after start vertical blanking interval line after start vertical blanking interval same time start vertical blanking interval (default) line before start vertical blanking interval lines before start vertical blanking interval Vertical blanking adjustable with respect standard vertical blanking intervals shown Table 2-15. setting this register determines timing GPCL signal when configured output vertical blank(see register 03). setting this register also used determine duration luma bypass function (see register 07). Table 2-15. Vertical Blanking Interval Start
STANDARD NTSC MPAL NPAL FIELD even even even even START LINE NUMBER 263.5 623.5 260.5 623.5 LINE NUMBER 284.5 23.5 284.5 23.5
2.11.15 Vertical Blanking VBLK Stop
Address VBLK
VBLK End: lines after vertical blanking interval line after vertical blanking interval same time vertical blanking interval (default) line before vertical blanking interval lines before vertical blanking interval Vertical blanking adjustable with respect standard vertical blanking intervals shown Table 2-16. setting this register determines timing GPCL signal when configured output vertical blank(see register 03). setting this register also used determine duration luma bypass function (see register 07).
2-42
2.11.16 Chrominance Control
Address Color Reset Chrominance Adaptive Comb Filter Enable Chrominance Comb Filter Enable
Chrominance Comb Filter Mode [2:0]
Automatic Color Gain Control
Table 2-16. Chrominance Comb Filter Selection
CM[2] CM[1] CM[0] COMB FILTER SELECTION Comb filter disabled Fixed 3-line comb filter with (1/4, 1/2, 1/4) coefficients Fixed 3-line comb filter with coefficients Fixed 2-line comb filter Adaptive between 3-line (1/4,1/2,1/4) comb filter 2-line comb filter Adaptive between 3-line (1/4,1/2,1/4) comb filter comb filter Adaptive between 3-line (1,0,1) comb filter 2-line comb filter Adaptive between 3-line (1,0,1) comb filter comb filter
Indicates default settings
Color reset: Color subcarrier reset. (default) Color subcarrier reset Color subcarrier reset zero color subcarrier then immediately returns zero. When this set, subcarrier phase reset transmitted GCLO terminal next occurrence specified line (NTSC PAL). Automatic color gain control: enabled (default) Reserved disabled frozen
2.11.17 Chrominance Control
Address Reserved Chrominance Filter Select
Chrominance Output Bandwidth (MHz): NTSC CCIR601 1.2129 0.8701 0.7183 0.5010 NTSC Square Pixel 1.1026 0.7910 0.6712 0.4554 CCIR601 1.2129 0.8701 0.7383 0.5010 Square Pixel 1.3252 0.9507 0.8066 0.5474
Refer Figures 2-6, 2-7, frequency responses filters. control default setting.
2-43
2.11.18 Interrupt Reset Register
Address Interrupt Reset Register (1C) Software Init Reset Reserved Command Ready Reset Field Rate Changed Reset Line Alternation Changed Reset Color Lock Changed Reset Lock Changed Reset TV/VCR Changed Reset
TV/VCR Changed Reset Lock Changed Reset Line Alternation Changed Reset Field Rate Changed Reset Command Ready Reset Software Init
effect interrupt register effect interrupt register effect interrupt register effect interrupt register effect interrupt register effect interrupt register
Reset TV/VCR changed Reset lock changed Reset color lock changed Reset line alternation changed Reset field rate changed Reset command ready Reset software init
Color Lock Changed Reset effect interrupt register
interrupt reset register used external processor reset interrupt status bits interrupt register Bits loaded with will allow corresponding interrupt status reset Bits loaded with have effect interrupt status bits.
2.11.19 Interrupt Enable Register
Address Interrupt Reset Register (1D) Software Init Complete Reserved Command Ready Field Rate Changed Line Alternation Changed Color Lock Changed Lock Changed TV/VCR Changed
TV/VCR Changed Lock Changed Color Lock Changed Field Rate Changed Command Ready Software Init Complete
TV/VCR status changed lock status changed Color lock status changed Field rate changed ready accept command Software initialization completed
TV/VCR mode detect changed lock status changed Color lock status changed Line alternation changed Field rate changed ready accept command Software initialization completed.
Line Alternation Changed Line alternation changed
interrupt enable register used external processor mask unnecessary interrupt sources interrupt Bits loaded with will allow corresponding interrupt condition generate interrupt external terminal. Conversely bits loaded with will mask corresponding interrupt condition from generating interrupt external terminal. Note this register only affects external terminal; does affect bits interrupt status register. given condition appropriate status register cause interrupt external terminal. determine this device driving interrupt terminal, either perform logical interrupt status register with interrupt enable register check state interrupt interrupt active register.
2-44
2.11.20 Interrupt Configuration Register
Address Interrupt Configuration Register Reserved Interrupt Polarity
Interrupt Polarity
Interrupt active low.
Interrupt active high.
Must same interrupt polarity interrupt configuration register address
interrupt configuration register used configure polarity interrupt external interrupt terminal. Note that when interrupt configured active terminal will driven when active 3-state when inactive (open-collector). Conversely, when interrupt configured active high will driven high active driven inactive.
2.11.21 Program Write
Address
program written program write register address
2.11.22 Microprocessor Reset Clear
Address
write with data this register must performed restart internal microprocessor after completion microcode download program RAM.
2.11.23 Major Software Revision Number
Address
Major Revision Number
This register contains major software revision number.
2-45
2.11.24 Status Register
Address Peak white detect status Line-alternating status Field rate status Lost lock detect Color subcarrier lock status Vertical sync lock status Horizontal sync lock status TV/VCR status
Peak white detect status: Peak white detected. Peak white detected. Line-alternating status: line-alternating Line alternating Field rate status: Lost lock detect: lost lock since status register last read. Lost lock since status register last read. Color subcarrier lock status: Color subcarrier locked. Color subcarrier locked. Vertical sync lock status: Vertical sync locked. Vertical sync locked. Horizontal sync lock status: Horizontal sync locked. TV/VCR status:
2-46
2.11.25 Status Register
Address switch polarity Field sequence status offset status Reserved
Reserved
switch polarity first line field: switch zero Color burst phase degree) switch (Color burst phase degree) Field sequence status: Even field field Automatic gain offset status: Automatic gain offset frozen. Automatic gain offset frozen.
2.11.26 Status Register
Address gain
gain (step size 0.831%):
2.11.27 Status Register
Address
Subcarrier horizontal (SCH) phase
(color subcarrier phase falling edge horizontal sync line field; step size deg/256): 0.00 degree 1.41 degree 2.81 degree 357.2 degree 358.6 degree
2-47
2.11.28 Interrupt Status Register
Address Interrupt Status Register (85) Software Init Reserved Command Ready Field Rate Changed Line Alternation Changed Color Lock Changed Lock Changed TV/VCR Changed
TV/VCR Changed Lock Changed Color Lock Changed Field Rate Changed Command Ready Software Init
TV/VCR status changed H/Vlock status changed Color lock status changed Field rate changed ready accept command Software Init ready
TV/VCR mode detect changed lock status changed Color lock status changed Line alternation changed Field rate changed ready accept command Software Init ready
Line Alternation Changed Line alternation changed
interrupt status register polled external processor determine interrupt source interrupt After interrupt condition reset writing interrupt reset register subaddress with appropriate bit.
2.11.29 Interrupt Active Register
Address Interrupt Active Register Interrupt
Interrupt
Interrupt active.
Interrupt active.
interrupt status register polled external processor determine interrupt active.
2.11.30 Minor Software Revision Number
This register contains minor revision number TVP5031 software. This number from
Address
Minor revision number
2-48
2.11.31 Status Register
This register contains information about detected video standard sampling rate digital video output data. (M)PAL video standard detected (Combination-N)PAL video standard detected Sampling rate d7:d3 Reserved
Address Reserved Reserved Reserved Reserved Sampling Rate NPAL MPAL
MPAL (M)PAL video standard detected (M)PAL video standard detected NPAL (Combination-N)PAL video standard detected (Combination-N)PAL video standard detected Sampling rate ITU-R BT.601 Square pixel
2.11.32 Program Read
Address
program read program read register address
2-49
2.11.33 Filter Parameters
Address
Filter Mask_1[3:0] Filter Mask_2[3:0] Filter Mask_3[3:0] Filter Mask_4[3:0] Filter Mask_5[3:0]
Filter Pattern_1[3:0] Filter Pattern_2[3:0] Filter Pattern_3[3:0] Filter Pattern_4[3:0] Filter Pattern_5[3:0]
NABTS system, packet prefix consists five bytes: Each byte contains data bits interlaced with Hamming protection bits. Pattern_1[3:0] corresponds P1[7], P1[5], P1[3], P1[1] Pattern_2[3:0] corresponds P2[7], P2[5], P2[3], P2[1] Pattern_3[3:0] corresponds P3[7], P3[5], P3[3], P3[1] Pattern_4[3:0] corresponds CI[7], CI[5], CI[3], CI[1] Pattern_5[3:0] corresponds PS[7], PS[5], PS[3], PS[1] (Packet address) (Packet address) (Packet address) (Continuity index) (Packet structure)
system (PAL NTSC), magazine address group consists bytes. bytes contain three bits magazine number (M[2:0]) bits address (R[4:0]), interlaced with eight Hamming protection bits. Pattern_1[3:0] corresponds R[0], M[2], M[1], M[0] Pattern_2[3:0] corresponds R[4], R[3], R2], R[1] Pattern_3[3:0] ignored Pattern_4[3:0] ignored Pattern_5[3:0] ignored (Magazine LSB) (Upper bits address)
mask bits enable filtering using corresponding pattern register. example, Mask_1 means that module should compare nibble_1 pattern register first data transaction. Mask_1 means that module should ignore first data transaction. NOTE: Filter parameters only written read when both Filter enable Filter enable bits When reading values, values must read consecutively, starting with first value. These registers hold search parameters Filter parameters used parse first five bytes NABTS Teletext transactions first bytes transactions. These bytes teletext expected always contain four data bits interlaced with four Hamming protection bits. protection bits ignored filter.
2-50
2.11.34 Filter Parameters
Address
Filter Mask_1[3:0] Filter Mask_2[3:0] Filter Mask_3[3:0] Filter Mask_4[3:0] Filter Mask_5[3:0]
Filter Pattern_1[3:0] Filter Pattern_2[3:0] Filter Pattern_3[3:0] Filter Pattern_4[3:0] Filter Pattern_5[3:0]
NABTS system, packet prefix consists five bytes: Each byte contains data bits interlaced with Hamming protection bits. Pattern_1[3:0] corresponds P1[7], P1[5], P1[3], P1[1] Pattern_2[3:0] corresponds P2[7], P2[5], P2[3], P2[1] Pattern_3[3:0] corresponds P3[7], P3[5], P3[3], P3[1] Pattern_4[3:0] corresponds CI[7], CI[5], CI[3], CI[1] Pattern_5[3:0] corresponds PS[7], PS[5], PS[3], PS[1] (Packet address) (Packet address) (Packet address) (Continuity index) (Packet structure)
system (PAL NTSC), magazine address group consists bytes. bytes contain three bits magazine number (M[2:0]) bits address (R[4:0]), interlaced with eight Hamming protection bits. Pattern_1[3:0] corresponds R[0], M[2], M[1], M[0] Pattern_2[3:0] corresponds R[4], R[3], R2], R[1] Pattern_3[3:0] ignored Pattern_4[3:0] ignored Pattern_5[3:0] ignored (Magazine LSB) (Upper bits address)
mask bits enable filtering using corresponding pattern register. example, Mask_1 means that module should compare nibble_1 pattern register first data transaction. Mask_1 means that module should ignore first data transaction. NOTE: Filter parameters only written read when both Filter enable Filter enable bits When reading values, values must read consecutively, starting with Filter parameters values. These registers hold search parameters Filter parameters used parse first five bytes NABTS Teletext transactions first bytes transactions. These bytes teletext expected always contain four data bits interlaced with four Hamming protection bits. protection bits ignored filter.
2-51
2.11.35 Error Filtering Enables
Address Error Filtering Enables (R/W) Error Enable Parity Error Enable Teletext Parity Error Enable Hamming Error Enable
Reserved
Hamming error enable Teletext parity error enable parity error enable error enable
disable disable disable disable
enable enable enable enable
default default default default
These bits allow module discard transactions based errors. hamming error enable allows error correction detection Hamming encoded bytes. teletext parity error enable allows discard Teletext transactions with parity errors. parity error enable allows discard closed caption transactions with parity errors. error enable allows discard Teletext transactions with longitudinal parity errors.
2.11.36 Transaction Processing Enables
Address Error Filtering Enables (R/W) Reserved Filter Enable Filter Enable Field Enable Even Field Enable Teletext Enable
Teletext enable field enable even field enable Filter enable Filter enable
disable disable disable disable disable
enable enable enable enable enable
default default default default default
These bits used enable disable certain features. teletext enable allows module receive teletext data. this outputs from remain idle while teletext data present. field enables allow receive closed caption data during odd, even, both fields. Filter enable allows module parse data based values Filter parameters register. Filter enable allows module parse data based values Filter parameters register.
2-52
2.11.37 Control Register
Address Control Register Reserved Full-Field Enable Custom Framing Code Enable Mode
Mode ENABLE Custom Sync Full Field Enable
NABTS Closed caption DISABLED default sync pattern search after area
Closed caption ENABLED sync pattern register search lines after
control register allows operating parameters controlled. Note that mode selection independent PAL/NTSC mode, which selected TVP5020. This effectively controls default framing code data rate. Closed caption affected lines lines (but NABTS/WST). NTSC data search Line B,G,I,N Line Custom framing code affects teletext data only closed caption data always uses default sync pattern.
2.11.38 Line Enable Registers
Enable Line 17/280 (14/327 Enable Line 25/288 (22/335) Enable Line 16/279 (13/326) Enable Line 24/287 (21/334) Enable Line 15/278 (12/325) Enable Line 23/286 (20/333) Enable Line 14/277 (11/324) Enable Line 22/285 (19/332) Enable Line 13/276 (10/323) Enable Line 21/284 (18/331) Enable Line 12/275 (9/322) Enable Line 20/283 (17/330) Enable Line 11/274 (8/321) Enable Line 19/282 (16/329) Enable Line 10/273 (7/320) Enable Line 18/281 (15/328)
Line Enable Register
Line Enable Register
NOTE: Line numbers parenthesis refer Line systems
Line Enable
Search Line
Search Line Data
both only full field modes, vertical interval lines individually enabled disabled. Only lines that enabled searched selected type teletext data. This allows some amount filtering physical location basis. closed caption data enabled, this overrides enable/disable Line (22). full field mode enabled, lines after vertical interval searched selected type teletext data. registers initialized 0x00 reset.
2-53
2.11.39 Sync Pattern Register
Address Custom Sync Pattern
Framing Code [7:0]
custom sync control register, sync comparator uses contents sync pattern register pattern teletext framing code. Otherwise, default sync patterns used. Relative sync pattern register, incoming bits shifted first. illustrate; default framing code would specified 0xE4 default NABTS framing code would specified 0xE7 (although versus. ambiguous latter). NOTE:The custom sync option only valid NABTS messages; closed caption always uses standard start pattern.
2.11.40 Teletext FIFO
Address Teletext FIFO
Teletext Data FIFO [7:0]
teletext FIFO accessed regular teletext FIFO register address Reading this location returns byte from FIFO that store teletext transactions. FIFO empty, read will return same value previous read. driver software's application software's responsibility assure that correct number bytes transaction read from teletext FIFO. transaction length depends whether data NABTS, WST-NTSC WST-PAL.
2.11.41 Closed Caption Data
Address
Closed Caption Data [7:0]
closed caption data contains bytes transaction. retrieve both bytes this register must read twice. first read returns first byte message; second read returns second byte. Further reads return first byte until data received. order distinguish between closed caption data received even fields, software test field sequence status (Address 82h,
2-54
2.11.42 Buffer Status
Address Buffer Status Reserved Avail FIFO Full Teletext Data Avail
Count [3:0]
Teletext Avail FIFO Full Count Avail
This indicates that least complete teletext transaction FIFO. This cleared when FIFO emptied. This indicates that maximum number complete teletext transactions FIFO. This value represents number complete teletext transactions FIFO. This status indicates that closed caption data been received. status cleared when both bytes have been read.
2.11.43 Interrupt Threshold
Address Interrupt Threshold (R/W)
Threshold Value [3:0]
Threshold Value This value determines many teletext transactions must received before teletext threshold interrupt status register. default value
2.11.44 Interrupt Line Number
Address Interrupt Line Number (R/W) Data Required
Interrupt Line Number [4:0]
Interrupt Line Number This value determines which video line number will used generate teletext data, even field field bits interrupt status register. register value examined start line. Since there line value zeros this register will disable three interrupt signals that this condition. default value (18h). Data Required this HIGH, teletext data will only there data FIFO. This does affect even field field bits. default value this
2-55
2.11.45 FIFO Control
Address FIFO Control (R/W) Reserved Reset Read Progress Test Output Enable FIFO Reset
FIFO Reset
When written this register bit, FIFO flushed. This done clearing read write pointers zero, clearing count zero clearing status flags. This automatically cleared back
Output Enable this register enables access teletext data FIFO through parallel host port disables access from output formatter. disables access from parallel host enables access from output formatter. default value one. TEST Setting this high allows micro write data into FIFO. this mode, data from ignored. This allows micro test writing reading test patterns. default value zero. This indicates that first byte teletext transaction been read, last byte been read. This used verify data alignment read from FIFO. When written this register bit, closed caption register reset. Also, status flag cleared This automatically cleared back
Read Progress Reset
2.11.46 FIFO Test
Address FIFO Test
FIFO test register provides diagnostic capability into internal teletext FIFO. This register written sequentially with block data. data read back using Teletext FIFO data register address verify correct operation FIFO.
2-56
2.11.47 Interrupt Status Register
Address Interrupt Status Register (R/W) TvpLOCK State TvpLOCK Interrupt Cycle Complete Error Field Even Field Teletext Threshold Teletext Data
Teletext Data
Teletext Threshold Even Field Field Error Cycle Complete tvpLOCK Interrupt
tvpLOCK State
Teletext data buffer empty have reached video line number that equals interrupt line number register Teletext data buffer contains complete transaction video line number interrupt line number register Note this configured occur whenever video line number interrupt line number register regardless data. Threshold reached Teletext data buffer reached configurable threshold Buffer empty Even field closed caption buffer contains data Buffer empty field closed caption buffer contains data error interface detected illegal access Read write cycle progress Read write cycle complete transition occurred tvpLOCK signal transition occurred tvpLOCK signal Note, interrupt will generated transition lock signal. locked video locked video signal Reflects present state tvpLOCK.
interrupt status register polled external processor determine interrupt source. After interrupt condition set, reset writing this register with appropriate bit(s).
2.11.48 Interrupt Enable Register
Address Interrupt Enable Register (R/W) tvpLOCK State tvpLOCK Interrupt Enable Cycle Complete Enable Error Enable Field Enable Even Field Enable Teletext Threshold Enable Teletext Data Enable
interrupt enable register used external processor mask unnecessary interrupt sources interrupt Bits loaded with will allow corresponding interrupt condition generate interrupt external terminal. Conversely bits loaded with will mask corresponding interrupt condition from generating interrupt external terminal. Note this register only affects interrupt external terminal, does affect bits interrupt status register given condition appropriate status register cause interrupt external terminal. determine this device driving interrupt terminal, either perform logical interrupt status register with interrupt enable register check state interrupt interrupt active register.
2-57
Address
Output Enable Interrupt Interrupt Polarity
Interrupt Configuration Register (R/W)
Reserved
Interrupt Polarity Interrupt
Interrupt active Interrupt active high Interrupt terminal active Interrupt terminal active Reflects state Interrupt external terminal. This read only.
Output Enable
terminals 3-state terminals active other conditions
interrupt configuration register used configure polarity external interrupt terminal. Note that when interrupt configured active terminal will driven when active 3-state when inactive (open-collector). Conversely, when terminal configured active high will driven high active driven inactive.
2.11.49 Parallel Host Interface Teletext FIFO
Address
This read-only register only accessible when interface enabled. access this register, direct address Notice almost registers accessed through indirect address scheme, writing indirect address address then write read from address This register contains same information teletext FIFO register indirect address recommended reading data from teletext FIFO efficiency.
2.11.50 Parallel Host Interface Status/Interrupt
Address
This read-write register only accessible when interface enabled. access this register, direct address Notice almost registers accessed through indirect address scheme, writing indirect address address then write read from address This register contains same information interrupt status register indirect address This recommended reading interrupt/status information efficiency. After interrupt condition set, reset writing this register with appropriate bit(s).
2-58
Electrical Specifications
Absolute Maximum Ratings
Digital power supply voltage, DVDD -0.3 Analog power supply voltage, AVDD -0.5 Digital input voltage, -0.3 DVdd+0.3 Operating free-air temperature, 70°C Storage temperature, Tstg -65°C 150°C Maximum total power dissipation,
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
Recommended Operating Conditions
Digital supply voltage, DVDD Analog supply voltage, AVDD Analog input voltage, Vi(p-p) coupling necessary) Digital input voltage high, Digital input voltage low, Input voltage high, mode, (I2C) Input voltage low, mode, (I2C) Output current, Vout Output current, Vout Operating free-air temperature, 1.26 UNIT
3.2.1
Crystal Specifications
14.31818 UNIT
Frequency Frequency tolerance
Electrical Characteristics Over Recommended Voltage Temperature Ranges, DVDD AVDD 70°C (unless otherwise noted)
3.3.1
IDD(D) IDD(A) Ilkg
Electrical Characteristics
PARAMETER Digital supply current Analog supply current Input leakage current Input capacitance Output voltage high Output voltage design TEST CONDITIONS UNIT
NOTE Measured with load parallel with
3.3.2
Vi(pp) G(Cont)
Analog Processing Converters
PARAMETER Input impedance, analog video inputs Input capacitance, analog Video inputs Input voltage range Gain control range differential nonlinearity Frequency response Noise spectrum Differential phase Differential gain only Multiburst IRE) Luminance ramp (100 full; tilt-null) Modulated ramp Modulated ramp design design Ccoupling 0.50 0.75 -0.9 0.5% TEST CONDITIONS 1.41 UNIT °(pk-pk)
ED(DC) f(response)
3.3.3
Clocks, Video Data, Sync Timing
PARAMETER TEST CONDITIONS (see NOTE Note Note UNIT
t(SCLK) (SCLK) tf(SCLK) tr(PCLK) tf(PCLK) td(PREF) td(PCLK) td(YUV) td(OUT)
Duty cycle PCLK, SCLK Rise time SCLK Fall time SCLK Rise time PCLK Fall time PCLK Delay time, SCLK rising edge PREF Delay time, SCLK falling edge PCLK Delay time, SCLK falling edge Delay time, SCLK falling edge digital outputs except PCLK, PREF,
NOTES: SCLK falling edge occur after PREF, output transitions.
t(SCLK) SCLK PREF td(PREF) td(PCLK)
PCLK td(YUV) AVID, HSYN, VSYN, PALI, FID,
3.3.4
t(buf) tsu(STA) th(STA) tsu(STO) tsu(DAT) th(DAT)
Host Port Timing
PARAMETER free time between stop start Setup time (repeated) start condition Hold time (repeated) start condition Setup time stop condition Data setup time Data hold time Rise time VC1(SDA) VC0(SCL) signal Fall time VC1(SDA) VC0(SCL) signal Capacitive load each line clock frequency Data VC1(SDA) t(buf) Data th(DAT) Change Data tsu(STA) tsu(DAT) tsu(ST) VC0(SCL) TEST CONDITIONS UNIT
th(STA)
th(STA)
3.3.5
Parallel Host Interface
A[0:1]
D[7:0] WRITE
Write Data
(CS)
(VC1)
(VC2)
DTACK (VC0)
Read Data
READ
Figure 3-1. Parallel Host Interface Timing
PARAMETER A[1:0],D[0:7],VC1 setup until Delay after A[1:0], D[0:7],VC1 hold after Delay high after high Delay low(next cycle) after high (Read cycle) D[7:0] setup until TEST CONDITIONS UNIT
D[7:0]
3.3.6
Parallel Host Interface
A[0:1]
(VC3)
(VC1) (VC2)
(VC0) D[7:0] WRITE
Write Data
D[7:0] READ
Read Data
Figure 3-2. Parallel Host Interface Timing
TEST CONDITIONS UNIT
PARAMETER
Delay active after valid A[1:0] A[1:0] hold after inactive Delay after active D[7:0] setup until active D[7:0] hold after inactive inactive pulse width inactive until command active (Read cycle) until D[7:0] 3-state (Read cycle) D[7:0] setup until inactive (Read cycle) D[7:0] hold after inactive Hold active after active
3.3.7
Parallel Host Interface
(CS)
A[0:1]
(R/W) D[7:0] WRITE
Write Data
(DS)
(DTACK) D[7:0] READ
Read Data
Figure 3-3. Parallel Host Interface Timing
PARAMETER A[1:0],D[0:7],VC1 setup until Delay after A[1:0], D[0:7],VC1 hold after Delay high after high Delay low(next cycle) after high (Read cycle) D[7:0] setup until (Read cycle) D[7:0] hold after high TEST CONDITIONS UNIT
Mechanical Data
(S-PQFP-G80)
0,27 0,17
PowerPADPLASTIC QUAD FLATPACK
0,50
0,08
Thermal (see Note
0,13
9,50 12,20 11,80 14,20 13,80 1,05 0,95
Gage Plane 0,25 0,15 0,05 0,75 0,45 Seating Plane
1,20
0,08 4146925/A 01/98
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion. package thermal performance enhanced bonding thermal external thermal plane. This electrically thermally connected backside possibly selected leads. Falls within JEDEC MS-026
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Customers responsible their applications using components. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Other recent searches
Y4420 - Y4420 Y4420 Datasheet
XN04214G - XN04214G XN04214G Datasheet
PUSN0005KA-A - PUSN0005KA-A PUSN0005KA-A Datasheet
DS06-20209-1E - DS06-20209-1E DS06-20209-1E Datasheet
BVS-301BE4 - BVS-301BE4 BVS-301BE4 Datasheet
ATA6833 - ATA6833 ATA6833 Datasheet
ATA6834 - ATA6834 ATA6834 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
