2-Way Pentium® XeonProcessor/Intel® 440GX AGPset AGTL+ Layout Guidelin

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AP-829 APPLICATION
2-Way Pentium® XeonProcessor/Intel® 440GX AGPset AGTL+ Layout Guidelines
Order Number: 245096-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® Xeonprocessor, Pentium® Xeonprocessor, Intel® 440GX AGPset contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com Copyright Intel Corporation 1999. Third-party brands names property their respective owners.
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CONTENTS
PAGE PAGE 5.0. MORE DETAILS INSIGHTS 5.1. Textbook Timing Equations 5.2. Effective Impedance Tolerance/Variation 5.3. Power/Reference Planes, Stackup, High Frequency Decoupling. 5.3.1. POWER DISTRIBUTION 5.3.2. REFERENCE PLANES STACKUP. 5.3.3. HIGH FREQUENCY DECOUPLING 5.3.4. SC330 CONNECTOR 5.4. Clock Routing. 5.5. Conclusion 0.VREF GUARDBAND 0.OVERDRIVE REGION 0.FLIGHT TIME DEFINITION MEASUREMENT.
0.INTRODUCTION. 0.ABOUT THIS DOCUMENT 2.1. Document Organization 2.2. References. 2.3. Definition Terms 3.0. AGTL+ DESIGN GUIDELINE. 3.1. Initial Timing Analysis 3.2. Determine General Topology, Layout, Routing Desired 3.3. Pre-Layout Simulation. 3.3.1. METHODOLOGY 3.3.2. SIMULATION CRITERIA. 3.4. Place Route Board. 3.4.1. ESTIMATE COMPONENT COMPONENT SPACING AGTL+ SIGNALS 3.4.2. LAYOUT ROUTE BOARD. 3.5. Post-Layout Simulation 3.5.1. INTERSYMBOL INTERFERENCE 3.5.2. CROSSTALK ANALYSIS. 3.5.3. MONTE CARLO ANALYSIS 3.6. Validation 3.6.1. MEASUREMENTS 3.6.2. FLIGHT TIME SIMULATION 3.6.3. FLIGHT TIME HARDWARE VALIDATION 4.0. THEORY. 4.1. AGTL+. 4.2. Timing Requirements 4.3. Noise Margin. 4.3.1. FALLING EDGE LEVEL NOISE MARGIN. 4.3.2. RISING EDGE HIGH LEVEL NOISE MARGIN. 4.4. Crosstalk Theory. 4.4.1. CROSSTALK MANAGEMENT. 4.4.2. POTENTIAL TERMINATION CROSSTALK PROBLEMS
FIGURES Figure Example 2-Way Network Topology Figure Test Load Actual System Load Figure Rising Edge Noise Margin Figure Aggressor Victim Networks Figure Transmission Line Geometry: Microstrip Stripline. Figure Signal Layer Reference Plane Figure Layer Switch with Reference Plane Figure Layer Switch with Multiple Reference Planes (same type) Figure Layer Switch with Multiple Reference Planes Figure Layer with Multiple Reference Planes
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Table Example Backward Crosstalk Coupling Factors with 4.5, VOH_MAX Figure Overdrive Region VREF Guardband.28 Figure Rising Edge Flight Time Measurement.28
TABLES Table Pentium® XeonProcessor 82443GX AGTL+ Parameters Example Calculations.9 Table Example TFLT_MAX Calculations Bus.10 Table Example TFLT_MIN Calculations (Frequency Independent).10 Table Segments Descriptions Lengths Figure
1.0. INTRODUCTION
Pentium® Xeonprocessor follow-on Pentium® Pentium® Xeonprocessors. Intel® 440BX AGPset Intel® 440GX AGPset have been designed provide high-performance memory, Advanced Graphics Port (AGP), subsystem Pentium Xeon processor based systems. Intel 440BX AGPset integrates memory controller that supports Gbyte main memory (Intel 440GX AGPset supports Gbyte). Pentium Xeon processor implements synchronous, latched protocol that allows full clock cycle signal transmission full clock cycle signal interpretation generation. This protocol simplifies interconnect timing requirements supports system designs using conventional interconnect technology. Pentium Xeon processor system operates using GTL+ signaling levels with type buffer utilizing active negation multiple termination. This logic called Assisted Gunning Transceiver Logic, AGTL+. goal this layout guideline provide system designer with information needed 2-way Pentium Xeon processor 82443GX AGTL+ portion layout. topology information presented this application note also apply Pentium Xeon processor/Intel 440GX AGPset system design. This layout guideline does cover designs using other AGPsets PCIsets. This document provides guidelines methodologies that used with good engineering practices. Pentium® XeonProcessor datasheet applicable Intel 440GX AGPset specification component specific electrical details. Intel strongly recommends running analog simulations using available buffer models together with layout information extracted from your specific design. actual guidelines start Section 3.0.
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insights. items Section 5.0. expand some rationale recommendations step-bystep methodology. This section also includes equations that used reference.
2.2.
References
Pentium® XeonProcessor (Order Number 245094-001) Pentium® XeonProcessor Power Distribution Guidelines (Order Number 245095-001) Pentium® XeonProcessor Terminator Design Guidelines (Order Number 243774-001) Pentium® Processor Developer's Manual (Order Number 243341) DC-DC Converter Design Guidelines (Order Number 243773-002) DC-DC Converter Design Guidelines (Order Number 243870-002)
2.3.
Definition Terms
Aggressor network that transmits coupled signal another network called aggressor network. AGTL+ Pentium Xeon processor system uses technology called AGTL+, Assisted Gunning Transceiver Logic. AGTL+ buffers opendrain require pull-up resistors providing high logic level termination. Pentium Xeon processor AGTL+ output buffers differ from GTL+ buffers with addition active pMOS pull-up transistor "assist" pull-up resistors during first clock low-to-high voltage transition. Additionally, Pentium Xeon processor Single Edge Connector (S.E.C.) cartridge contains internal pull-up resistors provide termination each load. Agent component group components that, when combined, represent single load AGTL+ bus. Corner describes component performs when parameters that could impact performance adjusted have same impact performance. Examples these parameters include variations manufacturing process, operating temperature, operating voltage. results performance electronic component that change result
2.0. 2.1.
ABOUT THIS DOCUMENT Document Organization
This section defines terms used document. Section 3.0. discusses specific system guidelines. This step-by-step methodology that Intel successfully used design 2-way Pentium Xeon processor systems using 82443GX. Section 4.0. introduces theories that applicable this layout guideline. Section 5.0. contains more details
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measurements taken. VREF Guardband takes into account sources noise that affect AGTL+ signal becomes valid receiver. definition VREF Guardband. Maximum Minimum Flight Time Flight time variations caused many different parameters. more obvious causes include variation board dielectric constant, changes load condition, crosstalk, noise, VREF noise, variation termination resistance differences buffer performance function temperature, voltage manufacturing process. Some less obvious causes include effects Simultaneous Switching Output (SSO) packaging effects. Maximum Flight Time largest flight time network will experience under variations conditions. Maximum flight time measured appropriate VREF Guardband boundary. Minimum Flight Time smallest flight time network will experience under variations conditions. Minimum flight time measured appropriate VREF Guardband boundary. more information flight time VREF Guardband, Appendix this guideline Pentium® Processor Developer's Manual. GTL+ technology used Pentium processor. This incident wave switching, opendrain with pull-up resistors which provide both high logic level termination. enhancement (Gunning Transceiver Logic) technology. Pentium® Processor Developer's Manual more details GTL+. Network trace Printed Circuit Board (PCB) that completes electrical connection between more components. Network Length distance between extreme agents network does include distance connecting agents termination resistors. Overdrive Region voltage range, receiver, located above below VREF signal integrity analysis. Pentium® Processor Developer's Manual more details. Overshoot Maximum voltage allowed signal processor core pad. Pentium® XeonProcessor datasheet overshoot specification.
(including, limited to): clock output time, output driver edge rate, output drive current, input drive current. Discussion "slow" corner would mean having component operating slowest, weakest drive strength performance. Similar discussion "fast" corner would mean having component operating fastest, strongest drive strength performance. Operation simulation component slow corner fast corner expected bound extremes between slowest, weakest performance fastest, strongest performance. Crosstalk reception victim network signal imposed aggressor network(s) through inductive capacitive coupling between networks. Backward Crosstalk coupling which creates signal victim network that travels opposite direction aggressor's signal. Forward Crosstalk coupling which creates signal victim network that travels same direction aggressor's signal. Even Mode Crosstalk coupling from multiple aggressors when aggressors switch same direction that victim switching. Mode Crosstalk coupling from multiple aggressors when aggressors switch opposite direction that victim switching. Edge Finger cartridge electrical contact which interfaces SC330 connector. Flight Time term timing equation that includes signal propagation delay, effects system driver, plus adjustments signal receiver needed guarantee setup time receiver. More precisely, flight time defined time difference between signal input receiving agent crossing VREF (adjusted meet receiver manufacturer's conditions required timing specifications; i.e., ringback, etc.), output driving agent crossing VREF driver driving Test Load used specify driver's timings. Section 3.6.2. details regarding flight time simulation validation. Figure Appendix shows VREF Guardband boundaries. where maximum minimum flight time
feature semiconductor contained within internal logic package S.E.C cartridge substrate used connect package bond wires. only observable simulation. feature logic package contained within S.E.C. cartridge used connect package internal substrate trace. Ringback voltage that signal rings back after achieving maximum absolute value. Ringback reflections, driver oscillations, etc. Pentium® XeonProcessor datasheet ringback specification. Settling Limit defines maximum amount ringing receiving that signal must reach before next transition. Pentium® XeonProcessor datasheet settling limit specification. Setup Window time between beginning Setup Clock (TSU_MIN) arrival valid clock edge. This window different each type agent system. Simultaneous Switching Output (SSO) Effects refers difference electrical timing parameters degradation signal quality caused multiple signal outputs simultaneously switching voltage levels (i.e., high-to-low) opposite direction from single signal (i.e., low-to-high) same direction (e.g., high-to-low). These respectively called odd-mode switching even-mode switching. This simultaneous switching multiple outputs creates higher current swings that cause additional propagation delay "pushout"), decrease propagation delay "pull-in"). These effects impact setup and/or hold times always taken into account simulations. System timing budgets should include margin effects. Stub branch from trunk terminating agent. Test Load Intel uses test load specifying components. Trunk main connection, excluding interconnect branches, terminating agent pads. Undershoot Maximum voltage allowed signal extend below processor core pad. Pentium® XeonProcessor datasheet undershoot specifications.
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Victim network that receives coupled crosstalk signal from another network called victim network. VREF Guardband guardband (VREF) defined above below VREF provide more realistic model accounting noise such crosstalk, noise, VREF noise.
3.0.
AGTL+ DESIGN GUIDELIN
following step-by-step guideline developed systems based Pentium Xeon processor loads 82443GX load. Systems using custom chipsets will require timing analysis analog simulations specific those components. guideline recommended this section based experience developed Intel while developing many different Pentium processor family Pentium Xeon processor based systems. Begin with initial timing analysis topology definition. Perform prelayout analog simulations detailed picture working "solution space" design. These prelayout simulations help define routing rules prior placement routing. After routing, extract interconnect database perform post-layout simulations refine timing signal integrity analysis. Validate analog simulations when actual systems become available. validation section describes method determining flight time actual system. Guideline Methodology: Initial Timing Analysis Determine General Topology, Layout, Routing Pre-Layout Simulation (Sensitivity sweep) Place Route Board Estimate Component Component Spacing AGTL+ Signals Layout Route Board Post-Layout Simulation Interconnect Extraction Intersymbol Interference (ISI), Crosstalk, Monte Carlo Analysis Validation Measurements Determining Flight Time
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Initial Timing Analysis
NOTE Clock Output (TCO) Setup Clock (TSU) timings both measured from signals last crossing VREF, with requirement that signal does violate ringback edge rate limits. Pentium® XeonProcessor datasheet Pentium® Processor Developer's Manual more details. Solving these equations TFLT results following equations: Equation Maximum Flight Time TFLT_MAX Clock Period TCO_MAX TSU_MIN CLKSKEW CLKJITTER MADJ Equation Minimum Flight Time TFLT_MIN THOLD CLKSKEW TCO_MIN MADJ There multiple cases consider. Note that while same trace connects components, component component minimum maximum flight time requirements component driving component well component driving component must met. cases considered are: Pentium® Xeonprocessor driving Pentium Xeon processor Pentium Xeon processor driving 82443GX 82443GX driving Pentium Xeon processor designer using components other than those listed above must evaluate additional combinations driver receiver. Table lists AGTL+ component timings Pentium Xeon processor 82443GX defined pins. These timings reference only; obtain component specifications from Pentium® XeonProcessor datasheet appropriate Intel 440GX AGPset component specification. Equation Setup Time TFLT_MAX MADJ Clock Period Equation Hold Time
3.1.
Perform initial timing analysis system using Equation Equation shown below. These equations basis timing analysis. complete initial timing analysis, values clock skew clock jitter needed, along with component specifications. These equations contain multi-bit adjustment factor, MADJ, account multi-bit switching effects such pushout pull-in that often hard simulate. These equations take into consideration signal integrity factors that affect timing. Additional timing margin should budgeted allow these sources noise.
TCO_MAX TSU_MIN CLKSKEW CLKJITTER
TCO_MIN TFLT_MIN MADJ THOLD CLKSKEW Symbols used Equation Equation TCO_MAX maximum clock output specification. TSU_MIN minimum required time specified setup before clock. CLKJITTER maximum clock edge-to-edge variation. CLKSKEW maximum variation between components receiving same clock edge. TFLT_MAX maximum flight time defined Section 2.3. TFLT_MIN minimum flight time defined Section 2.3. MADJ multi-bit adjustment factor account pushout pull-in. TCO_MIN specification. minimum clock output
THOLD minimum specified input hold time.
Parameters Clock Output maximum (TCO_MAX) Clock Output minimum (TCO_MIN) Setup time (TSU_MIN) Hold time (THOLD) Pentium® XeonProcessor 2.70 -0.07 1.75 0.62 Table gives example AGTL+ initial maximum flight time calculation MHz, 2-way Pentium Xeon processor/Intel 440GX AGPset system bus. Note that assumed values clock skew clock jitter were used. Clock skew clock jitter values dependent clock components distribution method chosen particular design must budgeted into initial timing equations appropriate each design. Intel highly recommends adding margin shown "MADJ" column offset degradation caused pushout other multi-bit switching effects. "Recommended TFLT_MAX" column contains recommended maximum flight time after incorporating MADJ value. edge rate, ringback, monotonicity requirements met, flight time correction must performed documented Pentium® Processor Developer's Manual with additional requirements noted Appendix commonly used "textbook" equations used calculate expected signal propagation rate board included Section 5.1. Simulation control baseboard design parameters ensure that signal quality maximum minimum flight times met. Baseboard propagation speed highly dependent transmission line geometry configuration (stripline microstrip), dielectric constant, loading. This layout guideline includes high-speed baseboard design practices that improve amount timing signal quality margin. magnitude MADJ highly dependent baseboard
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Table Pentium® XeonProcessor 82443GX AGTL+ Parameters Example Calculations1,2 82443GX 4.45 0.83 2.98 -0.09
NOTES: times nanoseconds. Numbers table reference only. These timing parameters subject change. Please check appropriate component datasheets valid timing parameter values.
design implementation (stackup, decoupling, layout, routing, reference planes, etc.) needs characterized budgeted appropriately each design. Table example calculation minimum flight time that frequency independent. Intel highly recommends adding margin shown "MADJ" column offset degradation caused pull-in other multi-bit switching effects. "Recommended TFLT_MIN" column contains recommended minimum flight time after incorporating MADJ value. Table Table derived assuming: CLKSKEW 0.15 (PCB skew only assumes zero driver skew tying clock driver outputs) CLKJITTER 0.15 Positive negative jitter allowed between adjacent cycles, will result AGTL+ CMOS timing degradation (i.e., TCO, TSU, THOLD will increase ps). Thus, system with jitter would need flight times that (100 additional jitter timing degradation both source receiver) better than system with jitter Pentium® XeonProcessor datasheet details amount timing degradation clock jitter specifications.
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Table Example TFLT_MAX Calculations Bus1
Receiver Pentium Xeon processor 82443GX Period 10.00 TCO_MAX 2.70 TSU_MIN 1.75 ClkSKEW 0.15 ClkJITTER 0.15 MADJ 2.15 Recommended TFLT_MAX2 3.10 10.00 2.70 2.98 0.15 0.15 0.92 3.10 Pentium Xeon processor 10.00 4.45 1.75 0.15 0.15 0.40 3.10
Driver Pentium® Xeonprocessor Pentium Xeon processor 82443GX
NOTES: times nanoseconds. flight times this column include margin account following phenomena which Intel observed when multiple bits switching simultaneously. These multi-bit effects adversely affect flight time signal quality sometimes accounted simulation. Accordingly, maximum flight times depend baseboard design additional adjustment factors margins recommended.
pushout pull-in. Rising falling edge rate degradation receiver caused inductance current return path, requiring extrapolation that causes additional delay.
Crosstalk internal package cause variation signals. There additional effects that necessarily covered multi-bit adjustment factor should budgeted appropriate baseboard design. Examples include:
effective board propagation constant (SEFF), which function
Dielectric constant material. type trace connecting components (stripline microstrip). length trace load components trace. Note that board propagation constant multiplied trace length component flight time necessarily equal flight time. Table Example TFLT_MIN Calculations (Frequency Independent)1
Driver Pentium® Xeonprocessor Pentium Xeon processor 82443GX
Receiver Pentium Xeon processor 82443GX Pentium Xeon processor
THOLD 0.62 -0.10 0.62
ClkSKEW 0.15 0.15 0.15
TCO_MIN -0.07 -0.07 0.83
MADJ 0.26 0.98 1.16
Recommended TFLT_MIN2 1.10 1.10 1.10
pushout pull-in.
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NOTES: times nanoseconds. flight times this column include margin account following phenomena which Intel observed when multiple bits switching simultaneously. These multi-bit effects adversely affect flight time signal quality sometimes accounted simulation. Accordingly, maximum flight times depend baseboard design additional adjustment factors margins recommended.
Rising falling edge rate degradation receiver caused inductance current return path, requiring extrapolation that causes additional delay.
Crosstalk internal package cause variation signals. There additional effects that necessarily covered multi-bit adjustment factor should budgeted appropriate baseboard design. Examples include:
effective board propagation constant (SEFF), which function
Dielectric constant material. type trace connecting components (stripline microstrip). length trace load components trace. Note that board propagation constant multiplied trace length component flight time necessarily equal flight time.
3.2.
Determine General Topology, Layout, Routing Desired
After calculating timing budget, determine approximate location Pentium Xeon processors Intel 440GX AGPset base board. example topology shown Figure This example topology valid Intel 440GX AGPset only, does cover designs using other AGPsets PCIsets. 82443GX should placed electrically center bus. Pentium Xeon processor slots should placed either allow processors terminate each end. termination resistors added this topology resistor Rt-CS CS-Fork intersection resistor Rt-T T-Fork intersection. CS-Fork connection point stub segments length resistor stub taken from
CS-Fork resistor package. length trace from CS-Fork 82443GX package pin. T-Fork where segment forks into segments Table gives segment descriptions length recommendations investigated topology shown Figure this given topology segment lengths, resistor values Rt-T Rt-CS (both with tolerance) recommended. 2-way Pentium Xeon processor/Intel 440GX AGPset designs, termination card must placed unused slot when only processor populated. This necessary ensure signal integrity requirements met. Refer Pentium® XeonProcessor Terminator Design Guidelines details regarding termination card design fabrication.
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Pentium Xeon Processor Processor RTT=150 ohms Core On-card Fork Rt-CS CS-Fork Slot Connector Rt-T T-Fork RTT=150 ohms Core Slot Connector Processor
7501-1
82443GX
Figure Example 2-Way Network Topology
Table Segments Descriptions Lengths Figure Segment Description Processor core package on-card fork Stub length on-card resistor Cartridge edge finger on-card fork SC330 connector T-Fork SC330 connector T-Fork T-Fork CS-Fork Rt-CS CS-Fork CS-Fork 82443GX T-Fork Rt-T length (inches) Fixed length Pentium® length (inches)
Xeonprocessor package
Minimum maximum Traces Pentium Xeon processor package Minimum maximum traces contained Pentium Xeon processor package 1.50 1.50 3.00 0.00 1.00 0.00 1.75 1.75 3.25 0.25 1.25 0.25
NOTE: does have equal
3.3.
3.3.1.
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Pre-Layout Simulation
METHODOLOGY
0.662 ohm*mil2/inch value annealed copper that published reference material. Using ohm*mil2/inch value increase accuracy lossy simulations. Positioning drivers with faster edges closer middle network typically results more noise than positioning them towards ends. However, Intel shown that worst-case noise margin generated drivers located positions (given appropriate variations other network parameters). Therefore, Intel recommends simulating networks from driver locations, analyzing each receiver each possible driver. Analysis shown that both fast slow corner conditions must both rising falling edge transitions. fast corner needed because fast edge rate creates most noise. slow corner needed because buffer's drive capability will minimum, causing shift which cause noise from slower edge exceed available budget. Slow corner models produce minimum flight time violations rising edges transition starts from higher VOL. Intel highly recommends checking minimum maximum flight time violations with both fast slow corner models. fast slow corner buffer models contained Pentium Xeon Intel 440GX AGPset electronic models provided Intel. transmission line package models must inserted between output buffer driving. Likewise, package model must also placed between input receiver model. This generally done editing simulator's description topology file. Intel found wide variation noise margins when varying stub impedance PCB's Intel therefore recommends that parameters controlled tightly possible, with sampling allowable simulated. recommended effective line impedance (ZEFF) +/-10%. Intel recommends running uncoupled simulations using package stubs; performing fully coupled simulations increased accuracy needed desired. Accounting crosstalk within device package varying stub impedance investigated found sufficiently accurate. This lead development full package models component packages.
Pentium Xeon processor designs require analog simulations. Start simulations prior layout. Pre-layout simulations provide detailed picture working "solution space" that meets flight time signal quality requirements. layout recommendations previous sections based pre-layout simulations conducted Intel. basing board layout guidelines solution space, iterations between layout post-layout simulation reduced. Intel recommends running simulations device pads signal quality device pins timing analysis. However, simulation results device pins used later correlate simulation performance against actual system measurements. Pre-layout analysis includes sensitivity analysis using parametric sweeps. Parametric sweep analysis involves varying system parameters while others such driver strength, package, held constant. This way, sensitivity proposed topology varying parameters analyzed systematically. Sensitivity minimum flight time, maximum flight time, signal quality should covered. Suggested sweep parameters include trace lengths, termination resistor values, other factors that affect flight time, signal quality, feasibility layout. Minimum flight time worst signal quality typically analyzed using fast buffers interconnect. Maximum flight time typically analyzed using slow buffers slow interconnect. Outputs from each sweep should analyzed determine which regions meet timing signal quality specifications. establish working solution space, find common space across sweeps that result passing timing signal quality. solution space should allow enough design flexibility feasible, cost-effective layout. 3.3.2. SIMULATION CRITERIA
Accurate simulations require that actual range parameters used simulations. Intel consistently measured cross-sectional resistivity copper approximately ohm*mil2/inch,
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Place Route Board
ESTIMATE COMPONENT COMPONENT SPACING AGTL+ SIGNALS Route intra-group AGTL+ signals (AGTL+ signals same group) with 5/10 trace width/spacing. Route same type AGTL+ signals isolated signal groups. Pentium® Processor Developer's Manual description different group types. Recommendation AGTL+ group group (inter-group) trace width/spacing 6/18 5/15 mil. Route AGTL+ non-AGTL+ signals with 6/24 5/20 trace width/spacing. spacing between various agents causes variations trunk impedance stub locations. These variations cause reflections which cause constructive destructive interference receivers. reduction noise obtained minimum spacing between agents. Unfortunately, tighter spacing results reduced component placement options lower hold margins. Therefore, adjusting inter-agent spacing change network's noise margin, mechanical constraints often limit usefulness this technique. Always sure validate signal quality after making changes agent locations changes inter-agent spacing. There AGTL+ signals that driven more than agent simultaneously. These signals require more attention during layout validation portions design. When signal asserted (driven low) more agents same clock edge, falling edge wave fronts will meet some point form negative voltage. ringback from this negative voltage easily cross into overdrive region. signals AERR#, BERR#, BINIT#, BNR#, HIT#, HITM#. This document addresses AGTL+ layout 2-way Pentium Xeon processor/Intel 440GX AGPset system. Power distribution chassis requirements cooling, connector location, memory location, etc., constrain system topology component placement location, therefore constraining board routing. These issues directly addressed this document. Section contains listing several documents that address some these issues.
3.4.
3.4.1.
Estimate number layers that will required. Then determine expected interconnect distances between each components AGTL+ bus. Using estimated interconnect distances, verify that placement support system timing requirements. maximum network length between agents determined required frequency maximum flight time propagation delay PCB. minimum network length independent required frequency. Table Table assume values CLKSKEW CLKJITTER parameters that controlled system designer. order reduce system clock skew minimum, clock buffers which allow their outputs tied together recommended. Intel strongly recommends running analog simulations ensure that each design adequate noise timing margin. 3.4.2. LAYOUT ROUTE BOARD
Route board satisfying estimated space timing requirements. Also stay within solution space from pre-layout sweeps. Estimate printed circuit board parameters from placement other information including following general guidelines: Distribute with power plane partial power plane. this cannot accomplished, wide trace possible route trace with same topology AGTL+ traces. Keep overall length short possible (but don't forget minimum component-to-component distances meet hold times). Plan minimize crosstalk with following guidelines developed example topology given (signal spacing recommendations were based fully coupled simulations spacing decreased based upon amount coupled length): spacing line width dielectric thickness ratio least 3:1:2. 4.5, this should limit coupling 3.4%. Minimize dielectric process variation used fab. Eliminate parallel traces between layers separated power ground plane.
3.5.
Post-Layout Simulation
Following layout, extract interconnect information board from layout tools. simulations verify that layout meets timing noise requirements. small amount "tuning"
required; experience Intel shown that sensitivity analysis dramatically reduces amount tuning required. post layout simulations should take into account expected variation interconnect parameters. Intel specifies signal integrity device pads therefore recommends running simulations device pads signal quality. However, Intel specifies core timings device pins, simulation results device pins should used later correlate simulation performance against actual system measurements. 3.5.1. INTERSYMBOL INTERFERENCE 3.5.3. MONTE CARLO ANALYSIS Lengths through Intersymbol Interference (ISI) refers distortion change waveform shape caused voltage transient energy network when driver begins next transition. Intersymbol Interference (ISI) occurs when transitions current cycle interfere with transitions subsequent cycles. occur when line driven high, low, then high consecutive cycles (the opposite case also valid). When driver drives high first cycle second cycle, signal settle minimum before next rising edge driven. This results improved flight times third cycle. simulations topology given this section were performed comparing flight times first third cycle. effects necessarily span only cycles necessary simulate beyond cycles certain designs. After simulating quantifying effects, adjust timing budget accordingly take these conditions into consideration. 3.5.2. CROSSTALK ANALYSIS
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Perform Monte Carlo analysis refine passing solution space region. Monte Carlo analysis involves randomly varying parameters (independent another) over their tolerance range. This analysis intends ensure that regions failing flight time signal quality exist between extreme corner cases prelayout simulations. example topology, vary following parameters during Monte Carlo simulations:
Termination resistance Pentium® Xeonprocessor cartridge Termination resistance Pentium Xeon processor cartridge traces Pentium Xeon processor cartridge traces Pentium Xeon processor cartridge traces Pentium Xeon processor cartridge traces Pentium Xeon processor cartridge Rt-T resistance Rt-CS resistance traces base board traces base board Fast slow corner Pentium Xeon processor buffer models cartridge Fast slow corner Pentium Xeon processor buffer models cartridge Fast slow package models Pentium Xeon processor cartridge Fast slow package models Pentium Xeon processor cartridge Fast slow corner 82443GX buffer models Fast slow 82443GX package models Refer Pentium® XeonProcessor datasheet electronic buffer models parameter ranges Pentium Xeon processor Intel 440GX AGPset.
AGTL+ crosstalk simulations consider Pentium Xeon processor core package, 82443GX package, SC330 connectors non-coupled. Treat traces Pentium Xeon processor cartridge baseboard fully coupled maximum crosstalk conditions. Simulate traces lossless worst case crosstalk, lossy where more accuracy needed. Evaluate both even mode crosstalk conditions. AGTL+ Crosstalk simulation involves following cases: Intra-group AGTL+ crosstalk Inter-group AGTL+ crosstalk CMOS AGTL+ crosstalk
3.6.
Validation
Build systems validate design simulation assumptions.
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MEASUREMENTS counting. TREF defined time that takes driver output reach measurement voltage, VREF, starting from beginning driver transition pad. TREF must generated using same test load TCO. Intel provides this timing value AGTL+ buffer models. this manner, following valid delay equation satisfied: Valid Delay Equation Valid Delay TFLIGHT-SYS TREF TCOFLIGHT TIME SIMULATION
MEASURED
3.6.1.
Note that AGTL+ specification signal quality component. expected method determining signal quality analog simulations pad. Then correlate simulations against actual system measurements pin. Good correlation leads confidence that simulation accurate. Controlling temperature voltage correspond buffer model extremes should enhance correlation between simulations actual system. 3.6.2.
TFLIGHT-MEASURED
defined earlier Section 2.3., flight time time difference between signal crossing VREF input receiver, output driver crossing VREF were driving test load. timings tables topologies discussed this guideline assume actual system load equal test load.
This valid delay equation total time from when driver sees valid clock pulse time when receiver sees valid data input. 3.6.3. FLIGHT TIME HARDWARE VALIDATION
Buffer
TEST
Driver
Test Load
Driver
When measurement made actual system, flight time need TREF correction since these actual numbers. These measurements include effects pertaining driver-system interface same true TCO. Therefore addition measured measured flight time must equal valid delay calculated above.
Buffer
4.0. 4.1.
THEORY AGTL+
Driver
Actual System Load
Receiver
FLIGHT-
SYSTEM
7501-2
Figure Test Load Actual System Load
Figure above shows different configurations testing flight time simulation. flip-flop represents logic input driver stage typical AGTL+ buffer. timings specified driver output. TFLIGHT-SYSTEM usually reported simulation tool time from driver starting transition time when receiver's input sees valid data input. Since both timing numbers (TCO TFLIGHT-SYSTEM) will include propagation time from pin, necessary subtract this time (TREF) from reported flight time avoid double
AGTL+ electrical technology used Pentium Xeon processor bus. This incident wave switching, open-drain with external pull-up resistors that provide both high logic level termination each load. Pentium Xeon processor AGTL+ drivers contain full cycle active pull-up device improve system timings. AGTL+ specification defines: Termination voltage (VTT). Receiver reference voltage (VREF) function termination voltage (VTT). Pentium® Xeonprocessor termination resistance (RTT). Input voltage (VIL). Input high voltage (VIH).
NMOS resistance (RONN). Edge rate specifications. Ringback specifications. Overshoot/Undershoot specifications. Settling Limit. complete AGTL+ specification found Pentium® XeonProcessor datasheet. Layout recommendations AGTL+ found Section this document.
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board loading impact effective system. amount skew jitter system clock generation distribution. Changes flight time crosstalk, noise, other effects.
4.3.
Noise Margin
4.2.
Timing Requirements
system timing AGTL+ dependent many things. Each following elements combine determine maximum minimum frequency AGTL+ support: range timings each agents system. Clock output [TCO]. (Note that system load likely different from "specification" load therefore observed system same from specification.) minimum required setup time clock [TSU_MIN] each receiving agent. range flight time between each component. This includes: velocity propagation loaded printed circuit board [SEFF].
goal this section describe total amount noise that tolerated system (the noise budget), identify sources noise system, recommend methods analyze control noise that allowed noise budget exceeded. There several sources noise which must accounted system noise budget, including: VREF variation VCCCORE variation Variation Crosstalk Ringback impedance variation along network, termination mismatch, and/or stubs network Simultaneous Switching Output Effects Calculate total noise budget taking difference worst case specified input level worst case driven output level.
BCLK Setup window
+100 -100
Noise Margin
VREF
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Figure Rising Edge Noise Margin
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Sections 4.3.1 Section 4.3.2. discuss noise margin calculations. These sections discuss ringback tolerant receivers that increase effective noise margin. appropriate component datasheets information about ringback tolerance. 4.3.1. FALLING EDGE LEVEL NOISE MARGIN
1.37/(25 12.5 36.5
Then VOLMAX VREF_MIN (36.5 12.5 Then, Noise MarginLOW LEVEL (VREF_MIN-100 VOLMAX (901 These example calculations effective termination resistance These calculations include resistive drop along trace. 4.3.2. RISING EDGE HIGH LEVEL NOISE MARGIN
Equation below shows method calculating falling edge noise margin when Pentium Xeon processor driving. example calculation follows. Equation Level Noise Margin Noise MarginLOW LEVEL VILMAX VOLMAX VREF_MIN VOLMAX VTT_MIN) VOLMAX Symbols Equation are: VILMAX maximum specified valid input level from component specification. this example, below reference voltage assumed. VOLMAX maximum output level component will drive. This VOLMAX maximum condition corresponds slow corner components models. VREF_MIN minimum valid voltage reference used threshold reference. VTT_MIN minimum termination voltage. following example calculations level high level noise margin, RON_MAX equal 12.5 assumed, along with VREF tolerance assumptions. These specs should obtained from Pentium® XeonProcessor datasheet. Solving VREF_MIN with VREF uncertainty:
Equation below shows method calculating rising edge noise margin when Pentium Xeon processor driving. example calculation follows. Equation High Level Noise Margin Noise MarginHIGH LEVEL VOH_MIN VIH_MIN VTT_MIN (VREF_MAX Symbols Equation are: VIH_MIN minimum specified valid input high level from component specification. this example, above reference voltage assumed. VOH_MIN minimum output high level component will drive. VTT_MIN minimum termination voltage. This assumed 1.37 VREF_MAX maximum valid voltage reference used threshold reference. Since VREF defined function VTT, maximum VREF with VTT_MIN (1.37 VOH_MIN AGTL+ signals VTT_MIN.
VREF_MIN VTT_MIN) (1.5 (1.37 output current case VTT_MIN, calculated shown below: Then Noise MarginHIGH LEVEL VTT_MIN (VREF_MAX 1.37
4.4. Crosstalk Theory
AGTL+ signals swing across smaller voltage range have correspondingly smaller noise margins than technologies that have traditionally been used personal computer designs. This requires that designers using AGTL+ more aware crosstalk than they have been past designs. Crosstalk caused through capacitive inductive coupling between networks. Crosstalk appears both backward crosstalk forward crosstalk. Backward
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crosstalk creates induced signal victim network that propagates direction opposite that aggressor's signal. Forward crosstalk creates signal that propagates same direction aggressor's signal. AGTL+ bus, driver aggressor network network, therefore sends signals both directions aggressor's network. Figure shows driver aggressor network receiver victim network that ends network. signal propagating each direction causes crosstalk victim network.
Victim
Signal Propagates both directions agressor line.
Aggressor
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Figure Aggressor Victim Networks
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SIGNAL LINES SIGNAL LINES DIELECTRIC, DIELECTRIC, GROUND PLANE MICROSTRIP STRIPLIN7501-5
Figure Transmission Line Geometry: Microstrip Stripline Additional aggressors possible z-direction, adjacent signal layers routed mutually perpendicular directions. Because crosstalk coupling coefficients decrease rapidly with increasing separation, rarely necessary consider aggressors which least five line widths separated from victim. maximum crosstalk occurs when aggressors switching same direction same time. There crosstalk internal packages, which also affect signal quality. Backward crosstalk present both stripline microstrip geometry's (see Figure remember which geometry stripline which microstrip that stripline geometry requires stripping layer away signal lines. backward coupled amplitude proportional backward crosstalk coefficient, aggressor's signal amplitude, coupled length network maximum which dependent rise/fall time aggressor's signal. Backward crosstalk reaches maximum (and remains constant) when propagation time coupled network length exceeds half rise time aggressor's signal. Assuming ideal ramp aggressor from 100% voltage swing, fall time unloaded coupled network, then:
Length Backward Crosstalk
Fall Time Board Delay Unit Length
example calculation fast corner fall time V/ns board delay ps/inch (2.1 ns/foot) follows: Fall time V/1.5 V/ns Length Backward Crosstalk 1000 ps/ns /175 ps/in 2.86 inches Agents AGTL+ drive signals each direction network. This will cause backward crosstalk from segments sides driver. pulses from backward crosstalk travel toward each other will meet certain moments positions bus. This cause voltage (noise) from crosstalk double. Table provides example coupling factors various stripline space width dielectric thickness ratios with dielectric constant 4.5, VOH_MAX Note that fast edge rates falling edges place limits maximum coupled length allowable, this table illustrates potential consequences maximum coupled lengths. Also, should noted that multiple parallel coupled lines will increase impact noise budget.
Table Example Backward Crosstalk Coupling Factors with Space:Width:Thickness 24:4:8 20:4:8 16:4:8 14:4:8 12:4:8 8:4:8 4:4:8 Forward crosstalk absent stripline topologies, present microstrip. (This ideal case with uniform dielectric constant. actual boards, forward crosstalk nearly absent stripline topologies, abundant microstrip.) forward coupled amplitude proportional forward crosstalk coefficient, aggressor's signal edge rate (dv/dt), coupled network's electrical length. forward crosstalk coefficient also function geometry. Unlike backward crosstalk, forward crosstalk grow with coupled section length, transition direction similar opposite that aggressor's edge. Unlike backward crosstalk, forward crosstalk victim signal will continue grow passes through more coupled length before aggressor's wave front absorbed termination. 4.4.1. CROSSTALK MANAGEMENT Coupling Factor 0.65% 1.3% 1.75% 2.5% 3.4% 6.55% 13.5% 26.2 37.5 51.0 98.2 202.5
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4.5, VOH_MAX
Maximum Crosstalk (mV)
result parallel traces that close enough each other have significant crosstalk. Minimize variation board impedance (Z0). example topology, assumed. Minimize nominal board impedance within AGTL+ specification while maintaining same trace width/spacing ratio. given dielectric constant, this reduces trace width/trace height ratio, which reduces backward forward crosstalk coefficients. Having reduced crosstalk coefficients reduces magnitude crosstalk. Minimize dielectric constant used fabrication. else being equal, this puts traces closer their reference planes reduces magnitude crosstalk. Watch voltage doubling receiving agent, caused adding backward crosstalk either side driver. Minimize total network length signals that have coupled sections. there closely spaced/coupled lines, place them near center net. This will cause point time that voltage doubling occurs before setup window. Route synchronous signals that could driven different components separate groups minimize crosstalk between these groups. Pentium® Xeonprocessor uses split transaction with independent buses (arbitration, request, error, snoop, response, data). This implies, that given clock cycle, each could driven different agent. these agents opposite process corner (one fast slow), then separating types will reduce impact crosstalk.
minimize crosstalk (and "cost" crosstalk) terms noise margin budget: Route adjacent trace layers different directions (orthogonal preferred) minimize forward backward crosstalk that occur from parallel traces adjacent layers. This reduces source crosstalk. Maximize spacing between traces. Where traces have close parallel each other, minimize distance that they close together, maximize distance between sections that have close spacing. Routing close together could occur where multiple signals have route between pair pins. When this happens signals should spread apart where possible. Also note that routing multiple layers same direction between reference planes
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Equation Effective Propagation Speed
Simulation shows that space line dielectric ratios less than 3:1:2 produce excessive crosstalk between networks Pentium Xeon processor bus. This lower voltage swing AGTL+, high frequencies (even with controlled edge rate buffers) likely long parallel traces. 4.4.2. POTENTIAL TERMINATION CROSSTALK PROBLEMS
(ns/ft)
Equation Effective Impedance
commonly used "pull-up" resistor networks AGTL+ termination suitable. These networks have common power ground extreme package, shared resistors (for 20-pin components). These packages generally have much inductance maintain voltage/current needed each resistive load. Intel recommends using discrete resistors, resistor networks with separate power/ground pins each resistor, working with resistor network vendor obtain resistor networks that have acceptable characteristics.
Equation Distributed Trace Capacitance
(pF/ft)
Equation Distributed Trace Inductance
5.0. 5.1.
MORE DETAILS INSIGHTS Textbook Timing Equations
(nH/ft)
Symbols Equation through Equation are: speed signal unloaded ns/ft. This referred board propagation constant. MICROSTRIP STRIPLINE refer speed signal unloaded microstrip stripline trace ns/ft. intrinsic impedance line function dielectric constant (r), line width, line height line space from plane(s). equations included this document. MECL System Design Handbook William Blood, these equations. distributed trace capacitance network pF/ft. distributed trace inductance network nH/ft. capacitance devices stubs divided length network's trunk, including portion connecting agents termination resistors pF/ft.
"textbook" equations used calculate propagation rate basis spreadsheet calculations timing margin based component parameters. These equations are: Equation Intrinsic Impedance
Equation Stripline Intrinsic Propagation Speed
STRIPLINE 1017 (ns/ft)
Equation Microstrip Intrinsic Propagation Speed
MICROSTRIP 1017 0.475 0.67 (ns/ft)
SEFF ZEFF effective propagation constant impedance when board "loaded" with components.
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5.2.
Effective Impedance Tolerance/Variation
area that used route traces. These partial planes also change impedance adjacent trace layers. (For instance, impedance calculations have been done microstrip geometry, adding partial plane other side trace layer turn microstrip into stripline.) 5.3.2. REFERENCE PLANES STACKUP
impedance needs controlled when fabricated. method specifying control impedance needs determined best suit each situation. Using stripline transmission lines (where trace between reference planes) likely give better results than microstrip (where trace external layer using adjacent plane reference with solder mask other side trace). This part difficulty precise control dielectric constant solder mask, difficulty limiting plated thickness microstrip conductors, which substantially increase crosstalk. effective line impedance (ZEFF) recommended +/-10%, where ZEFF defined Equation
type number layers need chosen balance many requirements. Many these requirements include: maximum trace resistance AGTL+ signal paths should exceed ohms. Depending trace width chosen vendor's process tolerance, this require ounce/ft2 thick copper instead ounce/ft2 thickness. higher trace resistivity increases voltage drop along trace, which reduces falling edge noise margin. Providing enough routing channels support minimum maximum timing requirements components. Providing stable voltage distribution each components. Providing uniform impedance Pentium® Xeonprocessor other signals needed. Provide ground plane under principal component side baseboard. Preferably under both sides active components mounted both sides. Minimizing coupling/crosstalk between networks. Minimizing emissions. Maximizing yield. Minimizing cost. Minimizing cost assemble PCB. following baseboard layout recommendations should help reduce amount Simultaneous Switching Output (SSO) effects experienced. recommended that baseboard stackup arranged such that AGTL+ signal routes traverse multiple signal layers, this create discontinuities signal's return path. also recommended that each AGTL+ signal have single reference plane entire route. Figure shows ideal case where particular signal routed entirely within same signal layer, with ground layer single reference plane.
5.3.
Power/Reference Planes, Stackup, High Frequency Decoupling
POWER DISTRIBUTION
5.3.1.
Designs using Pentium Xeon processor require several different voltages. following paragraphs describe some impact three common methods used distribute required voltages. Refer Pentium® XeonProcessor Power Distribution Guidelines more information power distribution. most conservative method distributing these voltages each them have dedicated plane. these planes used ground" reference traces control trace impedance board, then plane needs coupled system ground plane. This method require more total layers than other methods. ounce/ft2 thick copper recommended power reference planes. second method power distribution partial planes immediate area needing power, place these planes routing layer as-needed basis. These planes still need decoupled ground ensure stable voltages components being supplied. This method disadvantage reducing
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Signal Layer Ground Plane
7501-6
Signal Layer Ground Plane Layer Layer Ground Plane Signal Layer
Figure Signal Layer Reference Plane
Signal Layer Ground Plane Signal Layer
7501-7
7508
Figure Layer Switch with Multiple Reference Planes (same type)
Figure Layer Switch with Reference Plane
When possible route entire AGTL+ signal single layer, there methods reduce effects layer switches whereby signal still references same plane (see Figure Figure shows another method minimizing layer switch discontinuities, less effective than Figure this case, signal still references same type reference plane (ground). such case, good practice stitch (i.e., connect) ground planes together with vias vicinity signal transition via.
When routing stackup constraints require that AGTL+ signal reference multiple planes, method minimizing adverse effects high-frequency decoupling wherever transitions occur, shown Figure Figure Such decoupling should, again, vicinity signal transition capacitors with minimal effective series resistance (ESR) effective series inductance (ESL). Dual vias these caps recommended since inductance sometimes higher than actual capacitor inductance.
Signal Layer Power Plane Layer Layer Ground Plane Signal Layer
7501-9
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providing adequate high-frequency decoupling across VCCCORE ground SC330 connector interface baseboard will minimize discontinuity signal's reference plane this junction. Please note that these additional high-frequency decoupling capacitors addition high-frequency decoupling already processor. Transmission line geometry also influences return path reference plane. following decoupling recommendations that take this into consideration: signal that transitions from stripline another stripline should have close proximity decoupling between four reference planes. signal that transitions from stripline microstrip vice versa) should have close proximity decoupling between three reference planes. signal that transitions from stripline microstrip through vias pins component (82443GX, etc.) should have close proximity decoupling across involved reference planes ground device. 5.3.4. SC330 CONNECTOR
Figure Layer Switch with Multiple Reference Planes
Signal Layer Ground Power
7501-10
Internal studies indicate that thermal reliefs connector layout pattern (especially ground pins) should minimized. Such reliefs (cartwheels wagonwheels) increase ground inductance reduce integrity ground plane which many signals referenced. Increased ground inductance been shown aggravate effects. Also, anti-pad diameter (clearance holes planes) signal pins should minimized since large anti-pads also reduce integrity ground plane increase inductance. Some additional layout EMI-reduction guidelines regarding SC330 connector follow: Extend power/ground planes SC330 connector pins. Extend reference planes AGTL+ other controlled-impedance signals SC330 connector pins. Minimize remove thermal reliefs power/ground pins. Route power with widest signal trace miniplane possible. Place decoupling caps across ground vicinity connector pins.
Figure Layer with Multiple Reference Planes
5.3.3.
HIGH FREQUENCY DECOUPLING
This section contains several high frequency decoupling recommendations that will improve return path AGTL+ signal. These design recommendations will very likely reduce amount effects. Just layer switching multiple reference planes create discontinuities AGTL+ signal return path, discontinuities also occur when signal transitions between baseboard cartridge. Therefore,
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Keep other traces away from clock traces. Lump loads trace multiple components supported single clock output. Have equal loads each network. ideal route each clock trace same single inner layer, next ground plane, isolated from other traces, with same total trace length, same type single load, with equal length ground trace parallel driven zero skew clock driver. When deviations from ideal required, going from single layer pair layers adjacent power/ground planes would good compromise. fewer number layers clocks routed smaller impedance difference between each trace likely Maintaining equal length parallel ground trace total length each clock ensures inductance ground return produces minimum current path loop area. (The parallel ground trace will have lower inductance than ground plane because mutual inductance current clock trace.)
ground plane under principal component side baseboard (and secondary side contains active components). Distribute decoupling capacitors across power ground pins evenly around connector (less than inch spacing) primary secondary sides. Minimize serpentine traces outer layers.
5.4.
Clock Routing
Analog simulations required ensure clock signal quality skew acceptable. clock skew Pentium Xeon processor based systems must kept minimum (the calculations simulations example topology given this document have total clock skew clock jitter). given design, clock distribution system, including clock components, must evaluated ensure these same values valid assumptions. Pentium® XeonProcessor datasheet specifies clock signal quality requirements Pentium Xeon processor systems. help meet these specifications, follow these general guidelines: clock driver outputs clock buffer supports this mode operation. Match electrical length type traces (microstrip stripline have different propagation velocities). Maintain consistent impedance clock traces. Minimize number vias each trace. Minimize number different trace layers used route clocks.
5.5.
Conclusion
AGTL+ routing requires significant amount effort. Planning ahead leaving necessary time available correctly designing board layout will provide designer with best chance avoiding more difficult task debugging inconsistent failures caused poor signal integrity. Intel recommends planning layout schedule that allows time each tasks outlined this document.
APPENDIX DEFINITIONS FLIGHT TIME MEASUREMENTS/CORRECTIONS SIGNAL QUALITY
Acceptable signal quality must maintained over operating conditions ensure reliable operation. Signal Quality defined four parameters: Overshoot, Undershoot, Settling Limit, Ringback. Pentium® XeonProcessor datasheet describes specifies values these parameters. Timings measured pins driver receiver, while signal integrity observed receiver chip pad. When signal integrity violates following guidelines adjustments need made flight time, adjusted flight time obtained chip assumed have been observed package pin, usually with small timing error penalty. 1.12 rising edge ringback 0.88 falling edge ringback
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guardbanded this places absolute ringback limits
violation these ringback limits requires flight time correction documented Pentium® Processor Developer's Manual.
7.0.
OVERDRIVE REGION
6.0.
VREF GUARDBAND
account noise sources that affect AGTL+ signal becomes valid receiver, VREF shifted VREF measuring minimum maximum flight times. VREF Guardband region bounded VREF-VREF VREF+VREF. VREF value which accounts following noise sources: motherboard coupling noise VREF noise example topology covered this guideline assumes ringback tolerance within VREF. Since VREF
overdrive region voltage range, receiver, from VREF VREF low-to-high going signal VREF VREF high-to-low going signal. overdrive regions encompass VREF Guardband. when VREF shifted VREF timing measurements, overdrive region does shift VREF. Figure below depicts this relationship. Corrections edge rate ringback documented Pentium® Processor Developer's Manual. However, there exception documented correction method. Pentium® Processor Developer's Manual states that extrapolations should made from last crossing overdrive region back VREF. Simulations performed this topology should extrapolate back appropriate VREF Guardband boundary, VREF. maximum rising edge correction, extrapolate back VREF VREF. maximum falling edge corrections, extrapolate back VREF VREF.
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VREF VREF VREF VREF VREF
VREF
VREF
Overdrive Region (200
VREF Guardband
Overdrive Region (200
7501-11
Figure Overdrive Region VREF Guardband
Receiver Driver into Test Load
VREF VREF VREF VREF
VREF (100 VREF
Overdrive Region
VREF Guardband
Tflight-max
Tflight-min
7501-12
Figure Rising Edge Flight Time Measurement
8.0. FLIGHT TIME DEFINITION MEASUREMENT
Timing measurements consist minimum maximum flight times take into account that devices turn anywhere VREF Guardband region. This region bounded VREF-VREF VREF+VREF. minimum flight time rising edge measured from time driver crosses
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VREF when terminated test load, time when signal first crosses VREF-VREF receiver (see Figure 12). Maximum flight time measured point where signal first crosses VREF+VREF, assuming that ringback, edge rate, monotonicity criteria met. Similarly, minimum flight time measurements falling edge taken VREF+VREF crossing maximum flight time taken VREF-VREF crossing.

2-Way Pentium® XeonProcessor/Intel® 440GX AGPset AGTL+ Layout Guidelin

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