AP-912 APPLICATION Order Number: 245095-001 Information this

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

AP-912 APPLICATION Order Number: 245095-001 Information this

Datasheet Thumbnail

Top Searches for this datasheet

Pentium® XeonProcessor Power Distribution Guidelines
AP-912 APPLICATION
Order Number: 245095-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® Xeonprocessor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com Copyright Intel Corporation 1999. Third-party brands names property their respective owners.
AP-912
CONTENTS
PAGE PAGE 0.THE AGTL+ POWER REQUIREMENTS. 5.1. Tolerance 5.2. Reference Voltage
0.INTRODUCTION. 1.1. Terminology 1.2. References. 0.TYPICAL POWER DISTRIBUTION 0.SC330 PROCESSOR POWER REQUIREMENTS. 3.1. Voltage Tolerance. 3.2. Multiple Voltages. 3.3. Voltage Sequencing. 3.3.1. NON-AGTL+ SIGNALS (2.5 3.3.2. BACK SIDE BUS. 3.3.3. SIGNALS 3.3.4. AGTL+ SIGNALS 3.3.5. MEMORY SIDE SIGNALS 3.3.6. SIDE SIGNALS 3.3.7. CLOCK INPUT 3.3.8. CLOCK RATIO INPUTS. 3.3.8.1. Mixed Frequency Processors. 0.MEETING SC330 PROCESSOR POWER REQUIREMENTS. 4.1. Voltage Budgeting. 4.2. Supplying Power 4.2.1. LOCAL DC-TO-DC CONVERTERS CENTRALIZED POWER SUPPLY 4.2.2. INPUT VOLTAGE 4.2.3. LINEAR REGULATORS SWITCHING REGULATORS. 4.3. Decoupling Technologies Transient Response. 4.3.1. BULK CAPACITANCE 4.3.2. HIGH FREQUENCY DECOUPLING. 4.4. Power Planes. 4.4.1. LOCATION HIGH FREQUENCY DECOUPLING. 4.4.2. LOCATION BULK DECOUPLING. 4.4.3. IMPEDANCE EMISSION EFFECTS POWER ISLANDS.
6.0. MEETING AGTL+ POWER REQUIREMENTS. 6.1. Generating VTT. 6.2. Generating VREF. 0.RECOMMENDATIONS. 7.1. VCC_CORE VCC_L2 7.2. VOLTAGE REGULATOR MODULE (VRM 8.3). 7.2.1. DESIGN. 7.2.2. RECOMMENDED SYSTEM DESIGN 7.2.3. OPTIONS MEETING TOLERANCES 7.3. Main Power Supply 7.4. 7.4.1. TERMINATION RESISTORS. 7.5. VREF. 7.6. Component Models 0.MEASURING TRANSIENTS 9.0. SC330 PROCESSOR POWER DISTRIBUTION NETWORK MODELING
FIGURES Figure Ideal SC330 Processor Power Supply Scheme Figure Power Distribution SC330 Processors Figure Detailed Power Distribution Model System with SC330 Processor Figure AGTL+ Termination Layout Figure SC330 Processor Substrate Cache. Figure Voltage Sequencing Example. Figure Non-AGTL+ Diodes
AP-912
Figure Placement Processor System.32 Figure VCC_CORE Power Delivery Model Transient Response.35 Figure VCC_L2 Power Delivery Model Transient Response Figure Power Delivery Model Transient Response TABLES Table SC330 Power Delivery Models.8 Table Voltage Tolerance Table Timing Parameters Compatibility Pins.13 Table Voltage Tolerance Table Efficiency Linear Regulator.16 Table Estimating Current Table Core Voltage Identification Code Table Pinout.28 Table Voltage Specifications SC330 Pins Table Various Component Models Used Intel (Not Vendor Specifications).34
Figure AGTL+ Diodes Figure Timing Diagram Compatibility Pins Figure Schematic Sharing.13 Figure System Design Model Figure Remote Sense.15 Figure Location Capacitance Power Model with DC-to-DC Converter Figure Effect Transients Power Supply Figure Cylindrical Capacitor.19 Figure Capacitor Model Figure Required Various Current Demands Figure Capacitance Required 8.5A, Figure Layer Stackup.23 Figure 1206 Capacitor Layouts.23 Figure VREF Figure Local Regulation.26 Figure Connections Patterns.29 Figure Layout Option 1.30 Figure Layout Option 2.30 Figure Layout Option 3.31 Figure Placement Processor System.31
1.0. INTRODUCTION
computer performance demands increase, new, higher speed logic with increased density developed fulfill these needs. reduce their overall power dissipation, modern microprocessors being designed with lower voltage implementations. This turn requires power supplies provide lower voltages with higher current capability. Because this, processor power becoming significant portion system design, demands special attention. more than ever, power distribution requires careful design practices. Pentium® Xeonprocessors have unique requirements voltages supplied them. Their implementation, called AGTL+ (Assisted Gunning Transceiver Logic+), requires voltage supply own. SC330 processor system operates using GTL+ (Gunning Transceiver Logic signaling levels with type buffer utilizing active negation multiple terminations. This logic called Assisted Gunning Transistor Logic, AGTL+. older personal computer designs, power plane with high frequency bulk decoupling capacitors spread evenly across system board cost ensure sufficient power distribution. switching rate current increases, cost power distribution system becomes significant enough merit careful calculation. Centralized distribution power, example, longer most cost effective solution power distribution. Another side effect lowering voltages some components existence multiple voltages within system. basic Pentium Xeon processorbased system board there will AGTL+ termination, processor cache, CMOS non-AGTL+ signals, chipset Bus, other components. sequencing possibilities these voltages must taken into account. This discussed Section 3.3. reader should familiar with basic electrical engineering theory, first sections this document explain detail issues involved designing system with proper power distribution.
AP-912
last sections discuss recommendations SC330 processor power distribution network modeling.
1.1.
Terminology
"Power-Good" "PWRGOOD" active high signal) indicates that supplies clocks within system stable. PWRGOOD should active constant time after system voltages stable should inactive soon these voltages fail their specifications. time constant should such that, working system, clocks other supply levels have reached stable condition before PWRGOOD goes active. VCC_CORE, VCC_L2 AGTL+ refer processor core's VCC, SC330 processor's cache supply voltage Assisted Gunning Transceiver Logic supply voltage, respectively. "AGTL+" between SC330 processor it's chipset. AGTL+ front side therefore synonymous. Further, this document, terminology SC330 processor Pentium Xeon processor been used refer same processor.
1.2.
References
This document contains references AP-587, Slot Processor Power Distribution Guidelines (Order Number 243332-002) AP-830, Pentium® XeonProcessor/Intel® 450NX PCIset AGTL+ Layout Guidelines (Order Number 243790-001) Pentium® XeonProcessor datasheet (Order Number 243770-001) Pentium® XeonProcessor Termination Design Guidelines (Order Number 243774-001) Pentium® XeonProcessor datasheet (Order Number 245094-001) DC-DC Converter Design Guidelines (Order Number 243773-002) DC-DC Converter Design Guidelines (Order Number 243870-002) SC330 Processor Guidelines Terminator Design
AP-912
exist determining amount each type capacitance that required. SC330 processor designs, system designer needs design beyond rule thumb architect power distribution system that meets SC330 processor specs. Figure shows ideal power model. However, more realistic power distribution scheme appears Figure Note that, SC330system, there capability four processors. Figure recommended solution involving local voltage regulator modules.
2.0.
TYPICAL POWER DISTRIBUTION
Power distribution generally thought getting power parts that need Most digital designers typically begin assuming that ideal supply will provided, plan their schematics with little thought power distribution until end. printed circuit board (PCB) designers attempt create ideal supply with power planes using large width traces distribute power. High frequency noise created when logic gates switch controlled with high frequency ceramic capacitors, which subsequently recharged from lower frequency bulk capacitors (such tantalum capacitors). Various rule thumb methods
3772-01
Figure Ideal SC330 Processor Power Supply Scheme
Voltage Regulator Module SC330 Processor Voltage Regulator Module SC330 Processor Power Supply Voltage Regulator Module SC330 Processor Voltage Regulator Module SC330 Processor
AP-912
3772-02
Figure Power Distribution SC330 Processors
Rcable Lcable
Rconn Lconn Lboard Rboard
Cbulk
cable Lcable Lconn
Rconn Lboard
Rboard
3772-03
Figure Detailed Power Distribution Model System with SC330 Processor completely model this system, must include inductance resistance which exists cables, connectors, PCB, pins body components (such resistors capacitors), edge fingers contacts processor voltage regulator. more detailed model showing these effects shown Figure past, voltage drops inductance Ldi/dt) resistance have been nearly negligible relative tolerance components most systems. This caused creation simple rules decoupling. example, with current amp, tolerance mV), could easily ignore effects resistance distribution path, since this amounts only drop. However, amps, this drop equal tolerance supply. Similarly, inductance typically ignored power distribution system, unless current transients amp/µs exist, seen SC330 processors. Ldi/dt drop this case equal
AP-912
Table SC330 Power Delivery Models Regulator Capacitance 8000 8000 8000 Regulator Inductance Regulator Resistance Motherboard Inductance (HOT) (RTN) (HOT) (RTN) (HOT) (RTN) Motherboard Resistance (HOT) (RTN) (HOT) (RTN) (HOT) (RTN)
Supply VCC_CORE VCC_L2
hipset
772-04
Figure AGTL+ Termination Layout high di/dt requirements SC330 processor must both taken into account successful design. Section describes requirements SC330 processor. Section discusses meeting these requirements. Pentium Xeon processor typically operate depending frequency operation will draw currents However, Flexible Mother Board (FMB) designers should keep mind that IccCORE requirements high Pentium Xeon processor allows Auto HALT, StopGrant Sleep states reduce power consumption stopping clock specific internal sections processor, depending each particular state. There Deep Sleep state Pentium Xeon processor. recommended termination AGTL+ shown Figure AGTL+ lines should terminated supply, through resistors. unused SC330 slots must terminated using Front Side Termination cards. This implementation allows loads speeds MHz. Pentium® XeonProcessor Termination
3.0.
SC330 PROCESSOR POWER REQUIREMENTS
This section describes issues related supplying power SC330 processor. detailed electrical specifications, please refer Pentium® XeonProcessor datasheet. maximum power SC330 processor specified maximum power substrate, maximum current specification each voltage source. This fact that components possibly running maximum power simultaneously.
Design Guidelines document describes termination card design requirements.
AP-912
3.1.
Voltage Tolerance
SC330 processor requires `steadystate' tolerance ±130 tolerance gold fingers. Table Voltage Tolerance Voltage VCC_L2 VCC_TAP VCC_SMBUS Tolerance ±125 ±135 ±125 ±165
Typical VCC_CORE Similarly, 8.2/8.3 module, which provides VCC_L2 supply caches, capability supplying voltages from Typical VCC_L2 2.7V (depending cache size). Reference Table and/or 8.2/8.3 DCDC Converter Design Guidelines document, available voltage details. Figure shows SC330 processor caches, each, substrate. Pentium Xeon processor will available introduction with 512K cache options. Typical multiple voltages required Pentium Xeon processor system are, VCC_CORE VCC_L2 VCC_TAP VCC_SM
3.3.
Voltage Sequencing
Failure meet these specifications low-end tolerance results transistors slowing down meeting timing specifications. meeting specifications high-end tolerance induce electro-migration, causing damage reducing life processor.
When designing system with multiple voltages, there always issue ensuring that damage occurs system during voltage sequencing. Voltage sequencing timing relationship between more voltages, such AGTL+ signals VCC_CORE. Sequencing applies when user turns power supply, system enters failure condition. Sequencing applies power voltage levels levels certain other crucial signals.
3.2.
Multiple Voltages
8.2/8.3 module, which provides VCC_CORE supply Pentium Xeon processor, capability supplying voltages from
3772-05
Figure SC330 Processor Substrate Cache
AP-912
rising first, falling first ANom BNom Volts Rises later, falls later ANom -BNom Time
3772-06
Figure Voltage Sequencing Example Figure shows example power voltage sequencing. Here, voltage levels powered different sequence. power-on, differential larger instant than nominal levels. power-off, voltage input actually exceed voltage instance time. Intel designed SC330 processors, AGTL+ bus, Intel's chipsets such that additional circuitry required power system ensure order voltage sequencing. However, systems should designed such that neither supply stays extended time while other off. Excessive exposure these conditions compromise long term component reliability. following discussions describes worst case situation where voltage while other off. Figure Figure highly simplified models buffers that show protection diodes. This model provided discussion purposes only meant imply implementation scheme.
3772-07
Figure Non-AGTL+ Diodes
AP-912
3772-08
Figure AGTL+ Diodes
3.3.1.
NON-AGTL+ SIGNALS (2.5
3.3.3.
SIGNALS
When VCC_CORE supply nonAGTL+ supply (2.5 off, protection diodes buffers reverse biased power supplied signal lines. processor sees RESET#, outputs switch high inactive state contention after comes avoided. supply while VCC_CORE supply off, supply delivers current SC330 processor core through string three protection diodes connecting pads VCC_CORE. pull-up used high level signals, then ohms will allow maximum only current supplied core cell. inputs driven CMOS output, then current from output should limited maximum output current SC330 processor pin. 3.3.2. BACK SIDE
There interaction with core. 3.3.4. AGTL+ SIGNALS
When VCC_CORE supply off, inputs appear there will current flowing AGTL+ bus. VCC_CORE off, AGTL+ attempts power core through protection diode. resulting VCC_CORE level will enough that significant current will consumed core. NOTE Every device must have power order AGTL+ operate properly. 3.3.5. MEMORY SIDE SIGNALS
sequencing issues exist back side bus. absolute maximum ratings table Pentium® XeonProcessor datasheet.
DRAM used with 450NX chipset. There memory side sequencing issues, when DRAM used.
AP-912
PWRGOOD should inactive anytime that VCC_CORE VCC_L2 invalid. This accomplished logically AND-ing `power good' signals from both supplies, connecting this output chipset SC330 processor's PWRGOOD input reset generation. this case, `power good' signal from each supply that indicates stable voltage levels that within tolerance.) 3.3.8. CLOCK RATIO INPUTS SIDE SIGNALS pins A20M#, IGNNE#, LINT1, LINT0 shared with function programming core clock multiplier ratio. These pins control setting clock multiplier ratio during RESET# until clocks beyond RESET# pulse. other times their functionality defined compatibility signals that pins named after. These signals have been made tolerant that they driven existing logic devices. This important both functions pins. Figure shows timing relationship required clock ratio signals with respect RESET# BCLK. Table shows timing parameters. Note that minimum setup time these signals This table also shows timing relationship compatibility signals. Figure also shows signal called CRESET# (CMOS Reset), with timing needed controlling multiplexing function required share pins. chipset generate CRESET#.
providing MIOC with PWRGOOD signal described Section 1.1), that asserts MRESET# RCGs MUXs, will drive lines DRAM inactive, reset data buffers soon receives This holds DRAM outputs keeps chipset buffer components reset during period power supply stabilization. This includes poor that would prevent AGTL+ RESET# signal from being created correctly. This action protects these devices from producing contention between themselves 3.3.6.
PCIRST# tells devices remain tri-state condition. controller holds this signal active when controller receives power PWR_GD signal inactive. controller also tri-states outputs during this time. addition, inputs input their protection. This eliminates issue with turning diodes. 3.3.7. CLOCK INPUT
clock input frequency must never exceed intended final value while PWRGOOD signal processor active. (See terminology Section 1.1.)
BCLK
RESET#
CRESET#
Ratio Pins#
Final Ratio
Final Ratio
Compatibility
3772-09
Figure Timing Diagram Compatibility Pins
Table Timing Parameters Compatibility Pins Parameter RESET# active CRESET# RESET# active Ratio Delay BCLK CRESET# Inactive BCLK Compatibility Ratio Setup RESET# rising Minimum Maximum Figure illustrates method using CRESET# select clock multiplier ratio normal functionality compatibility signals. pins processors bussed together allow either them compatibility processor. outputs multiplexer must meet requirements stated nonAGTL+ tolerant buffer specified above.
AP-912
Units
BCLKs
BCLKs
compatibility inputs multiplexer must meet input specifications multiplexer. This require level translation before multiplexer inputs unless inputs signals driving them already compatible.
A20M# IGNNE# LINT1/NMI LINT0/INTR
Processors
Ratio:
CRESET#
3772-10
Figure Schematic Sharing
AP-912
Mixed Frequency Processors higher current requirements order maintain power supply tolerance, SC330 processor requires either local regulation power supply with remote sense capabilities. loss occurs over power distribution system resistance such things cables, power planes, connectors. formula represents this loss. Where voltage loss, current effective resistance distribution system. system with consistent current demand, setting voltage slightly higher than nominal value overcomes resistance distribution system. This ensures that voltage farthest reaches system remains within specification. However, systems where current change significantly between high state (i.e., high), changes significantly well. formula represents this change voltage. tighter tolerance specification SC330 processors make this loss significant. Intel recommends local regulation (the supply regulator near load) create voltage needed. example, local DC-to-DC converter, placed close load, converts higher voltage lower level using either linear switching regulator. Distributing lower current higher voltage converter minimizes unwanted losses (Power companies this same method high tension lines distribute electricity from generating source local residential use.) More importantly however, discrete regulator regulates voltage locally which minimizes line losses eliminating RCABLE reducing RBOARD processor voltage. Power supplies with remote sense work local regulation appropriate. power supply typically regulates voltage terminals before cabling board. Again, changing distribution losses based current demand make difficult hold tight tolerance load. remote sense, shown Figure solve this problem running separate connection from near load feedback loop power supply. feedback loop very current draw µamp range) does suffer from line losses described above. This allows supply regulate output based voltage level load that affected line losses. Remote-sense supplies suffer from added inductance cabling power supply noise induced remote sense feedback signal. Section explains this issue. system designer must also deal with finding representative load point that applies processors multi-processor system.
3.3.8.1.
Intel does support validate mixing processors rated different frequencies.
4.0.
MEETING SC330 PROCESSOR POWER REQUIREMENTS
SC330 processor power supply design requires tradeoffs between power supply, distribution decoupling technologies. This section discusses design system using more accurate power distribution model shown Figure step time. Even though this chapter deals with different type power supplies different configurations, Intel recommends using local regulation (VRM 8.2/8.3 modules) VCC_CORE VCC_L2.
4.1.
Voltage Budgeting
Before beginning design power distribution system must have idea budget tolerance specifications different points system. This provides target component board layout helps reduce iterations reach solution. Table provides estimation effects factors that system designers need consider when calculating voltage tolerance budget. Table also lists tolerable voltage fluctuations/ losses gold fingers. Table Voltage Tolerance Location gold fingers (mV) (mV) ±100 ±130
4.2.
Supplying Power
power distribution system starts with source power, power supply. central power supply unit create required voltages. Another option, local regulation create voltages closer load. section below discusses tradeoffs involved.
Power
Rcabl Lcab Lboard Rboard
AP-912
Lcab Lboard
Rboard
3772-11
Figure System Design Model
Amps (Large Power Source µAmps (Small
3772-12
Load
Figure Remote Sense
Either method regulation easily maintain accuracy, plus small ripple noise budget, under stable load. However, further demands SC330 processor abilities remote-sense supply. large current transients SC330 processor means that system designer must exercise extreme care eliminate noise coupling ringing when using remote sense feedback. 4.2.1. LOCAL DC-TO-DC CONVERTERS CENTRALIZED POWER SUPPLY
distribution scheme. distributed local DC-toDC converters provides another alternative. Distributed local DC-to-DC converters improve upgrade potential. Sockets allow these converters added replaced required. Furthermore, self-adjusting regulators meet varying needs processor socket. While decision lies hands system designer, Intel recommends local regulators. Refer 8.2/8.3 DC-DC Converter Design Guidelines more details such regulators. 4.2.2. INPUT VOLTAG
Most desktop computers today utilize self-contained multiple output power supply. This convenient cost effective strategy isolates issues power generation from system designer allows creation large reusable sub-system. However, lower operating voltages increased transient response make long distribution schemes self-contained supplies less suitable resistance inductance
SC330 processor voltage created directly from line voltage from voltage central power supply.
AP-912
Linear regulators tend have faster reaction times than switching regulators. However, high power loss linear regulator, designers should consider switching regulators high output current ratings required SC330 processors. switching regulator achieve efficiency amps. Table Efficiency Linear Regulator VOUT Efficiency with Power Loss Amps switching regulator first chops input voltage make AC-like. faster switches chops, faster converter's reaction time. faster reaction time reduces capacitance requirements. switching regulators operate switching rate, while high devices start MHz.
Creating voltage from voltage generally easier than converting from level another. DC-to-DC voltage converter must first chop voltage order create alternating voltage before converter step that voltage down. Typically however, power supplies today provide voltage taps system. Creating additional voltage from line voltage requires addition extra winding line transformer. This incurs additional costs suffers from issues distribution explained next sections. Changing output voltage this system requires changing transformer, which makes design less versatile. Creating additional voltage from existing voltage requires DC-to-DC converter. These converters work well market they work existing taps typical power supplies, manufactured high volumes. System designers place DC-to-DC converters very near SC330 processor (thus reducing distribution loss) design them into existing power supply case. They also design DC-to-DC converters have selectable output voltages, well. 4.2.3. LINEAR REGULATORS SWITCHING REGULATORS
4.3.
Decoupling Technologies Transient Response
linear regulator drops variable voltage across itself order maintain output voltage within tolerance regardless load changes (within specifications). their simplicity, linear regulators respond load changes fairly quickly (about response time). linear regulator's efficiency drops input/output voltage differential increases, evidenced Equation Equation Loss Within Linear Regulator
shown earlier, inductance also issue distribution power. inductance system cables power planes further slows power supply's ability respond quickly current transient. Decoupling power plane broken into several independent parts. Figure shows each locations where capacitance could theoretically applied. closer load capacitor placed, more inductance that bypassed. bypassing inductance leads, power planes, etc., less capacitance required. However, closer load there less room capacitance. Therefore tradeoffs must made. Typically digital component causes switching transients. These sharp surges current occur each clock edge taper cycle. Intel designed SC330 processor such that manages highest frequency components current transients. Intel accomplished this adding capacitance cartridge (CHF) well directly (CDIE). lower SC330 connector substrate inductance (LCONN LSUB) well board inductance (LBOARD),
PLOSS (VIN-VOUT)
linear regulator also requires minimum drop from input output about diode drop (0.5 making impossible have small changes from VOUT. formula efficiency VOUT/VIN approximates efficiency linear regulator. Table illustrates significant power loss poor efficiency linear regulator fixed output current amps.
SC330 processor designed with approximately ground pins VCC_CORE pins. These processor design considerations reduce current slew rate order 20A/µ.s. SC330 processors require external high frequency capacitance, since sufficient lower di/dt A/µs. Larger bulk storage (CBULK),
AP-912
such electrolytic capacitors, supply current during longer lasting changes current demand component, such coming idle condition. Similarly, they storage well current when entering idle condition from running condition.
Cartridge
BOARD LCONN DC-to-DC Converter LSUB LBOARD LCONN CDIE LSUB
CBULK
3772-13
Figure Location Capacitance Power Model with DC-to-DC Converter
AP-912
3.10 3.05 3.00 2.95 2.90 2.85 2.80 Time (ns) Current Poorly Controlled Supply Current Transients Well Controlled Supply Voltage (Volts)
3772-14
Figure Effect Transients Power Supply
this power bypassing required relatively slow speed which power supply DC-toDC converter react. typical voltage converter reaction time order while processor's current transients order Bulk capacitance supplies energy from time high frequency decoupling capacitors drained until power supply react demand. More correctly, bulk capacitors system slow transient requirement seen power source rate that able supply, while high frequency capacitors slow transient requirement seen bulk capacitors rate that they supply. Figure shows poorly controlled supply versus wellcontrolled supply during increase current demand. Notice poorly controlled supply dips below allowed tolerance specification. similar situation exists current demand decreases. load-change transient occurs when coming entering power mode. SC330 processor this load-change transient order amps. These only quick changes current demand, also long lasting average current requirements. This occurs when STPCLK# asserted de-asserted during AutoHALT. AutoHALT power state that processor enters when HALT op-code executed. Note that even during normal operation current demand still change much amps activity levels change within SC330 processor component. Maintaining voltage tolerance, during these changes current, requires high-density bulk capacitors with Effective Series Resistance (ESR). thorough analysis when choosing these components. 4.3.1. BULK CAPACITANCE Length Width
AP-912
unrolling metal capacitor appears sheet. This sheet some linear resistance /inch. longer sheet (bigger diameter capacitor) increases ESR. wider sheet (taller capacitor) decreases ESR.
3772-15
Figure Cylindrical Capacitor
Another effect fairly high inductance bulk capacitors. These elements modeled shown Figure
3772-16
Figure Capacitor Model
Again, this taken from complex model Figure Overcoming discussed here while assuming that inductance effect will addressed high frequency decoupling capacitors discussed Section 4.3.2. Figure shows relationship between current delivered (with budget) capacitors. Even with infinite capacitance, drops full budget shown Equation
understand just adding more capacitance always effective, must consider capacitance being added. This inherent resistance capacitor plate material. understand where comes from, recognize capacitor, analyze cylindrical capacitor.
AP-912
Equation Capacitance Needed Ohms
Required Ohms 0.030 0.025 0.020 0.015 0.010 0.005 0.000 11.000 14.000 17.000 20.000 2.000 5.000 8.000
4250 0.060V
Combining above formulae remove resistive drop from budget bulk capacitance gives Equation Equation Capacitance
Amps
3772-17
Figure Required Various Current Demands
Equation Allowed Budget
Another useful formula estimating amount bulk capacitance required shown Equation This ignores component furnishes amount capacitance that would required from ideal component. Equation Capacitance Ideal Capacitor
This equation leads capacitance graph shown Figure when assumed assumed 8.5A, reaction time power source capacitance value falling area below curve, Figure sufficient this application. Again this provides figure that used feel type capacitors required. example, satisfy this equation could twelve 1000 capacitors each parallel resistance capacitors would parallel capacitance would 12,000 which falls area above curve, Figure
represents current that bulk capacitance must able deliver sink. This equal difference between high current states since power supply will initially continue supply same current that been prior load change. allowable voltage change budgeted bulk capacitive (discharge) over period reaction time power source.
Assuming some representative numbers capacitance required shown Equation
Capacitance (uF)
30000 25000 20000 15000 10000 5000 0.000 0.001 0.002 0.003 0.004 0.005 0.006
Resistance (Ohms)
3772-18
Figure Capacitance Required 8.5A,
This fairly conservative analysis. Using reaction time power source assumes that power source does compensate change current demand until passed, then immediately capable delivering that demand. Also, unnecessarily conservative assume that drop full drop whole period which capacitor discharges current drops capacitor discharges. analyze power distribution system more detail requires running simulation from power source model SC330 processor power model, including board, cable, capacitor effects. Section more information component models Section SC330 processor power model. Note that numbers used various calculations, this section (4.3.1), assumed values represent DS2P actual values. 4.3.2. HIGH FREQUENCY DECOUPLING
AP-912
design design appropriately with additional components. Since capacitor inductance package related, choose largest value available package that been chosen. highest capacitance obtainable will most beneficial design since amount capacitance behind this inductance still critical. This simple inductance useful example estimating number high frequency capacitors required: Equation Simple Inductance
voltage drop that will seen inductance. di/dt value expressed A/µs inductance series combination via, trace, high frequency capacitors parallel. Section ideas reducing trace inductance. Once allowable inductance budgeted voltage drop (due high frequency transitions) calculated, number capacitors required estimated Equation Number Capacitors Required
SC330 processors contain capacitors necessary high frequency decoupling properly designed system. This section discusses high frequency decoupling background purposes only. Since bulk storage only contains effective series resistance, also fairly high inductance, these capacitors need assisted other capacitors that have lower inductance (but typically less capacitance). These high frequency capacitors control switching transients hold-over power planes during average load change until higher inductance capacitors react. 1206 surface mount package fairly inductance package, actually lower than inductance 0603 package geometry board interconnects. even lower inductance 0612 package since board interconnect area gets even larger. 0612 same size 1206 pads along long edge. However, complexity mass producing them, cost these significantly higher. 1206 package capacitors other hand readily available cost. difficulty simulating with high frequency capacitors however, that vendors readily offer specification inductance their parts. Section some measured values from capacitors that Intel investigated which should verified against vendors' parts that will actually used design. After calculating number capacitors required, look impact that averaging tolerances over many measured components
where inductance single capacitor inductance required that calculated above. example, meet A/ns di/dt produce more than noise high frequency capacitor inductance (1.9 from Table would simply plug into Equation Equation Equation Inductance Allowed
0.060V 0.2nH
Equation Number Capacitors
19nH 0.2nH 10capacitors
above analysis also include resistance high frequency capacitors.
AP-912
Multilayer boards approximately times superior double sided boards, terms both emissions susceptibility. Figure shows configuration layer board, which separate plane allocated VTT. However, cost main consideration, fewer layers embedding plane other planes. that situation, thorough analysis recommended. Power should definitely distributed plane. This plane constructed island layer used other signals, supply plane with other power islands, dedicated layer PCB. Processor power should never distributed traces alone. fact that SC330 processor voltage unique most system designs, voltage island, islands, will probably most cost effective means distributing power processors. This island from source power load should have breaks, minimize inductance plane. should also completely surround pins source pins load. 4.4.1. LOCATION HIGH FREQUENCY DECOUPLING
While above calculation provides theoretical number capacitors required meet di/dt requirement, high frequency noise persist. More capacitors necessary control noise from other sources. However, mixing additional values design create higher resonance points should useful since capacitors described (1206 package) have very high resonant frequencies already. This shown using values from Table Equation Equation Resonant Frequency
7.3MHz (0.47
Note that 1206 capacitors will have basically same inductance value that smaller components actually have more inductance. Also, inductance vias larger contributors actually cause resonance more like MHz.
4.4.
Power Planes
imperfections power planes themselves have been ignored. These also introduce unwanted resistance inductance into power distribution system. complex model Figure refers these imperfections RBOARD LBOARD.
SC330 processor contains high frequency decoupling required properly designed system.
AP-912
3772-19
Figure Layer Stackup
Good
Good
Very Good
Excellent
Vias
Pads
Capacitors
3772-20
Figure 1206 Capacitor Layouts
AP-912
components does require particular board stack-up. either event, controlling emissions, planes islands should well decoupled. amount decoupling required controlling emission will determined exact board layout, chassis design. should plan ahead allowing additional pads capacitors added case they discovered necessary during initial testing.
Where needed, high frequency decoupling should placed close power pins load physically possible. both sides board necessary placing components order achieve optimum proximity power pins. This vital inductance board's metal plane layers could cancel usefulness these inductance components. Another method lower inductance that should considered shorten path from capacitor pads pins that decoupling. possible, place vias connecting planes within capacitor. this possible, keep traces short feasible. Possibly both ends capacitor connected directly processor without via. Even simulation results look good, these practical suggestions used create even better decoupling situation where they applied layout. Figure illustrates these concepts. 4.4.2. LOCATION BULK DECOUPLING
5.0.
AGTL+ POWER REQUIREMENTS
AGTL+ multiple terminated, open-drain bus. Intel recommends terminating used SC330 slots with termination cards, shown Figure (1.5 supplies current when output drivers turn There approximately AGTL+ lines SC330 processor system. AGTL+ power requirements present different situation than creating power SC330 processors. While AGTL+ requires less current than processor, still tight tolerance specification. Just processor start stop executing within clock cycles, usage follows, which turns causes load changes transients power supply. must available termination resistors different locations, shown Figure This best accomplished having separate plane allocated VTT, multilayer base board having dedicated Power Supply. AGTL+ buffer sinks maximum When considering duty cycle signals, signals draw maximum about 6.57 amps 100% utilization bus. Table illustrates AGTL+ current draw using relatively conservative duty cycles. Utilization bus, value AGTL+ termination resistors, chipset functionality motherboard design limit actual current draw. Power supply designers need take these benefits into account well. typical system, addition front side bus, MIOC Memory F-16 buses exist. estimated that F-16 buses draw about 1.5A each MIOC memory draws about Hence, dedicated supply with around rating will sufficient.
location bulk capacitance critical since more inductance already expected these components. However, knowing their location inductance values involved will useful simulation. this example bulk capacitance voltage converter module electrically behind inductance converter pins. This Intel's recommended solution. 4.4.3. IMPEDANCE EMISSION EFFECTS POWER ISLANDS
There impedance consequences signals that cross over under edges power island that exists another layer. While neither these necessary most designs, there reasonable options consider which protect system from these consequences. SC330 processor power islands isolated from signals solid power plane layers such ground layer. This forces particular stack-up model. Another option that helps, does completely eliminate radiation effects, decouple edges processor power islands ground regular intervals about using good high frequency decoupling capacitors (1206 packages). This requires more
Table Estimating Current Signal Group Data Address Parity Arbitration Request Error Response Other Total Quantity Signals Duty Cycle Average Current 3.96 1.29
AP-912
6.0.
MEETING AGTL+ POWER REQUIREMENTS
different nature powering AGTL+ versus powering processor, meeting requirements addressed different way.
6.1.
0.39 0.26 0.06 0.11 0.50 6.57
Generating
Intel recommends terminating AGTL+ shown Figure using single regulator with dedicated plane distribution. used SC330 slots must terminated termination cards, shown Figure cost purposes, mother board designers choose have dedicated plane. such cases, board designers should conduct thorough analysis optimize layout distribution.
5.1.
Tolerance
6.2.
Generating VREF
processor edge fingers must held ±9%. recommended that regulator that maintain current draw used order guarantee over conditions. again important note that this tolerance specification covers voltage anomalies including power supply ripple, power supply tolerance, current transient response, noise. meeting specification high will change rise fall time specifications. Failure meet this specification will also result reduced margins AGTL+ buffers thus making more difficult meet timing specifications.
VREF current input (about device) differential receivers within each components AGTL+ bus. Each SC330 processor generates VREF. simple voltage divider generate VREF. Because VREF used only input buffers, does need maintain tight tolerance from component component. does however, need meet specification VREF inputs. Equation uses generate VREF nominal value VTT. Figure illustrates using resistors generate VREF specification
5.2.
Reference Voltage
VREF IREF
3772-21
AGTL+ requires Voltage Reference called VREF well. SC330 processor generates copy VREF. VREF PCIset. simple voltage divider resistors meet VREF current requirements, very current draw this signal most device). Bear mind that leakage current varies significant when building voltage divider.
Figure VREF
AP-912
7.0. RECOMMENDATIONS
Intel recommends using simulation design verify SC330 processor based systems. With above estimates, model power source, model SC330 processor provided Section system developers begin analog modeling. Intel recommends following starting point benchmark.
Equation Creating VREF
VREF
should small enough values that current drawn VREF inputs (IREF) negligible versus current caused complete analysis this circuit's currents into center node, Equation will provide final VREF circuit. number IREF inputs supplied divider. Equation Node Analysis
7.1.
VCC_CORE VCC_L2
Plugging currents rearranging, gives: Equation Node Analysis Terms Voltage
Intel recommends using socketed local Voltage Regulator Module 8.2/8.3 (VRM 8.2/8.3) DC-to-DC converter, shown Figure both VCC_CORE VCC_L2. This removes cable inductance from distribution, reduces board inductance. These modules should capable accepting signals, used indicate voltage required individual processor unit. Table lists Core Voltage Identification Codes. Refer 8.2/8.3 DC-DC Converter Design Guidelines document actual specification.
VREF VREF
Which leads
3772-22
Equation Solving VREF
VREF
IREF
Figure Local Regulation
worst case VREF should analyzed with IREF maximum minimum values determined number loads being provided voltage. number loads change from model model because upgrades, this should taken into account well. Analyze Equation with extremes their tolerance specifications.
benefits using separate regulators processor ability vary processor types system, allowed product line future. Intel recommends placing bulk decoupling DC-to-DC converter module. Since these capacitors tend large available surface mount technology, makes sense isolate these smaller module that different manufacturing environment than typical system board designs. SC330 processor contains high frequency decoupling required properly designed system.
Table Core Voltage Identification Code1, Processor Pins VID4 VID3 VID2 00110b 01111b VID1 VID0 Reserved 1.80 1.85 1.90 1.95 2.00 2.05 core Core3
AP-912
NOTES: Processor connected VSS, Open processor; pulled motherboard. 8.2/8.3 DC-DC Converter Design Guidelines. output should disabled VCCCORE values less than 1.80 Required
AP-912
VOLTAGE REGULATOR MODULE (VRM 8.3)
Table Pinout Ishare VID0 VID2 VID4 VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE SENSE OUTEN VID1 VID3 PWRGOOD VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE DESIGN
7.2.
Intel defined derivative, called 8.3. definition will include remote-sense input will specify VCCCORE SC330 input. suppliers elect provide products that meet both requirements. following sections cover design recommendations designing systems with 8.3. third section provides four layout options, first using 8.2, third using fourth using 8.2/8.3 four processor configuration, meeting tolerances. 7.2.1.
design guidelines will include expectation that, installed into header with (remote sense input 8.3) connected baseboard, static output pins will exceed VID-selected voltage Table shows pinout:
Remote sense input (Pin
Table Voltage Specifications SC330 Pins Processor Core Frequency (MHz) Symbol VCCCORE/L2 Parameter processor core/L2 cache VCCCORE/L2 static tolerance pins system board VCCCORE/L2 static tolerance SC330 connector VCCCORE/L2 transient tolerance pins system board -0.060 -0.060 -0.060 -0.070 -0.070 -0.070 -0.100 -0.100 -0.100 Minimum Typical 0.060 0.060 0.060 0.070 0.070 0.070 0.100 0.100 0.100 Maximum
AP-912
Unit
Table depicts output voltage specification SC330 pins frequencies (VRM Design Guidelines will include frequencies above MHz). 7.2.2. RECOMMENDED SYSTEM DESIGN
System boards include SENSE input trace each 8.3. trace resistance should greater than Ohm. following information explains route SENSE trace: Route SENSE trace from mid-point SC330 VCCCORE pins core Route SENSE trace from mid-point VCCL2 island (assuming processor share VRM) each processor VRM, then route SENSE trace from middle VCCL2 DS2P connector meet transient response resistances greater than 0.5m inductances greater than 0.2n
necessary capacitors connector example 22uF polymer capacitors VCCCORE VCCL2. avoid loss characteristic polymer capacitor, connections patterns should wide capacitor with multiple holes connection, shown Figure addition, some experiments have shown need bulk decoupling (300-600u However, mechanical interference with cartridge heatsink, this situation, must considered. these information guideline, system requirements might vary.
3772-23
Figure Connections Patterns
AP-912
Output pins VccCORE pins
Output pins
VccL2 pins
VccCORE power island
power island
3772-24
Figure Layout Option
CORE power island
power island pins Output pins min.
3772-25
Output pins
CORE pins
Figure Layout Option
7.2.3.
OPTIONS MEETING TOLERANCES
VCCCORE VCCL2 static transient tolerances Pentium Xeon processor corresponding tolerances assume power distribution paths with resistances greater than 0.5m inductances greater than 0.2n SC330 layout constraints, meeting these limits challenge. This section introduces four layout options system board developers consider order meet required tolerances; first using 8.2, third using fourth using 8.2/8.3, four processor configuration.
possible meet 0.5m 0.2n limits placing each VRMs side Pentium® Xeonprocessor, with output pins near SC330 VCCCORE VCCL2 input pins, shown Figure possible meet 0.5m 0.2n limits placing each VRMs ends Pentium Xeon processor closest SC330 VCCCORE VCCL2 input pins shown Figure using plane copper, planes copper parallel.
third option, sense output voltage system board Pentium Xeon processor connector using DC-DC converter, shown Figure on-board capacitors needed.
AP-912
Figure Figure provide another layout option using 8.2, respectively, four processor configuration.
sense
VccCORE power island
VccCORE pins
VccL2 pins
Output pins
VccL2 power island Output sense pins VccCORE pins VccL2 pins Output VccCORE power island pins sense
3772-26
Figure Layout Option
Processor
Processor
Processor
Processor
Remote Sense Point
Remote Sense Point
3772-28
Figure Placement Processor System
AP-912
CORE CORE CORE Processor Processor Processor Processor Note: plane copper planes copper parallel keep losses minimum
3772-28
Figure Placement Processor System
7.3.
Main Power Supply
7.4.1.
TERMINATION RESISTORS
main supply must provide power DC-to-DC converter well rest system. should ensure that input voltage converter meets converter's requirements, that DC-to-DC converter does create transient problem outputs main supply.
avoid large quantities resistors required system, Intel recommends using resistor network termination resistors. best resistor networks have separate access each side every resistor package. This minimizes inductance crosstalk within package.
7.4.
Intel recommends using single regulator distributing single dedicated plane. Intel also recommends capacitor each termination resistor package high frequency decoupling. equivalent inductance values further lowered using 0.001 each resistor package. However, this over kill. either case, 0805 package. Place these capacitors near termination resistors possible.
When using resistor networks with single corner connections AGTL+ termination, beware inductive packages. Intel found that these packages cause significant voltage drops inductance SOIC packages being used this purpose. better option resistor networks which both ends each resistor available pins.
7.5. VREF
Intel recommends voltage divider each component. SC330 processor generates VREF internally. VREF inputs each component together. Assume maximum amps leakage current load. Note that these leakage currents positive negative. following discussion illustrates using single voltage divider support VREF Loads. Using resistors voltage divider Figure make resistor, This creates static usage (1.5 V/225) voltage divider. After looking combinations (above below tolerance) IREF (±30 µA), worst case solution Equation found with IREF 30µamps, tolerance specification (148.5), high tolerance specification (75.75). This yields: Equation Resistor Tolerance Analysis
AP-912
easily verify other corners. Varying over tolerance range minimal effect. These values chosen have additional benefits: parallel combination terminates VREF line ohms. This generally available resistance value reduces resistor cost. Further, resistance value (75) generated using resistors parallel. This way, probability getting resistors with similar tolerance will higher. Decouple VREF each VREF input voltage divider with 0.001 capacitor VSS. Decoupling VREF voltage dividers with 0.001 capacitor further enhance ability VREF track VTT. actual benefit this decoupling controversial. When routing VREF pins, 30-50 trace (the wider better) keep short feasible. Also, keep other signals least mils away from VREF trace. This provides impedance line without cost additional plane island.
VREF 1.5/75.75 .000030 0.99V 1/75.75 1/148.5
Since target 1.00 this setting within 0.97% point satisfies specification. spreadsheet program allows reader
7.6.
Component Models
Acquire component models from their manufacturers. Intel guarantee specifications another manufacturer's components. This section contains some models developed Intel simulations. SC330 processor model found Section
AP-912
Table Various Component Models Used Intel (Not Vendor Specifications) Component Simulation 0.100 0.120 0.005 0.100 0.143 0.053 0.031 0.000 (nH) 1.60 0.47 0.30 0.602 2.37 0.40 ESL+ Trace (nH)
0.1µF Ceramic 0603 package 1.0µF Ceramic 1206 package 100µF (2.05"x0.71") 47µF, Tantalum Case 330µF, Aluminum Electrolytic 1000 Aluminum Electrolytic (20mm) 1000 Aluminum Electrolytic (25mm) LBOARD. used VSS, VCC_CORE. This estimate accommodates traces vias, planes socket connections plane.
8.0.
MEASURING TRANSIENTS
9.0.
order measure transients voltage island, requires clean connection. Achieve this placing coaxial connection directly into power island during layout. type connector used should placed near centrum voltage island. Cable signal directly into oscilloscope take reading with oscilloscope bandwidth limited MHz. This filters components noise that processor also filter out. There need decouple frequencies above this range since SC330 processor filters them out.
SC330 PROCESSOR POWER DISTRIBUTION NETWORK MODELING
Intel provides electrical models shown Figure Figure Figure simulation transient response SC330 processor power delivery systems. tool capability limitations, these models have been greatly simplified provided rough illustration SC330 power delivery systems.
AP-912
load
tr=1uS
3772-29
Figure VCC_CORE Power Delivery Model Transient Response
mb_vc Lmb_
=9.4
Lmb_
1.0nH
3772-30
Figure VCC_L2 Power Delivery Model Transient Response
AP-912
8000
3772-31
Figure Power Delivery Model Transient Response

AP-912 APPLICATION Order Number: 245095-001 Information this

Top Searches for this datasheet

Other recent searches