Quad 2-Input Exclusive Gate MC74HC7266 identical pinout LS266 HC2

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Quad 2-Input Exclusive Gate MC74HC7266 identical pinout LS266 HC2

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Quad 2-Input Exclusive Gate
MC74HC7266 identical pinout LS266 HC266. HC7266 standard CMOS outputs instead open-drain outputs. device inputs compatible with standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs. Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance with Requirements Defined JEDEC Standard Chip Complexity: FETs Equivalent Gates
MC74HC7266
SUFFIX PLASTIC PACKAGE CASE 646-06
SUFFIX SOIC PACKAGE CASE 751A-03
ORDERING INFORMATION MC74HCXXXXN MC74HCXXXXD Plastic SOIC
ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Output
10/95
Motorola, Inc. 1995
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: mW/_C from 125_C SOIC Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D).
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
RECOMMENDED OPERATING CONDITIONS
MAXIMUM RATINGS*
MC74HC7266
Symbol
Vin, Vout
Symbol
Symbol
Vout
Tstg
Iout
Lead Temperature, from Case Seconds (Plastic SOIC Package)
Storage Temperature
Power Dissipation Still
Supply Current, Pins
Output Current,
Input Current,
Output Voltage (Referenced GND)
Input Voltage (Referenced GND)
Supply Voltage (Referenced GND)
Input Rise Fall Time (Figure
Operating Temperature, Package Types
Input Voltage, Output Voltage (Referenced GND)
Supply Voltage (Referenced GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Plastic SOIC Package
|Iout|
|Iout|
Iout
|Iout| |Iout|
|Iout| |Iout|
Vout |Iout|
Vout |Iout|
Test Conditions
Value
1000
Unit
Unit
25_C
3.15
0.26 0.26
3.98 5.48
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Guaranteed Limit
85_C 125_C
High-Speed CMOS Logic Data DL129 3.15 0.33 0.33 3.84 5.34
3.15 0.40 0.40 3.70 5.20
Unit
MC74HC7266
ELECTRICAL CHARACTERISTICS Input
Guaranteed Limit Symbol tPLH, tPHL tTLH, tTHL Parameter 25_C
85_C 125_C
Unit
Maximum Propagation Delay, Input Output (Figures Maximum Output Transition Time, Output (Figures Maximum Input Capacitance
NOTES: propagation delays with loads other than Chapter Motorola High-Speed CMOS Data Book (DL129/D). Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Gate)*
Used determine no-load dynamic power consumption: load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
TEST POINT tPHL DEVICE UNDER TEST OUTPUT
INPUT tPLH
OUTPUT tTLH tTHL
Includes probe capacitance
Figure Switching Waveforms
Figure Test Circuit
LOGIC DETAIL (1/4 Device)
High-Speed CMOS Logic Data DL129
MC74HC7266
APPLICATION INFORMATION
defined biphase-level code. Also known Manchester Code, this technique utilizes binary phase shift keying (PSK). output shown Figure carries both data synchronization information; therefore, separate data clock lines required transfer information. positive-going transition middle interval indicates logic zero; negative-going transition indicates logic (see Figure NRZ-L shown Figure non-return-to-zero level code. This simply serial data shift register, such HC597. signal must phase coherent (i.e., glitches). Therefore, NRZ-L clock transitions must coincident.
HC7266 NRZ-L CLOCK
Figure Biphase-Level Encoder (Manchester Encoder)
NRZ-L
CLOCK
POSITIVE LOGIC DATA
INTERVAL
Figure Timing Diagram
High-Speed CMOS Logic Data DL129
MC74HC7266
OUTLINE DIMENSIONS
SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE
NOTES: LEADS WITHIN 0.13 (0.005) RADIUS TRUE POSITION SEATING PLANE MAXIMUM MATERIAL CONDITION. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 0.052 0.095 0.008 0.015 0.115 0.135 0.300 0.015 0.039 MILLIMETERS 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 1.32 2.41 0.20 0.38 2.92 3.43 7.62 0.39 1.01
SEATING PLANE
SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE
0.25 (0.010)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION.
SEATING PLANE
0.25 (0.010)
MILLIMETERS 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 0.25 0.19 0.25 0.10 5.80 6.20 0.25 0.50
INCHES 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; Ping Industrial Park, Ting Road, N.T., Hong Kong. 852-26629298
High-Speed CMOS Logic Data DL129
CODELINE
*MC74HC7266/D*
MC74HC7266/D

Quad 2-Input Exclusive Gate MC74HC7266 identical pinout LS266 HC2

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