Available 1.13 GHz, 1.0B GHz, 933, 866, 800EB, 733, 667, 600B, 600EB,
|
|
|
Top Searches for this datasheet
Pentium® Processor SC242 1.13
Available 1.13 GHz, 1.0B GHz, 933, 866, 800EB, 733, 667, 600B, 600EB, 533B, 533EB speeds support system (`B' denotes support system where processor available same specific core frequency seperate Front Side versions; denotes support Advanced Transfer Cache Advanced System Buffering) Available GHz, 850, 800, 750, 700, 650, 600E, 600, 550E, 550, 500, speeds support system (`E' denotes support Advanced Transfer Cache Advanced System Buffering) Available versions that incorporate Advanced Transfer Cache (on-die, full speed Level (L2) cache with Error Correcting Code (ECC)) versions that incorporate discrete, half-speed, in-package cache with Dual Independent (DIB) architecture increases bandwidth performance over single-bus processors Internet Streaming SIMD Extensions enhanced video, sound performance
Binary compatible with applications running previous members Intel microprocessor line Dynamic execution micro architecture Power Management capabilities System Management mode Multiple low-power states Intel Processor Serial Number Optimized 32-bit applications running advanced 32-bit operating systems Single Edge Contact Cartridge (S.E.C.C.) S.E.C.C.2 packaging technology; S.E.C. cartridges deliver high performance with improved handling protection socketability Integrated high performance instruction data, nonblocking, level cache Enables systems which scaleable processors Error-correcting code System data
Pentium® processor designed high-performance desktops workstations servers. binary compatible with previous Intel Architecture processors. Pentium® processor provides great performance applications running advanced operating systems such Windows* Windows UNIX*. This achieved integrating best attributes Intel processors-the dynamic execution, Dual Independent architecture plus Intel MMXtechnology Internet Streaming SIMD Extensions-bringing level performance systems buyers. Pentium® processor scaleable processors multiprocessor system extends power Pentium® processor with performance headroom business media, communication internet capabilities. Systems based Pentium® processors also include latest features simplify system management lower cost ownership large small business environments. Pentium® processor offers great performance today's tomorrow's applications. SC242 SECC2 Package
July 2000 Order Number: 244452-008
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Designers must rely absence characteristics features instructions marked "reserved" "undefined". Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel make changes specifications product descriptions time, without notice. Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2000 *Third-party brands names property their respective owners.
Pentium® Processor SC242 1.13
Content1.0 Introduction. Terminology.10 1.1.1 S.E.C.C.2 S.E.C.C. Packaged Processor Terminology 1.1.2 Processor Naming Convention.11 Related Documents.12 Processor System VREF Clock Control Power States.14 2.2.1 Normal State-State 2.2.2 AutoHALT Powerdown State-State 2.15 2.2.3 Stop-Grant State-State 2.2.4 HALT/Grant Snoop State-State 2.2.5 Sleep State-State 5.16 2.2.6 Deep Sleep State-State 2.2.7 Clock Control.17 Power Ground Pins Decoupling Guidelines 2.4.1 Processor VCCCORE Decoupling.18 2.4.2 Processor System AGTL+ Decoupling.18 Processor System Clock Processor Clocking Voltage Identification Processor System Unused Pins.20 Processor System Signal Groups 2.8.1 Asynchronous Synchronous System Signals 2.8.2 System Frequency Select Signal (BSEL0).22 Test Access Port (TAP) Connection.23 Maximum Ratings.24 Processor Specifications.25 AGTL+ System Specifications System Specifications BCLK, PICCLK, PWRGOOD Signal Quality Specifications Measurement Guidelines AGTL+ Non-AGTL+ Overshoot/Undershoot Specifications Measurement Guidelines 3.2.1 Overshoot/Undershoot Magnitude 3.2.2 Overshoot/Undershoot Pulse Duration.42 3.2.3 Overshoot/Undershoot Activity Factor.42 3.2.4 Reading Overshoot/Undershoot Specification Tables.43 3.2.5 Determining System meets Overshoot/Undershoot Specifications AGTL+ Non-AGTL+ Ringback Specifications Measurement Guidelines 3.3.1 Settling Limit Guideline.48
Electrical Specifications.13
2.10 2.11 2.12 2.13
Signal Quality Specifications
Pentium® Processor SC242 1.13
Thermal Specifications Design Considerations. Thermal Specifications. 4.1.1 Thermal Diode. S.E.C.C. Mechanical Specifications. S.E.C.C.2 Mechanical Specification. S.E.C.C.2 Structural Mechanical Specification Processor Package Materials Information Intel® Pentium® Processor Signal Listing. Intel® Pentium® Processor Core Substrate Assignments 5.6.1 Processor Core Assignments (CPUID 067xh). 5.6.2 Processor Core Signal Assignments (CPUID 067xh) 5.6.3 Processor Core Assignments (CPUID 068xh). Introduction Heatsink Mechanical Specifications. 6.2.1 Boxed Processor Heatsink Dimensions 6.2.2 Boxed Processor Heatsink Weight. 6.2.3 Boxed Processor Retention Mechanism Heatsink Electrical Requirements 6.3.1 Heatsink Power Supply Heatsink Thermal Specifications. 6.4.1 Boxed Processor Cooling Requirements Alphabetical Signals Reference Signal Summaries
S.E.C.C. S.E.C.C.2 Mechanical Specifications.
Boxed Processor Specifications.
Intel® Pentium® Processor Signal Description
Pentium® Processor SC242 1.13
Figure1 Second Level (L2) Cache Implementation AGTL+ Topology Stop Clock State Machine BSEL[1:0] Example System Design (100 Processor Installed) BSEL[1:0] Example 100/133 Capable System (100 Processor Installed) BSEL[1:0] Example 100/133 Capable System (133 Processor Installed) BCLK, PICCLK, Generic Clock Waveform.37 System Valid Delay Timings System Setup Hold Timings.38 System Reset Configuration Timings.38 Power-On Reset Configuration Timings.38 Test Timings (TAP Connection) Test Reset Timings BCLK PICCLK Generic Clock Waveform Maximum Acceptable AGTL+ Non-AGTL+ Overshoot/Undershoot Waveform.46 High AGTL+ Non-AGTL+ Receiver Ringback Tolerance Signal Overshoot/Undershoot, Settling Limit, Ringback 1.48 S.E.C.Cartridge 3-Dimensional View.49 S.E.C.Cartridge Substrate View Processor Functional Layout (CPUID 0686h).52 Processor Functional Layout CPUID 0683h).52 S.E.C.C. Packaged Processor Multiple Views.54 S.E.C.C. Packaged Processor Extended Thermal Plate Side Dimensions S.E.C.C. Packaged Processor Bottom View Dimensions.55 S.E.C.C. Packaged Processor Latch Arm, Extended Thermal Plate Lug, Cover Dimensions S.E.C.C. Packaged Processor Latch Arm, Extended Thermal Plate, Cover Detail Dimensions (Reference Dimensions Only).57 S.E.C.C. Packaged Processor Extended Thermal Plate Attachment Detail Dimensions S.E.C.C. Packaged Processor Extended Thermal Plate Attachment Detail Dimensions, Continued S.E.C.C. Packaged Processor Substrate Edge Finger Contact Dimensions S.E.C.C. Packaged Processor Substrate Edge Finger Contact Dimensions, Detail Intel® Pentium® Processor Markings (S.E.C.C. Packaged Processor).60 S.E.C.C.2 Packaged Processor Multiple Views.61 S.E.C.C.2 Packaged Processor Assembly Primary View.62 S.E.C.C.2 Packaged Processor Assembly Cover View with Dimensions S.E.C.C.2 Packaged Processor Assembly Heat Sink Attach Boss Section S.E.C.C.2 Packaged Processor Assembly Side View Detail View Cover Vicinity Substrate Attach Features.63 S.E.C.C.2 Packaged Processor Substrate Edge Finger Contact Dimensions64 S.E.C.C.2 Packaged Processor Substrate Edge Finger Contact Dimensions (Detail A).64
Pentium® Processor SC242 1.13
S.E.C.C.2 Packaged Processor Substrate (CPUID 067xh) Keep Zones S.E.C.C.2 Packaged Processor Substrate (CPUID 068xh) Keep Zones S.E.C.C.2 Packaged Processor Substrate (CPUID 067xh) Keep-Out Zone S.E.C.C.2 Packaged Processor Substrate (CPUID 068xh) Keep-Out Zone Intel® Pentium® Processor Markings (S.E.C.C.2 Package) Substrate Deflection Away From Heat Sink Substrate Deflection Toward Heatsink. S.E.C.C.2 Packaged Processor Specifications. Processor Core Assignments Intel® Pentium® Processor S.E.C.C. Boxed Intel® Pentium® Processor S.E.C.C.2 Packaging (Fan Power Cable Shown) Side View Space Requirements Boxed Processor with S.E.C.C.2 Packaging Front View Space Requirements Boxed Processor with S.E.C.C.2 Packaging View Space Requirements Boxed Processor. Boxed Processor Heatsink Power Cable Connector Description Recommended Baseboard Power Header Placement Relative Power Connector Intel® Pentium® Processor
Pentium® Processor SC242 1.13
Table1 Processor Identification Related Documents.12 Voltage Identification Definition System Signal Groups Frequency Select Truth Table BSEL[1:0].22 Absolute Maximum Ratings (CPUID 067xh) Absolute Maximum Ratings (CPUID 068xh) Voltage Current Specifications AGTL+ Signal Groups Specifications Non-AGTL+ Signal Group Specifications AGTL+ Specifications System Specifications (Clock) Processor Core Pins Valid System Bus, Core Frequency, Cache Frequencies System Specifications (AGTL+ Signal Group) Processor Core Pins System Specifications (CMOS Signal Group) Processor Core Pins System Specifications (Reset Conditions) System Specifications (APIC Clock APIC I/O) Processor Core Pins System Specifications (TAP Connection) Processor Core Pins BCLK, PICCLK, PWRGOOD Signal Quality Specifications Processor Core AGTL+ Signal Group Overshoot/Undershoot Tolerance AGTL+ Signal Group Overshoot/Undershoot Tolerance Non-AGTL+ Signal Group Overshoot/Undershoot Tolerance.45 Signal Ringback Specifications Signal Simulation AGTL+ Non-AGTL+ Signal Groups Ringback Tolerance Specifications Thermal Specifications S.E.C.C. Packaged Processors Thermal Specifications S.E.C.C.2 Packaged Processors.51 Thermal Diode Parameters Thermal Diode Interface.53 Description Table Processor Markings (S.E.C.C. Packaged Processor).61 Description Table Processor Markings (S.E.C.C.2 Packaged Processor) S.E.C.C.2 Pressure Specifications.68 S.E.C.C. Materials.69 S.E.C.C.2 Materials.69 Signal Listing Order Number Signal Listing Order Signal Name.73 Listing Order Signal Name Listing Order Location.83 Boxed Processor Heatsink Spatial Dimensions Heatsink Power Signal Specifications.92 Baseboard Power Connector Location Signal Description Output Signals.101 Input Signals.101 Input/Output Signals (Single Driver).102 Input/Output Signals (Multiple Driver) .102
Pentium® Processor SC242 1.13
This page intentionally left blank.
Pentium® Processor SC242 1.13
Introduction
Intel® Pentium® processor next member family, Intel IA-32 processor line. Like Intel® Pentium® processor, Intel® Pentium® processor implements Dynamic Execution microarchitecture unique combination multiple branch prediction, data flow analysis, speculative execution. This enables these processors deliver higher performance than Pentium processor, while maintaining binary compatibility with previous Intel Architecture processors. Pentium processor also executes MMXtechnology instructions enhanced media communication performance just it's predecessor, Pentium processor. Pentium processor executes Internet Streaming SIMD Extensions enhanced floating point application performance. addition, Pentium processor extends concept processor identification with addition processor serial number. Refer Intel® Processor Serial Number application note (Order Number 245125) more detailed information. Pentium processor utilizes multiple low-power states such AutoHALT, Stop-Grant, Sleep, Deep Sleep conserve power during idle times. Pentium processor utilizes same multiprocessing system technology Pentium processor. This allows higher level performance both uni-processor twoway multiprocessor (2-way systems. Please Pentium® Processor Specification Update (Order Number 244453) guidelines which processors mixed system. Memory cacheable addressable memory space, allowing significant headroom desktop systems. Pentium processor available with different second level (L2) cache implementations. "Discrete" cache version (CPUID 067xh) uses commercially available parts cache. cache composed external processor silicon) TagRAM burst pipelined synchronous static (BSRAM), seen Figure "Advanced Transfer Cache" (CPUID 068xh) does commercially available cache parts. cache resides entirely within processor silicon, seen Figure Refer Table determine cache implementation each Pentium processor. Pentium processors offered either Single Edge Contact Cartridge (S.E.C.C.) Single Edge Contact Cartridge (S.E.C.C.2) package technologies. S.E.C.C. package following features: extended thermal plate, cover, substrate with edge finger connection. extended thermal plate allows heatsink attachment customized thermal solutions. S.E.C.C.2 package cover substrate with edge finger connection. This allows thermal solutions placed directly onto processor core package. edge finger connection maintains socketability system configuration. edge finger connector called `SC242 connector' this other documentation.
Figure Second Level (L2) Cache Implementation
Processor Core Processor Core
Discrete Cache
Advanced Transfer Cache
Pentium® Processor SC242 1.13
Terminology
this document, symbol after signal name refers active signal. This means that signal active state (based name signal) when driven level. example, when FLUSH# low, flush been requested. When high, nonmaskable interrupt occurred. case signals where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D[3:0]# `LHLH' also refers High logic level, logic level). term "system bus" refers interface between processor, system core logic (a.k.a. AGPset components), other agents. system multiprocessing interface processors, memory, I/O. term "cache bus" refers interface between processor cache components (TagRAM BSRAMs). cache does connect system bus, visible other agents system bus.
1.1.1
S.E.C.C.2 S.E.C.C. Packaged Processor Terminology
following terms used often this document explained here clarification:
Pentium® processor-The entire product including internal components, substrate, cover
S.E.C.C. packaged processors, extended thermal plate.
S.E.C.C.-The processor package technology called "Single Edge Contact Cartridge." S.E.C.C.2-The follow-on S.E.C.C. processor package technology. This differs from itpredecessor that extended thermal plate, thus reducing thermal resistance.
Processor substrate-The board which components mounted inside S.E.C.C.
S.E.C.C.2 packaged processor (with without components attached).
Processor core-The processor's execution engine. Extended Thermal Plate-This S.E.C.C. package feature surface used attach
heatsink other thermal solution processor.
Cover-The plastic casing that covers backside substrate. Latch arms-An S.E.C.C. package feature which used means securing
processor retention mechanism.
OLGA Organic Land Grid Array. This package technology permits attaching heatsink
directly die. Additional terms referred this other related documentation:
SC242-The 242-contact slot connector (previously referred Slot connector) that
S.E.C.C. S.E.C.C.2 plug into, just Pentium® processor uses Socket processor SC242 connector.
Retention mechanism-A mechanical piece which holds S.E.C.C. S.E.C.C.2 packaged Heatsink support-The support pieces that mounted baseboard provide added
support heatsinks.
Keep-out zone-The area near S.E.C.C. S.E.C.C.2 packaged processor substrate
that systems designs utilize.
Keep-in zone-The area center S.E.C.C. S.E.C.C.2 packaged processor
substrate that thermal solutions utilize. cache, TagRAM BSRAM die, industry designated names.
Pentium® Processor SC242 1.13
1.1.2
Processor Naming Convention
letter(s) added certain processors (e.g., 600B MHz) when core frequency alone uniquely identify processor. Below summary what letter means well table listing Pentium processors currently available.
System Frequency Processor with "Advanced Transfer Cache" (CPUID 068xh)
Table Processor Identification
Processor 533B 533EB 550E 600B 600E 600EB 800EB 1.0B 1.13 Core Frequency (MHz) 1000 1000 1133 System Frequency (MHz) Cache Size (Kbytes) Cache Type Discrete Discrete Discrete
CPUID1 067xh 067xh 067xh 068xh 067xh 068xh 067xh 067xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh
Discrete
Discrete Discrete
ATC2
ATC2
ATC2
ATC2
NOTES: Refer Pentium® Processor Specification Update exact CPUID each processor. Advanced Transfer Cache. Cache integrated same processor core. With ATC, interface between processor core Cache 256-bits wide, runs same frequency processor core enhanced buffering.
Pentium® Processor SC242 1.13
Related DocumentThe reader this specification should also familiar with material concepts documents listed Table These documents, complete list Pentium processor reference material, found Intel Developers' Insight site located http://developer.intel.com.
Table
Related DocumentDocument AP-485, Intel Order Number 241618 243330 243333 243334 243748 244454 244457 245087 245086 245085 245119 243867 243193 243190 243191 243192 244001 243657 243502 244453 243409 243397 245335
Intel®
Processor Identification CPUID Instruction
AP-585, Pentium Processor GTL+ Guidelines AP-588, Mechanical Assembly Technology S.E.C. Cartridge Processors AP-589, Design AP-826, Mechanical Assembly Customer Manufacturing Technology S.E.P. Packages AP-902, S.E.C.C.2 Heatsink Installation Removal AP-903, Mechanical Assembly Customer Manufacturing Technology Processor S.E.C.C.2 Packages AP-905, Pentium® Processor Thermal Design Guidelines AP-906, AGTL+ Layout Guidelines Pentium® Processor Intel® 440BX AGPset AP-907, Pentium® Processor Power Distribution Guideline
Intel®
Processor Serial Number
CK97 Clock Synthesizer Design Guidelines Intel® Architecture Software Developer's Manual
Volume Basic Architecture Volume Instruction Reference Volume III: System Programming Guide
Family Processors Hardware Developer's Manual Pentium® Processor 350, datasheet Pentium®
Pentium®
Processor Developer's Manual
Processor Buffer Model
Pentium Processor Specification Update
SC242 Termination Card Design Guidelines Slot Connector Specification DC-DC Converter Design Guidelines
These models available Viewlogic* XTK* model format (formerly known QUAD format) Intel Developer's Website http://developer.intel.com.
Pentium® Processor SC242 1.13
Electrical SpecificationProcessor System VREF
Most Intel® Pentium® processor signals variation voltage Gunning Transceiver Logic (GTL) signaling technology. Pentium processor system specification similar specification, enhanced provide larger noise margins reduced ringing. improvements accomplished increasing termination voltage level controlling edge rates. This specification different from specification, referred GTL+. more information GTL+ specifications, GTL+ buffer specification Pentium® Processor Developer's Manual (Order Number 243502). Pentium processor varies from Pentium processor output buffer implementation. buffers that drive system signals Pentium processor actively driven clock cycle after high transition improve rise times. These signals should still considered open-drain require termination supply that provides high signal level. Because this specification different from GTL+ specification, referred AGTL+ this other documentation. AGTL+ logic GTL+ logic compatible with each other both used same system bus. more information AGTL+ routing, AP-906, AGTL+ Layout Guidelines Pentium III® Processor Intel® 440BX AGPset (Order Number 245086) appropriate platform design guide. AGTL+ inputs differential receivers which require reference signal (VREF). VREF used receivers determine signal logical logical generated S.E.C.C. S.E.C.C.2 packages processor core. Local copies should generated baseboard other devices AGTL+ system bus. Termination (usually resistor each signal trace) used pull high voltage level control reflections transmission line. processor contains termination resistors that provide termination Pentium processor system bus. These specifications assume another resistor each signal trace ensure adequate signal quality AGTL+ signals; Table termination voltage specifications AGTL+. Refer Pentium® Processor Developer's Manual (Order Number 243502) GTL+ specification. Solutions exist single-ended termination well, though this implementation changes system design. Figure schematic representation AGTL+ topology with Pentium processors. AGTL+ depends incident wave switching. Therefore timing calculations AGTL+ signals based flight time opposed capacitive deratings. Analog signal simulation Pentium processor system including trace lengths highly recommended when designing system with heavily loaded AGTL+ bus, especially systems using single termination resistors (i.e., those processor substrate). Such designs will match solution space allowed installation termination resistors baseboard. Intel's Developer's Website (http://developer.intel.com) download Pentium® Processor Buffer Models, Viewlogic* XTK* model format (formerly known QUAD format).
Pentium® Processor SC242 1.13
Figure AGTL+ Topology
Pentium® Processor
ASIC
Pentium Processor
Clock Control Power StatePentium processors allow AutoHALT, Stop-Grant, Sleep, Deep Sleep states reduce power consumption stopping clock internal sections processor, depending each particular state. Figure visual representation Pentium processor power states.
Figure Stop Clock State Machine
HALT Instruction HALT Cycle Generated Auto HALT Power Down State BCLK running. Snoops interrupts allowed. INIT#, BINIT#, INTR, SMI#, RESET# ,NMI Normal State Normal execution.
STPCLK# Asserted Snoop Event Occurs Snoop Event Serviced STPCLK# De-asserted STPCLK# Asserted STPCLK# De-asserted
Stop-Grant State entered from AutoHALT
Snoop Event Occurs Snoop Event Serviced
HALT/Grant Snoop State BCLK running. Service snoops caches.
Stop Grant State BCLK running. Snoops interrupts allowed.
SLP# Asserted
SLP# De-asserted
Sleep State BCLK running. snoops interrupts allowed. BCLK Input Stopped BCLK Input Restarted
Deep Sleep State BCLK stopped. snoops interrupts allowed.
PCB757a
Pentium® Processor SC242 1.13
processor fully realize current consumption Stop-Grant, Sleep, Deep Sleep states, Model Specific Register (MSR) must set. 02Ah (Hex), must (this power default setting) processor stop internal clocks during these modes. more information, Intel Architecture Software Developer's Manual, Volume System Programming Guide (Order Number 243192). inability processors recognize transactions during Sleep Deep Sleep states, 2-way systems allowed have processor Sleep/Deep Sleep state other processor Normal Stop-Grant state simultaneously.
2.2.1
Normal State-State
This normal operating state processor.
2.2.2
AutoHALT Powerdown State-State
AutoHALT power state entered when processor executes HALT instruction. processor will transition Normal state upon occurrence SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR). RESET# will cause processor immediately initialize itself. return from System Management Interrupt (SMI) handler either Normal Mode AutoHALT Power Down state. Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide (Order Number 243192) more information. FLUSH# will serviced during AutoHALT state, processor will return AutoHALT state. system generate STPCLK# while processor AutoHALT Power Down state. When system deasserts STPCLK# interrupt, processor will return execution HALT state.
2.2.3
Stop-Grant State-State
Stop-Grant state processor entered when STPCLK# signal asserted. Since AGTL+ signal pins receive power from system bus, these pins should driven (allowing level return VTT) minimum power drawn termination resistors this state. addition, other input pins system should driven inactive state. BINIT# FLUSH# will serviced during Stop-Grant state. RESET# will cause processor immediately initialize itself, processor will stay Stop-Grant state. transition back Normal state will occur with deassertion STPCLK# signal. transition HALT/Grant Snoop state will occur when processor detects snoop system (see Section 2.2.4). transition Sleep state (see Section 2.2.5) will occur with assertion SLP# signal. While Stop-Grant State, SMI#, INIT#, LINT[1:0] will latched processor, only serviced when processor returns Normal state. Only occurrence each event will recognized serviced upon return Normal state.
Pentium® Processor SC242 1.13
2.2.4
HALT/Grant Snoop State-State
processor will respond snoop transactions Pentium processor system while Stop-Grant state AutoHALT Power Down state. During snoop transaction, processor enters HALT/Grant Snoop state. processor will stay this state until snoop Pentium processor system been serviced (whether processor another agent Pentium processor system bus). After snoop serviced, processor will return Stop-Grant state AutoHALT Power Down state, appropriate.
2.2.5
Sleep State-State
Sleep state very power state which processor maintains context, maintains phase-locked loop (PLL), stopped internal clocks. Sleep state only entered from Stop-Grant state. Once Stop-Grant state, SLP# asserted, causing processor enter Sleep state. SLP# recognized Normal AutoHALT states. Snoop events that occur while Sleep State during transition into Sleep state will cause unpredictable behavior. Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals (with exception SLP# RESET#) allowed system while processor Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior. RESET# driven active while processor Sleep state, held active specified RESET# specification, then processor will reset itself, ignoring transition through Stop-Grant State. RESET# driven active while processor Sleep State, SLP# STPCLK# signals should deasserted immediately after RESET# asserted ensure processor correctly executes Reset sequence. While Sleep state, processor capable entering lowest power state, Deep Sleep state, stopping BCLK input (see Section 2.2.6). Once Sleep Deep Sleep states, SLP# deasserted another asynchronous system event occurs. SLP# minimum assertion BCLK period.
2.2.6
Deep Sleep State-State
Deep Sleep state lowest power state processor enter while maintaining context. Deep Sleep state entered stopping BCLK input (after Sleep state entered from assertion SLP# pin). processor Deep Sleep state immediately after BCLK stopped. recommended that BCLK input held during Deep Sleep State. Stopping BCLK input lowers overall current consumption leakage levels. re-enter Sleep state, BCLK input must restarted. period allow stabilization) must occur before processor considered Sleep state. Once Sleep state, SLP# deasserted re-enter Stop-Grant state. While Deep Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals allowed system while processor Deep Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior.
Pentium® Processor SC242 1.13
2.2.7
Clock Control
processor provides clock signal cache. During AutoHALT Power Down Stop-Grant states, processor will process system snoop. processor will stop clock cache during AutoHALT Power Down Stop-Grant states. Entrance into Halt/ Grant Snoop state will allow cache snooped, similar Normal state. When processor Sleep Deep Sleep states, will respond interrupts snoop transactions. During Sleep state, clock cache stopped. During Deep Sleep state, clock cache stopped. clock cache will restarted only after internal clocking mechanism processor stable (i.e., processor re-entered Sleep state). PICCLK should removed during AutoHALT Power Down Stop-Grant states. PICCLK removed during Sleep Deep Sleep states. When transitioning from Deep Sleep state Sleep state, PICCLK must restarted with BCLK.
Power Ground PinFor clean on-chip power distribution, Pentium processors have (power) (ground) inputs. pins further divided provide different voltage levels components. VCCCORE inputs processor core some cache components account pins, while inputs (1.5 used provide AGTL+ termination voltage processor VCCL2/VCC3.3 inputs (3.3 either used off-chip cache TagRAM BSRAMs (CPUID 067xh) voltage clamp logic (CPUID 068xh). VCC5 provided test equipment tools. VCC5, VCCL2/VCC3.3, VCCCORE must remain electrically separated from each other. circuit board, VCCCORE pins must connected voltage island VCCL2/VCC3.3 pins must connected separate voltage island island portion power plane that been divided, entire plane). Similarly, pins must connected system ground plane. Note: voltage clamp logic acts voltage translator between processor's tolerant CMOS signals CMOS voltage motherboard. This logic only available with Pentium processors with CPUID=068xh.
Decoupling GuidelineDue large number transistors high internal clock speeds, processor capable generating large average current swings between full power states. This causes voltages power planes below their nominal values bulk decoupling adequate. Care must taken board design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations reduced lifetime processor.
Pentium® Processor SC242 1.13
2.4.1
Processor VCCCORE Decoupling
Regulator solutions need provide bulk capacitance with Effective Series Resistance (ESR) keep interconnect resistance from regulator pins) SC242 connector less than This accomplished keeping maximum distance inches between regulator output SC242 connector. recommended VCCCORE interconnect inch wide inch long (maximum distance between SC242 connector connector) plane segment with 1-ounce plating. Bulk decoupling large current swings when part powering entering/exiting power states, provided voltage regulation module (VRM). using Intel's enabled solutions developer.intel.com specification list qualified vendors. VCCCORE input should capable delivering recommended minimum dIccCORE/dt (defined Table while maintaining required tolerances (also defined Table
2.4.2
Processor System AGTL+ Decoupling
Pentium processor contains high frequency decoupling capacitance processor substrate; bulk decoupling must provided system baseboard proper AGTL+ operation. AP-906, AGTL+ Layout Guidelines Pentium® Processor Intel® 440BX AGPset (Order Number 245086) appropriate platform design guide, AP-907, Pentium® Processor Power Distribution Guidelines (Order Number 245085), GTL+ buffer specification Pentium® Processor Developer's Manual (Order Number 243502) more information.
Processor System Clock Processor Clocking
BCLK input directly controls operating speed Pentium processor system interface. Pentium processor system timing parameters specified with respect rising edge BCLK input. Family Processors Hardware Developer's Manual (Order Number 244001) further details.
Voltage Identification
There five voltage identification pins SC242 connector. These pins used support automatic selection power supply voltages. These pins signals, either open circuit short circuit processor. combination opens shorts defines voltage required processor core. pins needed cleanly support voltage specification variations current future Pentium processors. VID[4:0] defined Table this table refers open refers short ground. power supply must supply voltage that requested disable itself. ensure system ready current future Pentium processors, range values bold Table should supported. smaller range will risk ability system migrate higher performance Pentium processor and/or maintain compatibility with current Pentium processors.
Pentium® Processor SC242 1.13
Table
Voltage Identification Definition
Processor Pins VID4 VID3 VID2 VID1 VID0 VccCORE 1.30 1.35 1.40 1.45 1.50 1.55 1.603 1.653 1.703 1.753 1.80 1.85 1.90 1.95 2.00 2.05 Core
NOTES: Processor connected VSS. Open processor; pulled baseboard. ensure system ready Pentium® processor, values BOLD Table should supported.
Note that `11111' (all opens) used detect absence processor core given connector long power supply used does affect these lines. Detection logic pull-ups should affect inputs power source (see Section 7.0). pins should pulled TTL-compatible level with external resistors power source regulator only required regulator external logic monitoring VID[4:0] signals. power source chosen must guaranteed stable whenever supply
Pentium® Processor SC242 1.13
voltage regulator stable. This will prevent possibility processor supply going above specified VCCCORE event failure supply lines. case DC-toDC converter, this accomplished using input voltage converter line pull-ups. resistor greater than equal used connect signals converter input.
Processor System Unused PinAll RESERVED pins must remain unconnected. Connection these pins VCCCORE, VCCL2/ VCC3.3, VSS, other signal (including each other) result component malfunction incompatibility with future Pentium processors. Section listing processor location each RESERVED pin. TESTHI pins must connected pull-up resistor. PICCLK must driven with valid clock input PICD[1:0] lines must pulled-up even when APIC will used. separate pull-up resistor must provided each APIC data line. reliable operation, always connect unused inputs bidirectional signals appropriate signal level. Unused AGTL+ inputs should left connects; AGTL+ termination provided processor. Unused active CMOS inputs should connected through resistor Unused active high inputs should connected through resistor ground (VSS). Unused outputs left unconnected. resistor must used when tying bidirectional signals power ground. When tying signal power ground, resistor will also allow system testability. unused pins, suggested that resistors used pull-ups (except PICD[1:0] discussed above), resistors used pull-downs.
Processor System Signal GroupIn order simplify following discussion, Pentium processor system signals have been combined into groups buffer type. Pentium processor system outputs open drain require high-level source provided externally termination pull-up resistor. However, Pentium processor includes on-cartridge (CPUID 067xh) on-die (CPUID 068xh) termination. AGTL+ input signals have differential input buffers, which VREF reference signal. AGTL+ output signals require termination this document, term "AGTL+ Input" refers AGTL+ input group well AGTL+ group when receiving. Similarly, "AGTL+ Output" refers AGTL+ output group well AGTL+ group when driving. pins connected baseboard ground and/or chassis ground through zero resistors. resistors should placed close proximity SC242 connector. path chassis ground should short length have impedance. CMOS, Clock, APIC, inputs each driven from ground CMOS, APIC, outputs open drain should pulled high This ensures only correct operation current Pentium processors, compatibility with future Pentium processors well. groups signals contained within each group shown Table Refer Section description these signals.
Pentium® Processor SC242 1.13
Table
System Signal GroupGroup Name AGTL+ Input AGTL+ Output AGTL+ CMOS Input5 CMOS Output5 System Clock APIC Clock APIC I/O5 Input
Signals BPRI#, BR1#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#1, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD2, SMI#, SLP#3, STPCLK# FERR#, IERR#, THERMTRIP#4 BCLK PICCLK PICD[1:0] TCK, TDI, TMS, TRST# VCCCORE, VCCL2/VCC3.3, VCC5, VID[4:0], VTT, VSS, SLOTOCC#, THERMDP, THERMDN, BSEL[1:0], EMI, TESTHI, Reserved
Output
Power/Other6
NOTES: BR0# only BREQ# signal that bidirectional. internal BREQ# signals mapped onto pins after agent determined. Section more information. Section information PWRGOOD signal. Section information SLP# signal. Section information THERMTRIP# signal. These signals specified operation. VCCCORE power supply processor core. VCCL2/VCC3.3 described Section 2.3. VID[4:0] described Section 2.6. used terminate system generate VREF processor substrate. system ground. TESTHI should connected with resistor. VCC5 connected Pentium® processor core. This supply used test equipment tools. SLOTOCC# described Section 7.0. BSEL[1:0] described Section 2.8.2 Section 7.0. pins described Section 7.0. THERMDP, THERMDN described Section 7.0.
2.8.1
Asynchronous Synchronous System SignalAll AGTL+ signals synchronous BCLK. CMOS, Clock, APIC, signals applied asynchronously BCLK. APIC signals synchronous PICCLK. signals synchronous TCK.
Pentium® Processor SC242 1.13
2.8.2
System Frequency Select Signal (BSEL0)
BSEL[1:0] signals (BSEL0 also known 100/66#) used select system frequency Pentium processor(s). Table defines possible combinations signals frequency associated with each combination. frequency determined processor(s), frequency synthesizer. system agents must operate same core system frequency 2-way Pentium processor configuration. 2-way system design, BSEL[1:0] signals must connected BSEL[1:0] pins both processors. Pentium processor operates either system frequency, both. system operation supported. systems that support only system clock, resistors processor cartridge will BSEL1 signal ground shown Figure This signal either left connect tied ground shown below. BSEL0 should pulled with resistor, provided frequency driver clock driver/synthesizer. baseboards which support operation either MHz, BSEL[1:0] signals should pulled with resistor shown Figure Figure BSEL1 provided frequency selection signal clock driver/synthesizer. BSEL0 signal also incorporated into system shutdown logic baseboard (thus forcing system shutdown long BSEL0 signal low). Figure shows this routing example with Pentium processor. Figure shows same routing example with Pentium processor.
Table
Frequency Select Truth Table BSEL[1:0]
BSEL1 BSEL0 Frequency 66MHz (unsupported) Reserved 133MHz
Figure BSEL[1:0] Example System Design (100 Processor Installed)
Intel Pentium Processor 3.3V BSEL1 Processor Core BSEL0 CK100
100/66#
Pentium® Processor SC242 1.13
Figure BSEL[1:0] Example 100/133 Capable System (100 Processor Installed)
3.3V
CK133 Intel Pentium Processor 133/100#
3.3V BSEL1 System Shutdown Logic BSEL0
Processor Core
Figure BSEL[1:0] Example 100/133 Capable System (133 Processor Installed)
3.3V
CK133 Intel Pentium Processor 133/100#
3.3V BSEL1 System Shutdown Logic BSEL0
Processor Core
Test Access Port (TAP) Connection
voltage levels supported other components Test Access Port (TAP) logic, recommended that Pentium processor first chain followed other components within system. translation buffer should used connect rest chain unless other components capable accepting input. Similar considerations must made TCK, TMS, TRST#. copies each signal required with each driving different voltage level. Debug Port should placed start chain with first component coming from Debug Port from last component going Debug Port. 2-way system, cautious when including empty SC242 connector scan chain. connectors scan chain must have processor installed complete chain system must support method bypass empty connectors; SC242 terminator substrates should connect order avoid placing pull-up resistors parallel. SC242 Terminator Card Design Guidelines (Order Number 243409) more details.
Pentium® Processor SC242 1.13
2.10
Maximum RatingTable contains Pentium processor stress ratings only. Functional operation absolute maximum minimum implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions given tables Section 2.11 Section 2.13. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Table
Absolute Maximum Ratings (CPUID 067xh)
Symbol TSTORAGE VCC(All) VinAGTL VinCMOS IVID ISLOTOCC Mech Latch Arms Mech Edge Fingers Parameter Processor storage temperature processor supply voltage with respect AGTL+ buffer input voltage with respect CMOS buffer input voltage with respect current SLOTOCC# current Mechanical integrity latch arms Mechanical integrity processor edge fingers -0.5 -0.3 -0.3 Operating voltage VCCCORE Unit Cycles Insertions/ Extractions Note
NOTES: Operating voltage voltage which component designed operate. Table This rating applies VCCCORE, VCCL2/VCC3.3, VCC5, input (except noted below) processor. Parameter applies CMOS, APIC, signal groups only. mechanical integrity latch arms specified last maximum cycles. electrical mechanical integrity processor edge fingers specified last insertion/ extraction cycles. While insertion/extraction cycling above insertions will cause increase contact resistance (above degradation material integrity edge finger gold plating, possible have processor functionality above specified limit. actual number insertions before processor failure will vary based upon system configuration environmental conditions. This specification only applies S.E.C.C. packaged processors.
Pentium® Processor SC242 1.13
Table
Absolute Maximum Ratings (CPUID 068xh)
Symbol TSTORAGE VCCCORE VCCL2/VCC3.3 Vin1.5 Vin2.5 IVID ISLOTOCC Mech Edge Fingers Parameter Processor storage temperature Processor core voltage Termination supply voltage with respect VCC3.3 with respect buffer input voltage buffer input voltage current SLOTOCC# current Mechanical integrity processor edge fingers -0.5 -0.5 -0.7 Unit Insertions/ Extractions Note
NOTES: Operating voltage voltage which component designed operate. Table Input voltage never above Input voltage never below Parameter applies processor core signals (BCLK, PICCLK, PWRGOOD). Parameter applies processor core signals (all signals except BCLK, PICCLK, PWRGOOD). electrical mechanical integrity processor edge fingers specified last insertion/ extraction cycles. While insertion/extraction cycling above insertions will cause increase contact resistance (above 0.1) degradation material integrity edge finger gold plating, possible have processor functionality above specified limit. actual number insertions before processor failure will vary based upon system configuration environmental conditions.
2.11
Processor SpecificationThe processor specifications this section defined Pentium processor core pins, edge fingers, SC242 connector pins. Section processor edge finger signal definitions Section core locations signal listing. Most signals Pentium processor system AGTL+ signal group. These signals specified terminated specifications these signals listed Table allow connection with other devices, Clock, CMOS, APIC, signals designed interface non-AGTL+ levels. specifications these pins listed Table Table through Table list specifications Pentium processors. Specifications valid only while meeting specifications case temperature, clock frequency, input voltages. Care should taken read notes associated with each parameter.
Pentium® Processor SC242 1.13
Table
Voltage Current SpecificationProcessor Parameter Core Freq CPUID 0672h 0673h 0672h 0673h 0672h 0673h 0681h 533EB 0683h 0686h 0672h 0673h 0681h 550E 0683h 0686h 600B 0672h 0673h 0672h 0673h 0681h 600E 0683h 0686h 0681h 600EB 0683h 0686h 0681h 0683h 0686h 0681h 0683h 0686h 0681h 0683h 0686h 0681h 0683h 0686h 0681h 0683h 0686h 0681h 0683h 0686h 2.00 2.00 2.00 2.00 2.00 2.00 1.65 1.65 1.70 2.00 2.00 1.65 1.65 1.70 2.05 2.05 2.05 2.05 1.65 1.65 1.70 1.65 1.65 1.70 1.65 1.65 1.70 1.65 1.65 1.70 1.65 1.65 1.70 1.65 1.65 1.70 1.65 1.65 1.70 1.65 1.65 1.70 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 Unit Notes1
Symbol
VccCORE
Processor Core
Pentium® Processor SC242 1.13
Table
Voltage Current Specifications (Continued)
Processor Parameter Core Freq CPUID 0681h 800EB 0683h 0686h 0681h 0683h 0686h 0681h 0683h 0686h 1.0B 1.13 0683h 0686h 0683h 0686h 0683h 0686h 0686h 3.135 1.365 -0.070 -0.080 -0.050 -0.055 -0.140 -0.080 -0.050 -0.055 -0.085 -0.110 -0.065 -0.075 -0.170 -0.110 -0.065 -0.075 1.65 1.65 1.70 1.65 1.65 1.70 1.65 1.65 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.80 1.50 3.465 1.635 0.070 0.040 0.040 0.040 0.140 0.050 0.050 0.050 0.085 0.040 0.040 0.040 0.170 0.080 0.080 0.080 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 Unit Notes1
Symbol
VccCORE
Processor Core
VCCL2/ VCC3.3 Baseboard Tolerance, Static Baseboard Tolerance, Transient VCCCORE Tolerance, Static VCCCORE Tolerance, Transient
second level cache voltage clamp logic AGTL+ termination voltage Processor core voltage static tolerance level SC242 pins Processor core voltage transient tolerance level SC242 pins Processor core voltage static tolerance level edge fingers Processor core voltage transient tolerance level edge finger
Pentium® Processor SC242 1.13
Table
Voltage Current Specifications (Continued)
Processor Parameter Core Freq 533B 533EB 550E 600B 600E 600EB 800EB 1.0B 1.13 533B 600B 533B 533EB 550E 600B 600E 600EB 800EB 1.0B 1.13 CPUID 14.5 16.1 16.7 10.6 17.0 11.0 17.8 17.8 13.0 13.0 13.0 13.3 14.0 14.6 15.0 16.0 16.0 16.2 16.3 17.7 19.4 19.4 23.0 1.08 1.21 1.29 1.33 1.45 1.45 1.20 1.40 1.49 2.50 1.54 2.50 1.68 1.68 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 3.20 Unit Notes1
Symbol
ICCCORE
processor core
ICCL2
second level cache
IVTT
Termination voltage supply current
ISGnt
Stop-Grant processor core
ISGntL2
Stop-Grant second level cache
Pentium® Processor SC242 1.13
Table
Voltage Current Specifications (Continued)
Processor Parameter Core Freq 533B 533EB 550E 600B 600E 600EB 800EB 1.0B 1.13 CPUID 0.80 0.90 1.00 2.50 1.00 2.50 1.00 1.00 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 3.30 0.50 2.20 3.00 4.75 5.00 5.25 Table Unit Notes1
Symbol
ISLP
Sleep processor core
ISLPL2 IDSLP IDSLPL2 dICCCORE/dt dICCL2/dt dICCVTT/dt VCC5 ICC5
Sleep second level cache Deep Sleep processor core Deep Sleep second level cache Power supply current slew rate cache power supply current slew rate Termination current slew rate supply voltage supply voltage
A/µs A/µs A/µs
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. This specification applies Pentium® processors. baseboard compatibility information Pentium processors, refer Pentium® Processor 350, datasheet (Order Number 243657). VCCCORE IccCORE supply processor core. variable voltage source should exist systems event that different voltage required. Section Table more information. Typical Voltage specification with Tolerance specifications provide correct voltage regulation processor. must held ±9%. recommended that held while Pentium processor system idle. This measured processor edge fingers across bandwidth. These tolerance requirements, across bandwidth, SC242 connector bottom side baseboard. requirements SC242 connector pins account voltage drops (and impedance discontinuities) across connector, processor edge fingers, processor core. VCCCORE must return within static voltage specification within after transient event; DC-DC Converter Design Guidelines (Order Number 245335) further details. These tolerance requirements, across bandwidth, processor edge fingers. requirements processor edge fingers account voltage drops (and impedance discontinuities) processor edge fingers processor core. VCCCORE must return within static voltage specification within after transient event.
Pentium® Processor SC242 1.13
VCCL2/VCC3.3 ICCL2/ICC3.3 supply second level cache ("Discrete" cache type only). Unless otherwise noted, this specification applies Pentium processor cache sizes. Systems should designed these specifications, even smaller cache size used. 10.Max measurements measured voltage, maximum temperature, under maximum signal loading conditions. currents specified occur simultaneously under stress measurement condition. Voltage regulators designed with minimum equivalent internal resistance ensure that output voltage, maximum current output, greater than nominal (i.e., typical) voltage level VCCCORE (VCCCORE_TYP). this case, maximum current level regulator, IccCORE_REG, reduced from specified maximum current IccCORE _MAX calculated equation: IccCORE_REG IccCORE_MAX VCCCORE_TYP (VCCCORE_TYP VCCCORE Tolerance, Transient) 12.The current specified current required single Pentium processor. similar amount current drawn through termination resistors opposite AGTL+ bus, unless single-ended termination used (see Section 2.1). 13.The current specified also AutoHALT state. 14.Maximum values specified design/characterization nominal VCCCORE nominal VCCL2/VCC3.3. 15.Based simulation averaged over duration change current. compute maximum inductance tolerable reaction time voltage regulator. This parameter tested. 16.dICC/dt specifications measured specified SC242 connector pins. 17.Vcc5 ICC5 used Pentium processors. VCC5 supply used test equipment tools. 18.This specification applies Pentium® processor with CPUID=067xh. 19.This specification applies Pentium® processor with CPUID=068xh. 20.Max measurements measured nominal voltage, maximum temperature, under maximum signal loading conditions. currents specified occur simultaneously under stress measurement condition. 21.This specification applies Pentium® processor with CPUID=0683h operating GHz. 22.This specification applies Pentium® processor with CPUID=0686h operating 1.13 GHz.
Pentium® Processor SC242 1.13
Table
AGTL+ Signal Groups Specifications
Symbol Parameter Input Voltage Input High Voltage Buffer Resistance Leakage Current -0.30 -0.15 1.22 VREF 0.20 0.82 VREF 0.20 16.67 ±100 ±100 Unit Note
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies. Pentium processor experience excursions above single system clock. However, input signal drivers must comply with signal quality specifications Section 3.0. Minimum maximum given Table Parameter correlated measure into resistor terminated Pentium processor experience excursions single clock. Leakage current affects input, output, signals. +5%). VOUT +5%). Refer Pentium Buffer Models characteristics. 10.(0 +5%). VOUT +5%). 12.This specification applies Pentium® processor with CPUID=067xh. 13.This specification applies Pentium® processor with CPUID=068xh.
Table Non-AGTL+ Signal Group Specifications
Symbol Parameter -0.30 -0.15 -0.30 -0.30 -0.15 2.625 2.625 2.625 ±100 2.625 Unit Notes BCLK only PICCLK only PWRGOOD only BCLK, PICCLK, PWRGOOD only outputs opendrain
Input Voltage
Input High Voltage
Output Voltage Output High Voltage Output Current Leakage Current
NOTES: Unless otherwise noted, specifications this table apply Intel® Pentium® processor frequencies. These values specified processor core pins. These values specified processor edge fingers. Parameter measured (for with inputs). Leakage current affects input, output signals. +5%). VOUT +5%). This specification applies Pentium® processor with CPUID=067xh. This specification applies Pentium® processor with CPUID=068xh. 10.Parameters apply non-AGTL+ signals except BCLK, PICCLK, PWRGOOD.
Pentium® Processor SC242 1.13
2.12
AGTL+ System SpecificationIt recommended that AGTL+ routed daisy-chain fashion with termination resistors each signal trace. These termination resistors placed electrically between ends signal traces voltage supply generally chosen approximate substrate impedance. valid high levels determined input buffers using reference voltage called VREF. Table lists nominal specification AGTL+ termination voltage (VTT). AGTL+ reference voltage (VREF) generated processor substrate processor core, should other AGTL+ logic using voltage divider baseboard. important that baseboard impedance specified held ±15% tolerance, that intrinsic trace capacitance AGTL+ signal group traces known well-controlled. more details GTL+ buffer specification, Pentium® Processor Developer's Manual (Order Number 243502) AP-585, Pentium® Processor GTL+ Guidelines (Order Number 243330).
Table AGTL+ Specifications
Symbol VREF Parameter Termination Voltage Termination Resistor Reference Voltage 0.95 1.365 1.50 1.05 1.635 Units Note
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies. Pentium processors contain AGTL+ termination resistors each signal trace processor substrate. Pentium processors generate VREF processor substrate using voltage divider supplied through connector. must held ±9%; dICCVTT/dt specified Table recommended that held while Pentium processor system idle. This measured processor edge fingers. must held within tolerance VREF generated processor substrate nominally.
2.13
System SpecificationThe Pentium processor system timings specified this section defined Pentium processor core pads. Unless otherwise specified, timings tested processor core during manufacturing. Section Pentium processor edge connector signal definitions. Section Pentium processor closest accessible core substrate assignment. Table through Table list specifications associated with Pentium processor system bus. These specifications broken into following categories: Table through Table contain system clock core frequency cache frequencies, Table contains AGTL+ specifications, Table contains CMOS signal group specifications, Table contains timings Reset conditions, Table covers APIC timing, Table covers timing. Pentium processor system specifications AGTL+ signal group relative rising edge BCLK input. AGTL+ timings referenced VREF both logic levels unless otherwise specified. timings specified this section should used conjunction with buffer models provided Intel. These buffer models, which include package information, available Pentium processor Viewlogic model format (formerly known QUAD format)
Pentium® Processor SC242 1.13
Pentium® Processor Buffer Models Intel's Developer's Website (http://developer.intel.com.) AGTL+ layout guidelines also available AP-906, AGTL+ Layout Guidelines Pentium® Processor Intel® 440BX AGPset (Order Number 245086) appropriate platform design guide. Care should taken read notes associated with particular timing parameter. Table System Specifications (Clock) Processor Core PinT# Parameter System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 1.60 1.60 10.0 ±250 100.00 133.33 Unit Notes @>2.0 @>2.0 @<0.5 @<0.5 (0.5 V-2.0 (2.0 V-0.5
Figure
Unless otherwise noted, specifications this table apply Pentium® processor frequencies. timings AGTL+ signals referenced BCLK rising edge 1.25 processor core pin. AGTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor core pins. timings CMOS signals referenced BCLK rising edge 1.25 processor core pin. CMOS signal timings (compatibility signals, etc.) referenced 1.25 processor core pins. internal core clock frequency derived from Pentium processor system clock. system clock core clock ratio fixed each processor. Individual processors will only operate their specified system frequency, either 100MHz MHz. Table shows supported ratios each processor. BCLK period allows +0.5 tolerance clock driver variation. difficulty accurately measuring clock jitter system, recommended that clock driver used that designed meet period stability specification into test load This should measured rising edges adjacent BCLKs crossing 1.25 processor core pin. jitter present must accounted component BCLK timing skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. 100% tested. Specified design characterization clock driver requirement. average period over period time must greater than minimum specified period. 10.This specification applies Pentium processor with system frequency MHz. This specification applies Pentium processor with system frequency MHz.
Pentium® Processor SC242 1.13
Table Valid System Bus, Core Frequency, Cache Frequencies
Processor 533B 533EB 550E 600B 600E 600EB 800EB 1.0B 1.13 Core Frequency (MHz) 666.67 1000.0 1000.0 1133.3 BCLK Frequency (MHz) Frequency Multiplier 11/2 11/2 13/2 11/2 15/2 17/2 13/2 15/2 17/2 Cache (MHz) 666.67 1000.0 1000.0 1133.3
NOTE: Contact your local Intel representative latest information processor frequencies and/or frequency multipliers.
Table System Specifications (AGTL+ Signal Group) Processor Core Pins
Parameter AGTL+ Output Valid Delay -0.20 -0.14 -0.10 1.90 1.20 1.20 0.85 0.58 0.80 1.00 3.15 2.20 2.70 Unit Figure Notes
AGTL+ Input Setup Time
AGTL+ Input Hold Time T10: RESET# Pulse Width
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies. These specifications tested during manufacturing. timings AGTL+ signals referenced BCLK rising edge 1.25 processor core pin. AGTL+ signal timings (compatibility signals, etc.) referenced 1.00 processor core pins. Valid delay timings these signals specified into with VREF Valid delay timings these signals specified into with VREF minimum clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. 2-way systems, RESET# should synchronous. Specification minimum 0.40 swing. Specification maximum swing.
Pentium® Processor SC242 1.13
10.This should measured after VCCCORE, VCCL2/VCC3.3, BCLK become stable. This specification applies Pentium® processor with system frequency MHz. 12.This specification applies Pentium® processor with system frequency MHz. 13.This specification applies Pentium® processor with CPUID=067xh. 14.This specification applies Pentium® processor with CPUID=068xh.
Table System Specifications (CMOS Signal Group) Processor Core Pins
Parameter T14: CMOS Input Pulse Width, except PWRGOOD T15: PWRGOOD Inactive Pulse Width Unit BCLKs BCLKs Figure Notes Active Inactive states
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies. These specifications tested during manufacturing. timings CMOS signals referenced BCLK rising edge processor core pins. CMOS signal timings (compatibility signals, etc.) referenced 1.25 These signals driven asynchronously. When driven inactive after VCCCORE, VCCL2/VCC3.3, BCLK become stable.
Table System Specifications (Reset Conditions)
Parameter T16: Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time T17: Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time Unit BCLKs Figure Notes Before deassertion RESET# After clock that deasserts RESET#
BCLK
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies.
Table System Specifications (APIC Clock APIC I/O) Processor Core Pins
Parameter T21: PICCLK Frequency T22: PICCLK Period T23: PICCLK High Time T24: PICCLK Time T25: PICCLK Rise Time T26: PICCLK Fall Time T27: PICD[1:0] Setup Time T28: PICD[1:0] Hold Time T29: PICD[1:0] Valid Delay T29a: PICD[1:0] Valid Delay (Rising Edge) T29b: PICD[1:0] Valid Delay (Falling Edge) 30.0 12.0 12.0 0.25 0.25 12.0 33.3 500.0 Unit Figure Note
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies. These specifications tested during manufacturing. timings APIC signals referenced PICCLK rising edge 1.25 processor core pins. APIC signal timings referenced 1.25 (CPUID 067xh) 0.75 (CPUID 068xh) processor core pins.
Pentium® Processor SC242 1.13
Referenced PICCLK rising edge. open drain signals, valid delay synonymous with float delay. Valid delay timings these signals specified into load pulled +5%. This specification applies Pentium® processor with CPUID=067xh. This specification applies Pentium® processor with CPUID=068xh.
Table System Specifications (TAP Connection) Processor Core PinT# Parameter T30: Frequency T31: Period T32: High Time T33: Time 60.0 25.0 25.0 25.0 25.0 40.0 14.0 10.0 25.0 25.0 25.0 13.0 16.667 Unit Figure Note
@1.7 @VREF 0.20 @0.7 @VREF 0.20 (0.7 V-1.7 (VREF 0.20 (VREF 0.20 (1.7 V-0.7 (VREF 0.20 (VREF 0.20 Asynchronous
T34: Rise Time
T35: Fall Time T36: TRST# Pulse Width T37: TDI, Setup Time T38: TDI, Hold Time T39: Valid Delay T40: Float Delay T41: Non-Test Outputs Valid Delay T42: Non-Test Inputs Setup Time T43: Non-Test Inputs Setup Time T44: Non-Test Inputs Hold Time
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies. timings signals referenced rising edge 1.25 (CPUID 067xh) 0.75 (CPUID 068xh) processor core pins. signal timings (TMS, TDI, etc.) referenced 1.25 (CPUID 067xh) 0.75 (CPUID 068xh) processor core pins. These specifications tested during manufacturing, unless otherwise noted. added maximum rise fall times every below 16.667 MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified +5%. Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals operations. During Debug Port operation, normal specified timings rather than signal timings. 10.Not 100% tested. Specified design characterization. This specification applies Pentium® processor with CPUID=067xh. 12.This specification applies Pentium® processor with CPUID=068xh.
Pentium® Processor SC242 1.13
Note:
Figure through Figure following apply: Figure through Figure used conjunction with Table through Table timings AGTL+ signals processor core pins referenced BCLK rising edge 1.25 AGTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor core pins.
Pentium
Figure BCLK, PICCLK, Generic Clock Waveform
T25, T34, (Rise Time) T26, T35, (Fall Time) T23, T32, (High Time) T24, T33, (Low Time) T22, (BCLK, TCK, PICCLK Period) 0.20V (CPUID 068xh) BCLK 0.5V, PICCLK 0.7V, 0.7V (CPUID 067xh) BCLK 1.25V, PICCLK 1.25V 1.25V (CPUID 067xh) 0.75V (CPUID 068xh) BCLK 2.0V, PICCLK 1.7V (CPUID 067xh) 2.0V (CPUID 068xh), 1.7V (CPUID 067xh) 0.20V (CPUID 068xh)
Figure System Valid Delay TimingCLK Valid Valid
Signal
T29, T29a, T29b (Valid Delay) T14, (Pulse Width) 1.0V AGTL+ signal group; 1.25V (CPUID 067xh) 0.75V (CPUID 068xh) APIC signal group762
Pentium® Processor SC242 1.13
Figure System Setup Hold TimingCLK Valid
Signal
(Setup Time) (Hold Time) 1.0V AGTL+ signal group; 1.25V (CPUID 067xh) 0.75V (CPUID 068xh) APIC signal group62
Figure System Reset Configuration TimingBCLK RESET# Valid (AGTL+ Input Hold Time) (AGTL+ Input Setup Time) (RESET# Pulse Width) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
Configuration (A[14:5]#, BR0#, FLUSH#, INT#)
Figure Power-On Reset Configuration TimingBCLK Vccp
PWRGOOD RESET#
GOOD Inacti (RESET# Pulse Width)
Pentium® Processor SC242 1.13
Figure Test Timings (TAP Connection)
TDI, Input Signal Output Signal
(All Non-Test Inputs Setup Time) (All Non-Test Inputs Hold Time) (TDO Float Delay) (TDI, Setup Time) (TDI, Hold TIme) (TDO Valid Delay) (All Non-Test Outputs Valid Delay) (All Non-Test Outputs Float Time) 1.25V (CPUID 067xh) 0.75V (CPUID 068xh)
Figure Test Reset TimingTRST#
(TRST# Pulse Width) 1.25V (CPUID 067xh) 0.75V (CPUID 068xh)
Pentium® Processor SC242 1.13
Signal Quality SpecificationSignals driven Pentium processor system should meet signal quality specifications ensure that components read data properly ensure that incoming signals affect long term reliability component. Specifications provided simulation measurement processor core; they should tested edge fingers. AGTL+ non-AGTL+ signal quality specifications listed this section apply Pentium processors with CPUID=068xh. recommended that these specifications used with Pentium processors with CPUID=067xh, however deviations from these guidelines must verified with specifications listed Pentium® Processor Developer's Manual (Order Number 243502).
BCLK, PICCLK, PWRGOOD Signal Quality Specifications Measurement GuidelineTable describes signal quality specifications processor core Pentium processor system clock (BCLK), APIC clock (PICCLK), PWRGOOD signals. Figure describes signal quality waveform system clock processor core pins.
Table BCLK, PICCLK, PWRGOOD Signal Quality Specifications Processor Core
Parameter Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback -0.7 Unit Figure Note
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage PICCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
Figure BCLK PICCLK Generic Clock Waveform
T6/T26
T5/T25
Pentium® Processor SC242 1.13
AGTL+ Non-AGTL+ Overshoot/Undershoot Specifications Measurement GuidelineOvershoot/Undershoot absolute value maximum voltage differential across input buffer relative termination voltage (VTT). overshoot/undershoot guideline limits transitions beyond fast signal edge rates. processor damaged repeated overshoot/undershoot events tolerant buffers charge large enough (i.e., overshoot/undershoot great enough). Determining impact overshoot/undershoot condition requires knowledge Magnitude, Pulse Duration, Activity Factor. When performing simulations determine impact overshoot/undershoot, diodes must properly characterized. protection diodes voltage clamps will provide overshoot/undershoot protection. diodes modeled within Intel provided Pentium® Processor Buffer Models clamp overshoot/undershoot will yield correct simulation results. other buffer models being used characterize Pentium processor performance, care must taken ensure that models clamp extreme voltage levels. Intel-provided Pentium® Processor Buffer Models also contains capacitance characterization. Therefore, removing diodes from buffer model will impact results yield excessive overshoot/undershoot.
3.2.1
Overshoot/Undershoot Magnitude
Overshoot/Undershoot Magnitude describes maximum potential difference between signal voltage reference level, (overshoot) (undershoot). While overshoot measured relative using probe (probe signal lead VSS), undershoot must measured relative VTT. This could accomplished simultaneously measuring plane while measuring signal undershoot. true waveform then calculated oscilloscope itself following oscilloscope date file analysis:
Converted Undershoot Waveform VTT- Signal_measured
Note: Note:
Converted Undershoot Waveform appears positive (overshoot) signal. Overshoot (rising edge) undershoot (falling edge) conditions separate their impact must determined independently. After conversion, Undershoot/Overshoot Specifications (Table through Table applied Converted Undershoot Waveform using same Magnitude Pulse Duration Specifications (Table through Table with overshoot waveform. Overshoot/undershoot magnitude levels must observe Absolute Maximum Specifications (Table through Table 22). These specifications must violated time regardless activity system state. Within these specifications threshold levels that define different allowed Pulse Durations. Provided that magnitude overshoot/undershoot within Absolute Maximum Specifications, impact Overshoot/Undershoot Magnitude determined based upon Pulse Duration Activity Factor.
Pentium® Processor SC242 1.13
3.2.2
Overshoot/Undershoot Pulse Duration
Overshoot/Undershoot Pulse duration describes total time overshoot/undershoot event exceeds Overshoot/Undershoot Reference Voltage (VOS_REF 1.635 total time could encompass several oscillations above Reference Voltage. Multiple overshoot/undershoot pulses within single overshoot/undershoot event need measured determine total Pulse Duration. Note: Oscillations below Reference Voltage subtracted from total Overshoot/ Undershoot Pulse Duration. Multiple Overshoot/Undershoot events occurring within same clock cycle must considered together event. Using worst case Overshoot/Undershoot Magnitude, together individual Pulse Durations determine total Overshoot/Undershoot Pulse Duration that total event.
Note:
3.2.3
Overshoot/Undershoot Activity Factor
Activity Factor (AF) describes frequency overshoot undershoot) occurrence relative clock. Since highest frequency assertion AGTL+ CMOS signal every other clock, indicates that specific overshoot undershoot) waveform occurs EVERY OTHER clock cycle. Thus, 0.01 indicates that specific overshoot undershoot) waveform occurs time every clock cycles. Overshoot/Undershoot Specifications (Table through Table show Maximum Pulse Duration allowed given Overshoot/Undershoot Magnitude specific Activity Factor. Each Table entry independent others, meaning that Pulse Duration reflects existence Overshoot/Undershoot Events that Magnitude ONLY. platform with overshoot/undershoot that just meets Pulse Duration specific Magnitude where means that there other Overshoot/Undershoot events, even lesser Magnitude (note that then event occurs times other events occur). Note: Overshoot (rising edge) undershoot (falling edge) conditions separate their impact must determined independently. Activity factor AGTL+ signals referenced BCLK frequency. Activity factor CMOS signals referenced PICCLK frequency.
Note: Note:
Pentium® Processor SC242 1.13
3.2.4
Reading Overshoot/Undershoot Specification TableThe overshoot/undershoot specification Pentium processor simple single value. Instead, many factors needed determine what over/undershoot specification addition magnitude overshoot, following parameters must also known: width overshoot measured above 1.635 Activity Factor (AF). determine allowed overshoot particular overshoot event, must following: Determine signal group that particular signal falls into. signal AGTL+ signal operating with system bus, Table signal AGTL+ signal operating with system bus, Table signal CMOS signal, Table Determine Magnitude overshoot (relative VSS). Determine Activity Factor (how often does this overshoot occur?). From appropriate Specification table, read Maximum Pulse Duration allowed. Compare specified Maximum Pulse Duration signal being measured. Pulse Duration measured less than Pulse Duration shown table, then signal meets specifications. above procedure similar undershoots after undershoot waveform been converted look like overshoot. Undershoot events must analyzed separately from Overshoot events they mutually exclusive. Below example showing maximum pulse duration determined given waveform relates measured value: Platform Information:
Signal Group AGTL+ Overshoot Magnitude (measured) Pulse Duration (measured) Activity Factor (measured)
Corresponding Maximum Pulse Duration Specification Given above parameters using table column), maximum allowed pulse duration Since measured pulse duration this particular overshoot event passes overshoot specifications, although this doesn't guarantee that combined overshoot/ undershoot events meet specifications.
Pentium® Processor SC242 1.13
3.2.5
Determining System meets Overshoot/Undershoot SpecificationThe overshoot/undershoot specifications (Table through Table specify allowable overshoot/undershoot single overshoot/undershoot event. However, most systems will have multiple overshoot and/or undershoot events that each have their parameters (magnitude, duration, AF). While each overshoot meet overshoot specification, when total impact overshoot events, system exceed specifications. guideline ensure system passes overshoot undershoot specifications shown below. Ensure signal (AGTL+ non-AGTL+) ever exceeds 1.635 only overshoot/undershoot event magnitude occurs, ensure meets over/undershoot specifications following tables. This means that whenever over/undershoot event occurs, always over/undershoots same level. multiple overshoots and/or multiple undershoots occur, measure worst case pulse duration each magnitude compare results against specifications (note: multiple overshoot/undershoot events within clock cycle must have their pulse durations summed together determine total pulse duration). these worst case overshoot undershoot events meet specifications (measured time specifications) table where then system passes.
Table AGTL+ Signal Group Overshoot/Undershoot Tolerance
Overshoot/Undershoot Magnitude 2.25 2.15 2.05 Maximum Pulse Duration Unit 0.01 2.53 4.93 16.6 0.25 0.49 0.91 1.67 Figure
NOTES: BCLK period These values specified processor core pins. Overshoot/Undershoot Magnitude absolute value should never exceeded. Overshoot measured relative VSS, while undershoot measured relative VTT. Overshoot/Undershoot Pulse Duration measured relative 1.635
Pentium® Processor SC242 1.13
Table AGTL+ Signal Group Overshoot/Undershoot Tolerance
Overshoot/Undershoot Magnitude 2.25 2.15 2.05 Maximum Pulse Duration Unit 0.01 12.5 0.19 0.37 0.68 1.25 2.28
Figure
NOTES: BCLK period These values specified processor core pins. Overshoot/Undershoot Magnitude absolute value should never exceeded. Overshoot measured relative VSS, while undershoot measured relative VTT. Overshoot/Undershoot Pulse Duration measured relative 1.635
Table Non-AGTL+ Signal Group Overshoot/Undershoot Tolerance
Overshoot/Undershoot Magnitude 2.25 2.15 2.05 Maximum Pulse Duration Unit 0.01 14.8 27.2 0.76 1.48 16.4 Figure
NOTES: PICCLK period This table applies tolerant non-AGTL+ signals. BCLK, PICCLK, PWRGOOD only nonAGTL+ signals that tolerant processor core pins. These values specified processor core pins. Overshoot/Undershoot Magnitude absolute value should never exceeded. Overshoot measured relative VSS, while undershoot measured relative VTT. Overshoot/Undershoot Pulse Duration measured relative 1.635
Pentium® Processor SC242 1.13
Figure Maximum Acceptable AGTL+ Non-AGTL+ Overshoot/Undershoot Waveform
Time Dependent Overshoot 2.3V 2.2V 2.1V 2.0V 1.635V Converted Undershoot Waveform
Overshoot Magnitude
Undershoot Magnitude
Overshoot Signal Magnitude Undershoot Magnitude Signal
Time Dependent Undershoot
AGTL+ Non-AGTL+ Ringback Specifications Measurement GuidelineRingback refers amount reflection seen after signal switched. ringback specification voltage that signal rings back after achieving maximum absolute value. (See Figure illustration ringback.) Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input each receiving agent. Violations signal ringback specification allowed under circumstances both AGTL+ non-AGTL+ signals. When performing simulations determine impact ringback, diodes must properly characterized. Intel provided Pentium Processor Buffer Models contain capacitance characterization. Therefore, removing diodes from buffer model will impact results yield incorrect ringback. other buffer models being used characterize Pentium processor performance, care must taken ensure that models account capacitance. Table signal ringback specifications both AGTL+ non-AGTL+ signals simulations processor core.
Pentium® Processor SC242 1.13
Table Signal Ringback Specifications Signal Simulation
Input Signal Group AGTL+ AGTL+ Non-AGTL+ Signals Non-AGTL+ Signals PWRGOOD Transition
Maximum Ringback (with Input Diodes Present) VREF 0.200 VREF 0.200 2.00
Unit
Figure
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies cache sizes. Non-AGTL+ signals except PWRGOOD.
There three signal quality parameters defined both AGTL+ non-AGTL+ signals: overshoot/undershoot, ringback, settling limit. three signal quality parameters shown Table AGTL+ non-AGTL+ signal group. Table AGTL+ Non-AGTL+ Signal Groups Ringback Tolerance SpecificationT# Parameter Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Squarewave Ringback 0.50 -200 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Pentium® processor frequencies cache sizes. These values specified processor core pins. Specifications edge rate V/ns. Figure generic waveform. Please Table maximum allowable overshoot. Ringback between VREF VREF VREF -200 VREF requires flight time measurements adjusted described AGTL+ Specification (Pentium® Developers Manual). Ringback below VREF 100mV above VREF supported. Intel recommends simulations exceed ringback value VREF allow margin other sources system noise. negative value indicates that amplitude ringback above VREF. (i.e., -100 specifies signal cannot ringback below VREF mV). measured relative VREF. measured relative VREF
Pentium® Processor SC242 1.13
Figure High AGTL+ Non-AGTL+ Receiver Ringback Tolerance
start Clock
0.7V
Time Note: High case analogou
Figure Signal Overshoot/Undershoot, Settling Limit, Ringback
Overshoot Settling Limit
Rising-Edge Ringback
Falling-Edge Ringback
Settling Limit
Time
Undershoot
000767
3.3.1
Settling Limit Guideline
Settling limit defines maximum amount ringing receiving that signal must reach before next transition. amount allowed percent total signal swing (VHI VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again. Signals that within their settling limit before transitioning risk unwanted oscillations which could jeopardize signal integrity. Simulations verify settling limit done either with without input protection diodes present. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
Pentium® Processor SC242 1.13
Thermal Specifications Design ConsiderationLimited quantities Pentium processors utilize S.E.C.C. package technology. This technology uses extended thermal plate heatsink attachment. extended thermal plate interface intended provide accessibility multiple types thermal solutions. majority SC242based Pentium processors S.E.C.C.2 packaging technology. S.E.C.C.2 package technology does incorporate extended thermal plate. This chapter provides needed data designing thermal solution. However, correct thermal measuring processes please refer AP-905, Pentium® Processor Thermal Design Guidelines (Order Number 245087). Figure provides 3-dimensional view S.E.C.C. package. This figure illustrates thermal plate location. Figure provides substrate view S.E.C.C.2 package.
Figure S.E.C.Cartridge 3-Dimensional View
Left Latch
Cover
Right Latch
Extended Thermal Plate
Pentium® Processor SC242 1.13
Figure S.E.C.Cartridge Substrate View
OLGA Package
Cache (CPUID 067xh Only
Substrate View
Thermal SpecificationTable Table provide thermal design power dissipation maximum minimum temperatures Pentium processors with S.E.C.C. S.E.C.C.2 package technologies respectively. While processor core dissipates majority thermal power, thermal power dissipated cache also impacts overall processor power specification. This total thermal power referred processor power following specifications. Systems should design highest possible processor power, even processor with lower thermal dissipation planned.
Table Thermal Specifications S.E.C.C. Packaged ProcessorProcessor Core Frequency (MHz) Cache Size (KBs) Processor Power 25.3 28.0 Extended Thermal Plate Power 25.5 28.2 TPLATE (°C)
TPLATE (°C)
TCOVER (°C)
TCOVER (°C)
NOTES: These values specified nominal VCCCORE processor core nominal VCCL2/VCC3.3 cache applicable). Processor power includes power dissipated processor core, cache, AGTL termination. maximum power each these components does occur simultaneously. Extended Thermal Plate power processor power that dissipated through extended thermal plate.
Pentium® Processor SC242 1.13
Table Thermal Specifications S.E.C.C.2 Packaged Processors
Proc. Core Freq. (MHz) Cache Size (Kbytes) Thermal Design Power Cache Power Power Density4 (W/cm2) CPUID 0683h 21.65 23.95 25.45 19.36 26.35 20.06 29.55 29.55 21.86 21.86 23.46 24.16 25.26 26.36 26.96 28.76 28.76 31.06 31.56 35.16 45.56 35.96 35.96 Power Density4 (W/cm2) CPUID 0686h6 22.0 22.8 24.8 24.8 26.7 27.5 28.7 30.0 30.6 32.6 32.6 35.2 35.9 39.9 40.9 40.9 55.5 TJUNCTION (°C) TJUNCTION Offset3 (°C) Cache TCASE (°C) Cache TCASE (°C) TCOVER (°C) TCOVER (°C)
533B 533EB 550E 600B 600E 600EB 800EB GHz8 1.0B 1.13GHz
25.3 28.0 29.7 14.0 30.8 14.5 34.5 34.5 15.8 15.8 17.0 17.5 18.3 19.1 19.5 20.8 20.8 22.5 22.9 25.5 26.1 26.1 35.5
1.26 1.33 1.37 1.37 1.60 1.60
2.07 2.17 2.37 2.37 2.57 2.57 2.77 2.87 2.87 3.07 3.07 3.37 3.37 4.77,8 3.87 3.87 5.27
NOTES: These values specified nominal VCCCORE processor core nominal VCCL2/VCC3.3 cache applicable). Thermal Design Power (TDP) represents maximum amount power thermal solution required dissipate. thermal solution should designed dissipate without exceeding maximum Tjunction specification. does represent power delivery voltage regulation requirements processor. TJUNCTIONOFFSET worst-case difference between thermal reading from on-die thermal diode hottest location processor's core. Power density maximum power processor dissipate (i.e. processor power) divided area over which power generated. Power these processors generated over entire processor (see Figure processor dimensions). Power these processors generated over core area (see Figure processor core area dimensions). Thermal solution designs should compensate this smaller heat flux area (core) assume that power uniformly distributed across entire area (core cache). TJUNCTION offset values include thermal diode measurement error. Diode measurement error must added TJUNCTION offset value from table, outlined Intel® Pentium® processor Thermal Metrology CPUID-068h Family Processors. Intel characterized Analog Devices AD1021 diode measurement found measurement error This specification applies Pentium® processor with CPUID=0683h operating GHz. These values estimates based preliminary simulation.
Pentium® Processor SC242 1.13
Figure Processor Functional Layout (CPUID 0686h) 0.337" 0.275" Area 0.90 Cache Area 0.26 Core Area 0.64 0.146" 0.414" Cache Area 0.04 Core Area 0.10 Area 0.14
Figure Processor Functional Layout CPUID 0683h) 0.362" 0.292" Area 1.05 Cache Area 0.32 Core Area 0.73 0.170" 0.448" Cache Area 0.05 Core Area 0.11 Area 0.16
S.E.C.C. packaged processors, extended thermal plate attach location thermal solutions. maximum minimum extended thermal plate temperatures specified Table S.E.C.C.2 packaged processors, thermal solutions attach processor connecting through substrate cover. maximum minimum temperatures pertinent locations specified Table thermal solution should designed ensure temperature specified locations never exceeds these temperatures. total processor power result heat dissipated processor core cache. overall system chassis thermal design must comprehend entire processor power. S.E.C.C. packaged processors, extended thermal plate power component this power, primarily composed processor core cache dissipating heat through extended thermal plate. heatsink need only designed dissipate extended thermal plate power. Table current Pentium processor S.E.C.C. thermal design specifications. extended thermal plate exists S.E.C.C.2 packaged processors, thermal solutions have attach directly processor core package. total processor power dissipated S.E.C.C.2 processor combination heat dissipated both processor core cache. Pentium processors that "Discrete" cache have separate TCASE specification (Table surface mounted BSRAM components substrate. JUNCTION encompasses cache processors that utilize "Advanced Transfer Cache", therefore separate cache measurement required. Specifics measure these specifications outlined AP-905, Pentium® Processor Thermal Design Guidelines (Order Number 245087).
Pentium® Processor SC242 1.13
4.1.1
Thermal Diode
Pentium processor incorporates on-die diode that used monitor temperature (junction temperature). thermal sensor located baseboard, stand-alone measurement kit, monitor temperature Pentium processor thermal management instrumentation purposes. Table Table provide diode parameter interface specifications.
Table Thermal Diode Parameters1
Symbol Iforward bias n_ideality 1.0000 1.0057 1.0065 1.0080 1.0173 1.0125 Unit Note
NOTES: Intel does support recommend operation thermal diode under reverse bias. room temperature with forward bias n_ideality diode ideality factor parameter, represented diode equation: I=Io(e (Vd*q)/(nkT) This specification applies Pentium® processor with CPUID=067xh. This specification applies Pentium® processor with CPUID=068xh.
Table Thermal Diode Interface
Name THERMDP THERMDN Connector Signal Description diode anode (p_junction) diode cathode (n_junction)
Pentium® Processor SC242 1.13
S.E.C.C. S.E.C.C.2 Mechanical SpecificationIntel® Pentium® processors either S.E.C.C. S.E.C.C.2 package technology. Both package types contain processor core, cache, other passive components. cartridges connect baseboard through edge connector. Mechanical specifications processor given this section. Section 1.1.1 complete terminology listing.
S.E.C.C. Mechanical SpecificationS.E.C.C. package drawings dimension details provided Figure through Figure Figure shows multiple views Pentium processor S.E.C.C. package; Figure through Figure show package dimensions; Figure Figure show extended thermal plate dimensions; Figure Figure provide details processor substrate edge finger contacts. Figure Table contain processor marking information. Section S.E.C.C.2 mechanical specifications. processor edge connector defined this document referred "SC242 connector." Slot Connector Specification (Order Number 243397) further details SC242 connector. Note: Figure through Figure following apply: Unless otherwise specified, following drawings dimensioned inches. dimensions provided with tolerances guaranteed normal production product. Figures drawings labeled "Reference Dimensions" provided informational purposes only. Reference Dimensions extracted from mechanical design database nominal dimensions with tolerance information applied. Reference Dimensions checked part processor manufacturing. Unless noted such, dimensions parentheses without tolerances Reference Dimensions. Drawings scale.
Figure S.E.C.C. Packaged Processor Multiple View
View Left Latch Cover Right Latch Thermal Plate
Left
Cover Side view
Right
Right Side
Right
Thermal Plate Side View
Left
v006a.vsd
Pentium® Processor SC242 1.13
Figure S.E.C.C. Packaged Processor Extended Thermal Plate Side Dimension3.805±.020
(0.750)
2.473±.016 2.070±.020 1.235±.020
(1.500)
.125±.005
.342±.005 These dimensions from bottom substrate edge fingers .365±.005 1.745±.005 1.877±.020
Figure S.E.C.C. Packaged Processor Bottom View Dimension5.255±.006 Cover
Thermal Plate 2.181±.015 5.341±.010 5.505±.010 3.243±.015
Pentium® Processor SC242 1.13
Figure S.E.C.C. Packaged Processor Latch Arm, Extended Thermal Plate Lug, Cover Dimension2X 0.238
2X0.103 0.103 0.005 ±0.005
0.174 ±0.005
0.488 ±0.020
0.647 ±0.020
0.058 ±0.005 0.253
0.136 ±0.005
Left
±0.005
0.136
001056a
Pentium® Processor SC242 1.13
Figure S.E.C.C. Packaged Processor Latch Arm, Extended Thermal Plate, Cover Detail Dimensions (Reference Dimensions Only)
0.075
0.236 0.122
0.113
0.084
Detail
Detail (Bottom Side View)
0.120 Min. 0.316 0.116 0.082 0.216 0.291 0.276
Detail
Detail
Detail
001057a
Note: dimensions without tolerance information considered reference dimensions only
Pentium® Processor SC242 1.13
Figure S.E.C.C. Packaged Processor Extended Thermal Plate Attachment Detail DimensionSee Detail 0.0625 ±0.002 +0.001 -0.002
0.124
Detail
0.365 ±0.005
0.978 ±0.008
0.500 ±0.008
0.250 ±0.008
0.375 ±0.008
0.000
0.000
2.110 ±0.008
Pentium® Processor SC242 1.13
Figure S.E.C.C. Packaged Processor Extended Thermal Plate Attachment Detail Dimensions, Continued
0.0032 1.000 1.000
1.250 2.500
v008
Figure S.E.C.C. Packaged Processor Substrate Edge Finger Contact DimensionThermal Plate
Cover
Substrate 2.835 2.992 ±.008 5.000 NOTE: dimensions without tolerance information considered reference dimensions only. 2.01 ±.008 Detail Next Figure 1.85 A121 .045
.062
+.007 -.005
007.vsd
Pentium® Processor SC242 1.13
Figure S.E.C.C. Packaged Processor Substrate Edge Finger Contact Dimensions, Detail
.098 .098
.010 .008 .360 .045 .138 ±.005 .039 .037 .074 ±.002 0.16 ±.002 .008 .002 .236
0.043 ±.002 .008 .002 NOTE:
Figure Intel Pentium Processor Markings (S.E.C.C. Packaged Processor)
dimensions without tolerance information considered reference dimensions only. reference datum shown Figure
note
Pentium
Hologram Loation
Note: Please refer Intel Pentium Processor Specification Update this information
Pentium® Processor SC242 1.13
Table Description Table Processor Markings (S.E.C.C. Packaged Processor)
Code Letter Logo Trademark Logo Product Name Dynamic Mark Area with matrix Description
S.E.C.C.2 Mechanical Specification
S.E.C.C.2 drawings dimension details provided Figure through Figure Figure shows multiple views Pentium processor S.E.C.C.2 package; Figure through Figure show S.E.C.C.2 package dimensions; Figure Figure provide dimensions processor substrate edge finger contacts; Figure shows heatsink solution keep-in zone; Figure shows multiple views S.E.C.C.2 packaged processor keep-out zone; Figure Table contain processor marking information. Section S.E.C.C. Mechanical Specifications.
Figure S.E.C.C.2 Packaged Processor Multiple View
View Cover OLGA Package
Pentium®
Cache (CPUID 067xh Only
Cover Side View
Right Side View
Substrate View
Pentium® Processor SC242 1.13
Figure S.E.C.C.2 Packaged Processor Assembly Primary View
Cache (CPUID 067xh Only
CPUID 067xh CPUID 068xh
0.725 ±0.13 0.685 ±0.13
0.954 ±0.13 0.954 ±0.13
Figure S.E.C.C.2 Packaged Processor Assembly Cover View with DimensionOLGA +.015 CPUID 067xh .021PLGA -.012 +.015 OLGA CPUID 068xh .017 -.012 4.918 ±0.006
1.849 ±0.010 2.440 ±0.005
0.615 ±0.013 1.546 ±0.013 5.000 ±0.016
Pentium® Processor SC242 1.13
Figure S.E.C.C.2 Packaged Processor Assembly Heat Sink Attach Boss Section
0.112 ±0.001 0.005 0.025 ±0.001 Substrate
0.100 0.062 +0.007 -0.005 0.283 0.020 ±0.010 0.154
5.0° Cover Dimensions inches 82.0°
Figure S.E.C.C.2 Packaged Processor Assembly Side View
OLGA CPUID 067xh 0.094" ±0.005" CPUID 068xh 0.090" ±0.005" Core Package
TQFP Package (067xh) 0.129 ±0.025
0.061 ±0.005
0.365 ±0.025
Dimensions inche2
Figure
Figure Detail View Cover Vicinity Substrate Attach Feature0.075 -Z0.280 0.340
Dimensions inche
Pentium® Processor SC242 1.13
Figure S.E.C.C.2 Packaged Processor Substrate Edge Finger Contact DimensionKeep Zone (Front Side View)
+.007 .062 -.005
.045
Figure S.E.C.C.2 Packaged Processor Substrate Edge Finger Contact Dimensions (Detail
.010 .008 .360 .045 .138 ±.005 .039 .037 .074 ±.002 0.16 ±.002 .008 .002 .236
0.043 ±.002 .008 .002 NOTE:
dimensions without tolerance information considered reference dimensions only. reference datum shown Figure
Pentium® Processor SC242 1.13
Figure S.E.C.C.2 Packaged Processor Substrate (CPUID 067xh) Keep Zone
NON-KEEPOUT AREA
.448 .0275 NON-KEEPOUT AREA
.405
Figure S.E.C.C.2 Packaged Processor Substrate (CPUID 068xh) Keep ZonePRIMARY SIDE
NON-KEEPOUT AREA
.632 .363
.0275 NON-KEEPOUT AREA
0.448 .440
Pentium® Processor SC242 1.13
Figure S.E.C.C.2 Packaged Processor Substrate (CPUID 067xh) Keep-Out Zone
Keep Zone (Bottom Side View)
Figure S.E.C.C.2 Packaged Processor Substrate (CPUID 068xh) Keep-Out Zone
Keep Zone (Front Side View)
.362 .363
.448
.440
Keep Zone (Bottom Side View)
Pentium® Processor SC242 1.13
Figure Intel® Pentium® Processor Markings (S.E.C.C.2 Package)
"""" """"" """"" """" """"" """"" """"" """"""
NOTE: Please refer Pentium Processor Specification Update this information.
Table Description Table Processor Markings (S.E.C.C.2 Packaged Processor)
Code Letter Logo Trademark Logo Dynamic Mark Area with matrix Description
S.E.C.C.2 Structural Mechanical Specification
intention structural specification S.E.C.C.2 ensure that package will exposed excessive stresses that could adversely affect device reliability. Figure illustrates deflection specification deflections away from heatsink. Figure illustrates deflection specification direction heatsink. heatsink attach solution must induce permanent stress into S.E.C.C.2 substrate with exception uniform load maintain heatsink processor thermal interface. Figure Table define pressure specification.
Figure Substrate Deflection Away From Heat Sink
Processor Substrate
cycles maximum
0.025
Pentium® Processor SC242 1.13
Figure Substrate Deflection Toward Heatsink
.160 max. deflection 0.050 seconds maximum cycles maximum F/2Processor ubstrate
Figure S.E.C.C.2 Packaged Processor SpecificationF
.080 max. defle seconds maxim cycles maximum
Table S.E.C.C.2 Pressure SpecificationParameter Static Compressive Force Transient Compressive Force Maximum Unit Figure Note
NOTES: This maximum static force that applied heatsink maintain heatsink processor interface. This specification applies uniform load. This specification applies nonuniform load.
Pentium® Processor SC242 1.13
Processor Package Materials Information
Both S.E.C.C. S.E.C.C.2 processor packages comprised multiple pieces make complete assembly. This section provides weight each piece entire package. Table Table contain piece-part information S.E.C.C. S.E.C.C.2 processor packages, respectively.
Table S.E.C.C. MaterialS.E.C.C. Piece Extended Thermal Plate Latch Arms Cover Total Pentium Processor
Piece Material Aluminum 6063-T6 Lexan 940-V0, glass filled Lexan 940-V0
Maximum Piece Weight (Grams) 84.0 Less than latch 24.0 112.0
Table S.E.C.C.2 MaterialS.E.C.C.2 Piece Cover Total Pentium® Processor Piece Material Lexan 940-V0 Maximum Piece Weight (Grams) 18.0 54.0
Intel® Pentium® Processor Signal Listing
Table Table provide processor edge finger signal definitions. signal locations SC242 edge connector used signal routing, simulation, component placement baseboard. Table Pentium processor substrate edge finger listing order number.
Table Signal Listing Order Number (Sheet
Name IERR# A20M# FERR# IGNNE# PWRGOOD TESTHI BSEL1 Signal Group Power/Other Power/Other Power/Other CMOS Output CMOS Input Power/Other CMOS Output CMOS Input Input Power/Other Output CMOS Input Power/Other Power/Other Name FLUSH# SMI# INIT# STPCLK# SLP# TRST# Reserved VCCCORE THERMDP Signal Group Power/Other CMOS Input CMOS Input CMOS Input Power/Other CMOS Input Input CMOS Input Power/Other Input Input Power/Other Power/Other Power/Other
Pentium® Processor SC242 1.13
Table Signal Listing Order Number (Sheet
Name THERMTRIP# Reserved LINT0/INTR PICD0 PREQ# BP3# BPM0# BINIT# DEP0# DEP1# DEP3# DEP5# DEP6# D61# D55# D60# D53# D57# D46# D49# D51# D42# D45# D39# Reserved D43# D37# D33# D35# Signal Group CMOS Output Power/Other CMOS Input Power/Other APIC CMOS Input AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other Power/Other AGTL+I/O AGTL+ Power/Other AGTL+ AGTL+ Name THERMDN LINT1/NMI CCCORE PICCLK BP2# Reserved BSEL0 PICD1 PRDY# BPM1# VCCCORE DEP2# DEP4# DEP7# VCCCORE D62# D58# D63# VCCCORE D56# D50# D54# VCCCORE D59# D48# D52# D41# D47# D44# VCCCORE D36# D40# D34# VCCCORE D38# D32# D28# Signal Group Power/Other CMOS Input Power/Other APIC Clock AGTL+ Power/Other Power/Other APIC AGTL+ Output AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+
Pentium® Processor SC242 1.13
Table Signal Listing Order Number (Sheet
Name D31# D30# D27# D24# D23# D21# D16# D13# D11# D10# D14# BCLK BR0# BERR# A33# A34# A30# A31# A27# A22# A23# Reserved A19# Signal Group AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other System AGTL+I/O AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ Power/Other AGTL+ Power/Other Name VCCCORE D29# D26# D25# VCCCORE D22# D19# D18# D20# D17# D15# VCCCORE D12# VCCCORE VCCCORE RESET# BR1# Reserved VCCCORE A35# A32# A29# A26# A24# A28# VCCCORE A20# A21# A25# VCCCORE A15# Signal Group Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ Input AGTL+ Input Power/Other. Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+
Pentium® Processor SC242 1.13
Table Signal Listing Order Number (Sheet
A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121 Name A18# A16# A13# A14# A10# BNR# BPRI# TRDY# DEFER# REQ2# REQ3# HITM# DBSY# RS1# Reserved ADS# Reserved AP0# VID2 VID1 VID4 Signal Group AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ Input AGTL+ Input AGTL+ Input Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ Input Power/Other Power/Other AGTL+ Power/Other AGTL+ Power/Other Power/Other Power/Other Power/Other B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 Name A17# A11# VCCCORE A12# VCCCORE SLOTOCC# REQ0# REQ1# REQ4# VCCCORE LOCK# DRDY# RS0# VCC5 HIT# RS2# Reserved VCCL2/VCC3.3 RSP# AP1# VCCL2/VCC3.3 AERR# VID3 VID0 VCCL2/VCC3.3 Signal Group AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ Power/Other Power/Other AGTL+ AGTL+ AGTL+ Power/Other AGTL+ AGTL+ AGTL+ Input Power/Other AGTL+ AGTL+ Input Power/Other Power/Other AGTL+ AGTL+ Input AGTL+ Power/Other AGTL+ Power/Other Power/Other Power/Other
Table Pentium processor substrate edge connector listing order signal name.
Pentium® Processor SC242 1.13
Table Signal Listing Order Signal Name (Sheet
A100 A115 B118 A117 Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADS# AERR# AP0# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ CMOS Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
Table Signal Listing Order Signal Name (Sheet
B116 A101 A103 Name AP1# BCLK BERR# BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BR1# BSEL0 BSEL1 D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# Signal Group AGTL+ System AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Input AGTL+I/O AGTL+ Input Power/Other Power/Other AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
Pentium® Processor SC242 1.13
Table Signal Listing Order Signal Name (Sheet
Name D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+I/O AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
Table Signal Listing Order Signal Name (Sheet
A111 A105 B107 B100 Name D60# D61# D62# D63# DBSY# DEFER# DEP0# DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# DRDY# FERR# FLUSH# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other Power/Other CMOS Output CMOS Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Pentium® Processor SC242 1.13
Table Signal Listing Order Signal Name (Sheet
A102 A106 A110 A114 A118 B110 A109 B106 B102 B103 A107 A108 B104 A113 Name HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# PICCLK PICD0 PICD1 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input AGTL+ APIC Clock APIC APIC AGTL+ Output CMOS Input CMOS Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power/Other Power/Other Power/Other Power/Other
Table Signal Listing Order Signal Name (Sheet
A116 B112 B114 B108 A112 B111 B115 B101 A104 B109 Name Reserved Reserved Reserved Reserved Reserved RESET# RS0# RS1# RS2# RSP# SLOTOCC# SLP# SMI# STPCLK# TESTHI THERMDN THERMDP THERMTRIP# TRDY# TRST# VCC5 VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE Signal Group Power/Other Power/Other Power/Other Power/Other. Power/Other AGTL+ Input AGTL+ AGTL+ Input AGTL+ Input AGTL+ Input AGTL+ Input Power/Other CMOS Input CMOS Input CMOS Input Input Input Output Power/Other Power/Other Power/Other CMOS Output Input AGTL+ Input Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Pentium® Processor SC242 1.13
Table Signal Listing Order Signal Name (Sheet
B105 B113 B117 Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCL2 VCCL2 Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Signal Listing Order Signal Name (Sheet
B121 B120 A120 A119 B119 A121 Name VCCL2 VID0 VID1 VID2 VID3 VID4 Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Pentium® Processor SC242 1.13
Intel® Pentium® Processor Core Substrate AssignmentThese test points closest locations processor core should used validate processor core timings signal quality back S.E.C.C. S.E.C.C.2 package. Please SECC Disassembly Process Application Note instructions removing cover SECC package.
5.6.1
Processor Core Assignments (CPUID 067xh)
Figure shows locations back processor substrate.
Figure Processor Core Assignment1
proc_core_pad_via
5.6.2
Processor Core Signal Assignments (CPUID 067xh)
Table Table shows signal signal assignments, respectively.
Pentium® Processor SC242 1.13
Table Listing Order Signal Name (Sheet
Signal Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADS# AERR# AP0# AP1# Locations
Table
Listing Order Signal Name (Sheet
Locations
Signal Name BCLK BERR# BINT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BR1# BSEL0 BSEL1 D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24#
Pentium® Processor SC242 1.13
Table Listing Order Signal Name (Sheet
Signal Name D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# Locations
Table
Listing Order Signal Name (Sheet
Locations
Signal Name D63# DBSY# DEFER# DEP0# DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# DRDY# FERR# FLUSH# HIT# HITM# IERR# IGNNE# INIT# LINT[0] LINT[1] LOCK# PICCLK PICD[0] PICD[1] PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESET# RS0# RS1# RS2#
Pentium® Processor SC242 1.13
Table
Listing Order Signal Name (Sheet
Locations
Table
Listing Order Signal Name (Sheet
Locations
Signal Name RSP# SLP# SMI# STPCLK# THERMTRIP# THRMDN THRMDP TRDY# TRST# VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE
Signal Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE
Pentium® Processor SC242 1.13
Table Listing Order Signal Name (Sheet
Signal Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE Locations
Table
Listing Order Signal Name (Sheet
Locations
Signal Name
Pentium® Processor SC242 1.13
Table
Listing Order Signal Name (Sheet
Locations
Table
Listing Order Signal Name (Sheet
Locations
Signal Name
Signal Name
Pentium® Processor SC242 1.13
Table Listing Order Location (Sheet
Locations Signal Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE PICCLK BPM0# DEP6# D55# D57# D49# VCCCORE VCCCORE BP2# DEP2# D56# D53# D42# D41# VCCCORE PICD[0] PRDY# DEP1# D63# D62# D51# D46#
Table
Listing Order Location (Sheet
Signal Name D45# D52# D40# VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE LINT[1] PREQ# BPM1# DEP4# D58# D59# D54# D48# D47# D39# D34# VCCCORE LINT[0] DEP7# D61# D37# D36# D44# VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE
Locations
Pentium® Processor SC242 1.13
Table
Listing Order Location (Sheet
Signal Name BP3# BINT# DEP3# D60#
Other recent searches
SLD432S - SLD432S SLD432S Datasheet
SAA7182A - SAA7182A SAA7182A Datasheet
SAA7183A - SAA7183A SAA7183A Datasheet
MS-21423 - MS-21423 MS-21423 Datasheet
MC74VHC1G03 - MC74VHC1G03 MC74VHC1G03 Datasheet
LT1109 - LT1109 LT1109 Datasheet
APM4358KP - APM4358KP APM4358KP Datasheet
2SB0788 - 2SB0788 2SB0788 Datasheet
2SB788 - 2SB788 2SB788 Datasheet
2SD0958 - 2SD0958 2SD0958 Datasheet
2SD958 - 2SD958 2SD958 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
