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CK97 Clock Synthesizer Design Guidelines
June 1998 Order Number: 243867-001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® Xeonprocessor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com Copyright Intel Corporation 1998. Third-party brands names property their respective owners.
CK97 Clock Synthesizer Design Guidelines
July 1998
Table Contents
Introduction Clock Synthesizer Overview.2 Audio Codec (AC97) support.2 Applicable Documents Drive Specification.3 Electrical Requirements.4 Specifications (Clock Driver) Buffer Specifications: Volt, Volt Clocks.8 2.2.1 TYPE (2.5V) Buffer Characteristics 2.2.2 TYPE IOAPIC (2.5V) Buffer Characteristics.10 2.2.3 TYPE 3.3V 48Mhz, Buffer Characteristics 2.2.4 TYPE SDRAM (3.3 Clock Buffer Characteristics.14 2.2.5 TYPE Clock Buffer Characteristics.16 2.2.6 Vendor Provided Specifications Timing Timing Requirements.20 Frequency Accuracy Frequency Accuracy 48Mhz outputs. Multiple Jitter Tracking Specification.22 Test Measurement System Considerations Obtain Reference Material.31 Reference IBIS Reference Audio Codec (AC97) Reference Considerations Appendices Appendix CK100 SSOP Pinouts.35 8.1.1 Spread Spectrum Clocking (SSC) Clarification:.38 8.1.2 CK100 System Considerations: 8.1.3 CK100 Power Management Appendix CKBF SSOP Pinouts 8.2.1 CKBF Default Conditions 8.2.2 CKBF Serial Configuration CKBF Power Management
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CK97 Clock Synthesizer Design Guidelines
Appendix CK100-SM Pinout Mobile Buffer Characteristic CK100-SM SSOP Pinout 8.5.1 Features SSOP Package):.54 8.5.2 Mobile Clock Buffer Specifications: Volt, Volt Clocks.57 8.5.3 Type Mobile (2.5V) Buffer Characteristics.58 8.5.4 Type Mobile SDRAM (3.3 Clock Buffer Characteristics.60 Appendix SSOP Package Data.62
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CK97 Clock Synthesizer Design Guidelines
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List Figures
FIGURE TYPE CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS FIGURE TYPE CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS. FIGURE TYPE IOAPIC CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS FIGURE TYPE IOAPIC CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS FIGURE TYPE 48MHZ, CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS. FIGURE TYPE 48MHZ, CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS FIGURE TYPE SDRAM CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS FIGURE TYPE SDRAM CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS FIGURE TYPE CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS FIGURE 2-10 TYPE CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS FIGURE HOST HOST SKEW FIGURE HOST OFFSET. FIGURE CK100 CLOCK WAVEFORMS. FIGURE 4-2A CKBF CLOCK WAVEFORMS. FIGURE 4-3B COMPONENT VERSUS SYSTEM MEASURE POINTS FIGURE STANDARD CLOCK LAYOUT TOPOLOGIES FIGURE OVERSHOOT UNDERSHOOT FIGURE TRIANGULAR FREQUENCY MODULATION PROFILE. FIGURE SPECTRAL FUNDAMENTAL FREQUENCY COMPARISON FIGURE DOWNSTREAM TRACKING SKEW MODULATION FREQUENCY FIGURE CK100 CPU_STOP# TIMING DIAGRAM FIGURE CK100 PCI_STOP# TIMING DIAGRAM FIGURE CK100 PWR_DWN# TIMING DIAGRAM. FIGURE TYPE MOBILE CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS. FIGURE TYPE MOBILE CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS FIGURE TYPE MOBILE SDRAM CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS FIGURE 8-10 TYPE MOBILE SDRAM CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS
List Tables
TABLE ABSOLUTE MAXIMUM POWER SUPPLY TABLE ABSOLUTE MAXIMUM TABLE OPERATING REQUIREMENTS. TABLE TYPE CLOCK BUFFER OPERATING REQUIREMENTS TABLE IOAPIC CLOCK BUFFER OPERATING REQUIREMENTS. TABLE 3.3V CLOCK OPERATING REQUIREMENTS. TABLE SDRAM CLOCK OPERATING REQUIREMENTS TABLE CLOCK OPERATING REQUIREMENTS TABLE HOST TIMING REQUIREMENTS TABLE 3-2A MAIN MEMORY TIMING REQUIREMENTS TABLE MINIMUM MAXIMUM EXPECTED CAPACITIVE LOADS TABLE LAYOUT DIMENSIONS TABLE BOARD LEVEL SIMULATION CONDITIONS TABLE TYPICAL CHARACTERISTICS CLOCK DESTINATION TABLE SIGNAL QUALITY REQUIREMENTS DESTINATION. TABLE CK100 DESCRIPTION TABLE TABLE MAXIMUM ALLOWED SPREAD AMOUNT TABLE DESIRED PEAK AMPLITUDE REDUCTION SSC. TABLE CK100 SELECT FUNCTIONS TABLE CK100 DRIVER TYPES USED.
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CK97 Clock Synthesizer Design Guidelines
TABLE CK100 CLOCK ENABLE CONFIGURATION. TABLE CK100 POWER MANAGEMENT REQUIREMENTS TABLE CKBF DESCRIPTION TABLE TABLE CKBF FUNCTIONALITY TABLE 8-10 CKBF DRIVER TYPES USED TABLE 8-11 CK100-SM DESCRIPTION TABLE. TABLE 8-12 TYPE MOBILE CLOCK BUFFER OPERATING REQUIREMENTS TABLE 8-13 TYPE MOBILE SDRAM CLOCK OPERATING REQUIREMENTS
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CK97 Clock Synthesizer Design Guidelines
July 1998
Introduction
This document designed provide industry with technical specifications required clock drivers synthesizers present future Intel Architecture platforms. Split power supply signaling provide 2.5V 3.3V clocks stated requirement these products. Additionally, clocking solution must provide processor chipset clock frequencies 66.6 (15.00 period) (10.00 period.) Certain applications also require processor chipset speeds 60.00 (16.67 period.) This document intended computer OEMs defining using clock synthesizer components desktop system level clocking requirements. 3.3V power supply used power portion core, 2.5V used power remaining outputs. Because power supplies independent, because current technology does control power sequencing turning turning system, latch-up potentially damaging conditions exist during these power sequencing phases. Your design required operate properly make requirement system sequence power supplies. 2.5V signaling specification follows JEDEC standard 8-X. should noted that preferred implementation 2.5V supply will 2.5V voltage regulator. Processor chipset clock voltages above specified variation allowed. 3.3V signaling specification follows JEDEC standard LVTTL signaling. 3.3V power delivery specification follows JEDEC standard range 3.3V ±5%. These guidelined provide baseline development Intel Architecture processor based platform clock driver requirements. only implementation that developed; however, this baseline functionality required most desktop platforms.
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CK97 Clock Synthesizer Design Guidelines
Clock Synthesizer Overview Clock synthesizers expected source multiple clock types: e.g., Host clock, clock, system clock, Super others defined system requirements. These guidelines deal with clock, other Host clocks, SDRAM (DIMM) clocks, clocks, IOAPIC clocks, 48MHz, Serial Clock, copies reference clock. These products will required generate clock Accelerated Graphics Port (AGP) devices. major technological challenge seen transition Host frequency. There references number clocks types clocks given clock driver chip will supply main body document. Examples clock synthesizer designs located appendix. number clocks types clocks, package type load conditions also shown. Timing electrical requirements above mentioned clocks provided. Information about reflects requirements specified specification Chapter Examples routing topologies, loading signal quality specifications outlined Section Audio Codec (AC97) support Information providing Audio clocks support Audio Codec (AC97) defined latest revision Audio Codec specification. Intel website address listed section
Applicable Documents latest revision following used reference documents: JEDEC Standard 8-1A, Interface Standard 3.3±0.3 Power Supply Digital Integrated Circuits. JEDEC Standard 8-X, 2.5V±0.2V (normal range), 1.8V 2.7V (wide range) Power supply Voltage Interface Standard Non-terminated Digital Integrated Circuit. Specification IBIS Modeling Specification Audio Codec Specification (AC97) Philips Peripherals Data handbook IC12 1996 Other Intel Clock Design Guidelines: CK25 Intel Clock Driver Design Guidelines 440FX chipset support CKDM66 Clock Driver Design Guidelines Mixed Voltage Clock Synthesizer/Driver Design Guidelines with SDRAM support Section obtain copies PCI, AC97 IBIS specifications.
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CK97 Clock Synthesizer Design Guidelines
July 1998
Drive Specification primary motivation this document address issues associated with split voltage effects system power delivery, signaling, timing test. signaling, timing, test characteristics change with different supply voltages need thoroughly understood simulated optimal system performance. clock driver output buffers specified terms their switching characteristics their drive characteristics such, primary electrical parameters voltage current relationship (V/I), rise fall time (Trise/Tfall) driver through active switching range, critical timing parameters.
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CK97 Clock Synthesizer Design Guidelines
Electrical Requirements
This section details electrical parameters types 2.5V clock output buffers, multiple types 3.3V clock output buffers 5.0V compatible 3.3V clock driver output buffer. different types 2.5V 3.3V drivers needed compensate corresponding board layout topologies. voltage (<3.0V) required CPU, signaling levels longer useable. signaling level support 2.5V being used that portion design. JEDEC standard called "2.5V±0.2V (normal range), 1.8V 2.7V (wide range) Power Supply Voltage Interface Standard Non-terminated Digital Integrated Circuit", hereafter referred 2.5V signaling 2.5V supply being used. 3.3V clocking requirements still support TTL-level compatible requirements will called their appropriate name, LVTTL, even though they signaling levels. clock driver designed operate 2.5V Pentium® processor Pentium processor signaling environment will necessarily operate correctly 3.3V LVTTL 5.0V signaling environment. Great care must taken this design environment properly support extremely tight timing requirements between clocks. clock driver clocks must generate monotonic edges through input threshold regions specified each signaling environment. Many conditions exist design clock driver system that affect monotonic operation clock driver. Power supply noise, inductance capacitance, ratio clock signals Vddq pins (SSO), routing topology will affect monotonicity these clocks. electrical requirements outlined here ensure components connect directly together without external buffers other "glue" logic. Series terminating resistors required keep noise within limits strong drivers under lightly loaded conditions. Components should designed operate within "commercial" range environmental parameters. However, this does preclude option other operating environments vendor's OEM's discretion. Clock driver output buffers specified terms their curves Trise/Tfall times. Limits acceptable curves provide maximum output impedance that achieve acceptable timing typical configurations, minimum output impedance that keeps reflected wave within reasonable bounds signal quality. important understand that drive strength layout topology hand hand. Point-to-Point multiple stubs receiver will work with weaker driver, whereas route that splits driver requires stronger buffer. signal quality problems strong driver under light loads negated somewhat with series termination resistor placed close driver possible. Section more detail. Examples possible clock driver designs contained appendices. These only solutions that achieved, good starting point design component meet specific design requirements. mixed power supplies required proper system operation, very important understand that specific power supply sequencing supported. clock synthesizer CAN'T force power sequencing requirements system.
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CK97 Clock Synthesizer Design Guidelines
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Specifications (Clock Driver) parameters must sustainable under steady state (DC) conditions.
Table Absolute Maximum Power Supply
Symbol VDD3 VDDQ2 VDDQ3 Parameter 3.3V Core Supply Voltage 2.5V Supply Voltage 3.3V Supply Voltage Storage Temperature Min. -0.5 -0.5 -0.5 Max. Units Notes
Table Absolute Maximum
Symbol Vih3 Vil3 prot. Parameter 3.3V Input High Voltage 3.3V Input Voltage Input protection Min. -0.5 -0.5 Max. Units Notes
Notes:
Maximum exceed maximum VDD. Human body model.
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CK97 Clock Synthesizer Design Guidelines
Table Operating Requirements
Symbol VDD3 VDDQ3 VDDQ2 Parameter 3.3V Core Supply Voltage 3.3V Supply Voltage 2.5V Supply Voltage Condition 3.3V 3.3V 2.5V 3.135 3.135 2.375 3.465 3.465 2.625 Units Notes
3.3V±5% Vih3 Vil3 3.3V Input High Voltage 3.3V Input Voltage Input Leakage Current VDDQ3 VDD3 VSS-0.3 VDD+0.3
VDDQ2 2.5V±5% Voh2 Vol2 2.5V Output High Voltage 2.5V Output Voltage
VDDQ3= 3.3V±5% Voh3 Vol3 3.3V Output High Voltage 3.3V Output Voltage
VDDQ3= 3.3V±5% Vpoh Vpol Output High Voltage Output Voltage 0.55
Cxtal Cout Lpin
Input Capacitance Xtal Capacitance Output Capacitance Inductance Ambient Temperature Airflow 13.5
22.5
Notes:
Signal edge required monotonic when transitioning through this region. This recommendation, absolute requirement package size type being specified. actual value should provided with component data sheet. Input Leakage Current does include inputs with Pull-Up Pull-down resistors. Inputs with resistors should state current requirements. power sequencing implied allowed required system. Conforms Signaling specification. seen crystal. Device intended used with 17-20pF crystal. next section more details. inputs referenced 3.3V power supply.
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CK97 Clock Synthesizer Design Guidelines
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Load Capacitance Seen External Crystal:
Earlier clock definitions specify target load capacitance clock synthesizer seen crystal. Most clock vendors targeted 12-13 historical reasons, vendors specified variation their datasheets. However, common crystals used today 17-20 range. This requires addition external capacitors frequency compensation. reduce ambiguity with this issue, require that clock driver load capacitance seen crystal, capacitance individual XTAL_IN XTAL_OUT pins) targeted 18pF 25%. This specification includes clock driver component only does include capacitance associated with board vias traces. Doing this: Directs vendors design same target load capacitance. Requires testing/guarantee design variation. eliminate external compensation capacitors frequency variation tolerated.
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CK97 Clock Synthesizer Design Guidelines
Buffer Specifications: Volt, Volt Clocks curves, Trise/Tfall specifications targeted achieving acceptable switching behavior under load conditions described section this specification. Pull-up pull-down sides each buffers have separate curves which provided following sections. drive curve specifies steady state conditions that must maintained, does indicate real output drive strength. parameters must guaranteed under transient switching (AC) conditions. sign current parameters (direction current flow) referenced ground inside component; i.e. positive currents flow into component while negative currents flow component.
Buffer Name IOAPIC 48MHz, SDRAM Range 2.375 2.625 2.375 2.625 3.135 3.465 3.135 3.465 3.135 3.465 Impedance (Ohms) 13.5 Buffer Type Type Type Type Type Type
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2.2.1 TYPE (2.5V) Buffer Characteristics
Table TYPE Clock Buffer Operating Requirements
Symbol Iohmin Iohmax Iolmin Iolmax Parameter Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current 2.5V Type Output Rise Edge Rate 2.5V Type Output Fall Edge Rate Condition Vout Vout 2.375 Vout Vout 2.5V 0.4V 2.0V 2.5V 2.0V 0.4V V/ns Units V/ns Notes
Notes:
Intended approximate impedance curve below. Device should checked against entire curve characterization testing. Production testing expected subset characterization testing. Output rise fall time. Figure CK100 Clock Waveform calculation measurement information. Output rise fall time must guaranteed across process temperature range. Receiver logic thresholds Vil=0.7 Vih=1.7 Volts. 13.5-45 with nominal driver impedance. Vout/Ioh, Vout/Iol measured VCC/2.
Pull-Up
Voltage 2.375 2.625
Pull-Up (mA)
(mA)
(mA) -107 -107 -107 -107 -105 -101
-100
-120 Vout
Figure TYPE Clock Output Buffer Pull-Up Characteristics
Notes (Figure 2-1)
Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next this drawing Table TYPE Clock Buffer Operating Requirements.
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CK97 Clock Synthesizer Design Guidelines
Voltage 2.375 2.625
Pull-Down (mA) (mA)
Pull-Down
(mA)
Vout
Figure TYPE Clock Output Buffer Pull-Down Characteristics
Notes (Figure 2-2):
Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next this drawing Table TYPE Clock Buffer Operating Requirements.
2.2.2 TYPE IOAPIC (2.5V) Buffer Characteristics
Table IOAPIC Clock Buffer Operating Requirements
Symbol Iohmin Iohmax Iolmin Iolmax Parameter Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current 2.5V Type Output Rise Edge Rate 2.5V Type Output Fall Edge Rate Condition Vout Vout 2.5V Vout Vout 2.5V 0.4V 2.0V 2.5V 2.0V 0.4V V/ns Units V/ns Notes
Notes:
Intended approximate impedance curve below. Device should checked against entire curve characterization testing. Production testing expected subset characterization testing. Output rise fall time. Figure CK100 Clock Waveform calculation measurement information. Output rise fall time must guaranteed across process temperature range. Receiver logic thresholds Vil=0.7 Vih=1.7 Volts. 9-30 with nominal driver impedance. Vout/Ioh, Vout/Iol measured VCC/2.
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CK97 Clock Synthesizer Design Guidelines
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APIC Pull-Up
Voltage 2.375 2.625
Pull-Up (mA)
(mA)
(mA) -159 -159 -159 -159 -157 -150 -140 -127 -109
-100 -120 -140 -160 Vout
Figure TYPE IOAPIC Clock Output Buffer Pull-Up Characteristics
Notes (Figure 2-3):
Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next this drawing Table IOAPIC Clock Buffer Operating Requirements.
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CK97 Clock Synthesizer Design Guidelines
Voltage 2.375 2.625
Pull-Down (mA) (mA)
APIC Pull-Down
(mA)
Vout
Figure TYPE IOAPIC Clock Output Buffer Pull-Down Characteristics
Notes (Figure 2-4):
Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next this drawing Table IOAPIC Clock Buffer Operating Requirements.
2.2.3 TYPE 3.3V 48Mhz, Buffer Characteristics
Table 3.3V Clock Operating Requirements
Symbol Iohmin Iohmax Iolmin Iolmax Parameter Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current 3.3V Type Output Rise Edge Rate 3.3V Type Output Fall Edge Rate Condition Vout Vout 3.135 Vout 1.95V Vout 3.3V 0.4V 2.4V 3.3V 2.4V 0.4V V/ns Units V/ns Notes
Notes:
Intended approximate impedance curve below. Device should checked against entire curve characterization testing. Production testing expected subset characterization testing. Output rise fall time. Figure CK100 Clock Waveform calculation measurement information. Output rise fall time must guaranteed across process temperature range. Receiver logic thresholds Vil=0.8 Vih=2.0 Volts. 20-60 with nominal driver impedance. Vout/Ioh, Vout/Iol measured VCC/2.
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Voltage 1.65 3.135 3.465
Pull-Up (mA)
48Mhz, Pull-Up
(mA)
(mA)
-100
-120 Vout
Figure TYPE 48Mhz, Clock Output Buffer Pull-Up Characteristics
Notes (Figure 2-5):
Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next this drawing Table 3.3V Clock Operating Requirements.
48Mhz, Pull-Down
Voltage 0.65 0.85 1.65 1.95 3.135
Pull-Down (mA) (mA)
(mA)
Vout
Figure TYPE 48Mhz, Clock Output Buffer Pull-Down Characteristics
Notes (Figure 2-6):
Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next this drawing Table 3.3V Clock Operating Requirements.
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CK97 Clock Synthesizer Design Guidelines
2.2.4 TYPE SDRAM (3.3 Clock Buffer Characteristics
Table SDRAM Clock Operating Requirements
Symbol Iohmin Iohmax Iolmin Iolmax trhSDRAM Parameter Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current 3.3V Type Output Rise Edge Rate. SDRAM ONLY. 3.3V Type Output Fall Edge Rate. SDRAM ONLY. Condition Vout Vout 3.135 Vout 1.0V Vout 3.3V 0.4V 2.4V 3.3V 2.4V 0.4V V/ns Units V/ns Notes
tfhSDRAM
Notes:
Intended approximate impedance curve below. Device should checked against entire curve characterization testing. Production testing expected subset characterization testing. Output rise fall time. Figure CK100 Clock Waveform calculation measurement information. Output rise fall time must guaranteed across process temperature range. Receiver logic thresholds Vil=0.8 Vih=2.0 Volts. 10-24 with nominal driver impedance. Vout/Ioh, Vout/Iol measured VCC/2. 1.5V/nS component spec required meet 1.0V/nS minimum rise/fall time SDRAM input. This required guarantee PC100 component timings which tested/specified with maximum 1.2nS from 0.8V 2.0V threshold levels.
SDRAM Pull-Up
Voltage 1.65 3.135 3.465
Pull-Up (mA)
(mA) -116 -116 -110 -107 -103
(mA) -198 -198 -188 -184 -177 -170 -157 -126 -107
-100 -120 -140 -160 -180 -200 Vout
Figure TYPE SDRAM Clock Output Buffer Pull-Up Characteristics
Notes (Figure 2-7):
Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next this drawing Table 3.3V Clock Operating Requirements.
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SDRAM Pull-Down
Voltage 0.65 0.85 1.65 1.95 3.135
Pull-Down (mA) (mA)
(mA)
Vout
Figure TYPE SDRAM Clock Output Buffer Pull-Down Characteristics
Notes (Figure 2-8): Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next this drawing Table 3.3V Clock Operating Requirements.
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CK97 Clock Synthesizer Design Guidelines
2.2.5 TYPE Clock Buffer Characteristics
Table Clock Operating Requirements
Symbol Iohmin Iohmax Iolmin Iolmax Parameter Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current 3.3V Type Output Rise Edge Rate 3.3V Type Output Fall Edge Rate Condition Vout Vout 3.135 Vout 1.95V Vout 3.3V 0.4V 2.4V 3.3V 2.4V 0.4V V/ns Units V/ns Notes
Notes:
Intended approximate impedance curve below. Device should checked against entire curve characterization testing. Production testing expected subset characterization testing. Output rise fall time. Figure CK100 Clock Waveform calculation measurement information. Output rise fall time must guaranteed across process temperature range. Receiver logic thresholds Vil=0.8 Vih=2.0 Volts. 12-55 with nominal driver impedance. Vout/Ioh, Vout/Iol measured VCC/2. specification additional details
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Test Point 3.135
Pull-Up Voltage (mA) (mA) (mA) -195 -194 -189 -184 1.65 -172 -25.5 -159 -140 -14.5 -100 3.135
Drive Point
Voltage
Drive Point
Typical Conditions
Current (mA)
-189
Figure TYPE Clock Output Buffer Pull-Up Characteristics
Notes (Figure 2-9):
Must meet temperature voltage range specified Table Operating Requirements. This drawing scale. Comparisons should made data provided table next Table Clock Operating Requirements
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CK97 Clock Synthesizer Design Guidelines
Typical Conditions
Pull-Down Voltage (mA) I(mA) (mA) 0.65 0.85 17.7 26.5 1.65 1.95 3.135
Drive Point
Voltage
Drive Point
Test Point Current (mA)
Figure 2-10 TYPE Clock Output Buffer Pull-Down Characteristics
Notes (Figure 2-10):
Must meet temperature voltage range specified Table Operating Requirements This drawing scale. Comparisons should made data provided table next Table Clock Operating Requirements
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2.2.6 Vendor Provided Specifications
Vendors should make following information available their data sheets: capacitance pins (min max). inductance pins (min max). Output curves under switching conditions. graphs/tables should given each output type used: driving high, other driving low. Both should show best-worst case conditions. Loaded rise/fall times each output type loads specified test section this specification. Absolute maximum data, including operating non-operating temperature, maximums, etc.
Component vendors should make following information electronically available IBIS model format. Include following minimum information: Output curves under switching conditions. curves should supplied: driving high, other driving low. Both should show best-typical-worst curves. Unloaded rise/fall times each output type specified IBIS. Package Resistance (R_pkg [min, max]); Package Inductance (L_pkg [min, max]); Package Capacitance (C_pkg [min, max]); Component Capacitance (C_comp [min, max]).
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CK97 Clock Synthesizer Design Guidelines
Timing
Timing Requirements
Table Host Timing Requirements
Symbol tHKP tHKH tHKL tHRISE tHFALL tJITTER Duty Cycle tHSKW tIOSKW tpZL, tpZH tpLZ, tpZH tIOSKW tHSTB tPKP tPKPS tPKH tPKL tPSKW tHPOFFSET tPSTB Parameter Host period Host high time Host time Host rise time Host fall time Host Jitter Measured 1.25V Host Skew IOAPIC Skew Output enable delay Output disable delay IOAPIC Skew Host Stabilization from power-up period period stability high time time Skew Host Clock Offset Stabilization from power-up 12.0 12.0 30.0 15.0 12.0 12.0 30.0 15.5 10.0 10.5 Units Notes
Notes:
Output drivers must have characteristics noted Section above. Figure measure points. Period, jitter, offset skew measured rising edge @1.25V 2.5V clocks 1.5V 3.3V clocks. Clock Host clock divided Host=66.6Mhz. clock Host clock divided three Host Mhz. Host must always lead shown Figure 3-2. This must guaranteed design under test load conditions. tHKH measured 2.0V shown Figure 4-1. tHKL measured 0.4V shown Figure 4-1. time specified measured from when Vddq achieves nominal operating level (typical condition Vddq 3.3V) till frequency output stable operating within specification. Defined once clock nominal operating frequency adjacent period changes exceed time specified. tHRISE tHFALL measured transition through threshold region 0.4V 2.0V (1mA) JEDEC Specification. average period over period time must greater than minimum specified period There pin-pin skew requirement between individual outputs within 48Mhz banks. Ideal specification would reduce 175pS. However, 250pS acceptable. Calculated minimum edge-rate (1V/nS) guarantee 45/55% duty-cycle 1.25 Volts. Pulsewidth required wider faster edge-rate ensure duty-cycle specification met. Should specified completeness only. Specs modified required.
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Table 3-2A Main Memory Timing Requirements
Symbol tSDKP tSDKH tSDKL tSDRISE tSDFALL tpLH tpHL tpZL, tpZH tpLZ, tpHZ Duty Cycle tSDSKW Parameter SDRAM period SDRAM high time SDRAM time SDRAM rise time SDRAM fall time SDRAM Buffer prop delay SDRAM Buffer prop delay SDRAM Buffer Enable delay SDRAM Buffer disable delay Measured pin-to-pin Skew 15.0 15.5 10.0 10.5 Units V/ns V/ns Notes
Notes:
Output drivers must have characteristics noted Section above. Clock period, skew measured rising edge 1.5V 3.3V clocks. tSDKH measured 2.4V shown Figure 4-1. tSDKL measured 0.4V shown Figure 4-1. Defined once clock nominal operating frequency adjacent period changes exceed time specified. tSDRISE tSDFALL measured transition through threshold region 0.4V 2.4V (1mA) JEDEC Specification. Measured with test loads described Test Measurement section Duty cycle should tested with 50/50% input. Over (20pF) discrete load, process, voltage temperature. Input edge rate these tests must faster than V/nS. Should specified completeness only. Specs modified required. Part part skew should minimized specified vendor completeness. requirement meet Intel yellow cover specification. Calculated minimum edge-rate (1.5nS) guarantee 45/55% duty-cycle Volts. Pulsewidth required wider faster edge-rate ensure duty-cycle specification met.
Frequency Accuracy Although target Host clock frequency (10.0 minimum), known that current generation 14.318 Mhz-based clock drivers will able produce extremely accurate nominal frequency without having effect jitter signature. Each vendor should aware trade-offs between counter values, update rate jitter. Sometimes looser device will have less jitter than device with variation. maximum period been defined minimum period plus intent this specification limit variability within various platform clocking solutions. Frequency Accuracy 48Mhz outputs. nominal frequency required +167 from 48.00Mhz conform with default. Failure comply with this requirement requires BIOS change deemed
unacceptable.
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CK97 Clock Synthesizer Design Guidelines
Multiple Jitter Tracking Specification.
clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. This relationship critical when clock driver drives more PLLs. worst case timing issue would occur attenuated jitter another device (PLL nonPLL) tracked jitter completely. reduce possibility this require that -20dB attenuation point less than equal 500Khz. Most clock vendors specify their jitter bandwidth characteristics specify only -3dB level. allow greatest flexibility loop design require vendor provide -20dB point. This specification guaranteed design and/or measured with spectrum analyzer.
This specification intended replace clarify Pentium® specification which stated ensure jitter frequency relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between clock operating frequency."
Ideal Closed Loop Jitter Bandwidth
(Not Scale)
-3dB
Peak 500Khz
Gain
dB/Decade
-20dB
About SPEC
Frequency
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2.5V
1.25V Host
2.5V
1.25V Host
tHSKW
Figure Host Host Skew
2.5V
1.25V Host
3.3V
1.5V
tHPOFFSET
tHPOFFSET
Figure Host Offset
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CK97 Clock Synthesizer Design Guidelines
Test Measurement
Board level simulations usually done using ideal output buffer models which defined/modeled with output load. typical source these models comes from more silicon level simulators. Clock driver vendor validation these models under load condition extremely time consuming. table below provides lumped load test loads over which vendor expected test/guarantee parameters clock driver. vendor encouraged provide information correlation between lumped load performance no-load performance applications exercise fully describe operation product.
Table Minimum Maximum Expected Capacitive Loads
Clock Clocks (HCLK) Clocks (PCLK) Clock SDRAM IOAPIC Notes:
Maximum rise/fall times guaranteed maximum specified load each type output buffer. Minimum rise/fall times guaranteed minimum specified load each type output buffer Rise/fall times specified with pure capacitive load shown. Testing done with additional resistor parallel properly correlated with capacitive load. Minimum load legacy spec from previous clock driver platforms. Does accurately reflect minimum load.
Load
Load
Units
Notes device load, possible loads. Must meet requirements device load SDRAM DIMM spec. device load device loads
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Output Buffer
Test Point Test Load
Clock Output Wave Form
tHKP Duty Cycle tHKH
2.5V Clocking Interface
1.25
tHKL
tHrise
tPKH
tHfall
tPKP
3.3V Clocking Interface (TTL)
tPKL
tPrise
tPfall
Figure CK100 Clock Waveforms
Tdly Measurement (CKBF Non-Inverting)
Input Waveform
1.5V
1.5V
tplh
Output Waveform 1.5V 1.5V
tphl
Figure 4-2A CKBF Clock Waveforms
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CK97 Clock Synthesizer Design Guidelines
Volt Measure Points
Component Measurement Points 2.0V 1.7V 1.25V 0.7V 0.4V System Measurement Points Vddq2
Volt Measure Points
Component Measurement Points 2.4V 2.0V 1.5V 0.8V 0.4V System Measurement Points Vddq3
Figure 4-3B Component Versus System Measure Points
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System Considerations
diagrams shown below typical clock routing topologies Pentium desktop platforms. These meant laying clocks Desktop platforms. also meant clock driver vendors simulate check their buffers.
LAYOUT
Rterm
Shorted 0.1"
LAYOUT
Rterm
Rterm
LAYOUT
Rterm Rterm
SDRAM Load Seen Single Clock Driver Output
Ohms
LAYOUT
stub
Rterm
Each Stub 0.15"
stub
Trace 1.2"
Ohms
Figure Standard Clock Layout Topologies
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CK97 Clock Synthesizer Design Guidelines
Table Layout Dimensions
IOAPIC 48MHz, SDRAM
Notes:
Primary topology outputs. load. Secondary topology outputs. loads. REQUIRED drive loads, split receiver. Point-to-Point only
Topology LAYOUT LAYOUT LAYOUT LAYOUT LAYOUT
0.25"- 0.1"- 0.25" 0.25"- 0.5" 0.25"- 0.5" 0.25" 0.5"
0.25"- 0.5" 0.9" 1.1"
0.6" 0.8"
RTERM
Notes
Table Board Level Simulation Conditions
Symbol VDDQ
Parameter Line Impedance Line Velocity Core Supply Voltage Supply Voltage Ambient Temperature airflow)
Slow ns/ft 3.135 2.375
ns/ft 3.30V
Fast ns/ft 3.465 2.625
topologies listed above Figure standard topologies desktop clock routings. parameters listed Table above give minimum maximum dimension ranges used clock buffer driver simulation. Series termination resistors will required control output driver variation from platform platform. Series termination should placed close driver possible best signal quality results. impedance outputs IOAPIC clocks required reduce sensitivity topology output buffer edge-rate variation point-to-point layout topologies shown Figure 5-1.
Table Typical Characteristics Clock Destination
Symbol Vih3 Vil3 Cinsdram Parameter 3.3V Input High Voltage 3.3V Input Voltage Input Capacitance SDRAM Input Capacitance Condition -0.3 VDDQ Units Notes
Notes:
Signal edge required monotonic when transitioning through this region.
clock input processor other system components must meet signal quality specifications guarantee clock signal sensed properly ensure clock signal does affect long term reliability components. There signal quality parameters defined: Overshoot/Undershoot Ringback.
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Typically, these values determined board designers result multiple system level simulations. However, data been provided allow clock driver vendor complete first approximation these system events. These simulations encouraged should seen step validation IBIS models device. Each device will have different sensitivity over undershoot, various input capacitance clamping circuits. Board impedance, termination trace topology will dominate these measurements. specifications should taken applications information design target clock driver vendor, should board designer. Current SDRAM DIMM specifications call input clamp diodes 100Mhz SDRAM components. This should help signal quality these devices allow faster clock risetimes acceptable. However, backwards compatibility 66Mhz SDRAM DIMMS (which have input clamp diodes) causes keep driver specifications same previous generations clock drivers.
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CK97 Clock Synthesizer Design Guidelines
Table Signal Quality Requirements Destination
Symbol tover SDRAM tring SDRAM tover CPU/Chipset tring CPU/Chipset Ring back Overshoot/Undershoot Voltage Ring back Vddq +0.7 Parameter Overshoot/Undershoot Voltage Duration Units Notes
Notes:
maximum SDRAM overshoot undershoot specified above below power rails. Settling time defined point which output voltage remains within clocks steady-state quiescent voltage. tover specification includes settling time. These values representative values system level design targets current JEDEC SDRAM dimms. Required support future Intel Silicon.
Overshoot
Maximum Overshoot VDDQ Maximum Ringback
Tsettling
Maximum Ringback
Maximum Undershoot
Undershoot
Figure Overshoot Undershoot
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Obtain Reference Material
Reference Special Interest Group industry-wide group that controls official specification. obtain latest copies specification contacting Special Interest Group following numbers: (800)433-5177 (503)797-4297 International (503)234-6762 There nominal obtaining this specification. IBIS Reference IBIS Open Forum industry-wide forum that controls official IBIS specification. Minutes IBIS meetings, email correspondence, proposals specification changes, etc. on-line "vhdl.org". join email discussions, send message "ibis-request@vhdl.org" request that your name added IBIS mail reflector. sure include your email address. IBIS home page found
Audio Codec (AC97) Reference AC97 home page found
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CK97 Clock Synthesizer Design Guidelines
Considerations
been chosen serial interface control these clock drivers. chosen support JEDEC proposal JC-42.5 Unbuffered SDRAM DIMM. vendors required determine intellectual property issues associated with manufacture devices. Address assignment: clock driver this specification single, address shown below. devices address only master clock driver used design. Intel believes that address re-used CKBF device other conflicting clock driver used system. following address confirmed Philips 09/04/96. R/W#
Note: R/W# used controller data direction bit. `zero' indicates transmission (WRITE) clock device.
`one' indicates request data (READ) from clock driver. Since definition clock buffer only allows controller WRITE data; R/W# address will always seen `zero.' Optimal address decoding this left vendor.
Options: understanding that metal mask options other pinouts this type clock driver will allowed same address original CKBF device. addresses defined terms function (master clock driver) rather than form (pinout, option.) Slave/Receiver: clock driver assumed require only slave/receiver functionality. Slave/transmitter functionality optional. Data Transfer Rate: kbits/s (standard mode) base functionality required. Fast mode (400 kbits/s) functionality optional. Logic Levels: logic levels based percentage controller other devices bus. Assume devices based Volt supply. Data Byte Format: Byte format Bits described following appendices. Data Protocol: simplify clock interface, clock driver serial protocol specified only block writes from controller. bytes must accessed sequential order from lowest highest byte with ability stop after complete byte been transferred. Indexed bytes allowed. However, Intel controller more specific format than generic protocol. clock driver must meet this protocol which more rigorous than previously stated protocol. Treat description from viewpoint controller. controller "writes" clock driver possible would "read" from clock driver (the clock driver slave/receiver only incapable this transaction.) "The block write begins with slave address write condition. After command code host (controller) issues byte count which describes many more bytes will follow message. host bytes send, first byte would number (14h), followed bytes data. byte count block write command allowed transfer maximum data bytes."
Start
bits Slave Address
bits Command Code
Byte Count
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Data Byte bits
Data Byte bits
Data Byte bits
Stop
Note: acknowledgment returned slave/receiver (the clock driver).
Consider command code byte count bytes required first bytes transfer. command code software programmable controller, will specified 0000 0000 clock specification. byte count byte number additional bytes required transfer, counting command code byte count bytes. Additionally, byte count byte required minimum byte maximum bytes satisfy above requirement. example:
Byte count byte 0000 0000 0000 0000 0000 0000 0000 0000 0010
Notes: allowed. Must have least byte. Data functional frequency select register (currently byte spec) Reads first bytes data. (byte then byte Reads first three bytes (byte order) Reads first four bytes (byte order) Reads first five bytes (byte order) Reads first bytes (byte order) Reads first seven bytes (byte order) byte count supported
transfer considered valid after acknowledge corresponding byte count read controller. serial controller interface simplified discarding information both command code byte count bytes simply reading bytes that sent clock driver after being addressed controller. expected that controller will provide more bytes than clock driver handle. clock vendor choose discard number bytes that exceed defined byte count. Clock Stretching: clock device must hold/stretch SCLOCK SDATA lines more than Clock stretching discouraged should only used last resort. Stretching clock/data lines longer than this time puts device error/time-out mode supported platforms. assumed that data transfers completed specified without clock/data stretching. General Call: assumed that clock driver will have respond "general call."
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CK97 Clock Synthesizer Design Guidelines
Electrical Characteristics: electrical characteristics must meet standard mode specifications found section specification. Pull-Up Resistors: internal resistor pull-ups SDATA SCLOCK inputs must stated individual datasheet. internal pull-ups these pins below 100K discouraged. Assume that board designer will single external pull-up resistor each line that these values range. Assume device DIMM (serial presence detect), controller, clock driver plus one/two more devices platform capacitive loading purposes. Input Glitch Filters: Only fast mode devices require input glitch filters suppress noise. clock driver specified standard mode device required support this feature. PWR_DWN#: clock driver placed PWR_DWN# mode, SDATA SCLK inputs must Tri2 Stated device must retain programming information. current circuitry must characterized datasheet.
specific information consult Philips Peripherals Data Handbook ICI2 (1996)
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Appendices
Appendix CK100 SSOP Pinouts following Addendum defines generic pinouts base requirements Intel Architecture based desktop mobile computing platforms. intended used with SSOP CKBF clock drivers described Appendix This addendum also used example development other custom clock synthesizer/driver components. This only solution that derived.
Features SSOP Package):
Four Copies Clock Eight Copies Clock (Synchronous w/CPU Clock) Copies IOAPIC Clock @14.31818 Copies 48MHz Clock Three Copies Ref. Clock @14.31818 Ref. 14.31818MHz Xtal Oscillator Input 100MHz 66MHz operation Power Management Control Input Pins Isolated core Vdd, pins noise reduction
REF0 REF1 Vssref XTAL_IN XTAL_OUT Vsspci0 PCICLK_F PCICLK1 Vddpci0 PCICLK2 PCICLK3 Vsspci1 PCICLK4 PCICLK5 Vddpci1 PCICLK6 PCICLK7 Vsspci2 Vddcore0 Vsscore0 Vdd48Mhz 48Mhz 48Mhz Vss48Mhz
CK100
Vddref REF2 Vddapic APIC0 APIC1 Vssapic Reserved Vddcpu0 CPUCLK0 CPUCLK1 Vsscpu0 Vddcpu1 CPUCLK2 CPUCLK3 Vsscpu1 Vddcore1 Vsscore1 PCISTOP# CPUSTOP# PWRDWN# Spread# SEL0 SEL1 SEL100/66#
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CK97 Clock Synthesizer Design Guidelines
Features SSOP Package):
Copies Clock Copies Clock (Synchronous w/CPU Clock) Copy Ref. Clock @14.31818 Ref. 14.31818MHz Xtal Oscillator Input 100MHz 66MHz operation Power Management Control Input Pins Isolated core Vdd, pins noise reduction
XTAL_IN XTAL_OUT Vsspci0 PCICLK_F PCICLK1 Vddpci0 PCICLK2 PCICLK3 Vddpci1 PCICLK4 PCICLK5 Vsspci1 Vddcore0 Vsscore0
CK100-M
Vssref Vddref Vddcpu CPUCLK0 CPUCLK1 Vsscpu Vddcore1 Vsscore1 PCISTOP# CPUSTOP# PWRDWN# SEL100/66#
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Table CK100 Description Table
Package -Qty Package output ground power input output ground output power output power ground power ground output input input input input input input power ground outputs ground power outputs input reserved [0-2] Vssref Vddref XTAL_IN XTAL_OUT Vsspci [0-2] PCICLK_F Vddpci [0-1] PCICLK [1-7] Vddcore [0-1] Vsscore [0-1] Vdd48MHz Vss48MHz 48MHz SEL[0-1] SEL100/66# PWRDWN# CPUSTOP# PCISTOP# Vddcpu [0-1] Vsscpu [0-1] CPUCLK0-3 Vssapic Vddapic APIC0-1 SPREAD# reserved 14.318 Clock output Ground Ref0-1 outputs Power Ref0-1 outputs 14.318 Crystal input 14.318 Crystal output Ground outputs Free running output Power outputs Clock outputs. compatible 3.3V Isolated power core Isolated ground core Power 48MHz outputs Ground 48MHz outputs 48MHz outputs Logic select pins. LVTTL levels Logic select. LVTTL levels (note Select enabling 100MHz 66MHz H=100MHz, L=66MHz Powers down device held Stops clocks held Stops clocks held Power outputs Ground outputs Host clock outputs 2.5V Ground Apic outputs Power Apic outputs Apic output @2.5Volts. 14.31818 OPTIONAL Enables Spread Spectrum feature when Reserved future modification Type Symbol Description
Notes:
names above table reflect likely internal power ground partition reduce effects internal noise performance device. reality, platform will configured with Vddapic Vddcpu pins tied 2.5V regulator, remaining pins tied common 3.3V supply pins being common. Vdd/Vss naming convention above done show pinout dominated need isolate signals.
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Reserved pins should true no-connects. treated open circuit current system platforms. There external device requirements these pins. Possible option includes additional IOAPIC processor output. (pin package) does either SEL[0-1] signals (pins package). Rather, logical SEL[0-1]. order maintain common silicon between both packages, silicon pads SEL[0-1] should both connected package SEL.
8.1.1 Spread Spectrum Clocking (SSC) Clarification:
Spread Spectrum functionality CK100 clock driver acts on/off switch different forms spread spectrum modulation techniques. Intel this feature platform level timing issues. following specifications added current CK100 definition: external modulation frequency source required CK100. Vendor needs synchronously modulate processor, output clocks. fixed frequency 48MHz clock outputs modulated. APIC clocks synchronous (16.6 MHz) processor they must modulated. clocks synchronous (14.318 MHz) they must modulated. device timings (including jitter, skew, min-max clock period, output rise/fall time) MUST meet existing non-spread spectrum specifications non-spread processor functionality must maintained spread spectrum mode (includes power management functions.) minimum clock period can't violated. preferred method adjust spread technique allow modulation above nominal frequency. This technique often called "downspreading". example triangular frequency modulation profile shown Figure 8-1. modulation profile modulation period expressed when when
where fnom nominal frequency non-SSC mode, modulation frequency, modulation amount, time.
fnom
(1-)fnom 0.5/f 1/fm
Figure Triangular Frequency Modulation Profile.
clock frequency deviation required more than amount specified table below absolute spread amount after fundamental frequency shown below width spectral distribution (between -3dB roll-off.) ratio this width fundamental frequency cannot exceed maximum allowed below each specific frequency modulation profile. This parameter measured frequency domain using spectrum analyzer. amount allowed spreading non-triangular modulation determined induced downstream tracking skew (see explanation which cannot exceed
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Table Maximum Allowed Spread Amount Modulation Type Linear (triangular) Non-Linear Fmod Fmod
maximum allowed spread values intended both clocks. Variation from table responsibility clock supplier user (see note more details.)
Highest peak
non-SSC
fnom fnom
Figure Spectral Fundamental Frequency Comparison
achieve sufficient system-level reduction, desired that reduce spectral peaks nonSSC mode amount specified below. peak reduction defined shown figure 8-2, difference between spectral peaks non-SSC modes specified measurement frequency.
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Table Desired Peak Amplitude Reduction SSC. Clock Freq. Peak Reduction Measurement Freq. (9th harmonics) (7th harmonics)
Notes:
spectral peak reduction necessarily same system reduction. However, this relative measurement gives component-level indication SSC's reduction capability system level. recommended that spectrum analyzer should used this measurement. spectrum analyzer should have measurement capability GHz. measured clock needs into spectrum analyzer highimpedance probe compatible with spectrum analyzer. output clock should loaded with capacitance. resolution bandwidth spectrum analyzer needs comply with measurement requirements. video band needs higher than appropriate display. used resolution bandwidth case measurement equipment limitation. display should with maximum hold. corresponding harmonic peak readings should recorded both non-SSC modes, compared determine magnitude spectral peak reduction.
modulation frequency required range 30-50 avoid audio band demodulation minimize system timing skew. modulation frequency desired range 30-33 downstream PLLs accurately track frequency modulation. downstream tracking skew, i.e., accumulative phase difference between downstream input output clocks, shown Figure 8-3, functions modulation frequency, modulation profile, spread amount. This plot obtained through behavior simulations assuming jitter-free ideal modulated input clock PLL. parameters simulated are:
(VCO gain) (charge-pump current) 2800 (Hz/V)(A), feedback -order 9.75 This skew should minimized reduces system timing margins. Different system implementations have different requirements characteristics, require tighter/looser skew. always true that lower modulation frequency results smaller tracking skew. skew proportional amount spreading. implemented modulation profile must induce less than 140-pS skew with above parameters properly adjusting spread amount. Sinusoidal modulation discouraged peak reduction capability.
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Linear Modulation 0.6%) Non-Linear Modulation 0.5%)
Figure Downstream tracking skew modulation frequency
Skew [ps]
Modulation Frequency [kHz]
Table CK100 Select Functions SEL100/66 Function Description Tri-State Test Mode Notes:
Requires internal decode logic three select inputs device, inputs device. TCLK test clock over driven XTAL_IN input during test mode. Range reference frequency allowed 14.316 nominal 14.31818 MHz, 14.32 MHz. Frequency accuracy 48MHz must +167PPM match default. Section details.
SEL1 pin)
SEL0 pin)
pin)
Function Tri-State (Reserved) (Reserved) Active 66MHz Test Mode (Reserved) (Reserved) Active 100MHz
Notes
Hi-Z TCLK/2
PCI, PCI_F Hi-Z TCLK/6
Outputs 48MHz REF0:2 Hi-Z TCLK/2 Hi-Z TCLK
IOAPIC Hi-Z TCLK
Notes
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CK97 Clock Synthesizer Design Guidelines
8.1.2 CK100 System Considerations:
SEL100/66# frequency select requires specific motherboard pull-up resistor Volts allow CK100 device sense maximum Host frequency processor automatically configure CK100 either 100MHz 66MHz. nominal resistor value desktop (slot one) applications Ohms with maximum allowed tolerance +/-5%. power dissipation resistor less than 1/16 Watts. mobile applications this resistor value critical typical external resistor value 100K Ohms.
internal pull-up pull-down resistors allowed SEL100/66# pin. Table CK100 Driver types used Package Package Driver Type Type Type Type Type Type Type Symbol REF0-2 PCICLK_F PCICLK CPUCLK APIC 48MHz Description 14.318 Clock outputs. 3.3V Free Running clock during PCICLK stopped. 3.3V Clock outputs compatible 3.3V. Host clock outputs 2.5V IOAPIC clock output 2.5V 48MHz clock output 3.3V
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8.1.3 CK100 Power Management
following power consumption conditions device should provided each vendor. values below estimates target specifications SSOP pinouts. power consumption should clearly lower lower pincount devices.
CK100 Condition Powerdown Mode (PWRDWN# Active 66MHz SEL100/66# Active 100MHz SEL100/66#
2.5V supply consumption discrete loads, Vddq2 2.625V static inputs Vddq3 100uA 72mA 100mA
3.3V supply consumption discrete loads Vddq3 3.465V static inputs Vddq3 Vss. 500uA 170mA 170mA
powerdown controller provides signal that latched with copy free running clock. theory, this should synchronous with clock driver output following quantified: flight time clock trace from PCI_F controller Input edge-rate controller, controller input load, set/hold time controller. Variance output edge-rate from PCI_F clock driver Internal delay from output PCI_F clock driver internal clock signal However, large number platform level variables that must taken into account input described "synchronous" clock driver output large highly dependent board design. simplify platform design, CPU_STOP# PCI_STOP# inputs defined ASYNCHRONOUS from clock driver external PCI_F clock. clock driver must synchronize input signal resynchronize with PCI_F clock output. This leaves board timing issues board designer rather than clock vendor. Clock sequencing must always guarantee full clock timing parameters times after system initially powered except where noted. During power power down operations using PWR_DWN# select pin, partial clocks allowed clock timing parameters must except following: understood that first clock pulse coming stopped clock condition could slightly distorted clock network charging requirements. Allowable distortion parameters will supplied later date. also understood that board routing signal loading have large impact initial clock distortion.
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Table CK100 Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK 100/66 100/66 PCICLK Other Clocks Stopped running running running running Crystal running running running running VCO's running running running running
Table CK100 Power Management Requirements
Latency Signal CPU_STOP# PCI_STOP# PWR_DWN# Signal State (disabled) (enabled) (disabled) (enabled) (normal operation) (power down) Notes:
Clock on/off latency defined number rising edges free running PCICLKs between clock disable goes low/high first valid clock comes device. Power latency when PWR_DWN# goes inactive (high) when first valid clocks driven from device.
rising edges free running PCICLK max.
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CPU_STOP# input clock synthesizer. used turn clocks power operation. CPU_STOP# asserted asynchronously external clock control logic with rising edge free running clock (and hence clock) must internally synchronized external PCI_F output. other clocks will continue while clocks disabled. clocks must always stopped state started such manner guarantee that high pulse width full pulse. clock latency needs clocks clock latency needs clocks.
CPUCLK
(internal)
PCICLK
(internal)
PCICLK
(Free-running)
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK
(external)
Figure CK100 CPU_STOP# Timing Diagram
Notes:
timing referenced CPUCLK Internal label means inside chip reference only. This fact that control designed. CPU_STOP# signal input signal that must made synchronous free running PCI_F ON/OFF latency shown diagram clocks. other clocks continue undisturbed. PWR_DWN# PCI_STOP# shown high state. Diagrams shown with respect 66MHz. Similar operation CPU=100MHz
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CK97 Clock Synthesizer Design Guidelines
PCI_STOP# input clock synthesizer must made synchronous clock driver PCI_F output. used turn clocks power operation. clocks required stopped state started such that full high pulse width guaranteed. There ONLY rising edge external PCICLK after clock control logic.
CPUCLK
(internal)
PCICLK
(internal)
PCICLK
(Free-running)
CPU_STOP# PCI_STOP# PWR_DWN# PCICLK
(external)
Figure CK100 PCI_STOP# Timing Diagram
Notes:
timing referenced CPUCLK. PCI_STOP# signal input signal which must made synchronous PCI_F output. Internal means inside chip. other clocks continue undisturbed. PWR_DWN# CPU_STOP# shown high state. Diagrams shown with respect 66MHz. Similar operation CPU=100MHz
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power down selection used part into very power state without turning power part. PWR_DWN# asynchronous active input. This signal needs synchronized internal device prior powering down clock synthesizer. PWR_DWN# asynchronous function powering system. Internal clocks running after device power down. When PWR_DWN# active clocks need driven value held prior turning VCO's Crystal. power latency needs less than power down latency should short possible conforming sequence requirements shown below. PCI_STOP# CPU_STOP# considered don't cares during power down operations. REF0 clock also expected stopped state soon possible. state internal logic, stopping holding REF0 clock output state require more than clock cycle complete.
CPUCLK
(internal)
PCICLK
(internal)
PWR_DWN# CPUCLK
(external)
PCICLK
(external)
Crystal
Figure CK100 PWR_DWN# Timing Diagram
Notes:
timing referenced CPUCLK Internal means inside chip PWR_DWN# asynchronous input metastable conditions could exist. This signal required synchronized inside part. Shaded sections Crystal signals indicate active clock Diagrams shown with respect 66MHz. Similar operation CPU=100MHz
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CK97 Clock Synthesizer Design Guidelines
Appendix CKBF SSOP Pinouts following Addendum defines generic pinouts base requirements Intel Architecture based desktop mobile computing platforms. intended used with SSOP CK100 clock drivers described Appendix This addendum also used example development other custom clock synthesizer/driver components. This only solution that derived. Features SSOP Package): High speed, noise non-inverting 1-18 buffer SDRAM clock buffer applications Supports four SDRAM DIMMS Serial Configuration interface Multiple Vdd, pins noise reduction Separate Tri-State testing
Reserved Reserved Vdd0 Sdram0 Sdram1 Vss0 Vdd1 Sdram2 Sdram3 Vss1 buf_in Vdd2 Sdram4 Sdram5 Vss2 Vdd3 Sdram6 Sdram7 Vss3 Vdd4 Sdram16 Vss4 Vddiic Sdata
CKBF
Reserved Reserved Vdd9 Sdram15 Sdram14 Vss9 Vdd8 Sdram13 Sdram12 Vss8 Vdd7 Sdram11 Sdram10 Vss7 Vdd6 Sdram9 Sdram8 Vss6 Vdd5 Sdram17 Vss5 Vssiic Sclock
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Features SSOP Package):
High speed, noise non-inverting 1-10 buffer SDRAM clock buffer applications Supports four SDRAM SO-DIMMS Serial Configuration interface Multiple Vdd, pins noise reduction Separate Tri-State testing
Vdd0 Sdram0 Sdram1 Vss0 Vdd1 Sdram2 Sdram3 Vss1 Vdd4 Sdram16 Vss4 Vddiic Sdata
CKBF-M
Vdd9 Sdram15 Sdram14 Vss9 Vdd8 Sdram13 Sdram12 Vss8 Vdd5 Sdram17 Vss5 Vssiic Sclock
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Table CKBF Description Table
Package -22, -Qty Package output output output output output input input power SDRAM [0-3] SDRAM [4-7] SDRAM [8-11] SDRAM [12-15] SDRAM [16-17] buf_in Sdata Sclock [0-9] SDRAM Byte clock output SDRAM Byte clock output SDRAM Byte clock output SDRAM Byte clock output SDRAM clock outputs useable feedback Input 1-18 buffer Tri-States outputs when held Data circuitry Clock circuitry Volt Power Supply SDRAM buffer Ground SDRAM buffer Type Symbol Description
ground
[0-9]
power ground Reserved
Vddiic Vssiic Reserved
Volt Power Supply circuitry Ground circuitry Reserved future modifications
Notes:
names above table reflect likely internal power ground partition reduce effects internal noise performance device. reality, platform will configured with pins tied common 3.3V supply pins common. Reserved pins should true no-connects. treated open circuit current system platforms. There exte rnal device requirements these pins. Possible option includes additional control inputs bank select capability.
Table CKBF Functionality
Notes:
Used test purposes only. Buffer Non-inverting.
SDRAM[0-3] Hi-Z buf_in
SDRAM[47] Hi-Z buf_in
SDRAM[8-11] Hi-Z buf_in
SDRAM[12-15] Hi-Z buf_in
SDRAM[16-17] Hi-Z buf_in
Notes
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8.2.1 CKBF Default Conditions
power SDRAM outputs enabled active. should have >100 internal pull-up resistor keep outputs active. Sdata Sclock inputs should both also have internal pull-up resistors with values above 100K Ohms well complete platform flexibility.
Table 8-10 CKBF Driver types used SDRAM Driver Type Symbol SDRAM [0-17] Description SDRAM outputs
8.2.2 CKBF Serial Configuration
serial bits will read clock driver following order: Byte Bits Byte Bits Byte Bits
unused register bits (reserved N/A) should designed don't care. expected that controller
will force these bits level.
register bits labeled "Initialize must written zero during initialization. Failure
result higher then normal operating current. controller will read back last written value.
Byte SDRAM Active/Inactive Register enable, disable) Notes:
Inactive means outputs held disabled from switching. These outputs designed configured power-on expected configured during normal modes operation,
CKBF CKBF
Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Description Initialize Initialize Initialize Initialize (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
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CK97 Clock Synthesizer Design Guidelines
Byte SDRAM Active/Inactive Register enable, disable) Notes:
Inactive means outputs held disabled from switching. These outputs designed configured power-on expected configured during normal modes operation,
CKBF
CKBF
Name SDRAM15 SDRAM14 SDRAM13 SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Initialize Initialize Initialize Initialize
Byte Optional Register Possible Future Requirements Notes:
Inactive means outputs held disabled from switching. These outputs designed configured power-on expected configured during normal modes operation.
CKBF
CKBF
Name SDRAM17 SDRAM16 Reserved Reserved Reserved Reserved Reserved Reserved
Description (Active/Inactive) (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved
Description (Active/Inactive) (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved
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CKBF Power Management following power-consumption conditions device should provided each vendor. values below estimates target specifications. Estimates based upon SSOP devices.
CKBF Condition Clock Mode (buf_in Vddq3 Vss) Internal Circuitry Active Active 66MHz (buf_in 66.66 MHz) Active 100MHz (buf_in 100.00 MHz)
3.3V supply consumption discrete loads Vddq3 3.465V static inputs Vddq3 Vss.
230mA 360mA
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Appendix CK100-SM Pinout Mobile Buffer Characteristic CK100-SM SSOP Pinout following Addendum defines generic pinout base requirements Intel Architecture based mobile computing platforms. intended alternate solution SSOP CK100-M clock drivers described Appendix This solution contains spread spectrum functionality outputs package. spread spectrum will apply only those clocks that synchronize processor clocks (CPU, SDRAM clocks). spread spectrum will affect asynchronous clocks (Reference MHz). This addendum also used example development other custom clock synthesizer/driver components. This only solution that derived.
8.5.1 Features SSOP Package):
Copies Clock Five Copies Clock (Synchronous w/CPU Clock) Copy free running Clock (Synchronous w/CPU Clock) Copies Ref. Clock @14.31818 Copy Copy selectable 48/24 Ref. 14.31818MHz X'tal Oscillator Input 100MHz 66MHz operation Power Management Control Input Pins Isolated core Vdd, pins noise reduction
Vssref XTAL_IN XTAL_OUT PCICLK PCICLK1 PCICLK2 Vsspci Vddpci PCICLK3 PCICLK4 PCICLK5 Vdd48 48MHz 48-24MHz/TS#
CK100-SM
Vddref REF1/SEL48# REF0/Spread# Vddcpu 2.5V CPUCLK0 Logic CPUCLK1 Vsscpu Vsscore PCISTOP# Vddcore CPUSTOP# PWRDWN# SEL100/66# Vss48
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CK97 Clock Synthesizer Design Guidelines
July 1998
Table 8-11 CK100-SM Description Table
Package Power Input Output Output Output Power Power Power Output Output Vssref XTAL_IN XTAL_OUT PCICLK_F PCICLK [1-5] Vsspci Vddpci Vdd48 48MHz 48-24MHz/TS# Ground 14.318 reference clock outputs 14.318 Crystal input 14.318 Crystal output 3.3V free running clock output 3.3V Clock outputs Ground clock outputs 3.3V power clock outputs 3.3V power 48/24 clocks 3.3V 48MHz clock output 3.3V output Tri-state strapping option (see note Strap Enter Tri-State mode testing, Strap High Normal operation. Power Input Input Input Power Input Power Power Output Power Output Vss48 SEL100/66# PWRDWN# CPUSTOP# Vddcore PCISTOP# Vsscore Vsscpu CPUCLK[1-0] Vddcpu REF0/Spread# Ground 48/24MHz clocks Select enabling 100MHz 66MHz clock High =100MHz, =66MHz Device enters power down mode when When signal Low, stop clocks state Isolated 3.3V power core When signal LOW, Stops clocks state except PCICLK_F output Isolated ground core Ground clock outputs 2.5V clock outputs 2.5V power clock outputs 3.3V 14.318 reference clock output poweron spread spectrum enable strap option (see note Strap Spread spectrum clocking enable, Strap High Spread spectrum clocking disable. Output REF1/SEL48# 3.3V 14.318 reference clock output poweron 48/24 select strap option (see note output when strapped Low, output when strapped High. Power Vddref 3.3V power 14.318 reference clock outputs Type Symbol Description
Notes:
names above table reflect likely internal power ground partition reduce effects internal noise
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CK97 Clock Synthesizer Design Guidelines
performance device. reality, platform will configured with same voltage pins tied common supply pins being common. Vdd/Vss naming convention above done show pinout dominated need isolate signals. output frequency this dependent power strapping option output when power strapped output when strapped High. This also serve Tri-Sate strapping option during power configuration. CK100-SM will sample value this during power Strapped Tri-State mode high normal operation. pull up/down resistor value this shall 100K Ohms. dual function pin. During power clock outputs disabled, CK100-SM will sample spread spectrum enable/disable strapping option. After strapped value latches, clock outputs will enabled simultaneously this will become 14.318 reference clock output. Power latency needs less than after supply voltage stabilized. external pull up/down resistor value this shall 100K Ohms. dual function pin. During power clock outputs disabled, CK100-SM will sample "48/24 clock output frequency strapping option. After strapped value latches, clock outputs will enabled simultaneously this will become another 14.318 reference clock output. Power latency needs less than after supply voltage stabilized. external pull up/down resistor value this shall 100K Ohms.
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CK97 Clock Synthesizer Design Guidelines
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8.5.2 Mobile Clock Buffer Specifications: Volt, Volt Clocks
curves, Trise/Tfall specifications targeted achieving acceptable switching behavior under load conditions described section this specification. Pull-up pull-down sides each buffers have separate curves which provided following sections. drive curve specifies steady state conditions that must maintained, does indicate real output drive strength. parameters must guaranteed under transient switching (AC) conditions. sign current parameters (direction current flow) referenced ground inside component; i.e. positive currents flow into component while negative currents flow component. mobile clock buffer characteristics same desktop version (CK100) with exception SDRAM clock buffers. Mobile platforms should buffer characteristic supplied this appendix simulation along with Intel mobile layout guideline (document title: MOBILE PENTIUM® PROCESSOR/440BX AGPSET ADVANCED PLATFORM RDDP-a) layout.
Buffer Name (mobile) 48MHz, SDRAM (mobile)
Range 2.375 2.625 3.135 3.465 3.135 3.465 3.135 3.465
Impedance (Ohms) 17.3 4.7- 12.3
Buffer Type Type Type Type Type
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CK97 Clock Synthesizer Design Guidelines
8.5.3 Type Mobile (2.5V) Buffer Characteristics
Table 8-12 Type Mobile Clock Buffer Operating Requirements
Symbol Iohmin Iohmax Iolmin Iolmax Parameter Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current 2.5V Type Output Rise Edge Rate 2.5V Type Output Fall Edge Rate Condition Vout Vout 2.375 Vout Vout 2.5V 0.4V 2.0V 2.5V 2.0V 0.4V V/ns Units V/ns Notes
Notes:
Intended approximate impedance curve below. Device should checked against entire curve characterization testing. Production testing expected subset characterization testing. Output rise fall time. Figure calculation measurement information. Output rise fall time must guaranteed across process temperature range. Receiver logic thresholds Vil=0.7 Vih=1.7 Volts. 6.8-17.3 with nominal driver impedance. Vout/Ioh, Vout/Iol measured VCC/2.
Voltage 2.28 2.375 2.625
Pull-Up I-min (mA) -78.7 -58.3 -46.3 -27.4 -16.4
I-typ (mA) -149.8 -149.8 -149.8 -149.8 -148 -143 -138 -128.1 -118.9 -113.9 -103.6 -91.5 -78.9
I-max (mA) -214 -214 -214 -214 -210 -205 -196 -186 -173 -162.7 -147.9 -131.1 -113 -94.7
Mobile Pull-Up
-100
-150
-200
-250
Vout
Figure Type Mobile Clock Output Buffer Pull-Up Characteristics
Notes:
Must meet temperature voltage range specified Table Operating Requirements. This drawing scale. Comparisons should made data provided table next this drawing Table 8-12 Type Mobile Clock Buffer Operating Requirements.
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CK97 Clock Synthesizer Design Guidelines
July 1998
Pull-Down Voltage 2.375 2.625 I-min (mA) 77.9 82.7 85.6 I-typ (mA) 154.8 I-max (mA) 212.5 223.1
Mobile Pull-Down
Vout
Figure Type Mobile Clock Output Buffer Pull-Down Characteristics
Notes:
Must meet temperature voltage range specified Table Operating Requirements. This drawing scale. Comparisons should made data provided table next this drawing Table Type Mobile Clock Buffer Operating Requirements.
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CK97 Clock Synthesizer Design Guidelines
8.5.4 Type Mobile SDRAM (3.3 Clock Buffer Characteristics
Table 8-13 Type Mobile SDRAM Clock Operating Requirements
Symbol Iohmin Iohmax Iolmin Iolmax trhSDRAM Parameter Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current 3.3V Type Output Rise Edge Rate. Mobile SDRAM ONLY. 3.3V Type Output Fall Edge Rate. Mobile SDRAM ONLY. Condition Vout Vout 3.135 Vout 1.0V Vout 3.3V 0.4V 2.4V 3.3V 2.4V 0.4V V/ns 85.5 Units V/ns Notes
tfhSDRAM
Notes:
Intended approximate impedance curve below. Device should checked against entire curve characterization testing. Production testing expected subset characterization testing. Output rise fall time. Figure calculation measurement information. Output rise fall time must guaranteed across process temperature range. Receiver logic thresholds Vil=0.8 Vih=2.0 Volts. 4.7-12.3 with nominal driver impedance. Vout/Ioh, Vout/Iol measured VCC/2. 1.5V/nS required meet 1.2V/nS minimum rise/fall time SDRAM input. This required guarantee SDRAM component timings which tested/specified with maximum 1.2nS from 0.8V 2.0V threshold levels.
Voltage 3.18 3.465
Pull-Up I-min (mA) -113 -110.5 -104.1 -101.2 -98.3 -93.7 -89.3 -79.1 -52.7 -41.1 -14.7 -8.7
I-typ (mA) -214.9 -190.2 -169.7 -164 -158.3 -152.7 -147 -141.4 -135.7 -101.8 -87.7 -44.8 -19.3
I-max (mA) -330.6 -292.6 -261 -252.3 -243.6 -234.9 -226.2 -217.5 -208.8 -160 -130.5 -71.3 -24.1
Mobile SDRAM Pull-Up
-100
-150
-200
-250
-300
-350
Vout
Figure Type Mobile SDRAM Clock Output Buffer Pull-Up Characteristics
Notes:
Must meet temperature voltage range specified Table Operating Requirements. This drawing scale. Comparisons should made data provided table next this drawing Table Type Mobile SDRAM Clock Operating Requirements.
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CK97 Clock Synthesizer Design Guidelines
July 1998
Voltage 3.135 3.465
Pull-Down I-min (mA) 56.5 135.6 135.6
I-typ (mA) 85.3 106.4 124.5 152.3 158.3 162.8 170.5 175.9 179.6 203.4 206.4 207.1
I-max (mA) 85.5 121.8 177.8 217.5 226.2 232.6 243.6 251.3 256.5 290.6 294.9 295.8 295.8
Mobile SDRAM Pull-Down
Vout
Figure 8-10 Type Mobile SDRAM Clock Output Buffer Pull-Down Characteristics
Notes:
Must meet temperature voltage range specified Table Operating Requirements. This drawing scale. Comparisons should made data provided table next this drawing Table 8-13 Type Mobile SDRAM Clock Operating Requirements.
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CK97 Clock Synthesizer Design Guidelines
Appendix SSOP Package Data
SSOP: Table Dimensions (inches, unless otherwise specified) Body (300mil) 0.291 0.299 0.395 0.420 0.009 0.013 0.020 0.040 Symbol 0.620 0.630 0.095 0.110 0.008 0.016 0.025 0.008 0.012
EIAJ SSOP: Table Dimensions (inches, unless otherwise specified) Body Symbol 0.197 0.291 0.009 0.025 0.390 (200mil) 0.220 0.323 0.013 0.041 0.413 0.079
0.002
0.65
0.009 0.015
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UNITED STATES, Intel Corporation 2200 Mission College Blvd., P.O. 58119, Santa Clara, 95052-8119 Tel: 765-8080 JAPAN, Intel Japan K.K. Tokodai, Tsukuba-shi, Ibaraki-ken 300-26 Tel: 81-29847-8522 FRANCE, Intel Corporation S.A.R.L. Quai Grenelle, 75015 Paris Tel: 1-45717171 UNITED KINGDOM, Intel Corporation (U.K.) Ltd. Pipers Way, Swindon, Wiltshire, England Tel: 1-793-641440 GERMANY, Intel GmbH Dornacher Strasse 85622 Feldkirchen/ Muenchen Tel: 89/99143-0 HONG KONG, Intel Semiconductor Ltd. 32/F Pacific Place, Queensway, Central Tel: +852 2844-4555 CANADA, Intel Semiconductor Canada, Ltd. Attwell Drive, Suite Rexdale, Ontario Tel: +416 675-2438

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