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The Pentium® II Xeon Processor Server Platform System Management Guide

June 1998 Intel Corporation

The Pentium® II Xeon Processor Server Platform System Management Guide
June 1998 Intel Corporation
Order Number: 243835-001
The Pentium ®II Xeon Processor Server Management Guide
I C is a two-wire communications bus / protocol developed by Philips. SMBus is a subset of theC bus / protocol and was developed by I 2 Intel. Implementations of the IC bus / protocol or the SMBus bus / protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
The Pentium ®II Xeon Processor Server Management Guide
Table Of Content
The Pentium ®II Xeon Processor Server Management Guide
List Of Tables Table 1, Processor Information ROM Data Position and Format .................................... 20
Reference Documents
Additional information on the topics discussed here may be obtained through: · · · · · · · Pentium® II Xeon Processor at 400MHz, Order Number 243770-001. Wired for Management, Intel Corporation. http://www.intel.com / managedpc Intelligent Platform Management Interface Specification , 1997, Intel Corporation. http://developer.intel.com / design / servers / ipmi / index.htm Web-Based Enterprise Management (WBEM). http://www.microsoft.com, http://www.freerange.com Desktop Management Task Force, DMI Rev.2.0. http://www.dmtf.org The I2C Bus and How to Use It, January 1992, Signetics / Philips Semiconductor. System Management Bus Specification , Intel Corporation. http://developer.intel.com / ial / powermgm / specs.htm
The Pentium ®II Xeon Processor Server Management Guide
1. System Management Overview
The Pentium ®II Xeon Processor Server Management Guide
1.0 Introduction
This information can also be used to automatically configure processor voltage, temperature, and frequency monitoring to match the specified operating ranges. Products that take advantage of this capability can eliminate manual configuration of these ranges as part of system integration or field upgrades.
The Pentium ®II Xeon Processor Server Management Guide
2.0 Software Elements of Server Platform Management
The Pentium ®II Xeon Processor Server Management Guide
3.0 Hardware Elements of Server Platform Management
In a server platform, the system management goal of reducing total cost of ownership (TCO) is measured by metrics associated with RASUM: · · · · · Reliability: Continuous self-checking and data correction, extensive redundancy for higher reliability Availability: Up-time, automatic data correction, failure tolerance, error-alerting mechanism, boot resiliency Serviceability: Fault detection and rapid repair Usability: Flexibility in customization Manageability: Availability of detailed information about the platform components and characteristics. Address asset management, inventory tracking, and configuration management
3.1 Common Platform Architecture
The first server management specification aimed at common platform architecture of a managed platform is the "Intelligent Platform Management Interface, " or IPMI. Implementing an IPMI architecture is just one example of many implementations that can be used to exploit the unique management features of the Pentium II Xeon processor. The IPMI specification is comprised of three sub-specifications, which define the interface to the platform hardware (IPMI), the internal intelligent platform management bus (IPMB), and the external bus for connecting additional IPMI-enabled systems. The bus operates autonomously the critical sensors and events are monitored and logged even if the processor is not operating and system management software is not available. IPMI defines a common interface and message-based protocol for accessing platform management hardware. This reduces TCO by improving server platform management functionality and compatibility while de-coupling the hardware and software. This allows hardware advances without impacting server management software.
The Pentium ®II Xeon Processor Server Management Guide The Pentium II Xeon processor interfaces the PRIOM, Scratch EEPROM and thermal sensor to a baseboard BMC through the SMBus interface. The SMBus, which is a two-wire bus interface and a subset of the industry-standard I2C serial bus, is compatible with the IPMI private management bus interface protocol. This allows a seamless, low-cost connection of the management components. The major building blocks of an IPMI manageable platforms are:
1. Baseboard Management Controller (BMC): A micro-controller connected to the
platform management components in the system through a private bus, typically an I2C or SMBus, or other direct connection. The controller operates autonomously, providing automatic monitoring and recovery functions independent of the system processors, system software, or operating system. This controller is typically mapped as an I / O device in the system interfacing with the central processing unit through the ISA bus. The baseboard management controller firmware is either download-able or permanently resident in the BMC.
2. System Interface Ports: Typically an I / O-mapped interface to the ISA bus. This
provides a standardized set of registers that provides communication between instrumentation software and the platform management hardware.
3. System Management Software (SMS): Software executing on the system that
interprets management application requests to retrieve management information and set management parameters. In addition to providing the interface to the platform management hardware, system management software typically provides access to management information from BIOS, add-in cards, and the operating system, as well.
4. Private Management Bus (PMB): Means by which the system management software
communicates with the manageable devices typically an I2C or SMBus. Access to the manageable devices is accomplished by establishing command communication with the BMC through the system interface ports. The BMC interprets requests from system management software and performs the requested operation on the targeted Private Management Bus device.
5. Sensors: Voltage, temperature and fan speed sensors are typical data-retrieving devices
The Pentium ®II Xeon Processor Server Management Guide
Figure 1. outlines an example block diagram of hardware interconnects of a managed server platform
System Bus Cache Processor core Thermal Sensor PIROM Scratch EPROM Voltage, Temperature, Fan Sensors IPMB Power Button Chassis Intrusion Private Management Bus (SMbus)
Cache Processor core Thermal Sensor PIROM Scratch EPROM
Reset Button
Cache Processor core Thermal Sensor PIROM Scratch EPROM
Baseboard Management controller (BMC)
System Event Log
ISA bus and sideband signals
Cache Processor core Thermal Sensor PIROM Scratch EPROM System Controller North Bridge PCI Peripheral controller South Bridge
Figure 1. Example Block Diagram of Hardware Interconnects of a Managed Server Platform
The Pentium ®II Xeon Processor Server Management Guide
4.0 Pentium® II Xeon Processor Manageability Features
The Pentium® II Xeon processor maintains all the management features offered in previous generations of processors system management mode (SMM), functional redundancy checking (FRC), low power states and clock control (halt, stop grant and sleep states), and advances processor manageability by integrating the following management features: · · · · System Management Bus Processor Information ROM Scratch EEPROM Thermal Sensor Devices
The Pentium ®II Xeon Processor Server Management Guide The Pentium II Xeon processor enables system management software to utilize the PIROM information for generating databases, which enhances inventory control and tracking and networked server platform configuration. This data includes: · · · · · · · · S-spec / QDF number Processor core family Processor core model Processor core stepping Cache / tag stepping ID Cartridge revision Substrate revision software ID Processor part number
This information can also be used to automatically configure processor voltage, temperature, and frequency monitoring to match the specified operating ranges. Products that take advantage of this capability can eliminate manual configuration of these ranges as part of system integration or field upgrades.
Processor Core Thermal Diode
SMBus Processor Information ROM PIROM Thermal Sensor Device
Scratch EPROM
VCC SMbus Write Protec SMBDATA, SMBCLK SA0, SA1, SA2 SMBALERT
Figure 2. Block Diagram of The Pentium ® II Xeon Processor Management Components
The Pentium ®II Xeon Processor Server Management Guide
4.1 System Management Mode (SMM)
SMM is a feature preserved from previous generations of Intel processors. Server platform designers may choose to use SMM in various system management applications. One example might be to use the SMM error recovery mechanism. In the event of detected internal errors, address parity errors or system bus multi-bit data errors, an SMM routine may be deployed to identify the source of the error, log the error, and disable malfunctioning hardware pieces. Another use of SMM is to flush out the processor data cache content in an attempt to preserve the data of an ailing processor.
4.2 Functional Redundancy Checking (FRC)
Functional Redundancy Checking (FRC) allows two Pentium II Xeon processors to be configured as a pair, with one processor acting as the master and the other as a checker. The pair operates as a single processor, increasing system fault detection and data integrity. In the case of a mismatch between the processors, the checker processor asserts FRCERR. This triggers the master processor to issue a Machine Check Exception (MCE), which results in a software fault detection and prevention mechanism to log and possible recover from the error. When this condition occurs, system management may choose to alert the system administer via system management instrumentation tools.
4.3.0 Low Power States and Clock Control
The Pentium II Xeon processor allows three power-down states: · · · HALT Stop-Grant Sleep
4.3.1 Auto-Halt Power-Down State
The first power-down state is entered by executing the HALT instruction. In this state, while the processor is halted, it continues to snoop the internal cache, allowing normal system operation. Depending on the stability of the system temperature, system management may choose to bring the processor back to a normal operating environment by issuing a System Management Interrupt (SMI), or it may choose to enter a lower level power state by going through the stop-clock / stop-clock acknowledge protocol, and entering the stop-grant state.
4.3.2 Stop-Grant State
The Stop-Grant state is entered by asserting the Stopclk# input and receiving a Stop-Clock Acknowledge from the processor. This state is entered from either the normal operating mode or from the Auto HALT power-down state. This is the second-level power-down state where the processor continues to snoop its internal cache and allow system operation. In the case of continuous temperature instability, the system management software may choose to enter the Sleep state. This preventive measure protects the processor from permanent damage.
The Pentium ®II Xeon Processor Server Management Guide
4.3.3 Sleep State
4.4 System Management Bus (SMBus)
The Pentium II Xeon processor incorporates an SMBus interface, which allows access to management components such as the PIROM, Scratch EEPROM and thermal sensor residing on the processor substrate. This addition is a major enhancement to the Pentium II Xeon processor cartridge, which provides mission-critical data to system management software, enabling implementation of advanced instrumentation and superior RASUM. The SMBus enables thermal monitoring, PIROM access, and Scratch EEPROM access, all via a common two-wire interface.
4.4.1 Processor Information ROM (PIROM)
Provide component authentication which can be a preventive measure against manufacturing and installation flaw.
The Pentium ®II Xeon Processor Server Management Guide
4.4.1.1 PIROM Processor Data
The PIROM processor information provides key information identifying cartridge specifications and characteristics that benefit system management in the areas of asset management, configuration management, server management, and inventory management. Data contained in this segment of the PIROM include: · · · Engineering sample processor versus production processor S-spec or Qualification Detail Form (QDF) number Checksum
These data identify the processor core as either an engineering sample, with the Qualification Detail Form (QDF) number along with specification revision or a production silicon. Management tools may use the PIROM processor data to closely match the installed processors in a server platform. The PIROM processor data can be used for inventory or configuration management, outlining detail information, such as the S-spec, of the Pentium II Xeon processor cartridges installed. The checksum byte validates accuracy and reliability of the data programmed in this segment of the PIROM.
4.4.1.2 PIROM Core Data
The PIROM core data provides key information identifying core specifications and characteristics that benefit system management in the areas of asset management, configuration management, performance management, and inventory management. The PIROM core contains: · · · · · · · · Processor core type Processor core family Processor core model Processor core stepping Maximum core frequency Core voltage I.D. Core voltage tolerance, high and low Checksum
The Pentium ®II Xeon Processor Server Management Guide processors. The checksum byte validates accuracy and reliability of the data programmed in this segment of the PIROM.
4.4.1.3 PIROM L2 Cache Data
The PIROM Level 2 (L2) cache data provides key information about the cartridge L2 cache specification and its characteristics. This information benefits system management in the areas of asset management, configuration management, performance management, and inventory management. The data in this segment of the PIROM includes: · · · · · · Level 2 cache size Number of synchronous RAM components Level 2 cache voltage I.D. Level 2 cache voltage tolerance, high and low Cache / tag stepping I.D. Checksum
4.4.1.4 PIROM Cartridge Data
The PIROM cartridge cache data provides key information identifying cartridge specification and characteristics that benefits system management in the areas of asset management, inventory management and configuration management. This includes: · · · Cartridge revision Substrate revision Checksum
The PIROM cartridge data provides the means of cross-checking the cartridge substrates installed in a server platform ensuring uniform installation. This information may also be used for instrumentation and platform configuration management, as well as inventory control and system management. System administrators may choose to use this data in identifying the cartridges required for upgrade due to
The Pentium ®II Xeon Processor Server Management Guide obsolescence or design improvements. The checksum byte validates accuracy and reliability of the data programmed in this segment of the PIROM.
4.4.1.5 PIROM Part Numbers Data
The PIROM part number data provides key information identifying cartridge specification and characteristics that benefit system management, asset management, security management and configuration management. This data includes: · · · · Processor part number Processor BOM I.D. Processor electronic signature Checksum
4.4.1.6 PIROM Thermal Reference Data
The PIROM thermal reference data provides key information that identifies cartridge specification and characteristics that benefits system management in the areas of reliability and configuration management. The is data includes: · · Processor thermal reference byte Checksum
The Pentium ®II Xeon Processor Server Management Guide
4.4.1.7 PIROM Features Data
The PIROM feature data provides key information identifying cartridge features enabled in the PIROM. The system management software uses these bytes to ensure validity of data in each segments of the PIROM. · · Processor core features flag Cartridge feature flags: · Electronic signature present · Thermal sensor present · Thermal reference byte present · Scratch EEPROM present · L2 cache VID present Checksum
System management software must use these data to validate the PIROM content for each of the segments. The checksum byte validates accuracy and reliability of the data programmed in this segment of the PIROM.
The Pentium ®II Xeon Processor Server Management Guide
Header
Byte 00h
Processor
L2 Cache
Cartridge
Part Numbers
Thermal Ref.
Features
Function Data Format Revision EEPROM Size Processor Data Address Processor Core Data Address L2 Cache Data Address SEC Cartridge Data Address Part Number Data Address Thermal Reference Data Address Feature Data Address Other Data Address Reserved Checksum S-spec / QDF Number Sample / Production Reserved Checksum Processor Core Type Processor Core Family Processor Core Model Processor Core Stepping Reserved Maximum Core Frequency Core Voltage ID Core Voltage Tolerance, High Core Voltage Tolerance, Low Reserved Checksum Reserved L2 Cache Size Number of SRAM Components Reserved L2 Cache Voltage ID L2 Cache Voltage Tolerance, High L2 Cache Voltage Tolerance, Low Cache / Tag Stepping ID Reserved Checksum Cartridge Revision Substrate Revision Software ID Reserved Checksum Processor Part Number Processor BOM ID Processor Electronic Signature Reserved Checksum Thermal Reference Byte Reserved Checksum Processor Core Features Flags Cartridge Feature Flags
Number of Devices in TAP Chain Reserved Checksum
Table 1, Processor Information ROM Data Position and Format
The Pentium ®II Xeon Processor Server Management Guide
4.4.2 Scratch EEPROM
The presence of scratch EEPROM (128 bytes of EEPROM) on the Pentium II Xeon processor allows system management software to store data on the processor cartridge. The Scratch EEPROM interfaces to the system management controller through the SMBus. The write-protect pin on the cartridge-edge fingers may be used by the controller on the baseboard to write-protect data in the scratch EEPROM. The EEPROM can be used to store a unique asset tag for the processor. For example, system management software may choose to store an encoded data that allows it to implement a tracking mechanism for the processors on a specific baseboard. The following flow diagram outlines this implementation, which is an attempt to prevent the unauthorized removal of the cartridge from the baseboards:
System Power Up
Re d PI ROM a Ele ctronic I .D
Pe rform OEM Spe cific Enc ing od Ye s Che k EEPROM da c ta a inst Fla d ta ga sh a No Ma tch Set Fla g, I nform Syste Administra m tor
Me ge to use sugge ssa r sting to e ble Se urity Environme na c nt
Sa the va in EEPROM ve lue a Ba boa Fla nd se rd sh
Match
Set Fla in EEPROM a g nd Continue
4.4.3 Thermal Sensor Device
The Pentium II Xeon processor includes a thermal sensor on the substrate of the cartridge. This device interfaces with the system management controller through the SMBus. This approach benefits processor thermal management by providing improved degrees of accuracy and correlation with
The Pentium ®II Xeon Processor Server Management Guide
5.0 Pentium® II Xeon Processor Manageability Benefits
5.1 The Pentium® II Xeon Processor Fits Common Platform Architecture
Addition of the SMBus to the Pentium II Xeon processor cartridge, allows seamless integration with an IPMI architecture, through BMC via a private management bus. The communication is a standard I2C serial bus protocol and is readily supported using other management hardware implementations. Using the Pentium II Xeon processor, together with an IPMI architecture, materializes benefits of the common platform architecture-based system management implementation. This allows: · · · Flexible access to platform management information Industry open implementation for easier server-platform instrumentation De-coupling server management software from hardware, which enables the hardware to change without impacting the software Reduced development time for new products and enabling remote management
5.2 The Pentium® II Xeon Processor Benefits Asset Management
Server platforms with the Pentium II Xeon processor provide detailed information about the cartridge, which helps IT manager perform asset tracking by: · · · · · · · · Cartridge part-number BOM ID the cartridge is built on Electronic signature of the cartridge Cartridge substrate revision Cartridge revision Cartridge cache size Processor core type Cartridge QDF number
The Pentium ®II Xeon Processor Server Management Guide This enables IT managers to build an extensive database on their existing inventory of Pentium II Xeon processor-based server platforms, re-arrange high-end server platform to high performance demanded users and detecting the nodes which need to be upgraded or serviced.
5.3 The Pentium® II Xeon Processor Benefits Configuration Management
Processor information allows the creation of a configuration manager that can inspect the installed Pentium II Xeon processors in a given server platform by reading back information about the cartridge: · · · · Core type and stepping Maximum core frequency Level 2 cache size Cartridge voltage requirements
The configuration manager can use this information for checking the installed processors are of the same kind, and configured to operate at the maximum clock frequency. This results in best system resource optimization. Additional mechanisms may be deployed to alert the system administrator of inefficient system usage and possible processor over-clocking conditions.
5.4 The Pentium® II Xeon Processor Benefits Inventory Management
Server platforms with the Pentium II Xeon processor provide detailed information about the cartridge installed in the platform, which helps IT manager in determining: · · · · · · · · Cartridge part-number Cartridge BOM ID Cartridge Electronic signature Cartridge substrate revision Cartridge revision Cartridge cache size Processor core type Cartridge QDF number
Using this information, IT managers can build an extensive database of Pentium II Xeon processorbased servers, optimizing performance level by matching demanding users with the most highpowered servers. IT managers may also use such a database for detecting and eliminating obsolete components.
5.5 The Pentium® II Xeon Processor Benefits Performance Management
Server platforms with the Pentium II Xeon processor provide detail information about the cartridge installed in the platform, which enables IT managers to determine: · · · Maximum clock frequency Processor core type L2 cache size
IT managers may choose to use this data to ensure that processors of the same kind and performance are being used on the same node to prevent under-utilization of any processor cartridge.
5.6 The Pentium® II Xeon Processor Benefits Security Management
The Pentium II Xeon processor cartridge with the electronic signature and Scratch EEPROM allows the creation of system management software that ties the cartridge to a specific baseboard. This prevents
The Pentium ®II Xeon Processor Server Management Guide unauthorized replacement of the cartridge from the nodes in restricted operating environments, or as a tool for aiding warranty tracking and repair.
5.7 The Pentium® II Xeon Processor Benefits Server Management
The Pentium ®II Xeon Processor Server Management Guide
APPENDIX A
A.1 Management Initiatives Background
The first management initiative primarily focused on cross-platform system management was first introduced by the Desktop Management Task Force(DMTF) a consortium of more than 100 vendors established in 1992 committed to make computing platforms easier to use, configure and manage. The DMTF developed the Desktop Management Interface (DMI) focusing on defining and standardizing software aspects of system management implementation. Earlier protocols, such as the Simple Network Management Protocol (SNMP), is complemented by the DMI. The DMI-to-SNMP mapping software is available that allows the DMI-based instrumentation to be cleanly integrated into the SNMP-based management environments. Since then additional system management initiatives, i.e., Wired for Management (WfM), Web-Based Enterprise Management (WBEM), Zero Administration Windows Initiative(ZAW) were formed with a common focus of utilizing system management as the primary means of reducing the Total Cost of Ownership (TCO). The first server management specification aimed at creating an industry open hardware implementation of a managed platform is the "Intelligent Platform Management interface" or IPMI. The IPMI specification defines a common interface and a message-based protocol for accessing platform management hardware. This helps reduce TCO by improving server platform management functionality and compatibility, while de-coupling the hardware implementation from the software. IPMI, an industry open based implementation, allows hardware advancements be implemented without impacting server management software.
A.2.0 Manageability and Management Areas
Manageability is defined as the use of technologies and products to enhance server RASUM (Reliability, Availability, Serviceability, Usability and Manageability), thus increasing up-time and reducing the cost of deployment, ownership and administration. Manageability rests on having a range of products, systems and system components working together to provide information and interfaces that system management software, management applications and operating systems can use to improve RASUM. Manageability includes asset management, configuration management, inventory management, network management, performance management, security management, server management and system management.
A.2.1 Asset Management
Asset management is the process of maximizing the use of assets to produce revenue while minimizing overall costs. Manageable Server platforms contribute to asset management by capturing inventory and tracking information, enabling organizations to analyze key cost variables and better discern the return on investment (ROI) of their technology purchases. The data gathered by manageable systems can assist asset management issues such as inventory consolidation and rationalizing license issues, leasing considerations, analyzing training costs, analyzing software upgrades for volume purchasing plans, evaluating the cost-efficiency of outsourcing and improving warranty usage.
A.2.2 Configuration Management
The Pentium ®II Xeon Processor Server Management Guide
A.2.3 Inventory Management
A.2.4 Network Management
Network management is one of the three major components of managing a computing environment. Network management includes the performance, configuration, security, failure analysis and repair of the infrastructure components such as switches, routers, bridges and gateways in a LAN, WAN or Internet / Intranet. Network management is a related, but different management area than "System Management" that focuses on the management of the computer system hardware and applications rather than the network.
A.2.5 Performance Management
Performance management analyzes usage pattern and attempts to optimize system responsiveness and network throughput. This enables IT to remotely monitor CPU utilization and pinpoint the user, application or process that is generating the excessive demand.
A.2.6 Security Management
Security management addresses the need to protect systems and data from unauthorized access. Examples include encryption, authentication, and firewalls.
A.2.7 Server Management
Server management aims to optimize the RASUM and performance of network servers and includes monitoring such factors as disk capacity and user accounts. Server hardware management includes reliability and failure tolerance features that are not commonly found in desktop systems. This includes features such as multiprocessor monitoring and recovery features, redundant cooling (fan) and power supply management, redundant driver array (RAID) management, multiple system board management and field replaceable unit identification, and multiple chassis management.
A.2.8 System Management
System management refers to controlling, configuring, installing and monitoring the applications, servers and clients in a distributed computing environment.
The Pentium ®II Xeon Processor Server Management Guide
APPENDIX B
B.1 Example DMI Software Stack
The DMI architecture defines the following software stack between the application software and managed components. The manageable feature is specified in a standard ASCII text file format called Management Information Format (MIF). Additional information can be obtained from the Desktop Management Task Force via their web site at http://www.dmtf.org. The DMI software stack illustration is following:
Management console
Management Application(MA)
LAN Management Application
(API)
Management Interface (MI)
(Local program) Service Provider (SP) MIF Dbase
(API) Component Interface (CI)
Pentium (R) II Xeon(TM) Processor #1
Pentium (R) II Xeon(TM) Processor #2
Pentium (R) II Xeon(TM) Processor #3
Pentium (R) II Xeon(TM) Processor #4
Other Manageable products, i.e. (O.S., Software Application, Hardware products)
Figure 3, Flow diagram of DMI software stack
1- Management Application (MA): Program that initiates management requests. The MA uses the
2- Management Interface(MI): An API that provides the interface between the Service Layer and
management applications and allows these applications to access, manage and control the platform components. The MI offers a consistent interface for any management application to the various mechanisms used to obtain information from products and components within a platform.
The Pentium ®II Xeon Processor Server Management Guide
UNITED STATES, Intel Corporation 2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119 Tel: +1 408 765-8080 JAPAN, Intel Japan K.K. 5-6 Tokodai, Tsukuba-shi, Ibaraki-ken 300-26 Tel: + 81-29847-8522 FRANCE, Intel Corporation S.A.R.L. 1, Quai de Grenelle, 75015 Paris Tel: +33 1-45717171 UNITED KINGDOM, Intel Corporation (U.K.) Ltd. Pipers Way, Swindon, Wiltshire, England SN3 1RJ Tel: +44 1-793-641440 GERMANY, Intel GmbH Dornacher Strasse 1 85622 Feldkirchen / Muenchen Tel: +49 89 / 99143-0 HONG KONG, Intel Semiconductor Ltd. 32 / F Two Pacific Place, 88 Queensway, Central Tel: +852 2844-4555 CANADA, Intel Semiconductor of Canada, Ltd. 190 Attwell Drive, Suite 500 Rexdale, Ontario M9W 6H8 Tel: +416 675-2438