Imaging Product Line RA1133J Full Frame Image Sensor square
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Imaging Product Line
RA1133J Full Frame Image Sensor
square pitch, 1100 pixel configuration
Description
RA1133J full frame sensor with reset capabilities designed specifically spectroscopy, biomedical imaging related scientific imaging applications. package array designed with integrated stage thermoelectric cooler. This enables device below ambient temperature, -15° when compared room temperature. combination very noise dark current make ideal light, high dynamic range high resolution applications.
Operation
major source dark current devices such this originates surface states Si-SiO2 interface. unigue design process enables RA1133J "multi-pinned phase" mode operation. This helps eliminate dark current generation interface surface states. holding vertical clocks negative potential during integration horizontal signal readout, surface will depleted surface state will generate dark current.
Features
363,000 picture elements (pixels) 1100 configuration square pixels 2-phase buried channel process On-chip amplifier noise high speed readout Dynamic range greater than 25,000:1 On-chip temperature sensor stage cooler integrated into package Hermetically sealed 100% fill factor data rate
imager structured with single output register imaging columns. lateral reset drain located adjacent this readout register which enables dumping accumulated charge from array. phase clocks needed drive readout register. Three phase clocks needed drive imaging cells. array available 30-pin metal package with integrated cooler shown Figure Package dimensions shown Figure Caution: While RA1133J imagers have been
designed resist electrostatic discharge (ESD), they damaged from such discharges. Always observe proper precautions when handling storing these sensors.
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DSP-303.01C- 8/2002W Page
Full Frame Sensor
Imaging Area
imaging area array 1100 columns (vertical shift registers). Each column picture elements. pixel size total imaging area 26.4 7.92 Typical spectral response function wavelength shown Figure This both standard array array coated with lumogen, phosphor that extends range detector into ultraviolet. vertical direction, each pixel corresponds stage (three electrodes) shift register. three electrode groups driven three-phases brought from both edges array improve clock electrode response time. Charge packets (imaging data) vertical register shifted horizontal readout clocking three phases transfer gate provided interface vertical register. transfer gate controls transferring charge into horizontal readout register. Charge flow from gate vertical shift register into gate horizontal readout register. control function performed pulsing transfer gate high permit charge flow from vertical register into horizontal register readout. When potential vertical register electrodes held steady, potential well created beneath storage gates When image impinges sensing area, electrical signal scene will collected potential well during this integration period. Following integration interval, collected charge (signal) array read full frame image transferring charge, more rows time, into horizontal shift register. From here, charge shifted serially output amplifier. mechanical shutter needed shield array from incident light during readout process. strobe illumination could used stimulate shuttered mode operation. Image smearing degrades performance, particularly data rates, unless shuttering provided.
Figure Pinout Configuration
TEMP+ TEMPVSUB
VSUB VOUT
Figure Quantum Efficiency
Quantum Efficiency
1000 1100
Wavelength,
Figure Functional Diagram
Imaging Area 1100 active pixels
Horizontal Register
horizontal shift register driven phase clocks horizontal register 1100 stages plus extension stages dummy stages, leading isolation stages trailing isolation stages). result, amplifier power dissipated more efficiently dark current generation localized heating minimized.
Horizontal Shift Output Buffer
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Full Frame Sensor
Summing Mode
horizontal register, there ouput summing well which clocked allow multiple-pixel summation scene. This summing well located after extra stages horizontal register prior biased gate (VOG) shown Figure summing gate clocked with horizontal clock phases with clock generator (see Figure summing gate timing). example, parallel lines charge additively transferred into serial register, then summing gate pulsed after charge from serial pixels been transferred into summing well. Thus, resulting signal represents charges four (2x2) contiguous pixels from imaging region. effectively reduces 1100 device array increases pixel size four times. Other variations this technique useful low-light level situations, i.e., scenes with contrast signal-tonoise ratio. There course, loss resolution that accompanies gain effective pixel size.
Figure Horizontal Shift Register Timing
Normal Mode
Mode
Table
Table Vertical Timing Diagram Characteristics
Item Units
Output Amplifier
There on-chip amplifier that located extended shift register. amplifier stage buried channel transistor amplifier shown Figure designed operate with data rates excess MHz. bandwidth approximately with load.
Temperature Monitoring
RA1133J device temperature sensor integrated into package monitoring array temperature.
Figure Horizontal Shift Register Timing
Timing Requirements
timing recommended RA1133J imager speed noise mode operation shown Figures duty cycyle, phase clock will drive horizontal register highest speed. Figure shows timing horizontal phase clocks, summing well clock reset clock. achieve high charge transfer, serial clocks must cross between peak voltage. addition, rise fall times phase clocks need more than order prevent injection spurious charge into channel.
Video Output
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Full Frame Sensor
Timing Requirements (cont.)
timing shown Figure repeated 1100 more) times allow readout complete line image. Figure shows timing requirements vertical register. Overlapping vertical clocks normally longer than Rise fall times clocks need longer order prevent spurious charge into channel. vertical clock transitions should occur when horizontal clocks held steady. Timing normal mode shown. difference between modes that during integration, clocks must held mode. potential which more positive than state channel potential transfer gate. Similar lateral antiblooming drain, charge will spill preferentially into rapid discharge drain. fixed potential barrier, HCCD cannot completely cleared charge thus horizontal shift sequence required before resumption valid data read.
Table Timing Diagram Characteristics
Item Units
rise/fall time clock period delay from edge rise/fall time delay from edge delay from edge rise/fall time pulse duration pulse duration
Array Cooling
Both dark current noise performance array improved cooling. dark current will reduced approximately every reduction array temperature. Cooling achieved integrated thermoelectric cooler. bias supplies TEC+ TEC- electronically control this cooler. This two-stage cooler capable reducing temperature array from ambient temperature. Additional cooling achieved decreasing ambient temperature cooling heat sink cooler shown Figure Figure
Figure Vertical Shift Register Timing Relationship Horizontal Clocks Normal Mode
Quiescent State Horizontal Phases During Transitions
Horizontal Clear 1135 Clock Cycles
1135 Clock Cycles read line
Region Interest
Rapid access regions interest facilitated lateral charge drain. drain constructed adjacent horizontal (HCCD) shift register. Unwanted lines data quickly disposed without requirement horizontal transfer. this manner, entire lines image data disposed single vertical shift sequence, with time penalty This contrasted with normal read sequence which includes both vertical shift µs), plus readout 1130 horizontal elements (2260 µs). unwanted lines transferred from storage region into HCCD, horizontal phases held high maintain surface
Integration Period Repeat 330(+) Times Read Entire Image Start Integration Period Normal Mode
Mode
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Full Frame Sensor
Figure Output Structure
Stage Amplifier
VSUB
VOUT
Figure Current Chip Temperature (Ambient Temperature)
Current Thermo-Electric Cooler,
TChip Ambient,
2.3° Heat Sink
1.8C/W Heat Sink Heat Sink Heat Sink Heat Sink
Figure Heat Sink Temperature Chip Temperature
Heat Sink Temperature THot, Current 1.1A Current 2.0A Current 2.5A Current
Chip Temperature TCPLP,
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Full Frame Sensor
Figure Package Dimensions
0.110 (2.794)
1.150 (29.21) 0.523 (13.28)
Image Center Apeture
holes 1.100 0.880 (27.94) (22.35) 0.440 (11.18) Measurements inches (millimeters)
Pixel
0.158 (4.013)
2.320 (58.93) 2.530 (64.26)
0.105 (2.667)
0.115 0.010 (2.921 0.254) Image surface inside window
0.330 (8.382) 0.620 (15.74)
0.451 0.010 (11.45 0.254) Bottom surface image surface 0.565 (14.35)
0.100 (Both sides) (2.540) 1.400 (35.56)
0.420 (10.67)
0.600 (15.24) 1.300 0.015 (33.02 0.381)
Table Absolute Maximum Ratings
Storage Temperature Operating Temperature
Table Table Typical Device Specifications
Parameter Format Pixel Size Imaging Area Dynamic Range Full Well Charge Saturation Voltage Dark Current Photo Response Uniformity Dark Signal Uniformity Charge Transfer Efficiency Output Amplifier Gain Operating Frequency Read Noise
1100 26.4 7.92 25,000:1 1200 0.99995
Units KemV pA/cm2 µV/eMHz
PRNU DSNU fclock
1000
0.9999
Notes: Full well/read noise, mode RLoad kOhms, mode mode Measured
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Full Frame Sensor
Table Table Recommended Operating Conditions
Signal (MPP) VSUB Function Horizontal Clocks Transfer Gate Clock Summing Gate Clock Vertical Clock (MPP Phase) Vertical Clocks Lateral Charge Gate Reset Gate Output Gate Amplifier Voltage Supply Lateral Charge Drain Amplifier Reset Drain Light Shield Video Amplifier Source Substrate Bias High High High High High High High Tolerance ±10% ±10%
Table Pinout Descriptions
TEMP+ TEMPVSUB Function Vertical Phase Vertical Phase Transfer Gate Lateral Charge Drain Lateral Charge Gate Light Shield Temp+ TempSubstrate Transfer Gate Vertical Phase Vertical Phase Vertical Phase Transfer Gate Summing Gate VOUT Function Output Gate Reset Gate Reset Drain Video Amplifier Source Lateral Charge Drain Video Output Video Amplifier Drain Lateral Charge Gate Horizontal Phase Horizontal Phase Light Shield Substrate Connection Transfer Gate Vertical Phase
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Full Frame Sensor
Ordering Information
While information provided this data sheet intended describe form, function this product, PerkinElmer reserves right make changes without notice.
Table Ordering Information
Part Number RA1133JAS-912
more information e-mail more information e-mail opto@perkinelmer.com visit site www.perkinelmer.com/opto. values nominal; specifications subject change without notice.
Table Sales Offices
North America
United States PerkinElmer Optoelectronics 2175 Mission College Blvd. Santa Clara, 95054 Toll Free: 800-775-OPTO (6786) Phone: +1-408-565-0830 Fax: +1-408-565-0703
Europe
Germany PerkinElmer Optoelectronics GmbH Wenzel-Jaksch-Str. D-65199 Wiesbaden, Germany Phone: +49-611-492-570 Fax: +49-611-492-165
Asia
Japan PerkinElmer Optoelectronics NEopt. 18F, Parale Mitsui Building Higashida-Cho, Kawasaki-Ku Kawasaki-Shi, Kanagawa-Ken 210-0005 Japan Phone: +81-44-200-9170 Fax: +81-44-200-9160 www.neopt.co.jp Ayer Rajah Crescent #06-12 Singapore 139947 Phone: +65-770-4925 Fax: +65-777-1008
Singapore
2001 PerkinElmer Inc. rights reserved.
PerkinElmer, PerkinElmer logo stylized trademarks PerkinElmer, Inc. Reticon registered trademark PerkinElmer, Inc.
DSP-303.01C 8/2002W
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